tree 04241ddde3d320d2625dff0e301c84144e3eed20
parent 276fd8eec9d293bad8aba82f6fe59622f9c4f34f
author Konstantin Porotchkin <kostap@marvell.com> 1601368632 +0300
committer Manish Pandey <manish.pandey2@arm.com> 1614247157 +0000

plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage

Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>