tree 3237c729ae888cb55542fbafd4d46fbc0b340e51
parent ac8c961a44db37e5cc9d6f261cf4194c55f476f6
author Olivier Deprez <olivier.deprez@arm.com> 1652110442 +0200
committer Olivier Deprez <olivier.deprez@arm.com> 1652110889 +0200

fix(cm): add barrier before el3 ns exit

In cm_prepare_el3_exit_ns, SCR_EL3.NS bit change (to non-secure) is not
committed before the EL2 restoration sequence happens.
At ICC_SRE_EL2 write in cm_el2_sysregs_context_restore, NS is still 0
from CPU perspective (with EEL2=0) which is an invalid condition and
triggers a fault. By adding ISB, SCR_EL3 gets synced with NS=1/EEL2=0
before ICC_SRE_EL2 write.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie72a6152aa7729e66b3344c1b7b0749f54cafb6f