| commit | d0dcbaafbc82876d85b72c05e6c2b0f5530dc41e | [log] [tgz] |
|---|---|---|
| author | Yann Gautier <yann.gautier@st.com> | Tue Jun 04 15:55:37 2019 +0200 |
| committer | Yann Gautier <yann.gautier@st.com> | Mon Jun 17 14:03:51 2019 +0200 |
| tree | 64a6e0de66ab7c1ba538dd25fbdbbc1ae5a17983 | |
| parent | 9d8bbcd76ffd31a1c3d581f88c653bbf3be13010 [diff] |
clk: stm32mp1: correctly handle Clock Spreading Generator To activate the CSG option, the driver needs to set the bit2 of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator. This bit should not be cleared when starting the PLL. Change-Id: Ie5c720ff03655f27a7e7e9e7ccf8295dd046112f Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>