tree 65291781470f3b468638ac0f3dc334ef7b715d2b
parent a1cf3c5c8c198944df53a647649d4f8e8e83f24b
author Varun Wadekar <vwadekar@nvidia.com> 1515632602 -0800
committer Varun Wadekar <vwadekar@nvidia.com> 1526424830 -0700

Workaround for CVE-2017-5715 on NVIDIA Denver CPUs

Flush the indirect branch predictor and RSB on entry to EL3 by issuing
a newly added instruction for Denver CPUs. Support for this operation
can be determined by comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.

To achieve this without performing any branch instruction, a per-cpu
vbar is installed which executes the workaround and then branches off
to the corresponding vector entry in the main vector table. A side
effect of this change is that the main vbar is configured before any
reset handling. This is to allow the per-cpu reset function to override
the vbar setting.

Change-Id: Ief493cd85935bab3cfee0397e856db5101bc8011
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>