mediatek: mt8183: refine GIC driver for low power scenarios
Implement rdist save/resore functions to support low power scenarios.
Change-Id: I9ddc077a04f843275fbe2e868cdd0bd00d622de7
diff --git a/plat/mediatek/mt8183/plat_mt_gic.c b/plat/mediatek/mt8183/plat_mt_gic.c
index ccb72be..35792b2 100644
--- a/plat/mediatek/mt8183/plat_mt_gic.c
+++ b/plat/mediatek/mt8183/plat_mt_gic.c
@@ -11,18 +11,17 @@
#include <bl31/interrupt_mgmt.h>
#include <mt_gic_v3.h>
#include <mtk_plat_common.h>
+#include "../drivers/arm/gic/v3/gicv3_private.h"
#include "plat_private.h"
#include <plat/common/platform.h>
#include <platform_def.h>
#include <stdint.h>
#include <stdio.h>
-#define NR_INT_POL_CTL 20
-
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
/* we save and restore the GICv3 context on system suspend */
-gicv3_redist_ctx_t rdist_ctx;
gicv3_dist_ctx_t dist_ctx;
static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
@@ -38,6 +37,16 @@
.mpidr_to_core_pos = mt_mpidr_to_core_pos,
};
+struct gic_chip_data {
+ unsigned int saved_group;
+ unsigned int saved_enable;
+ unsigned int saved_conf0;
+ unsigned int saved_conf1;
+ unsigned int saved_grpmod;
+};
+
+static struct gic_chip_data gic_data;
+
void clear_sec_pol_ctl_en(void)
{
unsigned int i;
@@ -54,15 +63,6 @@
gicv3_driver_init(&mt_gicv3_data);
}
-void mt_gic_init(void)
-{
- gicv3_distif_init();
- gicv3_rdistif_init(plat_my_core_pos());
- gicv3_cpuif_enable(plat_my_core_pos());
-
- clear_sec_pol_ctl_en();
-}
-
void mt_gic_set_pending(uint32_t irq)
{
gicv3_set_interrupt_pending(irq, plat_my_core_pos());
@@ -78,35 +78,83 @@
gicv3_cpuif_disable(plat_my_core_pos());
}
-void mt_gic_pcpu_init(void)
+void mt_gic_rdistif_init(void)
{
- gicv3_rdistif_init(plat_my_core_pos());
+ unsigned int proc_num;
+ unsigned int index;
+ uintptr_t gicr_base;
+
+ proc_num = plat_my_core_pos();
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+ /* set all SGI/PPI as non-secure GROUP1 by default */
+ mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
+ mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
+
+ /* setup the default PPI/SGI priorities */
+ for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
+ gicr_write_ipriorityr(gicr_base, index,
+ GICD_IPRIORITYR_DEF_VAL);
}
-void mt_gic_irq_save(void)
+void mt_gic_distif_save(void)
{
- gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
gicv3_distif_save(&dist_ctx);
}
-void mt_gic_irq_restore(void)
+void mt_gic_distif_restore(void)
{
gicv3_distif_init_restore(&dist_ctx);
- gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
}
-void mt_gic_sync_dcm_enable(void)
+void mt_gic_rdistif_save(void)
+{
+ unsigned int proc_num;
+ uintptr_t gicr_base;
+
+ proc_num = plat_my_core_pos();
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+ gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
+ gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
+ gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
+ gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
+ gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
+
+ rdist_has_saved[proc_num] = 1;
+}
+
+void mt_gic_rdistif_restore(void)
{
- unsigned int val = mmio_read_32(GIC_SYNC_DCM);
+ unsigned int proc_num;
+ uintptr_t gicr_base;
- val &= ~GIC_SYNC_DCM_MASK;
- mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_ON);
+ proc_num = plat_my_core_pos();
+ if (rdist_has_saved[proc_num] == 1) {
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
+ mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable);
+ mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
+ mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
+ mmio_write_32(gicr_base + GICR_IGRPMODR0, gic_data.saved_grpmod);
+ }
}
+void mt_gic_sync_dcm_enable(void)
+{
+ mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON);
+}
+
void mt_gic_sync_dcm_disable(void)
{
+ mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF);
+}
+
+void mt_gic_init(void)
+{
- unsigned int val = mmio_read_32(GIC_SYNC_DCM);
+ gicv3_distif_init();
+ gicv3_cpuif_enable(plat_my_core_pos());
+ mt_gic_rdistif_init();
- val &= ~GIC_SYNC_DCM_MASK;
- mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_OFF);
+ clear_sec_pol_ctl_en();
}