Merge pull request #617 from leon-chen-mtk/refactor_common_1
Refactor MediaTek platform common code
diff --git a/Makefile b/Makefile
index c5ec6d1..b1560a2 100644
--- a/Makefile
+++ b/Makefile
@@ -136,7 +136,7 @@
$(eval $(call add_define,DEBUG))
ifneq (${DEBUG}, 0)
BUILD_TYPE := debug
- CFLAGS += -g
+ TF_CFLAGS += -g
ASFLAGS += -g -Wa,--gdwarf-2
# Use LOG_LEVEL_INFO by default for debug builds
LOG_LEVEL := 40
@@ -179,12 +179,12 @@
-Werror -Wmissing-include-dirs \
-mgeneral-regs-only -D__ASSEMBLY__ \
${DEFINES} ${INCLUDES}
-CFLAGS += -nostdinc -ffreestanding -Wall \
+TF_CFLAGS += -nostdinc -ffreestanding -Wall \
-Werror -Wmissing-include-dirs \
-mgeneral-regs-only -mstrict-align \
-std=c99 -c -Os \
${DEFINES} ${INCLUDES}
-CFLAGS += -ffunction-sections -fdata-sections
+TF_CFLAGS += -ffunction-sections -fdata-sections
LDFLAGS += --fatal-warnings -O1
LDFLAGS += --gc-sections
@@ -331,7 +331,7 @@
# Check if -pedantic option should be used
ifeq (${DISABLE_PEDANTIC},0)
- CFLAGS += -pedantic
+ TF_CFLAGS += -pedantic
endif
# Using the ARM Trusted Firmware BL2 implies that a BL33 image also needs to be
@@ -487,7 +487,7 @@
# Check if deprecated declarations should be treated as error or not.
ifeq (${ERROR_DEPRECATED},0)
- CFLAGS += -Wno-error=deprecated-declarations
+ TF_CFLAGS += -Wno-error=deprecated-declarations
endif
# Expand build macros for the different images
diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S
index b22ce71..7f5a86b 100644
--- a/bl31/aarch64/crash_reporting.S
+++ b/bl31/aarch64/crash_reporting.S
@@ -346,11 +346,8 @@
bl do_cpu_reg_dump
bl str_in_crash_buf_print
- /* Print the gic registers */
- plat_print_gic_regs
-
- /* Print the interconnect registers */
- plat_print_interconnect_regs
+ /* Print some platform registers */
+ plat_crash_print_regs
/* Done reporting */
bl plat_panic_handler
diff --git a/common/bl_common.c b/common/bl_common.c
index d5b095a..2e23fbf 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -38,6 +38,7 @@
#include <io_storage.h>
#include <platform.h>
#include <string.h>
+#include <xlat_tables.h>
unsigned long page_align(unsigned long value, unsigned dir)
{
diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md
index c57dc7e..df2fbd8 100644
--- a/docs/cpu-specific-build-macros.md
+++ b/docs/cpu-specific-build-macros.md
@@ -22,14 +22,19 @@
ARM Trusted Firmware exports a series of build flags which control the
errata workarounds that are applied to each CPU by the reset handler. The
errata details can be found in the CPU specific errata documents published
-by ARM. The errata workarounds are implemented for a particular revision
-or a set of processor revisions. This is checked by reset handler at runtime.
-Each errata workaround is identified by its `ID` as specified in the processor's
+by ARM:
+
+* [Cortex-A53 MPCore Software Developers Errata Notice][A53 Errata Notice]
+* [Cortex-A57 MPCore Software Developers Errata Notice][A57 Errata Notice]
+
+The errata workarounds are implemented for a particular revision or a set of
+processor revisions. This is checked by the reset handler at runtime. Each
+errata workaround is identified by its `ID` as specified in the processor's
errata notice document. The format of the define used to enable/disable the
errata workaround is `ERRATA_<Processor name>_<ID>`, where the `Processor name`
is for example `A57` for the `Cortex_A57` CPU.
-All workarounds are disabled by default. The platform is reponsible for
+All workarounds are disabled by default. The platform is responsible for
enabling these workarounds according to its requirement by defining the
errata workaround build flags in the platform specific makefile. In case
these workarounds are enabled for the wrong CPU revision then the errata
@@ -60,6 +65,21 @@
* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57
CPU. This needs to be enabled only for revision r0p0 of the CPU.
+* `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57
+ CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+* `ERRATA_A57_826977`: This applies errata 826977 workaround to Cortex-A57
+ CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+* `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57
+ CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+* `ERRATA_A57_829520`: This applies errata 829520 workaround to Cortex-A57
+ CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
+* `ERRATA_A57_833471`: This applies errata 833471 workaround to Cortex-A57
+ CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
3. CPU Specific optimizations
------------------------------
@@ -94,3 +114,5 @@
_Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved._
[A57 SW Optimization Guide]: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
+[A53 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
+[A57 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 5e14823..5004d30 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -76,8 +76,8 @@
A platform port must enable the Memory Management Unit (MMU) as well as the
instruction and data caches for each BL stage. Setting up the translation
tables is the responsibility of the platform port because memory maps differ
-across platforms. A memory translation library (see `lib/aarch64/xlat_tables.c`)
-is provided to help in this setup. Note that although this library supports
+across platforms. A memory translation library (see `lib/xlat_tables/`) is
+provided to help in this setup. Note that although this library supports
non-identity mappings, this is intended only for re-mapping peripheral physical
addresses and allows platforms with high I/O addresses to reduce their virtual
address space. All other addresses corresponding to code and data must currently
@@ -448,6 +448,14 @@
Defines the maximum number of open IO handles. Attempting to open more IO
entities than this value using `io_open()` will fail with -ENOMEM.
+* **#define : MAX_IO_BLOCK_DEVICES**
+
+ Defines the maximum number of registered IO block devices. Attempting to
+ register more devices this value using `io_dev_open()` will fail
+ with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
+ With this macro, multiple block devices could be supported at the same
+ time.
+
If the platform needs to allocate data within the per-cpu data framework in
BL31, it should define the following macro. Currently this is only required if
the platform decides not to use the coherent memory section by undefining the
@@ -489,20 +497,15 @@
the following macro defined. In the ARM development platforms, this file is
found in `plat/arm/board/<plat_name>/include/plat_macros.S`.
-* **Macro : plat_print_gic_regs**
+* **Macro : plat_crash_print_regs**
- This macro allows the crash reporting routine to print GIC registers
- in case of an unhandled exception in BL31. This aids in debugging and
- this macro can be defined to be empty in case GIC register reporting is
- not desired.
-
-* **Macro : plat_print_interconnect_regs**
-
- This macro allows the crash reporting routine to print interconnect
+ This macro allows the crash reporting routine to print relevant platform
registers in case of an unhandled exception in BL31. This aids in debugging
- and this macro can be defined to be empty in case interconnect register
- reporting is not desired. In ARM standard platforms, the CCI snoop
- control registers are reported.
+ and this macro can be defined to be empty in case register reporting is not
+ desired.
+
+ For instance, GIC or interconnect registers may be helpful for
+ troubleshooting.
2.2 Handling Reset
diff --git a/docs/user-guide.md b/docs/user-guide.md
index e5e28a3..2bb9eac 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -8,27 +8,40 @@
3. [Tools](#3--tools)
4. [Getting the Trusted Firmware source code](#4--getting-the-trusted-firmware-source-code)
5. [Building the Trusted Firmware](#5--building-the-trusted-firmware)
-6. [Building the rest of the software stack](#6--building-the-rest-of-the-software-stack)
+6. [Building a FIP for Juno and FVP](#6--building-a-fip-for-juno-and-fvp)
7. [EL3 payloads alternative boot flow](#7--el3-payloads-alternative-boot-flow)
8. [Preloaded BL33 alternative boot flow](#8--preloaded-bl33-alternative-boot-flow)
-9. [Preparing the images to run on FVP](#9--preparing-the-images-to-run-on-fvp)
-10. [Running the software on FVP](#10--running-the-software-on-fvp)
-11. [Running the software on Juno](#11--running-the-software-on-juno)
-12. [Changes required for booting Linux on FVP in GICv3 mode](#12--changes-required-for-booting-linux-on-fvp-in-gicv3-mode)
+9. [Running the software on FVP](#9--running-the-software-on-fvp)
+10. [Running the software on Juno](#10--running-the-software-on-juno)
1. Introduction
----------------
-This document describes how to build ARM Trusted Firmware and run it with a
+This document describes how to build ARM Trusted Firmware (TF) and run it with a
tested set of other software components using defined configurations on the Juno
ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is
possible to use other software components, configurations and platforms but that
is outside the scope of this document.
-This document should be used in conjunction with the [Firmware Design] and the
-[Instructions for using the Linaro software deliverables][Linaro SW Instructions].
+This document assumes that the reader has previous experience running a fully
+bootable Linux software stack on Juno or FVP using the prebuilt binaries and
+filesystems provided by [Linaro][Linaro Release Notes]. Further information may
+be found in the [Instructions for using the Linaro software deliverables][Linaro
+SW Instructions]. It also assumes that the user understands the role of the
+different software components required to boot a Linux system:
+* Specific firmware images required by the platform (e.g. SCP firmware on Juno)
+* Normal world bootloader (e.g. UEFI or U-Boot)
+* Device tree
+* Linux kernel image
+* Root filesystem
+
+This document also assumes that the user is familiar with the FVP models and
+the different command line options available to launch the model.
+
+This document should be used in conjunction with the [Firmware Design].
+
2. Host machine requirements
-----------------------------
@@ -48,53 +61,28 @@
3. Tools
---------
-In addition to the mandatory prerequisite tools listed in the [instructions for
-using the Linaro software deliverables][Linaro SW Instructions], the following
-optional tools may be needed:
+Install the required packages to build Trusted Firmware with the following
+command:
-* `device-tree-compiler` package if you need to rebuild the Flattened Device
- Tree (FDT) source files (`.dts` files) provided with this software.
+ sudo apt-get install build-essential gcc make git
-* For debugging, ARM [Development Studio 5 (DS-5)][DS-5] v5.22.
+Download and install the AArch64 little-endian GCC cross compiler as indicated
+in the [Linaro instructions][Linaro SW Instructions].
+In addition, the following optional packages and tools may be needed:
-4. Getting the Trusted Firmware source code
---------------------------------------------
-
-The Trusted Firmware (TF) source code can be obtained as part of the standard
-Linaro releases, which provide a full software stack, including TF, normal
-world firmware, Linux kernel and device tree, file system as well as any
-additional micro-controller firmware required by the platform. This TF version
-is tested with the [Linaro 15.10 Release][Linaro Release Notes].
-
-Note 1: Both the LSK kernel or the latest tracking kernel can be used with TF;
-choose the one that best suits your needs.
-
-Note 2: Currently to run the latest tracking kernel on FVP with GICv3 driver,
-some modifications are required to UEFI. Refer
-[here](#11--changes-required-for-booting-linux-on-fvp-in-gicv3-mode)
-for more details.
-
-The TF source code will then be in `arm-tf/`. This is the upstream git
-repository cloned from GitHub. The revision checked out by the `repo` tool is
-indicated by the manifest file. Depending on the manifest file you're using,
-this might not be the latest upstream version. To synchronize your copy of the
-repository and get the latest updates, use the following commands:
+* `device-tree-compiler` package if you need to rebuild the Flattened Device
+ Tree (FDT) source files (`.dts` files) provided with this software.
- # Change to the Trusted Firmware directory.
- cd arm-tf
+* `libssl-dev` package if Trusted Board Boot is enabled in the build.
- # Download the latest code from GitHub.
- git fetch github
+* For debugging, ARM [Development Studio 5 (DS-5)][DS-5].
- # Update your working copy to the latest master.
- # This command will create a local branch master that tracks the remote
- # branch master from GitHub.
- git checkout --track github/master
+4. Getting the Trusted Firmware source code
+--------------------------------------------
-Alternatively, the TF source code can be separately cloned from the upstream
-GitHub repository:
+Download the Trusted Firmware source code from Github:
git clone https://github.com/ARM-software/arm-trusted-firmware.git
@@ -102,60 +90,42 @@
5. Building the Trusted Firmware
---------------------------------
-To build the Trusted Firmware images, change to the root directory of the
-Trusted Firmware source tree and follow these steps:
+* Before building Trusted Firmware, the environment variable `CROSS_COMPILE`
+ must point to the Linaro cross compiler:
-1. Set the compiler path, specify a Non-trusted Firmware image (BL33) and
- a valid platform, and then build:
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
- BL33=<path-to>/<bl33_image> \
- make PLAT=<platform> all fip
+* Change to the root directory of the Trusted Firmware source tree and build:
- If `PLAT` is not specified, `fvp` is assumed by default. See the "Summary of
- build options" for more information on available build options.
+ make PLAT=<platform> all
- The BL33 image corresponds to the software that is executed after switching
- to the non-secure world. UEFI can be used as the BL33 image. Refer to the
- "Building the rest of the software stack" section below.
+ Notes:
- The TSP (Test Secure Payload), corresponding to the BL32 image, is not
- compiled in by default. Refer to the "Building the Test Secure Payload"
- section below.
+ * If `PLAT` is not specified, `fvp` is assumed by default. See the
+ "Summary of build options" for more information on available build
+ options.
- By default this produces a release version of the build. To produce a debug
- version instead, refer to the "Debugging options" section below.
+ * The TSP (Test Secure Payload), corresponding to the BL32 image, is not
+ compiled in by default. Refer to the "Building the Test Secure Payload"
+ section below.
- The build process creates products in a `build` directory tree, building
- the objects and binaries for each boot loader stage in separate
- sub-directories. The following boot loader binary files are created from
- the corresponding ELF files:
+ * By default this produces a release version of the build. To produce a
+ debug version instead, refer to the "Debugging options" section below.
- * `build/<platform>/<build-type>/bl1.bin`
- * `build/<platform>/<build-type>/bl2.bin`
- * `build/<platform>/<build-type>/bl31.bin`
+ * The build process creates products in a `build` directory tree, building
+ the objects and binaries for each boot loader stage in separate
+ sub-directories. The following boot loader binary files are created
+ from the corresponding ELF files:
- where `<platform>` is the name of the chosen platform and `<build-type>` is
- either `debug` or `release`. A Firmware Image Package (FIP) will be created
- as part of the build. It contains all boot loader images except for
- `bl1.bin`.
+ * `build/<platform>/<build-type>/bl1.bin`
+ * `build/<platform>/<build-type>/bl2.bin`
+ * `build/<platform>/<build-type>/bl31.bin`
- * `build/<platform>/<build-type>/fip.bin`
+ where `<platform>` is the name of the chosen platform and `<build-type>`
+ is either `debug` or `release`. The actual number of images might differ
+ depending on the platform.
- For more information on FIPs, see the "Firmware Image Package" section in
- the [Firmware Design].
-
-2. (Optional) Some platforms may require a SCP_BL2 image to boot. This image can
- be included in the FIP when building the Trusted Firmware by specifying the
- `SCP_BL2` build option:
-
- SCP_BL2=<path-to>/<scp_bl2_image>
-
-3. Output binary files `bl1.bin` and `fip.bin` are both required to boot the
- system. How these files are used is platform specific. Refer to the
- platform documentation on how to use the firmware images.
-
-4. (Optional) Build products for a specific build variant can be removed using:
+* Build products for a specific build variant can be removed using:
make DEBUG=<D> PLAT=<platform> clean
@@ -165,16 +135,6 @@
make realclean
-5. (Optional) Path to binary for certain BL stages (BL2, BL31 and BL32) can be
- provided by specifying the BLx=<path-to>/<blx_image> where BLx is the BL stage.
- This will bypass the build of the BL component from source, but will include
- the specified binary in the final FIP image. Please note that BL32 will be
- included in the build, only if the `SPD` build option is specified.
-
- For example, specifying `BL2=<path-to>/<bl2_image>` in the build option,
- will skip compilation of BL2 source in trusted firmware, but include the BL2
- binary specified in the final FIP image.
-
### Summary of build options
ARM Trusted Firmware build system supports the following build options. Unless
@@ -223,9 +183,6 @@
optional. It is only needed if the platform makefile specifies that it
is required in order to build the `fwu_fip` target.
-* `CROSS_COMPILE`: Prefix to toolchain binaries. Please refer to examples in
- this document for usage.
-
* `DEBUG`: Chooses between a debug and release build. It can take either 0
(release) or 1 (debug) as values. 0 is the default.
@@ -525,79 +482,22 @@
* `FVP_USE_GIC_DRIVER` : Selects the GIC driver to be built. Options:
- `FVP_GICV2` : The GICv2 only driver is selected
- `FVP_GICV3` : The GICv3 only driver is selected (default option)
- - `FVP_GICV3_LEGACY`: The Legacy GICv3 driver is selected (deprecated).
-
- Note that if the FVP is configured for legacy VE memory map, then ARM
- Trusted Firmware must be compiled with GICv2 only driver using
- `FVP_USE_GIC_DRIVER=FVP_GICV2` build option.
+ - `FVP_GICV3_LEGACY`: The Legacy GICv3 driver is selected (deprecated)
+ Note: If Trusted Firmware is compiled with this option on FVPs with
+ GICv3 hardware, then it configures the hardware to run in GICv2
+ emulation mode
* `FVP_CLUSTER_COUNT` : Configures the cluster count to be used to
build the topology tree within Trusted Firmware. By default the
Trusted Firmware is configured for dual cluster topology and this option
can be used to override the default value.
-### Creating a Firmware Image Package
-
-FIPs are automatically created as part of the build instructions described in
-the previous section. It is also possible to independently build the FIP
-creation tool and FIPs if required. To do this, follow these steps:
-
-Build the tool:
-
- make -C tools/fip_create
-
-It is recommended to remove the build artifacts before rebuilding:
-
- make -C tools/fip_create clean
-
-Create a Firmware package that contains existing BL2 and BL31 images:
-
- # fip_create --help to print usage information
- # fip_create <fip_name> <images to add> [--dump to show result]
- ./tools/fip_create/fip_create fip.bin --dump \
- --tb-fw build/<platform>/debug/bl2.bin --soc-fw build/<platform>/debug/bl31.bin
-
- Firmware Image Package ToC:
- ---------------------------
- - Trusted Boot Firmware BL2: offset=0x88, size=0x81E8
- file: 'build/<platform>/debug/bl2.bin'
- - EL3 Runtime Firmware BL31: offset=0x8270, size=0xC218
- file: 'build/<platform>/debug/bl31.bin'
- ---------------------------
- Creating "fip.bin"
-
-View the contents of an existing Firmware package:
-
- ./tools/fip_create/fip_create fip.bin --dump
-
- Firmware Image Package ToC:
- ---------------------------
- - Trusted Boot Firmware BL2: offset=0x88, size=0x81E8
- - EL3 Runtime Firmware BL31: offset=0x8270, size=0xC218
- ---------------------------
-
-Existing package entries can be individually updated:
-
- # Change the BL2 from Debug to Release version
- ./tools/fip_create/fip_create fip.bin --dump \
- --tb-fw build/<platform>/release/bl2.bin
-
- Firmware Image Package ToC:
- ---------------------------
- - Trusted Boot Firmware BL2: offset=0x88, size=0x7240
- file: 'build/<platform>/release/bl2.bin'
- - EL3 Runtime Firmware BL31: offset=0x72C8, size=0xC218
- ---------------------------
- Updating "fip.bin"
-
### Debugging options
To compile a debug version and make the build more verbose use
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
- BL33=<path-to>/<bl33_image> \
- make PLAT=<platform> DEBUG=1 V=1 all fip
+ make PLAT=<platform> DEBUG=1 V=1 all
AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
example DS-5) might not support this and may need an older version of DWARF
@@ -615,9 +515,7 @@
Extra debug options can be passed to the build system by setting `CFLAGS`:
CFLAGS='-O0 -gdwarf-2' \
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
- BL33=<path-to>/<bl33_image> \
- make PLAT=<platform> DEBUG=1 V=1 all fip
+ make PLAT=<platform> DEBUG=1 V=1 all
It is also possible to introduce an infinite loop to help in debugging the
post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with
@@ -639,6 +537,7 @@
# Resume execution
continue
+
### Building the Test Secure Payload
The TSP is coupled with a companion runtime service in the BL31 firmware,
@@ -647,49 +546,102 @@
"Secure-EL1 Payloads and Dispatchers" section in the [Firmware Design].
First clean the Trusted Firmware build directory to get rid of any previous
-BL31 binary. Then to build the TSP image and include it into the FIP use:
+BL31 binary. Then to build the TSP image use:
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
- BL33=<path-to>/<bl33_image> \
- make PLAT=<platform> SPD=tspd all fip
+ make PLAT=<platform> SPD=tspd all
An additional boot loader binary file is created in the `build` directory:
-* `build/<platform>/<build-type>/bl32.bin`
+ `build/<platform>/<build-type>/bl32.bin`
-The FIP will now contain the additional BL32 image. Here is an example
-output from an FVP build in release mode including BL32 and using
-`FVP_AARCH64_EFI.fd` as BL33 image:
- Firmware Image Package ToC:
- ---------------------------
- - Trusted Boot Firmware BL2: offset=0xD8, size=0x6000
- file: './build/fvp/release/bl2.bin'
- - EL3 Runtime Firmware BL31: offset=0x60D8, size=0x9000
- file: './build/fvp/release/bl31.bin'
- - Secure Payload BL32 (Trusted OS): offset=0xF0D8, size=0x3000
- file: './build/fvp/release/bl32.bin'
- - Non-Trusted Firmware BL33: offset=0x120D8, size=0x280000
- file: '../FVP_AARCH64_EFI.fd'
- ---------------------------
- Creating "build/fvp/release/fip.bin"
+### Checking source code style
+When making changes to the source for submission to the project, the source
+must be in compliance with the Linux style guide, and to assist with this check
+the project Makefile contains two targets, which both utilise the
+`checkpatch.pl` script that ships with the Linux source tree.
-### Building the Certificate Generation Tool
+To check the entire source tree, you must first download a copy of
+`checkpatch.pl` (or the full Linux source), set the `CHECKPATCH` environment
+variable to point to the script and build the target checkcodebase:
+
+ make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
-The `cert_create` tool can be built separately through the following commands:
+To just check the style on the files that differ between your local branch and
+the remote master, use:
- $ cd tools/cert_create
- $ make PLAT=<platform> [DEBUG=1] [V=1]
+ make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
-`DEBUG=1` builds the tool in debug mode. `V=1` makes the build process more
-verbose. The following command should be used to obtain help about the tool:
+If you wish to check your patch against something other than the remote master,
+set the `BASE_COMMIT` variable to your desired branch. By default, `BASE_COMMIT`
+is set to `origin/master`.
+
+
+### Building and using the FIP tool
+
+Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware
+project to package firmware images in a single binary. The number and type of
+images that should be packed in a FIP is platform specific and may include TF
+images and other firmware images required by the platform. For example, most
+platforms require a BL33 image which corresponds to the normal world bootloader
+(e.g. UEFI or U-Boot).
+
+The TF build system provides the make target `fip` to create a FIP file for the
+specified platform using the FIP creation tool included in the TF project. For
+example, to build a FIP file for FVP, packaging TF images and a BL33 image:
+
+ make PLAT=fvp BL33=<path/to/bl33.bin> fip
- $ ./cert_create -h
+The resulting FIP may be found in:
-The `cert_create` tool is automatically built with the `fip` target when
-`GENERATE_COT=1`.
+ `build/fvp/<build-type>/fip.bin`
+For advanced operations on FIP files, it is also possible to independently build
+the tool and create or modify FIPs using this tool. To do this, follow these
+steps:
+
+It is recommended to remove old artifacts before building the tool:
+
+ make -C tools/fip_create clean
+
+Build the tool:
+
+ make [DEBUG=1] [V=1] fiptool
+
+The tool binary can be located in:
+
+ ./tools/fip_create/fip_create
+
+Invoking the tool with `--help` will print a help message with all available
+options.
+
+Example 1: create a new Firmware package `fip.bin` that contains BL2 and BL31:
+
+ ./tools/fip_create/fip_create \
+ --tb-fw build/<platform>/<build-type>/bl2.bin \
+ --soc-fw build/<platform>/<build-type>/bl31.bin \
+ fip.bin
+
+Example 2: view the contents of an existing Firmware package:
+
+ ./tools/fip_create/fip_create --dump <path-to>/fip.bin
+
+Example 3: update the entries of an existing Firmware package:
+
+ # Change the BL2 from Debug to Release version
+ ./tools/fip_create/fip_create \
+ --tb-fw build/<platform>/release/bl2.bin \
+ build/<platform>/debug/fip.bin
+
+Example 4: unpack all entries from an existing Firmware package:
+
+ # Images will be unpacked to the working directory
+ ./tools/fip_create/fip_create --unpack <path-to>/fip.bin
+
+More information about FIP can be found in the [Firmware Design document]
+[Firmware Design].
+
### Building FIP images with support for Trusted Board Boot
@@ -742,18 +694,17 @@
Example of command line using RSA development keys:
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
- BL33=<path-to>/<bl33_image> \
MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
ARM_ROTPK_LOCATION=devel_rsa \
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
+ BL33=<path-to>/<bl33_image> \
all fip
- The result of this build will be the bl1.bin and the fip.bin binaries, with
- the difference that the FIP will include the certificates corresponding to
- the Chain of Trust described in the TBBR-client document. These certificates
- can also be found in the output build directory.
+ The result of this build will be the bl1.bin and the fip.bin binaries. This
+ FIP will include the certificates corresponding to the Chain of Trust
+ described in the TBBR-client document. These certificates can also be found
+ in the output build directory.
3. The optional FWU_FIP contains any additional images to be loaded from
Non-Volatile storage during the [Firmware Update] process. To build the
@@ -766,15 +717,14 @@
Example of Juno command line for generating both `fwu` and `fwu_fip`
targets using RSA development:
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
- BL33=<path-to>/<bl33_image> \
- SCP_BL2=<path-to>/<scp_bl2_image> \
- SCP_BL2U=<path-to>/<scp_bl2u_image> \
- NS_BL2U=<path-to>/<ns_bl2u_image> \
MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
ARM_ROTPK_LOCATION=devel_rsa \
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
+ BL33=<path-to>/<bl33_image> \
+ SCP_BL2=<path-to>/<scp_bl2_image> \
+ SCP_BL2U=<path-to>/<scp_bl2u_image> \
+ NS_BL2U=<path-to>/<ns_bl2u_image> \
all fip fwu_fip
Note: The BL2U image will be built by default and added to the FWU_FIP.
@@ -789,92 +739,75 @@
Chain of Trust described in the TBBR-client document. These certificates
can also be found in the output build directory.
-
-### Checking source code style
-
-When making changes to the source for submission to the project, the source
-must be in compliance with the Linux style guide, and to assist with this check
-the project Makefile contains two targets, which both utilise the
-`checkpatch.pl` script that ships with the Linux source tree.
-To check the entire source tree, you must first download a copy of
-`checkpatch.pl` (or the full Linux source), set the `CHECKPATCH` environment
-variable to point to the script and build the target checkcodebase:
-
- make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
-
-To just check the style on the files that differ between your local branch and
-the remote master, use:
-
- make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
-
-If you wish to check your patch against something other than the remote master,
-set the `BASE_COMMIT` variable to your desired branch. By default, `BASE_COMMIT`
-is set to `origin/master`.
-
-
-6. Building the rest of the software stack
--------------------------------------------
+### Building the Certificate Generation Tool
-The Linaro release provides a set of scripts that automate the process of
-building all components of the software stack. However, the scripts only support
-a limited number of Trusted Firmware build options. Therefore, it is recommended
-to modify these scripts to build all components except Trusted Firmware, and
-build Trusted Firmware separately as described in the section "Building the
-Trusted Firmware" above.
+The `cert_create` tool is built as part of the TF build process when the `fip`
+make target is specified and TBB is enabled (as described in the previous
+section), but it can also be built separately with the following command:
-The instructions below are targeted at an OpenEmbedded filesystem.
+ make PLAT=<platform> [DEBUG=1] [V=1] certtool
-1. To exclude Trusted Firmware from the automated build process, edit the
- variant file `build-scripts/variants/<platform>-oe`, where `<platform>`
- is either `fvp` or `juno`. Add the following lines at the end of the file:
+Specifying the platform is mandatory since the tool is platform specific.
+`DEBUG=1` builds the tool in debug mode. `V=1` makes the build process more
+verbose. The following command should be used to obtain help about the tool:
- # Disable ARM Trusted Firmware build
- ARM_TF_BUILD_ENABLED=0
+ ./tools/cert_create/cert_create -h
-2. Launch the build script:
- CROSS_COMPILE=aarch64-linux-gnu- \
- build-scripts/build-all.sh <platform>-oe
+6. Building a FIP for Juno and FVP
+-----------------------------------
-### Preparing the Firmware Image Package
+This section provides Juno and FVP specific instructions to build Trusted
+Firmware, obtain the additional required firmware, and pack it all together in
+a single FIP binary. It assumes that a [Linaro Release][Linaro Release Notes]
+has been installed.
-The EDK2 binary should be specified as `BL33` in the `make` command line when
-building the Trusted Firmware. See the "Building the Trusted Firmware" section
-above. The EDK2 binary for use with the ARM Trusted Firmware can be found here:
+Note: follow the full instructions for one platform before switching to a
+different one. Mixing instructions for different platforms may result in
+corrupted binaries.
- uefi/edk2/Build/ArmVExpress-FVP-AArch64-Minimal/DEBUG_GCC49/FV/FVP_AARCH64_EFI.fd [for FVP]
- uefi/edk2/Build/ArmJuno/DEBUG_GCC49/FV/BL33_AP_UEFI.fd [for Juno]
+1. Clean the working directory
-### Building an alternative EDK2
+ make realclean
-* By default, EDK2 is built in debug mode. To build a release version instead,
- change the following line in the variant file:
+2. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
- UEFI_BUILD_MODE=DEBUG
+ Use the fip_create tool to extract the SCP_BL2 and BL33 images from the FIP
+ package included in the Linaro release:
- into:
+ # Build the fip_create tool
+ make [DEBUG=1] [V=1] fiptool
- UEFI_BUILD_MODE=RELEASE
+ # Unpack firmware images from Linaro FIP
+ ./tools/fip_create/fip_create --unpack \
+ <path/to/linaro/release>/fip.bin
-* On FVP, if legacy GICv2 locations are used, the EDK2 platform makefile must
- be updated. This is required as EDK2 does not support probing for the GIC
- location. To do this, first clean the EDK2 build directory:
+ The unpack operation will result in a set of binary images extracted to the
+ working directory. The SCP_BL2 image corresponds to `scp-fw.bin` and BL33
+ corresponds to `nt-fw.bin`.
- build-scripts/build-uefi.sh fvp-oe clean
+ Note: the fip_create tool will complain if the images to be unpacked already
+ exist in the current directory. If that is the case, either delete those
+ files or use the `--force` option to overwrite.
- Then edit the following file:
+3. Build TF images and create a new FIP
- uefi/edk2/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.mak
+ # Juno
+ make PLAT=juno SCP_BL2=scp-fw.bin BL33=nt-fw.bin all fip
- and add the following build flag into the `EDK2_MACROS` variable:
+ # FVP
+ make PLAT=fvp BL33=nt-fw.bin all fip
- -D ARM_FVP_LEGACY_GICV2_LOCATION=1
+The resulting BL1 and FIP images may be found in:
- Then rebuild everything as described above in step 2.
+ # Juno
+ ./build/juno/release/bl1.bin
+ ./build/juno/release/fip.bin
- Finally rebuild the Trusted Firmware to generate a new FIP using the
- instructions in the "Building the Trusted Firmware" section.
+ # FVP
+ ./build/fvp/release/bl1.bin
+ ./build/fvp/release/fip.bin
7. EL3 payloads alternative boot flow
@@ -1006,7 +939,6 @@
will create a FIP without a BL33 and prepare to jump to a BL33 image loaded at
address 0x80000000:
- CROSS_COMPILE=<path-to>/bin/aarch64-linux-gnu- \
make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
#### Boot of a preloaded bootwrapped kernel image on Base FVP
@@ -1040,61 +972,8 @@
JTAG on Juno.
-9. Preparing the images to run on FVP
---------------------------------------
-
-Note: This section can be ignored when booting an EL3 payload, as no Flattened
-Device Tree or kernel image is needed in this case.
-
-### Obtaining the Flattened Device Trees
-
-Depending on the FVP configuration and Linux configuration used, different
-FDT files are required. FDTs for the Foundation and Base FVPs can be found in
-the Trusted Firmware source directory under `fdts/`. The Foundation FVP has a
-subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
-and MMC support, and has only one CPU cluster.
-
-Note: It is not recommended to use the FDTs built along the kernel because not
-all FDTs are available from there.
-
-* `fvp-base-gicv2-psci.dtb`
-
- (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
- Base memory map configuration.
-
-* `fvp-base-gicv2legacy-psci.dtb`
-
- For use with AEMv8 Base FVP with legacy VE GIC memory map configuration.
-
-* `fvp-base-gicv3-psci.dtb`
-
- For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base memory map
- configuration and Linux GICv3 support.
-
-* `fvp-foundation-gicv2-psci.dtb`
-
- (Default) For use with Foundation FVP with Base memory map configuration.
-
-* `fvp-foundation-gicv2legacy-psci.dtb`
-
- For use with Foundation FVP with legacy VE GIC memory map configuration.
-
-* `fvp-foundation-gicv3-psci.dtb`
-
- For use with Foundation FVP with Base memory map configuration and Linux
- GICv3 support.
-
-Copy the chosen FDT blob as `fdt.dtb` to the directory from which the FVP
-is launched. Alternatively a symbolic link may be used.
-
-### Preparing the kernel image
-
-Copy the kernel image file `linux/arch/arm64/boot/Image` to the directory from
-which the FVP is launched. Alternatively a symbolic link may be used.
-
-
-10. Running the software on FVP
---------------------------------
+9. Running the software on FVP
+-------------------------------
This version of the ARM Trusted Firmware has been tested on the following ARM
FVPs (64-bit versions only).
@@ -1117,14 +996,39 @@
The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
downloaded for free from [ARM's website][ARM FVP website].
-The Linaro release provides a script to run the software on FVP. However, it
-only supports a limited number of model parameter options. Therefore, it is
-recommended to launch the FVP manually for all use cases described below.
-
Please refer to the FVP documentation for a detailed description of the model
parameter options. A brief description of the important ones that affect the ARM
Trusted Firmware and normal world software behavior is provided below.
+### Obtaining the Flattened Device Trees
+
+Depending on the FVP configuration and Linux configuration used, different
+FDT files are required. FDTs for the Foundation and Base FVPs can be found in
+the Trusted Firmware source directory under `fdts/`. The Foundation FVP has a
+subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
+and MMC support, and has only one CPU cluster.
+
+Note: It is not recommended to use the FDTs built along the kernel because not
+all FDTs are available from there.
+
+* `fvp-base-gicv2-psci.dtb`
+
+ For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
+ Base memory map configuration.
+
+* `fvp-base-gicv3-psci.dtb`
+
+ (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
+ memory map configuration and Linux GICv3 support.
+
+* `fvp-foundation-gicv2-psci.dtb`
+
+ For use with Foundation FVP with Base memory map configuration.
+
+* `fvp-foundation-gicv3-psci.dtb`
+
+ (Default) For use with Foundation FVP with Base memory map configuration
+ and Linux GICv3 support.
### Running on the Foundation FVP with reset to BL1 entrypoint
@@ -1142,81 +1046,17 @@
--data="<path-to>/<kernel-binary>"@0x80080000 \
--block-device="<path-to>/<file-system-image>"
-1. The `--data="<path-to-some-binary>"@0x...` parameters are used to load
- binaries into memory.
-
- * BL1 is loaded at the start of the Trusted ROM.
- * The Firmware Image Package is loaded at the start of NOR FLASH0.
- * The Linux kernel image and device tree are loaded in DRAM.
-
-2. The `--block-device` parameter is used to specify the path to the file
- system image provided to Linux via VirtioBlock. Note that it must point to
- the real file and that a symbolic link to this file cannot be used with the
- FVP.
-
-The default use-case for the Foundation FVP is to enable the GICv3 device in
-the model but use the GICv2 FDT, in order for Linux to drive the GIC in GICv2
-emulation mode.
-
-### Notes regarding Base FVP configuration options
-
-Please refer to these notes in the subsequent "Running on the Base FVP"
-sections.
-
-1. The `-C bp.flashloader0.fname` parameter is used to load a Firmware Image
- Package at the start of NOR FLASH0 (see the "Building the Trusted Firmware"
- section above).
-
-2. Using `cache_state_modelled=1` makes booting very slow. The software will
- still work (and run much faster) without this option but this will hide any
- cache maintenance defects in the software.
-
-3. The `-C bp.virtioblockdevice.image_path` parameter is used to specify the
- path to the file system image provided to Linux via VirtioBlock. Note that
- it must point to the real file and that a symbolic link to this file cannot
- be used with the FVP. Ensure that the FVP doesn't output any error messages.
- If the following error message is displayed:
-
- ERROR: BlockDevice: Failed to open "<path-to>/<file-system-image>"!
-
- then make sure the path to the file-system image in the model parameter is
- correct and that read permission is correctly set on the file-system image
- file.
-
-4. Setting the `-C bp.secure_memory` parameter to `1` is only supported on
- Base FVP versions 5.4 and newer. Setting this parameter to `0` is also
- supported. The `-C bp.tzc_400.diagnostics=1` parameter is optional. It
- instructs the FVP to provide some helpful information if a secure memory
- violation occurs.
-
-5. The `--data="<path-to-some-binary>"@<base-address-of-binary>` parameter is
- used to load images into Base FVP memory. The base addresses used should
- match the image base addresses used while linking the images. This parameter
- is used to load the Linux kernel image and device tree into DRAM.
-
-6. This and the following notes only apply when the firmware is built with
- the `RESET_TO_BL31` option.
-
- The `--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`
- parameter is needed to load the individual bootloader images in memory.
- BL32 image is only needed if BL31 has been built to expect a Secure-EL1
- Payload.
-
-7. The `-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>` parameter, where
- X and Y are the cluster and CPU numbers respectively, is used to set the
- reset vector for each core.
-
-8. Changing the default value of `ARM_TSP_RAM_LOCATION` will also require
- changing the value of
- `--data="<path-to><bl32-binary>"@<base-address-of-bl32>` to the new value of
- `BL32_BASE`.
-
+Notes:
+* BL1 is loaded at the start of the Trusted ROM.
+* The Firmware Image Package is loaded at the start of NOR FLASH0.
+* The Linux kernel image and device tree are loaded in DRAM.
+* The default use-case for the Foundation FVP is to use the `--gicv3` option
+ and enable the GICv3 device in the model. Note that without this option,
+ the Foundation FVP defaults to legacy (Versatile Express) memory map which
+ is not supported by ARM Trusted Firmware.
### Running on the AEMv8 Base FVP with reset to BL1 entrypoint
-Please read "Notes regarding Base FVP configuration options" section above for
-information about some of the options to run the software.
-
The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
with 8 CPUs using the ARM Trusted Firmware.
@@ -1235,9 +1075,6 @@
### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
-Please read "Notes regarding Base FVP configuration options" section above for
-information about some of the options to run the software.
-
The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
boot Linux with 8 CPUs using the ARM Trusted Firmware.
@@ -1254,9 +1091,6 @@
### Running on the AEMv8 Base FVP with reset to BL31 entrypoint
-Please read "Notes regarding Base FVP configuration options" section above for
-information about some of the options to run the software.
-
The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
with 8 CPUs using the ARM Trusted Firmware.
@@ -1282,10 +1116,24 @@
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
-### Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
+Notes:
-Please read "Notes regarding Base FVP configuration options" section above for
-information about some of the options to run the software.
+* Since a FIP is not loaded when using BL31 as reset entrypoint, the
+ `--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`
+ parameter is needed to load the individual bootloader images in memory.
+ BL32 image is only needed if BL31 has been built to expect a Secure-EL1
+ Payload.
+
+* The `-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>` parameter, where
+ X and Y are the cluster and CPU numbers respectively, is used to set the
+ reset vector for each core.
+
+* Changing the default value of `ARM_TSP_RAM_LOCATION` will also require
+ changing the value of
+ `--data="<path-to><bl32-binary>"@<base-address-of-bl32>` to the new value of
+ `BL32_BASE`.
+
+### Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
boot Linux with 8 CPUs using the ARM Trusted Firmware.
@@ -1310,90 +1158,8 @@
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
-### Configuring the GICv2 memory map
-
-The Base FVP models support GICv2 with the default model parameters at the
-following addresses. The Foundation FVP also supports these addresses when
-configured for GICv3 in GICv2 emulation mode.
-
- GICv2 Distributor Interface 0x2f000000
- GICv2 CPU Interface 0x2c000000
- GICv2 Virtual CPU Interface 0x2c010000
- GICv2 Hypervisor Interface 0x2c02f000
-
-The AEMv8 Base FVP can be configured to support GICv2 at addresses
-corresponding to the legacy (Versatile Express) memory map as follows. These are
-the default addresses when using the Foundation FVP in GICv2 mode.
- GICv2 Distributor Interface 0x2c001000
- GICv2 CPU Interface 0x2c002000
- GICv2 Virtual CPU Interface 0x2c004000
- GICv2 Hypervisor Interface 0x2c006000
-
-The choice of memory map is reflected in the build variant field (bits[15:12])
-in the `SYS_ID` register (Offset `0x0`) in the Versatile Express System
-registers memory map (`0x1c010000`).
-
-* `SYS_ID.Build[15:12]`
-
- `0x1` corresponds to the presence of the Base GIC memory map. This is the
- default value on the Base FVPs.
-
-* `SYS_ID.Build[15:12]`
-
- `0x0` corresponds to the presence of the Legacy VE GIC memory map. This is
- the default value on the Foundation FVP.
-
-This register can be configured as described in the following sections.
-
-NOTE: If the legacy VE GIC memory map is used, then Trusted Firmware must be
-compiled with the GICv2 only driver, and the corresponding FDT and BL33 images
-should be used.
-
-#### Configuring AEMv8 Foundation FVP GIC for legacy VE memory map
-
-The following parameters configure the Foundation FVP to use GICv2 with the
-legacy VE memory map:
-
- <path-to>/Foundation_Platform \
- --cores=4 \
- --secure-memory \
- --visualization \
- --no-gicv3 \
- --data="<path-to>/<bl1-binary>"@0x0 \
- --data="<path-to>/<FIP-binary>"@0x8000000 \
- --block-device="<path-to>/<file-system-image>"
-
-Explicit configuration of the `SYS_ID` register is not required.
-
-#### Configuring AEMv8 Base FVP GIC for legacy VE memory map
-
-The following parameters configure the AEMv8 Base FVP to use GICv2 with the
-legacy VE memory map. They must added to the parameters described in the
-"Running on the AEMv8 Base FVP" section above:
-
- -C cluster0.gic.GICD-offset=0x1000 \
- -C cluster0.gic.GICC-offset=0x2000 \
- -C cluster0.gic.GICH-offset=0x4000 \
- -C cluster0.gic.GICH-other-CPU-offset=0x5000 \
- -C cluster0.gic.GICV-offset=0x6000 \
- -C cluster0.gic.PERIPH-size=0x8000 \
- -C cluster1.gic.GICD-offset=0x1000 \
- -C cluster1.gic.GICC-offset=0x2000 \
- -C cluster1.gic.GICH-offset=0x4000 \
- -C cluster1.gic.GICH-other-CPU-offset=0x5000 \
- -C cluster1.gic.GICV-offset=0x6000 \
- -C cluster1.gic.PERIPH-size=0x8000 \
- -C gic_distributor.GICD-alias=0x2c001000 \
- -C gicv3.gicv2-only=1 \
- -C bp.variant=0x0
-
-The `bp.variant` parameter corresponds to the build variant field of the
-`SYS_ID` register. Setting this to `0x0` allows the ARM Trusted Firmware to
-detect the legacy VE memory map while configuring the GIC.
-
-
-11. Running the software on Juno
+10. Running the software on Juno
---------------------------------
This version of the ARM Trusted Firmware has been tested on Juno r0 and Juno r1.
@@ -1406,17 +1172,6 @@
### Preparing Trusted Firmware images
-The Juno platform requires a SCP_BL1 and a SCP_BL2 image to boot up. The
-SCP_BL1 image contains the ROM firmware that runs on the SCP (System Control
-Processor), whereas the SCP_BL2 image contains the SCP Runtime firmware. Both
-images are embedded within the Juno board recovery image, these are the files
-`bl0.bin` and `bl30.bin`, respectively. Please note that these filenames still
-use the old terminology.
-
-The SCP_BL2 file must be part of the FIP image. Therefore, its path must be
-supplied using the `SCP_BL2` variable on the command line when building the
-FIP. Please refer to the section "Building the Trusted Firmware".
-
After building Trusted Firmware, the files `bl1.bin` and `fip.bin` need copying
to the `SOFTWARE/` directory of the Juno SD card.
@@ -1430,67 +1185,16 @@
### Testing SYSTEM SUSPEND on Juno
The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
-to RAM. For more details refer to section 5.16 of [PSCI]. The [Linaro Release
-Notes] point to the required SCP and motherboard firmware binaries supporting
-this feature on Juno. The mainline linux kernel does not yet have support for
-this feature on Juno but it is queued to be merged in v4.4. Till that becomes
-available, the feature can be tested by using a custom kernel built from the
-following repository:
+to RAM. For more details refer to section 5.16 of [PSCI]. To test system suspend
+on Juno, at the linux shell prompt, issue the following command:
- git clone git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/linux.git
- cd linux
- git checkout firmware/psci-1.0
-
-Configure the linux kernel:
-
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
- make ARCH=arm64 defconfig
-
-The feature is tested conveniently by using the RTC. Enable the RTC driver in
-menuconfig
-
- make ARCH=arm64 menuconfig
-
-The PL031 RTC driver can be enabled at the following location in menuconfig
-
- ARM AMBA PL031 RTC
- | Location:
- | -> Device Drivers
- | -> Real Time Clock
-
-Build the kernel
-
- make ARCH=arm64 Image -j8
-
-Replace the kernel image in the `SOFTWARE/` directory of the Juno SD card with
-the `Image` from `arch/arm64/boot/` of the linux directory.
-
-Reset the board and wait for it to boot. At the shell prompt issue the
-following command:
-
- echo +10 > /sys/class/rtc/rtc1/wakealarm
+ echo +10 > /sys/class/rtc/rtc0/wakealarm
echo -n mem > /sys/power/state
The Juno board should suspend to RAM and then wakeup after 10 seconds due to
wakeup interrupt from RTC.
-12. Changes required for booting Linux on FVP in GICv3 mode
-------------------------------------------------------------
-
-In case the TF FVP port is built with the build option
-`FVP_USE_GIC_DRIVER=FVP_GICV3`, then the GICv3 hardware cannot be used in
-GICv2 legacy mode. The default build of UEFI for FVP in
-[latest tracking kernel][Linaro Release Notes] configures GICv3 in GICv2 legacy
-mode. This can be changed by setting the build flag
-`gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy` to FALSE in
-`uefi/edk2/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc`.
-
-Recompile UEFI as mentioned [here][FVP Instructions].
-
-The GICv3 DTBs found in ARM Trusted Firmware source directory can be
-used to test the GICv3 kernel on the respective FVP models.
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._
@@ -1498,7 +1202,7 @@
[Firmware Design]: firmware-design.md
[ARM FVP website]: http://www.arm.com/fvp
-[Linaro Release Notes]: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1510
+[Linaro Release Notes]: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1602
[ARM Platforms Portal]: https://community.arm.com/groups/arm-development-platforms
[Linaro SW Instructions]: https://community.arm.com/docs/DOC-10803
[Juno Instructions]: https://community.arm.com/docs/DOC-10804
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index ee6bf8d..e533587 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -191,8 +191,8 @@
*/
void tzc400_configure_region(unsigned int filters,
int region,
- uintptr_t region_base,
- uintptr_t region_top,
+ unsigned long long region_base,
+ unsigned long long region_top,
tzc_region_attributes_t sec_attr,
unsigned int nsaid_permissions)
{
diff --git a/drivers/arm/tzc/tzc_common_private.c b/drivers/arm/tzc/tzc_common_private.c
index f570daf..dae6c3a 100644
--- a/drivers/arm/tzc/tzc_common_private.c
+++ b/drivers/arm/tzc/tzc_common_private.c
@@ -42,42 +42,42 @@
#define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \
static inline void _tzc##fn_name##_write_region_base( \
- uintptr_t base, \
- int region_no, \
- uintptr_t region_base) \
+ uintptr_t base, \
+ int region_no, \
+ unsigned long long region_base) \
{ \
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
- TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \
- (unsigned int)region_base); \
+ TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \
+ (uint32_t)region_base); \
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \
- (unsigned int)(region_base >> 32)); \
+ (uint32_t)(region_base >> 32)); \
}
#define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \
static inline void _tzc##fn_name##_write_region_top( \
- uintptr_t base, \
- int region_no, \
- uintptr_t region_top) \
+ uintptr_t base, \
+ int region_no, \
+ unsigned long long region_top) \
{ \
mmio_write_32(base + \
TZC_REGION_OFFSET \
(TZC_##macro_name##_REGION_SIZE, \
region_no) + \
TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \
- (unsigned int)region_top); \
+ (uint32_t)region_top); \
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \
- (unsigned int)(region_top >> 32)); \
+ (uint32_t)(region_top >> 32)); \
}
#define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \
@@ -146,8 +146,8 @@
void _tzc##fn_name##_configure_region(uintptr_t base, \
unsigned int filters, \
int region_no, \
- uintptr_t region_base, \
- uintptr_t region_top, \
+ unsigned long long region_base, \
+ unsigned long long region_top, \
tzc_region_attributes_t sec_attr, \
unsigned int nsaid_permissions) \
{ \
@@ -155,8 +155,8 @@
VERBOSE("TrustZone : Configuring region " \
"(TZC Interface Base: %p, region_no = %d)" \
"...\n", (void *)base, region_no); \
- VERBOSE("TrustZone : ... base = %p, top = %p," \
- "\n", (void *)region_base, (void *)region_top);\
+ VERBOSE("TrustZone : ... base = %llx, top = %llx," \
+ "\n", region_base, region_top);\
VERBOSE("TrustZone : ... sec_attr = 0x%x," \
" ns_devs = 0x%x)\n", \
sec_attr, nsaid_permissions); \
diff --git a/drivers/arm/tzc/tzc_dmc500.c b/drivers/arm/tzc/tzc_dmc500.c
index 16a53a4..b2f0bf6 100644
--- a/drivers/arm/tzc/tzc_dmc500.c
+++ b/drivers/arm/tzc/tzc_dmc500.c
@@ -196,8 +196,8 @@
* for this region (see comment for that function).
*/
void tzc_dmc500_configure_region(int region_no,
- uintptr_t region_base,
- uintptr_t region_top,
+ unsigned long long region_base,
+ unsigned long long region_top,
tzc_region_attributes_t sec_attr,
unsigned int nsaid_permissions)
{
diff --git a/drivers/emmc/emmc.c b/drivers/emmc/emmc.c
new file mode 100644
index 0000000..5fe28ef
--- /dev/null
+++ b/drivers/emmc/emmc.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Defines a simple and generic interface to access eMMC device.
+ */
+
+#include <arch_helpers.h>
+#include <assert.h>
+#include <debug.h>
+#include <emmc.h>
+#include <errno.h>
+#include <string.h>
+
+static const emmc_ops_t *ops;
+static unsigned int emmc_ocr_value;
+static emmc_csd_t emmc_csd;
+
+static int emmc_device_state(void)
+{
+ emmc_cmd_t cmd;
+ int ret;
+
+ do {
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD13;
+ cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
+ cmd.resp_type = EMMC_RESPONSE_R1;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+ assert((cmd.resp_data[0] & STATUS_SWITCH_ERROR) == 0);
+ /* Ignore improbable errors in release builds */
+ (void)ret;
+ } while ((cmd.resp_data[0] & STATUS_READY_FOR_DATA) == 0);
+ return EMMC_GET_STATE(cmd.resp_data[0]);
+}
+
+static void emmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
+{
+ emmc_cmd_t cmd;
+ int ret, state;
+
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD6;
+ cmd.cmd_arg = EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
+ EXTCSD_VALUE(value) | 1;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ /* wait to exit PRG state */
+ do {
+ state = emmc_device_state();
+ } while (state == EMMC_STATE_PRG);
+ /* Ignore improbable errors in release builds */
+ (void)ret;
+}
+
+static void emmc_set_ios(int clk, int bus_width)
+{
+ int ret;
+
+ /* set IO speed & IO bus width */
+ if (emmc_csd.spec_vers == 4)
+ emmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH, bus_width);
+ ret = ops->set_ios(clk, bus_width);
+ assert(ret == 0);
+ /* Ignore improbable errors in release builds */
+ (void)ret;
+}
+
+static int emmc_enumerate(int clk, int bus_width)
+{
+ emmc_cmd_t cmd;
+ int ret, state;
+
+ ops->init();
+
+ /* CMD0: reset to IDLE */
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD0;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ while (1) {
+ /* CMD1: get OCR register */
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD1;
+ cmd.cmd_arg = OCR_SECTOR_MODE | OCR_VDD_MIN_2V7 |
+ OCR_VDD_MIN_1V7;
+ cmd.resp_type = EMMC_RESPONSE_R3;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+ emmc_ocr_value = cmd.resp_data[0];
+ if (emmc_ocr_value & OCR_POWERUP)
+ break;
+ }
+
+ /* CMD2: Card Identification */
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD2;
+ cmd.resp_type = EMMC_RESPONSE_R2;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ /* CMD3: Set Relative Address */
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD3;
+ cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
+ cmd.resp_type = EMMC_RESPONSE_R1;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ /* CMD9: CSD Register */
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD9;
+ cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
+ cmd.resp_type = EMMC_RESPONSE_R2;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+ memcpy(&emmc_csd, &cmd.resp_data, sizeof(cmd.resp_data));
+
+ /* CMD7: Select Card */
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD7;
+ cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
+ cmd.resp_type = EMMC_RESPONSE_R1;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+ /* wait to TRAN state */
+ do {
+ state = emmc_device_state();
+ } while (state != EMMC_STATE_TRAN);
+
+ emmc_set_ios(clk, bus_width);
+ return ret;
+}
+
+size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size)
+{
+ emmc_cmd_t cmd;
+ int ret;
+
+ assert((ops != 0) &&
+ (ops->read != 0) &&
+ ((buf & EMMC_BLOCK_MASK) == 0) &&
+ ((size & EMMC_BLOCK_MASK) == 0));
+
+ inv_dcache_range(buf, size);
+ ret = ops->prepare(lba, buf, size);
+ assert(ret == 0);
+
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ if (size > EMMC_BLOCK_SIZE)
+ cmd.cmd_idx = EMMC_CMD18;
+ else
+ cmd.cmd_idx = EMMC_CMD17;
+ if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
+ cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
+ else
+ cmd.cmd_arg = lba;
+ cmd.resp_type = EMMC_RESPONSE_R1;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ ret = ops->read(lba, buf, size);
+ assert(ret == 0);
+
+ /* wait buffer empty */
+ emmc_device_state();
+
+ if (size > EMMC_BLOCK_SIZE) {
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD12;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+ }
+ /* Ignore improbable errors in release builds */
+ (void)ret;
+ return size;
+}
+
+size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size)
+{
+ emmc_cmd_t cmd;
+ int ret;
+
+ assert((ops != 0) &&
+ (ops->write != 0) &&
+ ((buf & EMMC_BLOCK_MASK) == 0) &&
+ ((size & EMMC_BLOCK_MASK) == 0));
+
+ clean_dcache_range(buf, size);
+ ret = ops->prepare(lba, buf, size);
+ assert(ret == 0);
+
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ if (size > EMMC_BLOCK_SIZE)
+ cmd.cmd_idx = EMMC_CMD25;
+ else
+ cmd.cmd_idx = EMMC_CMD24;
+ if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
+ cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
+ else
+ cmd.cmd_arg = lba;
+ cmd.resp_type = EMMC_RESPONSE_R1;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ ret = ops->write(lba, buf, size);
+ assert(ret == 0);
+
+ /* wait buffer empty */
+ emmc_device_state();
+
+ if (size > EMMC_BLOCK_SIZE) {
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD12;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+ }
+ /* Ignore improbable errors in release builds */
+ (void)ret;
+ return size;
+}
+
+size_t emmc_erase_blocks(int lba, size_t size)
+{
+ emmc_cmd_t cmd;
+ int ret, state;
+
+ assert(ops != 0);
+ assert((size != 0) && ((size % EMMC_BLOCK_SIZE) == 0));
+
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD35;
+ cmd.cmd_arg = lba;
+ cmd.resp_type = EMMC_RESPONSE_R1;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD36;
+ cmd.cmd_arg = lba + (size / EMMC_BLOCK_SIZE) - 1;
+ cmd.resp_type = EMMC_RESPONSE_R1;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ memset(&cmd, 0, sizeof(emmc_cmd_t));
+ cmd.cmd_idx = EMMC_CMD38;
+ cmd.resp_type = EMMC_RESPONSE_R1B;
+ ret = ops->send_cmd(&cmd);
+ assert(ret == 0);
+
+ /* wait to TRAN state */
+ do {
+ state = emmc_device_state();
+ } while (state != EMMC_STATE_TRAN);
+ /* Ignore improbable errors in release builds */
+ (void)ret;
+ return size;
+}
+
+static inline void emmc_rpmb_enable(void)
+{
+ emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
+ PART_CFG_BOOT_PARTITION1_ENABLE |
+ PART_CFG_PARTITION1_ACCESS);
+}
+
+static inline void emmc_rpmb_disable(void)
+{
+ emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
+ PART_CFG_BOOT_PARTITION1_ENABLE);
+}
+
+size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size)
+{
+ size_t size_read;
+
+ emmc_rpmb_enable();
+ size_read = emmc_read_blocks(lba, buf, size);
+ emmc_rpmb_disable();
+ return size_read;
+}
+
+size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size)
+{
+ size_t size_written;
+
+ emmc_rpmb_enable();
+ size_written = emmc_write_blocks(lba, buf, size);
+ emmc_rpmb_disable();
+ return size_written;
+}
+
+size_t emmc_rpmb_erase_blocks(int lba, size_t size)
+{
+ size_t size_erased;
+
+ emmc_rpmb_enable();
+ size_erased = emmc_erase_blocks(lba, size);
+ emmc_rpmb_disable();
+ return size_erased;
+}
+
+void emmc_init(const emmc_ops_t *ops_ptr, int clk, int width)
+{
+ assert((ops_ptr != 0) &&
+ (ops_ptr->init != 0) &&
+ (ops_ptr->send_cmd != 0) &&
+ (ops_ptr->set_ios != 0) &&
+ (ops_ptr->prepare != 0) &&
+ (ops_ptr->read != 0) &&
+ (ops_ptr->write != 0) &&
+ (clk != 0) &&
+ ((width == EMMC_BUS_WIDTH_1) ||
+ (width == EMMC_BUS_WIDTH_4) ||
+ (width == EMMC_BUS_WIDTH_8)));
+ ops = ops_ptr;
+
+ emmc_enumerate(clk, width);
+}
diff --git a/drivers/io/io_block.c b/drivers/io/io_block.c
new file mode 100644
index 0000000..198b723
--- /dev/null
+++ b/drivers/io/io_block.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <debug.h>
+#include <errno.h>
+#include <io_block.h>
+#include <io_driver.h>
+#include <io_storage.h>
+#include <platform_def.h>
+#include <string.h>
+
+typedef struct {
+ io_block_dev_spec_t *dev_spec;
+ uintptr_t base;
+ size_t file_pos;
+ size_t size;
+} block_dev_state_t;
+
+#define is_power_of_2(x) ((x != 0) && ((x & (x - 1)) == 0))
+
+io_type_t device_type_block(void);
+
+static int block_open(io_dev_info_t *dev_info, const uintptr_t spec,
+ io_entity_t *entity);
+static int block_seek(io_entity_t *entity, int mode, ssize_t offset);
+static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
+ size_t *length_read);
+static int block_write(io_entity_t *entity, const uintptr_t buffer,
+ size_t length, size_t *length_written);
+static int block_close(io_entity_t *entity);
+static int block_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info);
+static int block_dev_close(io_dev_info_t *dev_info);
+
+static const io_dev_connector_t block_dev_connector = {
+ .dev_open = block_dev_open
+};
+
+static const io_dev_funcs_t block_dev_funcs = {
+ .type = device_type_block,
+ .open = block_open,
+ .seek = block_seek,
+ .size = NULL,
+ .read = block_read,
+ .write = block_write,
+ .close = block_close,
+ .dev_init = NULL,
+ .dev_close = block_dev_close,
+};
+
+static block_dev_state_t state_pool[MAX_IO_BLOCK_DEVICES];
+static io_dev_info_t dev_info_pool[MAX_IO_BLOCK_DEVICES];
+
+/* Track number of allocated block state */
+static unsigned int block_dev_count;
+
+io_type_t device_type_block(void)
+{
+ return IO_TYPE_BLOCK;
+}
+
+/* Locate a block state in the pool, specified by address */
+static int find_first_block_state(const io_block_dev_spec_t *dev_spec,
+ unsigned int *index_out)
+{
+ int result = -ENOENT;
+ for (int index = 0; index < MAX_IO_BLOCK_DEVICES; ++index) {
+ /* dev_spec is used as identifier since it's unique */
+ if (state_pool[index].dev_spec == dev_spec) {
+ result = 0;
+ *index_out = index;
+ break;
+ }
+ }
+ return result;
+}
+
+/* Allocate a device info from the pool and return a pointer to it */
+static int allocate_dev_info(io_dev_info_t **dev_info)
+{
+ int result = -ENOMEM;
+ assert(dev_info != NULL);
+
+ if (block_dev_count < MAX_IO_BLOCK_DEVICES) {
+ unsigned int index = 0;
+ result = find_first_block_state(NULL, &index);
+ assert(result == 0);
+ /* initialize dev_info */
+ dev_info_pool[index].funcs = &block_dev_funcs;
+ dev_info_pool[index].info = (uintptr_t)&state_pool[index];
+ *dev_info = &dev_info_pool[index];
+ ++block_dev_count;
+ }
+
+ return result;
+}
+
+
+/* Release a device info to the pool */
+static int free_dev_info(io_dev_info_t *dev_info)
+{
+ int result;
+ unsigned int index = 0;
+ block_dev_state_t *state;
+ assert(dev_info != NULL);
+
+ state = (block_dev_state_t *)dev_info->info;
+ result = find_first_block_state(state->dev_spec, &index);
+ if (result == 0) {
+ /* free if device info is valid */
+ memset(state, 0, sizeof(block_dev_state_t));
+ memset(dev_info, 0, sizeof(io_dev_info_t));
+ --block_dev_count;
+ }
+
+ return result;
+}
+
+static int block_open(io_dev_info_t *dev_info, const uintptr_t spec,
+ io_entity_t *entity)
+{
+ block_dev_state_t *cur;
+ io_block_spec_t *region;
+
+ assert((dev_info->info != (uintptr_t)NULL) &&
+ (spec != (uintptr_t)NULL) &&
+ (entity->info == (uintptr_t)NULL));
+
+ region = (io_block_spec_t *)spec;
+ cur = (block_dev_state_t *)dev_info->info;
+ assert(((region->offset % cur->dev_spec->block_size) == 0) &&
+ ((region->length % cur->dev_spec->block_size) == 0));
+
+ cur->base = region->offset;
+ cur->size = region->length;
+ cur->file_pos = 0;
+
+ entity->info = (uintptr_t)cur;
+ return 0;
+}
+
+/* parameter offset is relative address at here */
+static int block_seek(io_entity_t *entity, int mode, ssize_t offset)
+{
+ block_dev_state_t *cur;
+
+ assert(entity->info != (uintptr_t)NULL);
+
+ cur = (block_dev_state_t *)entity->info;
+ assert((offset >= 0) && (offset < cur->size));
+
+ switch (mode) {
+ case IO_SEEK_SET:
+ cur->file_pos = offset;
+ break;
+ case IO_SEEK_CUR:
+ cur->file_pos += offset;
+ break;
+ default:
+ return -EINVAL;
+ }
+ assert(cur->file_pos < cur->size);
+ return 0;
+}
+
+static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
+ size_t *length_read)
+{
+ block_dev_state_t *cur;
+ io_block_spec_t *buf;
+ io_block_ops_t *ops;
+ size_t aligned_length, skip, count, left, padding, block_size;
+ int lba;
+
+ assert(entity->info != (uintptr_t)NULL);
+ cur = (block_dev_state_t *)entity->info;
+ ops = &(cur->dev_spec->ops);
+ buf = &(cur->dev_spec->buffer);
+ block_size = cur->dev_spec->block_size;
+ assert((length <= cur->size) &&
+ (length > 0) &&
+ (ops->read != 0));
+
+ skip = cur->file_pos % block_size;
+ aligned_length = ((skip + length) + (block_size - 1)) &
+ ~(block_size - 1);
+ padding = aligned_length - (skip + length);
+ left = aligned_length;
+ do {
+ lba = (cur->file_pos + cur->base) / block_size;
+ if (left >= buf->length) {
+ /* Since left is larger, it's impossible to padding. */
+ if (skip) {
+ /*
+ * The beginning address (file_pos) isn't
+ * aligned with block size, we need to use
+ * block buffer to read block. Since block
+ * device is always relied on DMA operation.
+ */
+ count = ops->read(lba, buf->offset,
+ buf->length);
+ } else {
+ count = ops->read(lba, buffer, buf->length);
+ }
+ assert(count == buf->length);
+ cur->file_pos += count - skip;
+ if (skip) {
+ /*
+ * Since it's not aligned with block size,
+ * block buffer is used to store data.
+ */
+ memcpy((void *)buffer,
+ (void *)(buf->offset + skip),
+ count - skip);
+ }
+ left = left - (count - skip);
+ } else {
+ if (skip || padding) {
+ /*
+ * The beginning address (file_pos) isn't
+ * aligned with block size, we have to read
+ * full block by block buffer instead.
+ * The size isn't aligned with block size.
+ * Use block buffer to avoid overflow.
+ */
+ count = ops->read(lba, buf->offset, left);
+ } else
+ count = ops->read(lba, buffer, left);
+ assert(count == left);
+ left = left - (skip + padding);
+ cur->file_pos += left;
+ if (skip || padding) {
+ /*
+ * Since it's not aligned with block size,
+ * block buffer is used to store data.
+ */
+ memcpy((void *)buffer,
+ (void *)(buf->offset + skip),
+ left);
+ }
+ /* It's already the last block operation */
+ left = 0;
+ }
+ skip = cur->file_pos % block_size;
+ } while (left > 0);
+ *length_read = length;
+
+ return 0;
+}
+
+static int block_write(io_entity_t *entity, const uintptr_t buffer,
+ size_t length, size_t *length_written)
+{
+ block_dev_state_t *cur;
+ io_block_spec_t *buf;
+ io_block_ops_t *ops;
+ size_t aligned_length, skip, count, left, padding, block_size;
+ int lba;
+
+ assert(entity->info != (uintptr_t)NULL);
+ cur = (block_dev_state_t *)entity->info;
+ ops = &(cur->dev_spec->ops);
+ buf = &(cur->dev_spec->buffer);
+ block_size = cur->dev_spec->block_size;
+ assert((length <= cur->size) &&
+ (length > 0) &&
+ (ops->read != 0) &&
+ (ops->write != 0));
+
+ skip = cur->file_pos % block_size;
+ aligned_length = ((skip + length) + (block_size - 1)) &
+ ~(block_size - 1);
+ padding = aligned_length - (skip + length);
+ left = aligned_length;
+ do {
+ lba = (cur->file_pos + cur->base) / block_size;
+ if (left >= buf->length) {
+ /* Since left is larger, it's impossible to padding. */
+ if (skip) {
+ /*
+ * The beginning address (file_pos) isn't
+ * aligned with block size, we need to use
+ * block buffer to write block. Since block
+ * device is always relied on DMA operation.
+ */
+ count = ops->read(lba, buf->offset,
+ buf->length);
+ assert(count == buf->length);
+ memcpy((void *)(buf->offset + skip),
+ (void *)buffer,
+ count - skip);
+ count = ops->write(lba, buf->offset,
+ buf->length);
+ } else
+ count = ops->write(lba, buffer, buf->length);
+ assert(count == buf->length);
+ cur->file_pos += count - skip;
+ left = left - (count - skip);
+ } else {
+ if (skip || padding) {
+ /*
+ * The beginning address (file_pos) isn't
+ * aligned with block size, we need to avoid
+ * poluate data in the beginning. Reading and
+ * skipping the beginning is the only way.
+ * The size isn't aligned with block size.
+ * Use block buffer to avoid overflow.
+ */
+ count = ops->read(lba, buf->offset, left);
+ assert(count == left);
+ memcpy((void *)(buf->offset + skip),
+ (void *)buffer,
+ left - skip - padding);
+ count = ops->write(lba, buf->offset, left);
+ } else
+ count = ops->write(lba, buffer, left);
+ assert(count == left);
+ cur->file_pos += left - (skip + padding);
+ /* It's already the last block operation */
+ left = 0;
+ }
+ skip = cur->file_pos % block_size;
+ } while (left > 0);
+ *length_written = length;
+ return 0;
+}
+
+static int block_close(io_entity_t *entity)
+{
+ entity->info = (uintptr_t)NULL;
+ return 0;
+}
+
+static int block_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info)
+{
+ block_dev_state_t *cur;
+ io_block_spec_t *buffer;
+ io_dev_info_t *info;
+ size_t block_size;
+ int result;
+
+ assert(dev_info != NULL);
+ result = allocate_dev_info(&info);
+ if (result)
+ return -ENOENT;
+
+ cur = (block_dev_state_t *)info->info;
+ /* dev_spec is type of io_block_dev_spec_t. */
+ cur->dev_spec = (io_block_dev_spec_t *)dev_spec;
+ buffer = &(cur->dev_spec->buffer);
+ block_size = cur->dev_spec->block_size;
+ assert((block_size > 0) &&
+ (is_power_of_2(block_size) != 0) &&
+ ((buffer->offset % block_size) == 0) &&
+ ((buffer->length % block_size) == 0));
+
+ *dev_info = info; /* cast away const */
+ (void)block_size;
+ (void)buffer;
+ return 0;
+}
+
+static int block_dev_close(io_dev_info_t *dev_info)
+{
+ return free_dev_info(dev_info);
+}
+
+/* Exported functions */
+
+/* Register the Block driver with the IO abstraction */
+int register_io_dev_block(const io_dev_connector_t **dev_con)
+{
+ int result;
+
+ assert(dev_con != NULL);
+
+ /*
+ * Since dev_info isn't really used in io_register_device, always
+ * use the same device info at here instead.
+ */
+ result = io_register_device(&dev_info_pool[0]);
+ if (result == 0)
+ *dev_con = &block_dev_connector;
+ return result;
+}
diff --git a/fdts/fvp-base-gicv2legacy-psci.dtb b/fdts/fvp-base-gicv2legacy-psci.dtb
deleted file mode 100644
index 4c6f37a..0000000
--- a/fdts/fvp-base-gicv2legacy-psci.dtb
+++ /dev/null
Binary files differ
diff --git a/fdts/fvp-base-gicv2legacy-psci.dts b/fdts/fvp-base-gicv2legacy-psci.dts
deleted file mode 100644
index 5a7ce2f..0000000
--- a/fdts/fvp-base-gicv2legacy-psci.dts
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/dts-v1/;
-
-/memreserve/ 0x80000000 0x00010000;
-
-/ {
-};
-
-/ {
- model = "FVP Base";
- compatible = "arm,vfp-base", "arm,vexpress";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- aliases {
- serial0 = &v2m_serial0;
- serial1 = &v2m_serial1;
- serial2 = &v2m_serial2;
- serial3 = &v2m_serial3;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
- method = "smc";
- cpu_suspend = <0xc4000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0xc4000003>;
- sys_poweroff = <0x84000008>;
- sys_reset = <0x84000009>;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&CPU4>;
- };
- core1 {
- cpu = <&CPU5>;
- };
- core2 {
- cpu = <&CPU6>;
- };
- core3 {
- cpu = <&CPU7>;
- };
- };
- };
-
- idle-states {
- entry-method = "arm,psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <40>;
- exit-latency-us = <100>;
- min-residency-us = <150>;
- };
-
- CLUSTER_SLEEP_0: cluster-sleep-0 {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x1010000>;
- entry-latency-us = <500>;
- exit-latency-us = <1000>;
- min-residency-us = <2500>;
- };
- };
-
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU1:cpu@1 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2:cpu@2 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU3:cpu@3 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU4:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU5:cpu@101 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU6:cpu@102 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x102>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU7:cpu@103 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x103>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x00000000 0x80000000 0 0x7F000000>,
- <0x00000008 0x80000000 0 0x80000000>;
- };
-
- gic: interrupt-controller@2c001000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0x2c001000 0 0x1000>,
- <0x0 0x2c002000 0 0x1000>,
- <0x0 0x2c004000 0 0x2000>,
- <0x0 0x2c006000 0 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
- <1 14 0xff01>,
- <1 11 0xff01>,
- <1 10 0xff01>;
- clock-frequency = <100000000>;
- };
-
- timer@2a810000 {
- compatible = "arm,armv7-timer-mem";
- reg = <0x0 0x2a810000 0x0 0x10000>;
- clock-frequency = <100000000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- frame@2a830000 {
- frame-number = <1>;
- interrupts = <0 26 4>;
- reg = <0x0 0x2a830000 0x0 0x10000>;
- };
- };
-
- pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <0 60 4>,
- <0 61 4>,
- <0 62 4>,
- <0 63 4>;
- };
-
- smb {
- compatible = "simple-bus";
-
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0 0x08000000 0x04000000>,
- <1 0 0 0x14000000 0x04000000>,
- <2 0 0 0x18000000 0x04000000>,
- <3 0 0 0x1c000000 0x04000000>,
- <4 0 0 0x0c000000 0x04000000>,
- <5 0 0 0x10000000 0x04000000>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 63>;
- interrupt-map = <0 0 0 &gic 0 0 4>,
- <0 0 1 &gic 0 1 4>,
- <0 0 2 &gic 0 2 4>,
- <0 0 3 &gic 0 3 4>,
- <0 0 4 &gic 0 4 4>,
- <0 0 5 &gic 0 5 4>,
- <0 0 6 &gic 0 6 4>,
- <0 0 7 &gic 0 7 4>,
- <0 0 8 &gic 0 8 4>,
- <0 0 9 &gic 0 9 4>,
- <0 0 10 &gic 0 10 4>,
- <0 0 11 &gic 0 11 4>,
- <0 0 12 &gic 0 12 4>,
- <0 0 13 &gic 0 13 4>,
- <0 0 14 &gic 0 14 4>,
- <0 0 15 &gic 0 15 4>,
- <0 0 16 &gic 0 16 4>,
- <0 0 17 &gic 0 17 4>,
- <0 0 18 &gic 0 18 4>,
- <0 0 19 &gic 0 19 4>,
- <0 0 20 &gic 0 20 4>,
- <0 0 21 &gic 0 21 4>,
- <0 0 22 &gic 0 22 4>,
- <0 0 23 &gic 0 23 4>,
- <0 0 24 &gic 0 24 4>,
- <0 0 25 &gic 0 25 4>,
- <0 0 26 &gic 0 26 4>,
- <0 0 27 &gic 0 27 4>,
- <0 0 28 &gic 0 28 4>,
- <0 0 29 &gic 0 29 4>,
- <0 0 30 &gic 0 30 4>,
- <0 0 31 &gic 0 31 4>,
- <0 0 32 &gic 0 32 4>,
- <0 0 33 &gic 0 33 4>,
- <0 0 34 &gic 0 34 4>,
- <0 0 35 &gic 0 35 4>,
- <0 0 36 &gic 0 36 4>,
- <0 0 37 &gic 0 37 4>,
- <0 0 38 &gic 0 38 4>,
- <0 0 39 &gic 0 39 4>,
- <0 0 40 &gic 0 40 4>,
- <0 0 41 &gic 0 41 4>,
- <0 0 42 &gic 0 42 4>;
-
- /include/ "rtsm_ve-motherboard.dtsi"
- };
-
- panels {
- panel@0 {
- compatible = "panel";
- mode = "XVGA";
- refresh = <60>;
- xres = <1024>;
- yres = <768>;
- pixclock = <15748>;
- left_margin = <152>;
- right_margin = <48>;
- upper_margin = <23>;
- lower_margin = <3>;
- hsync_len = <104>;
- vsync_len = <4>;
- sync = <0>;
- vmode = "FB_VMODE_NONINTERLACED";
- tim2 = "TIM2_BCD", "TIM2_IPC";
- cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
- caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
- bpp = <16>;
- };
- };
-};
diff --git a/fdts/fvp-foundation-gicv2legacy-psci.dtb b/fdts/fvp-foundation-gicv2legacy-psci.dtb
deleted file mode 100644
index efded44..0000000
--- a/fdts/fvp-foundation-gicv2legacy-psci.dtb
+++ /dev/null
Binary files differ
diff --git a/fdts/fvp-foundation-gicv2legacy-psci.dts b/fdts/fvp-foundation-gicv2legacy-psci.dts
deleted file mode 100644
index e6e4012..0000000
--- a/fdts/fvp-foundation-gicv2legacy-psci.dts
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of the ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/dts-v1/;
-
-/memreserve/ 0x80000000 0x00010000;
-
-/ {
-};
-
-/ {
- model = "FVP Foundation";
- compatible = "arm,fvp-base", "arm,vexpress";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- aliases {
- serial0 = &v2m_serial0;
- serial1 = &v2m_serial1;
- serial2 = &v2m_serial2;
- serial3 = &v2m_serial3;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
- method = "smc";
- cpu_suspend = <0xc4000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0xc4000003>;
- sys_poweroff = <0x84000008>;
- sys_reset = <0x84000009>;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
- };
-
- idle-states {
- entry-method = "arm,psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <40>;
- exit-latency-us = <100>;
- min-residency-us = <150>;
- };
-
- CLUSTER_SLEEP_0: cluster-sleep-0 {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x1010000>;
- entry-latency-us = <500>;
- exit-latency-us = <1000>;
- min-residency-us = <2500>;
- };
- };
-
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU1:cpu@1 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2:cpu@2 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU3:cpu@3 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x00000000 0x80000000 0 0x7F000000>,
- <0x00000008 0x80000000 0 0x80000000>;
- };
-
- gic: interrupt-controller@2c001000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0x2c001000 0 0x1000>,
- <0x0 0x2c002000 0 0x1000>,
- <0x0 0x2c004000 0 0x2000>,
- <0x0 0x2c006000 0 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
- <1 14 0xff01>,
- <1 11 0xff01>,
- <1 10 0xff01>;
- clock-frequency = <100000000>;
- };
-
- timer@2a810000 {
- compatible = "arm,armv7-timer-mem";
- reg = <0x0 0x2a810000 0x0 0x10000>;
- clock-frequency = <100000000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- frame@2a830000 {
- frame-number = <1>;
- interrupts = <0 26 4>;
- reg = <0x0 0x2a830000 0x0 0x10000>;
- };
- };
-
- pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <0 60 4>,
- <0 61 4>,
- <0 62 4>,
- <0 63 4>;
- };
-
- smb {
- compatible = "simple-bus";
-
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0 0x08000000 0x04000000>,
- <1 0 0 0x14000000 0x04000000>,
- <2 0 0 0x18000000 0x04000000>,
- <3 0 0 0x1c000000 0x04000000>,
- <4 0 0 0x0c000000 0x04000000>,
- <5 0 0 0x10000000 0x04000000>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 63>;
- interrupt-map = <0 0 0 &gic 0 0 4>,
- <0 0 1 &gic 0 1 4>,
- <0 0 2 &gic 0 2 4>,
- <0 0 3 &gic 0 3 4>,
- <0 0 4 &gic 0 4 4>,
- <0 0 5 &gic 0 5 4>,
- <0 0 6 &gic 0 6 4>,
- <0 0 7 &gic 0 7 4>,
- <0 0 8 &gic 0 8 4>,
- <0 0 9 &gic 0 9 4>,
- <0 0 10 &gic 0 10 4>,
- <0 0 11 &gic 0 11 4>,
- <0 0 12 &gic 0 12 4>,
- <0 0 13 &gic 0 13 4>,
- <0 0 14 &gic 0 14 4>,
- <0 0 15 &gic 0 15 4>,
- <0 0 16 &gic 0 16 4>,
- <0 0 17 &gic 0 17 4>,
- <0 0 18 &gic 0 18 4>,
- <0 0 19 &gic 0 19 4>,
- <0 0 20 &gic 0 20 4>,
- <0 0 21 &gic 0 21 4>,
- <0 0 22 &gic 0 22 4>,
- <0 0 23 &gic 0 23 4>,
- <0 0 24 &gic 0 24 4>,
- <0 0 25 &gic 0 25 4>,
- <0 0 26 &gic 0 26 4>,
- <0 0 27 &gic 0 27 4>,
- <0 0 28 &gic 0 28 4>,
- <0 0 29 &gic 0 29 4>,
- <0 0 30 &gic 0 30 4>,
- <0 0 31 &gic 0 31 4>,
- <0 0 32 &gic 0 32 4>,
- <0 0 33 &gic 0 33 4>,
- <0 0 34 &gic 0 34 4>,
- <0 0 35 &gic 0 35 4>,
- <0 0 36 &gic 0 36 4>,
- <0 0 37 &gic 0 37 4>,
- <0 0 38 &gic 0 38 4>,
- <0 0 39 &gic 0 39 4>,
- <0 0 40 &gic 0 40 4>,
- <0 0 41 &gic 0 41 4>,
- <0 0 42 &gic 0 42 4>;
-
- /include/ "fvp-foundation-motherboard.dtsi"
- };
-};
diff --git a/include/common/context_mgmt.h b/include/common/context_mgmt.h
index 11786a1..a76ecbe 100644
--- a/include/common/context_mgmt.h
+++ b/include/common/context_mgmt.h
@@ -55,7 +55,6 @@
unsigned int security_state);
void *cm_get_context(uint32_t security_state);
void cm_set_context(void *context, uint32_t security_state);
-inline void cm_set_next_context(void *context);
void cm_init_context(uint64_t mpidr,
const struct entry_point_info *ep) __deprecated;
void cm_init_my_context(const struct entry_point_info *ep);
@@ -80,7 +79,7 @@
* return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
* the required security state
******************************************************************************/
-inline void cm_set_next_context(void *context)
+static inline void cm_set_next_context(void *context)
{
#if DEBUG
uint64_t sp_mode;
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index 3085688..d8af7e1 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -139,8 +139,8 @@
unsigned int ns_device_access);
void tzc400_configure_region(unsigned int filters,
int region,
- uintptr_t region_base,
- uintptr_t region_top,
+ unsigned long long region_base,
+ unsigned long long region_top,
tzc_region_attributes_t sec_attr,
unsigned int ns_device_access);
void tzc400_set_action(tzc_action_t action);
@@ -157,8 +157,8 @@
static inline void tzc_configure_region(
unsigned int filters,
int region,
- uintptr_t region_base,
- uintptr_t region_top,
+ unsigned long long region_base,
+ unsigned long long region_top,
tzc_region_attributes_t sec_attr,
unsigned int ns_device_access) __deprecated;
static inline void tzc_set_action(tzc_action_t action) __deprecated;
@@ -180,8 +180,8 @@
static inline void tzc_configure_region(
unsigned int filters,
int region,
- uintptr_t region_base,
- uintptr_t region_top,
+ unsigned long long region_base,
+ unsigned long long region_top,
tzc_region_attributes_t sec_attr,
unsigned int ns_device_access)
{
diff --git a/include/drivers/arm/tzc_dmc500.h b/include/drivers/arm/tzc_dmc500.h
index 70f8ad2..e21818f 100644
--- a/include/drivers/arm/tzc_dmc500.h
+++ b/include/drivers/arm/tzc_dmc500.h
@@ -160,8 +160,8 @@
void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr,
unsigned int nsaid_permissions);
void tzc_dmc500_configure_region(int region_no,
- uintptr_t region_base,
- uintptr_t region_top,
+ unsigned long long region_base,
+ unsigned long long region_top,
tzc_region_attributes_t sec_attr,
unsigned int nsaid_permissions);
void tzc_dmc500_set_action(tzc_action_t action);
diff --git a/include/drivers/emmc.h b/include/drivers/emmc.h
new file mode 100644
index 0000000..61d4495
--- /dev/null
+++ b/include/drivers/emmc.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __EMMC_H__
+#define __EMMC_H__
+
+#include <stdint.h>
+
+#define EMMC_BLOCK_SIZE 512
+#define EMMC_BLOCK_MASK (EMMC_BLOCK_SIZE - 1)
+#define EMMC_BOOT_CLK_RATE (400 * 1000)
+
+#define EMMC_CMD0 0
+#define EMMC_CMD1 1
+#define EMMC_CMD2 2
+#define EMMC_CMD3 3
+#define EMMC_CMD6 6
+#define EMMC_CMD7 7
+#define EMMC_CMD8 8
+#define EMMC_CMD9 9
+#define EMMC_CMD12 12
+#define EMMC_CMD13 13
+#define EMMC_CMD17 17
+#define EMMC_CMD18 18
+#define EMMC_CMD24 24
+#define EMMC_CMD25 25
+#define EMMC_CMD35 35
+#define EMMC_CMD36 36
+#define EMMC_CMD38 38
+
+#define OCR_POWERUP (1 << 31)
+#define OCR_BYTE_MODE (0 << 29)
+#define OCR_SECTOR_MODE (2 << 29)
+#define OCR_ACCESS_MODE_MASK (3 << 29)
+#define OCR_VDD_MIN_2V7 (0x1ff << 15)
+#define OCR_VDD_MIN_2V0 (0x7f << 8)
+#define OCR_VDD_MIN_1V7 (1 << 7)
+
+#define EMMC_RESPONSE_R1 1
+#define EMMC_RESPONSE_R1B 1
+#define EMMC_RESPONSE_R2 4
+#define EMMC_RESPONSE_R3 1
+#define EMMC_RESPONSE_R4 1
+#define EMMC_RESPONSE_R5 1
+
+#define EMMC_FIX_RCA 6 /* > 1 */
+#define RCA_SHIFT_OFFSET 16
+
+#define CMD_EXTCSD_PARTITION_CONFIG 179
+#define CMD_EXTCSD_BUS_WIDTH 183
+#define CMD_EXTCSD_HS_TIMING 185
+
+#define PART_CFG_BOOT_PARTITION1_ENABLE (1 << 3)
+#define PART_CFG_PARTITION1_ACCESS (1 << 0)
+
+/* values in EXT CSD register */
+#define EMMC_BUS_WIDTH_1 0
+#define EMMC_BUS_WIDTH_4 1
+#define EMMC_BUS_WIDTH_8 2
+#define EMMC_BOOT_MODE_BACKWARD (0 << 3)
+#define EMMC_BOOT_MODE_HS_TIMING (1 << 3)
+#define EMMC_BOOT_MODE_DDR (2 << 3)
+
+#define EXTCSD_SET_CMD (0 << 24)
+#define EXTCSD_SET_BITS (1 << 24)
+#define EXTCSD_CLR_BITS (2 << 24)
+#define EXTCSD_WRITE_BYTES (3 << 24)
+#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
+#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
+
+#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
+#define STATUS_READY_FOR_DATA (1 << 8)
+#define STATUS_SWITCH_ERROR (1 << 7)
+#define EMMC_GET_STATE(x) (((x) >> 9) & 0xf)
+#define EMMC_STATE_IDLE 0
+#define EMMC_STATE_READY 1
+#define EMMC_STATE_IDENT 2
+#define EMMC_STATE_STBY 3
+#define EMMC_STATE_TRAN 4
+#define EMMC_STATE_DATA 5
+#define EMMC_STATE_RCV 6
+#define EMMC_STATE_PRG 7
+#define EMMC_STATE_DIS 8
+#define EMMC_STATE_BTST 9
+#define EMMC_STATE_SLP 10
+
+typedef struct emmc_cmd {
+ unsigned int cmd_idx;
+ unsigned int cmd_arg;
+ unsigned int resp_type;
+ unsigned int resp_data[4];
+} emmc_cmd_t;
+
+typedef struct emmc_ops {
+ void (*init)(void);
+ int (*send_cmd)(emmc_cmd_t *cmd);
+ int (*set_ios)(int clk, int width);
+ int (*prepare)(int lba, uintptr_t buf, size_t size);
+ int (*read)(int lba, uintptr_t buf, size_t size);
+ int (*write)(int lba, const uintptr_t buf, size_t size);
+} emmc_ops_t;
+
+typedef struct emmc_csd {
+ unsigned char not_used: 1;
+ unsigned char crc: 7;
+ unsigned char ecc: 2;
+ unsigned char file_format: 2;
+ unsigned char tmp_write_protect: 1;
+ unsigned char perm_write_protect: 1;
+ unsigned char copy: 1;
+ unsigned char file_format_grp: 1;
+
+ unsigned short reserved_1: 5;
+ unsigned short write_bl_partial: 1;
+ unsigned short write_bl_len: 4;
+ unsigned short r2w_factor: 3;
+ unsigned short default_ecc: 2;
+ unsigned short wp_grp_enable: 1;
+
+ unsigned int wp_grp_size: 5;
+ unsigned int erase_grp_mult: 5;
+ unsigned int erase_grp_size: 5;
+ unsigned int c_size_mult: 3;
+ unsigned int vdd_w_curr_max: 3;
+ unsigned int vdd_w_curr_min: 3;
+ unsigned int vdd_r_curr_max: 3;
+ unsigned int vdd_r_curr_min: 3;
+ unsigned int c_size_low: 2;
+
+ unsigned int c_size_high: 10;
+ unsigned int reserved_2: 2;
+ unsigned int dsr_imp: 1;
+ unsigned int read_blk_misalign: 1;
+ unsigned int write_blk_misalign: 1;
+ unsigned int read_bl_partial: 1;
+ unsigned int read_bl_len: 4;
+ unsigned int ccc: 12;
+
+ unsigned int tran_speed: 8;
+ unsigned int nsac: 8;
+ unsigned int taac: 8;
+ unsigned int reserved_3: 2;
+ unsigned int spec_vers: 4;
+ unsigned int csd_structure: 2;
+} emmc_csd_t;
+
+size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size);
+size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size);
+size_t emmc_erase_blocks(int lba, size_t size);
+size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
+size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
+size_t emmc_rpmb_erase_blocks(int lba, size_t size);
+void emmc_init(const emmc_ops_t *ops, int clk, int bus_width);
+
+#endif /* __EMMC_H__ */
diff --git a/include/drivers/io/io_block.h b/include/drivers/io/io_block.h
new file mode 100644
index 0000000..ebf43cd
--- /dev/null
+++ b/include/drivers/io/io_block.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IO_BLOCK_H__
+#define __IO_BLOCK_H__
+
+#include <io_storage.h>
+
+/* block devices ops */
+typedef struct io_block_ops {
+ size_t (*read)(int lba, uintptr_t buf, size_t size);
+ size_t (*write)(int lba, const uintptr_t buf, size_t size);
+} io_block_ops_t;
+
+typedef struct io_block_dev_spec {
+ io_block_spec_t buffer;
+ io_block_ops_t ops;
+ size_t block_size;
+} io_block_dev_spec_t;
+
+struct io_dev_connector;
+
+int register_io_dev_block(const struct io_dev_connector **dev_con);
+
+#endif /* __IO_BLOCK_H__ */
diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h
index 970ab2c..243f688 100644
--- a/include/drivers/io/io_storage.h
+++ b/include/drivers/io/io_storage.h
@@ -44,6 +44,7 @@
IO_TYPE_SEMIHOSTING,
IO_TYPE_MEMMAP,
IO_TYPE_FIRMWARE_IMAGE_PACKAGE,
+ IO_TYPE_BLOCK,
IO_TYPE_MAX
} io_type_t;
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index f9b8ed6..07bbd89 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -359,80 +359,6 @@
#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
-/* Miscellaneous MMU related constants */
-#define NUM_2MB_IN_GB (1 << 9)
-#define NUM_4K_IN_2MB (1 << 9)
-#define NUM_GB_IN_4GB (1 << 2)
-
-#define TWO_MB_SHIFT 21
-#define ONE_GB_SHIFT 30
-#define FOUR_KB_SHIFT 12
-
-#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
-#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
-#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
-
-#define INVALID_DESC 0x0
-#define BLOCK_DESC 0x1
-#define TABLE_DESC 0x3
-
-#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
-#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
-#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
-
-#define LEVEL1 1
-#define LEVEL2 2
-#define LEVEL3 3
-
-#define XN (1ull << 2)
-#define PXN (1ull << 1)
-#define CONT_HINT (1ull << 0)
-
-#define UPPER_ATTRS(x) (x & 0x7) << 52
-#define NON_GLOBAL (1 << 9)
-#define ACCESS_FLAG (1 << 8)
-#define NSH (0x0 << 6)
-#define OSH (0x2 << 6)
-#define ISH (0x3 << 6)
-
-#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
-#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT)
-#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
-#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
-
-#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */
-#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT)
-
-#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT
-#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
-
-/* Values for number of entries in each MMU translation table */
-#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
-#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
-#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
-
-/* Values to convert a memory address to an index into a translation table */
-#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
-#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
-#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
-
-/*
- * AP[1] bit is ignored by hardware and is
- * treated as if it is One in EL2/EL3
- */
-#define AP_RO (0x1 << 5)
-#define AP_RW (0x0 << 5)
-
-#define NS (0x1 << 3)
-#define ATTR_NON_CACHEABLE_INDEX 0x2
-#define ATTR_DEVICE_INDEX 0x1
-#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
-#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
-#define ATTR_NON_CACHEABLE (0x44)
-#define ATTR_DEVICE (0x4)
-#define ATTR_IWBWA_OWBWA_NTR (0xff)
-#define MAIR_ATTR_SET(attr, index) (attr << (index << 3))
-
/* Exception Syndrome register bits and bobs */
#define ESR_EC_SHIFT 26
#define ESR_EC_MASK 0x3f
diff --git a/include/lib/aarch64/xlat_tables.h b/include/lib/aarch64/xlat_tables.h
deleted file mode 100644
index d21100e..0000000
--- a/include/lib/aarch64/xlat_tables.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __XLAT_TABLES_H__
-#define __XLAT_TABLES_H__
-
-
-/*
- * Flags to override default values used to program system registers while
- * enabling the MMU.
- */
-#define DISABLE_DCACHE (1 << 0)
-
-#ifndef __ASSEMBLY__
-#include <stdint.h>
-
-/* Helper macro to define entries for mmap_region_t. It creates
- * identity mappings for each region.
- */
-#define MAP_REGION_FLAT(adr, sz, attr) MAP_REGION(adr, adr, sz, attr)
-
-/* Helper macro to define entries for mmap_region_t. It allows to
- * re-map address mappings from 'pa' to 'va' for each region.
- */
-#define MAP_REGION(pa, va, sz, attr) {(pa), (va), (sz), (attr)}
-
-/*
- * Shifts and masks to access fields of an mmap_attr_t
- */
-#define MT_TYPE_MASK 0x7
-#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK)
-/* Access permissions (RO/RW) */
-#define MT_PERM_SHIFT 3
-/* Security state (SECURE/NS) */
-#define MT_SEC_SHIFT 4
-
-/*
- * Memory mapping attributes
- */
-typedef enum {
- /*
- * Memory types supported.
- * These are organised so that, going down the list, the memory types
- * are getting weaker; conversely going up the list the memory types are
- * getting stronger.
- */
- MT_DEVICE,
- MT_NON_CACHEABLE,
- MT_MEMORY,
- /* Values up to 7 are reserved to add new memory types in the future */
-
- /*
- * The following values are organised so that a clear bit gives a more
- * restrictive mapping than a set bit, that way a bitwise-and of two
- * sets of attributes will never give an attribute which has greater
- * access rights than any of the original attributes.
- */
- MT_RO = 0 << MT_PERM_SHIFT,
- MT_RW = 1 << MT_PERM_SHIFT,
-
- MT_SECURE = 0 << MT_SEC_SHIFT,
- MT_NS = 1 << MT_SEC_SHIFT,
-} mmap_attr_t;
-
-/*
- * Structure for specifying a single region of memory.
- */
-typedef struct mmap_region {
- unsigned long base_pa;
- unsigned long base_va;
- unsigned long size;
- mmap_attr_t attr;
-} mmap_region_t;
-
-void mmap_add_region(unsigned long base_pa, unsigned long base_va,
- unsigned long size, unsigned attr);
-void mmap_add(const mmap_region_t *mm);
-
-void init_xlat_tables(void);
-
-void enable_mmu_el1(uint32_t flags);
-void enable_mmu_el3(uint32_t flags);
-
-#endif /*__ASSEMBLY__*/
-#endif /* __XLAT_TABLES_H__ */
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index 8a53891..6b8157e 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -96,7 +96,7 @@
#endif /* __USE_COHERENT_MEM__ */
-inline void bakery_lock_init(bakery_lock_t *bakery) {}
+static inline void bakery_lock_init(bakery_lock_t *bakery) {}
void bakery_lock_get(bakery_lock_t *bakery);
void bakery_lock_release(bakery_lock_t *bakery);
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index c512129..ac4ae57 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -61,9 +61,15 @@
******************************************************************************/
#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
+#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59)
+#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
#define CPUACTLR_DIS_OVERREAD (1 << 52)
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
#define CPUACTLR_DCC_AS_DCCI (1 << 44)
+#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38)
+#define CPUACTLR_DIS_STREAMING (3 << 27)
+#define CPUACTLR_DIS_L1_STREAMING (3 << 25)
+#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
/*******************************************************************************
* L2 Control register specific definitions.
diff --git a/include/lib/xlat_tables.h b/include/lib/xlat_tables.h
new file mode 100644
index 0000000..abe46ed
--- /dev/null
+++ b/include/lib/xlat_tables.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __XLAT_TABLES_H__
+#define __XLAT_TABLES_H__
+
+/* Miscellaneous MMU related constants */
+#define NUM_2MB_IN_GB (1 << 9)
+#define NUM_4K_IN_2MB (1 << 9)
+#define NUM_GB_IN_4GB (1 << 2)
+
+#define TWO_MB_SHIFT 21
+#define ONE_GB_SHIFT 30
+#define FOUR_KB_SHIFT 12
+
+#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
+#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
+#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
+
+#define INVALID_DESC 0x0
+#define BLOCK_DESC 0x1
+#define TABLE_DESC 0x3
+
+#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
+#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
+#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
+
+#define LEVEL1 1
+#define LEVEL2 2
+#define LEVEL3 3
+
+#define XN (1ull << 2)
+#define PXN (1ull << 1)
+#define CONT_HINT (1ull << 0)
+
+#define UPPER_ATTRS(x) (x & 0x7) << 52
+#define NON_GLOBAL (1 << 9)
+#define ACCESS_FLAG (1 << 8)
+#define NSH (0x0 << 6)
+#define OSH (0x2 << 6)
+#define ISH (0x3 << 6)
+
+#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
+#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT)
+#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
+#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
+
+#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */
+#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT)
+
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
+
+/* Values for number of entries in each MMU translation table */
+#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
+#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
+
+/* Values to convert a memory address to an index into a translation table */
+#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+/*
+ * AP[1] bit is ignored by hardware and is
+ * treated as if it is One in EL2/EL3
+ */
+#define AP_RO (0x1 << 5)
+#define AP_RW (0x0 << 5)
+
+#define NS (0x1 << 3)
+#define ATTR_NON_CACHEABLE_INDEX 0x2
+#define ATTR_DEVICE_INDEX 0x1
+#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
+#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
+#define ATTR_NON_CACHEABLE (0x44)
+#define ATTR_DEVICE (0x4)
+#define ATTR_IWBWA_OWBWA_NTR (0xff)
+#define MAIR_ATTR_SET(attr, index) (attr << (index << 3))
+
+/*
+ * Flags to override default values used to program system registers while
+ * enabling the MMU.
+ */
+#define DISABLE_DCACHE (1 << 0)
+
+#ifndef __ASSEMBLY__
+#include <stddef.h>
+#include <stdint.h>
+
+/* Helper macro to define entries for mmap_region_t. It creates
+ * identity mappings for each region.
+ */
+#define MAP_REGION_FLAT(adr, sz, attr) MAP_REGION(adr, adr, sz, attr)
+
+/* Helper macro to define entries for mmap_region_t. It allows to
+ * re-map address mappings from 'pa' to 'va' for each region.
+ */
+#define MAP_REGION(pa, va, sz, attr) {(pa), (va), (sz), (attr)}
+
+/*
+ * Shifts and masks to access fields of an mmap_attr_t
+ */
+#define MT_TYPE_MASK 0x7
+#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK)
+/* Access permissions (RO/RW) */
+#define MT_PERM_SHIFT 3
+/* Security state (SECURE/NS) */
+#define MT_SEC_SHIFT 4
+
+/*
+ * Memory mapping attributes
+ */
+typedef enum {
+ /*
+ * Memory types supported.
+ * These are organised so that, going down the list, the memory types
+ * are getting weaker; conversely going up the list the memory types are
+ * getting stronger.
+ */
+ MT_DEVICE,
+ MT_NON_CACHEABLE,
+ MT_MEMORY,
+ /* Values up to 7 are reserved to add new memory types in the future */
+
+ /*
+ * The following values are organised so that a clear bit gives a more
+ * restrictive mapping than a set bit, that way a bitwise-and of two
+ * sets of attributes will never give an attribute which has greater
+ * access rights than any of the original attributes.
+ */
+ MT_RO = 0 << MT_PERM_SHIFT,
+ MT_RW = 1 << MT_PERM_SHIFT,
+
+ MT_SECURE = 0 << MT_SEC_SHIFT,
+ MT_NS = 1 << MT_SEC_SHIFT,
+} mmap_attr_t;
+
+/*
+ * Structure for specifying a single region of memory.
+ */
+typedef struct mmap_region {
+ unsigned long long base_pa;
+ uintptr_t base_va;
+ size_t size;
+ mmap_attr_t attr;
+} mmap_region_t;
+
+/* Generic translation table APIs */
+void init_xlat_tables(void);
+void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
+ size_t size, unsigned int attr);
+void mmap_add(const mmap_region_t *mm);
+
+/* AArch64 specific translation table APIs */
+void enable_mmu_el1(unsigned int flags);
+void enable_mmu_el3(unsigned int flags);
+
+#endif /*__ASSEMBLY__*/
+#endif /* __XLAT_TABLES_H__ */
diff --git a/include/plat/arm/common/aarch64/cci_macros.S b/include/plat/arm/common/aarch64/cci_macros.S
index 40f9d7e..902fb15 100644
--- a/include/plat/arm/common/aarch64/cci_macros.S
+++ b/include/plat/arm/common/aarch64/cci_macros.S
@@ -44,7 +44,7 @@
* Clobbers: x0 - x9, sp
* ------------------------------------------------
*/
- .macro plat_print_interconnect_regs
+ .macro print_cci_regs
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
diff --git a/include/plat/arm/css/common/aarch64/css_macros.S b/include/plat/arm/css/common/aarch64/css_macros.S
index 9124fdc..518867b 100644
--- a/include/plat/arm/css/common/aarch64/css_macros.S
+++ b/include/plat/arm/css/common/aarch64/css_macros.S
@@ -40,7 +40,7 @@
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
- .macro plat_print_gic_regs
+ .macro css_print_gic_regs
mov_imm x16, PLAT_ARM_GICD_BASE
mov_imm x17, PLAT_ARM_GICC_BASE
arm_print_gic_regs
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 5857501..42260e9 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -56,7 +56,7 @@
/*******************************************************************************
* Mandatory common functions
******************************************************************************/
-uint64_t plat_get_syscnt_freq(void);
+unsigned long long plat_get_syscnt_freq(void);
int plat_get_image_source(unsigned int image_id,
uintptr_t *dev_handle,
uintptr_t *image_spec);
diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c
index 269743f..b140f29 100644
--- a/lib/aarch64/xlat_tables.c
+++ b/lib/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,366 +28,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <arch.h>
-#include <arch_helpers.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <cassert.h>
-#include <debug.h>
-#include <platform_def.h>
-#include <string.h>
-#include <xlat_tables.h>
-
-#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
-#define LVL0_SPACER ""
-#define LVL1_SPACER " "
-#define LVL2_SPACER " "
-#define LVL3_SPACER " "
-#define get_level_spacer(level) \
- (((level) == 0) ? LVL0_SPACER : \
- (((level) == 1) ? LVL1_SPACER : \
- (((level) == 2) ? LVL2_SPACER : LVL3_SPACER)))
-#define debug_print(...) tf_printf(__VA_ARGS__)
-#else
-#define debug_print(...) ((void)0)
-#endif
-
-#define IS_POWER_OF_TWO(x) (((x) & ((x) - 1)) == 0)
-
-/*
- * The virtual address space size must be a power of two (as set in TCR.T0SZ).
- * As we start the initial lookup at level 1, it must also be between 2 GB and
- * 512 GB (with the virtual address size therefore 31 to 39 bits). See section
- * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.i) for more
- * information.
- */
-CASSERT(ADDR_SPACE_SIZE >= (1ull << 31) && ADDR_SPACE_SIZE <= (1ull << 39) &&
- IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size);
-
-#define UNSET_DESC ~0ul
-
-#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
-
-static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
-__aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
-
-static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
-__aligned(XLAT_TABLE_SIZE) __section("xlat_table");
-
-static unsigned next_xlat;
-static unsigned long max_pa;
-static unsigned long max_va;
-static unsigned long tcr_ps_bits;
-
/*
- * Array of all memory regions stored in order of ascending base address.
- * The list is terminated by the first entry with size == 0.
+ * This file is deprecated and is retained here only for compatibility.
+ * The xlat_tables library can be found in `lib/xlat_tables` directory.
*/
-static mmap_region_t mmap[MAX_MMAP_REGIONS + 1];
-
-
-static void print_mmap(void)
-{
-#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
- debug_print("mmap:\n");
- mmap_region_t *mm = mmap;
- while (mm->size) {
- debug_print(" VA:0x%lx PA:0x%lx size:0x%lx attr:0x%x\n",
- mm->base_va, mm->base_pa, mm->size, mm->attr);
- ++mm;
- };
- debug_print("\n");
+#if !ERROR_DEPRECATED
+#include "../xlat_tables/xlat_tables_common.c"
+#include "../xlat_tables/aarch64/xlat_tables.c"
#endif
-}
-
-void mmap_add_region(unsigned long base_pa, unsigned long base_va,
- unsigned long size, unsigned attr)
-{
- mmap_region_t *mm = mmap;
- mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1;
- unsigned long pa_end = base_pa + size - 1;
- unsigned long va_end = base_va + size - 1;
-
- assert(IS_PAGE_ALIGNED(base_pa));
- assert(IS_PAGE_ALIGNED(base_va));
- assert(IS_PAGE_ALIGNED(size));
-
- if (!size)
- return;
-
- /* Find correct place in mmap to insert new region */
- while (mm->base_va < base_va && mm->size)
- ++mm;
-
- /* Make room for new region by moving other regions up by one place */
- memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
-
- /* Check we haven't lost the empty sentinal from the end of the array */
- assert(mm_last->size == 0);
-
- mm->base_pa = base_pa;
- mm->base_va = base_va;
- mm->size = size;
- mm->attr = attr;
-
- if (pa_end > max_pa)
- max_pa = pa_end;
- if (va_end > max_va)
- max_va = va_end;
-}
-
-void mmap_add(const mmap_region_t *mm)
-{
- while (mm->size) {
- mmap_add_region(mm->base_pa, mm->base_va, mm->size, mm->attr);
- ++mm;
- }
-}
-
-static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa,
- unsigned level)
-{
- unsigned long desc = addr_pa;
- int mem_type;
-
- desc |= level == 3 ? TABLE_DESC : BLOCK_DESC;
-
- desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0;
-
- desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
-
- desc |= LOWER_ATTRS(ACCESS_FLAG);
-
- mem_type = MT_TYPE(attr);
- if (mem_type == MT_MEMORY) {
- desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH);
- if (attr & MT_RW)
- desc |= UPPER_ATTRS(XN);
- } else if (mem_type == MT_NON_CACHEABLE) {
- desc |= LOWER_ATTRS(ATTR_NON_CACHEABLE_INDEX | OSH);
- if (attr & MT_RW)
- desc |= UPPER_ATTRS(XN);
- } else {
- assert(mem_type == MT_DEVICE);
- desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH);
- desc |= UPPER_ATTRS(XN);
- }
-
- debug_print((mem_type == MT_MEMORY) ? "MEM" :
- ((mem_type == MT_NON_CACHEABLE) ? "NC" : "DEV"));
- debug_print(attr & MT_RW ? "-RW" : "-RO");
- debug_print(attr & MT_NS ? "-NS" : "-S");
-
- return desc;
-}
-
-static int mmap_region_attr(mmap_region_t *mm, unsigned long base_va,
- unsigned long size)
-{
- int attr = mm->attr;
- int old_mem_type, new_mem_type;
-
- for (;;) {
- ++mm;
-
- if (!mm->size)
- return attr; /* Reached end of list */
-
- if (mm->base_va >= base_va + size)
- return attr; /* Next region is after area so end */
-
- if (mm->base_va + mm->size <= base_va)
- continue; /* Next region has already been overtaken */
-
- if ((mm->attr & attr) == attr)
- continue; /* Region doesn't override attribs so skip */
-
- /*
- * Update memory mapping attributes in 2 steps:
- * 1) Update access permissions and security state flags
- * 2) Update memory type.
- *
- * See xlat_tables.h for details about the attributes priority
- * system and the rules dictating whether attributes should be
- * updated.
- */
- old_mem_type = MT_TYPE(attr);
- new_mem_type = MT_TYPE(mm->attr);
- attr &= mm->attr;
- if (new_mem_type < old_mem_type)
- attr = (attr & ~MT_TYPE_MASK) | new_mem_type;
-
- if (mm->base_va > base_va ||
- mm->base_va + mm->size < base_va + size)
- return -1; /* Region doesn't fully cover our area */
- }
-}
-
-static mmap_region_t *init_xlation_table(mmap_region_t *mm,
- unsigned long base_va,
- unsigned long *table, unsigned level)
-{
- unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) *
- XLAT_TABLE_ENTRIES_SHIFT;
- unsigned level_size = 1 << level_size_shift;
- unsigned long level_index_mask = XLAT_TABLE_ENTRIES_MASK << level_size_shift;
-
- assert(level <= 3);
-
- debug_print("New xlat table:\n");
-
- do {
- unsigned long desc = UNSET_DESC;
-
- if (!mm->size) {
- /* Done mapping regions; finish zeroing the table */
- desc = INVALID_DESC;
- } else if (mm->base_va + mm->size <= base_va) {
- /* Area now after the region so skip it */
- ++mm;
- continue;
- }
-
- debug_print("%s VA:0x%lx size:0x%x ", get_level_spacer(level),
- base_va, level_size);
-
- if (mm->base_va >= base_va + level_size) {
- /* Next region is after area so nothing to map yet */
- desc = INVALID_DESC;
- } else if (mm->base_va <= base_va && mm->base_va + mm->size >=
- base_va + level_size) {
- /* Next region covers all of area */
- int attr = mmap_region_attr(mm, base_va, level_size);
- if (attr >= 0)
- desc = mmap_desc(attr,
- base_va - mm->base_va + mm->base_pa,
- level);
- }
- /* else Next region only partially covers area, so need */
-
- if (desc == UNSET_DESC) {
- /* Area not covered by a region so need finer table */
- unsigned long *new_table = xlat_tables[next_xlat++];
- assert(next_xlat <= MAX_XLAT_TABLES);
- desc = TABLE_DESC | (unsigned long)new_table;
-
- /* Recurse to fill in new table */
- mm = init_xlation_table(mm, base_va,
- new_table, level+1);
- }
-
- debug_print("\n");
-
- *table++ = desc;
- base_va += level_size;
- } while ((base_va & level_index_mask) && (base_va < ADDR_SPACE_SIZE));
-
- return mm;
-}
-
-static unsigned int calc_physical_addr_size_bits(unsigned long max_addr)
-{
- /* Physical address can't exceed 48 bits */
- assert((max_addr & ADDR_MASK_48_TO_63) == 0);
-
- /* 48 bits address */
- if (max_addr & ADDR_MASK_44_TO_47)
- return TCR_PS_BITS_256TB;
-
- /* 44 bits address */
- if (max_addr & ADDR_MASK_42_TO_43)
- return TCR_PS_BITS_16TB;
-
- /* 42 bits address */
- if (max_addr & ADDR_MASK_40_TO_41)
- return TCR_PS_BITS_4TB;
-
- /* 40 bits address */
- if (max_addr & ADDR_MASK_36_TO_39)
- return TCR_PS_BITS_1TB;
-
- /* 36 bits address */
- if (max_addr & ADDR_MASK_32_TO_35)
- return TCR_PS_BITS_64GB;
-
- return TCR_PS_BITS_4GB;
-}
-
-void init_xlat_tables(void)
-{
- print_mmap();
- init_xlation_table(mmap, 0, l1_xlation_table, 1);
- tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
- assert(max_va < ADDR_SPACE_SIZE);
-}
-
-/*******************************************************************************
- * Macro generating the code for the function enabling the MMU in the given
- * exception level, assuming that the pagetables have already been created.
- *
- * _el: Exception level at which the function will run
- * _tcr_extra: Extra bits to set in the TCR register. This mask will
- * be OR'ed with the default TCR value.
- * _tlbi_fct: Function to invalidate the TLBs at the current
- * exception level
- ******************************************************************************/
-#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
- void enable_mmu_el##_el(uint32_t flags) \
- { \
- uint64_t mair, tcr, ttbr; \
- uint32_t sctlr; \
- \
- assert(IS_IN_EL(_el)); \
- assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
- \
- /* Set attributes in the right indices of the MAIR */ \
- mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
- mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
- ATTR_IWBWA_OWBWA_NTR_INDEX); \
- mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
- ATTR_NON_CACHEABLE_INDEX); \
- write_mair_el##_el(mair); \
- \
- /* Invalidate TLBs at the current exception level */ \
- _tlbi_fct(); \
- \
- /* Set TCR bits as well. */ \
- /* Inner & outer WBWA & shareable + T0SZ = 32 */ \
- tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
- TCR_RGN_INNER_WBA | \
- (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \
- tcr |= _tcr_extra; \
- write_tcr_el##_el(tcr); \
- \
- /* Set TTBR bits as well */ \
- ttbr = (uint64_t) l1_xlation_table; \
- write_ttbr0_el##_el(ttbr); \
- \
- /* Ensure all translation table writes have drained */ \
- /* into memory, the TLB invalidation is complete, */ \
- /* and translation register writes are committed */ \
- /* before enabling the MMU */ \
- dsb(); \
- isb(); \
- \
- sctlr = read_sctlr_el##_el(); \
- sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
- \
- if (flags & DISABLE_DCACHE) \
- sctlr &= ~SCTLR_C_BIT; \
- else \
- sctlr |= SCTLR_C_BIT; \
- \
- write_sctlr_el##_el(sctlr); \
- \
- /* Ensure the MMU enable takes effect immediately */ \
- isb(); \
- }
-
-/* Define EL1 and EL3 variants of the function enabling the MMU */
-DEFINE_ENABLE_MMU_EL(1,
- (tcr_ps_bits << TCR_EL1_IPS_SHIFT),
- tlbivmalle1)
-DEFINE_ENABLE_MMU_EL(3,
- TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
- tlbialle3)
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 4c0b8ce..60929a0 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -167,6 +167,142 @@
ret
endfunc a57_disable_ldnp_overread
+ /* ---------------------------------------------------
+ * Errata Workaround for Cortex A57 Errata #826974.
+ * This applies only to revision <= r1p1 of Cortex A57.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Clobbers : x0 - x5
+ * ---------------------------------------------------
+ */
+func errata_a57_826974_wa
+ /*
+ * Compare x0 against revision r1p1
+ */
+ cmp x0, #0x11
+ b.ls apply_826974
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ b print_revision_warning
+#else
+ ret
+#endif
+apply_826974:
+ mrs x1, CPUACTLR_EL1
+ orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB
+ msr CPUACTLR_EL1, x1
+ ret
+endfunc errata_a57_826974_wa
+
+ /* ---------------------------------------------------
+ * Errata Workaround for Cortex A57 Errata #826977.
+ * This applies only to revision <= r1p1 of Cortex A57.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Clobbers : x0 - x5
+ * ---------------------------------------------------
+ */
+func errata_a57_826977_wa
+ /*
+ * Compare x0 against revision r1p1
+ */
+ cmp x0, #0x11
+ b.ls apply_826977
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ b print_revision_warning
+#else
+ ret
+#endif
+apply_826977:
+ mrs x1, CPUACTLR_EL1
+ orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE
+ msr CPUACTLR_EL1, x1
+ ret
+endfunc errata_a57_826977_wa
+
+ /* ---------------------------------------------------
+ * Errata Workaround for Cortex A57 Errata #828024.
+ * This applies only to revision <= r1p1 of Cortex A57.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Clobbers : x0 - x5
+ * ---------------------------------------------------
+ */
+func errata_a57_828024_wa
+ /*
+ * Compare x0 against revision r1p1
+ */
+ cmp x0, #0x11
+ b.ls apply_828024
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ b print_revision_warning
+#else
+ ret
+#endif
+apply_828024:
+ mrs x1, CPUACTLR_EL1
+ /*
+ * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
+ * instructions here because the resulting bitmask doesn't fit in a
+ * 16-bit value so it cannot be encoded in a single instruction.
+ */
+ orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA
+ orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING)
+ msr CPUACTLR_EL1, x1
+ ret
+endfunc errata_a57_828024_wa
+
+ /* ---------------------------------------------------
+ * Errata Workaround for Cortex A57 Errata #829520.
+ * This applies only to revision <= r1p2 of Cortex A57.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Clobbers : x0 - x5
+ * ---------------------------------------------------
+ */
+func errata_a57_829520_wa
+ /*
+ * Compare x0 against revision r1p2
+ */
+ cmp x0, #0x12
+ b.ls apply_829520
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ b print_revision_warning
+#else
+ ret
+#endif
+apply_829520:
+ mrs x1, CPUACTLR_EL1
+ orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR
+ msr CPUACTLR_EL1, x1
+ ret
+endfunc errata_a57_829520_wa
+
+ /* ---------------------------------------------------
+ * Errata Workaround for Cortex A57 Errata #833471.
+ * This applies only to revision <= r1p2 of Cortex A57.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Clobbers : x0 - x5
+ * ---------------------------------------------------
+ */
+func errata_a57_833471_wa
+ /*
+ * Compare x0 against revision r1p2
+ */
+ cmp x0, #0x12
+ b.ls apply_833471
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ b print_revision_warning
+#else
+ ret
+#endif
+apply_833471:
+ mrs x1, CPUACTLR_EL1
+ orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH
+ msr CPUACTLR_EL1, x1
+ ret
+endfunc errata_a57_833471_wa
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A57.
* Clobbers: x0-x5, x15, x19, x30
@@ -200,6 +336,31 @@
bl a57_disable_ldnp_overread
#endif
+#if ERRATA_A57_826974
+ mov x0, x15
+ bl errata_a57_826974_wa
+#endif
+
+#if ERRATA_A57_826977
+ mov x0, x15
+ bl errata_a57_826977_wa
+#endif
+
+#if ERRATA_A57_828024
+ mov x0, x15
+ bl errata_a57_828024_wa
+#endif
+
+#if ERRATA_A57_829520
+ mov x0, x15
+ bl errata_a57_829520_wa
+#endif
+
+#if ERRATA_A57_833471
+ mov x0, x15
+ bl errata_a57_833471_wa
+#endif
+
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index a3a08e1..0659bff 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -53,26 +53,47 @@
$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT))
-# CPU Errata Build flags. These should be enabled by the
-# platform if the errata needs to be applied.
+# CPU Errata Build flags.
+# These should be enabled by the platform if the erratum workaround needs to be
+# applied.
-# Flag to apply errata 826319 during reset. This errata applies only to
-# revision <= r0p2 of the Cortex A53 cpu.
+# Flag to apply erratum 826319 workaround during reset. This erratum applies
+# only to revision <= r0p2 of the Cortex A53 cpu.
ERRATA_A53_826319 ?=0
-# Flag to apply errata 836870 during reset. This errata applies only to
-# revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this
-# errata is enabled by default.
+# Flag to apply erratum 836870 workaround during reset. This erratum applies
+# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this
+# erratum workaround is enabled by default.
ERRATA_A53_836870 ?=0
-# Flag to apply errata 806969 during reset. This errata applies only to
-# revision r0p0 of the Cortex A57 cpu.
+# Flag to apply erratum 806969 workaround during reset. This erratum applies
+# only to revision r0p0 of the Cortex A57 cpu.
ERRATA_A57_806969 ?=0
-# Flag to apply errata 813420 during reset. This errata applies only to
-# revision r0p0 of the Cortex A57 cpu.
+# Flag to apply erratum 813420 workaround during reset. This erratum applies
+# only to revision r0p0 of the Cortex A57 cpu.
ERRATA_A57_813420 ?=0
+# Flag to apply erratum 826974 workaround during reset. This erratum applies
+# only to revision <= r1p1 of the Cortex A57 cpu.
+ERRATA_A57_826974 ?=0
+
+# Flag to apply erratum 826977 workaround during reset. This erratum applies
+# only to revision <= r1p1 of the Cortex A57 cpu.
+ERRATA_A57_826977 ?=0
+
+# Flag to apply erratum 828024 workaround during reset. This erratum applies
+# only to revision <= r1p1 of the Cortex A57 cpu.
+ERRATA_A57_828024 ?=0
+
+# Flag to apply erratum 829520 workaround during reset. This erratum applies
+# only to revision <= r1p2 of the Cortex A57 cpu.
+ERRATA_A57_829520 ?=0
+
+# Flag to apply erratum 833471 workaround during reset. This erratum applies
+# only to revision <= r1p2 of the Cortex A57 cpu.
+ERRATA_A57_833471 ?=0
+
# Process ERRATA_A53_826319 flag
$(eval $(call assert_boolean,ERRATA_A53_826319))
$(eval $(call add_define,ERRATA_A53_826319))
@@ -88,3 +109,23 @@
# Process ERRATA_A57_813420 flag
$(eval $(call assert_boolean,ERRATA_A57_813420))
$(eval $(call add_define,ERRATA_A57_813420))
+
+# Process ERRATA_A57_826974 flag
+$(eval $(call assert_boolean,ERRATA_A57_826974))
+$(eval $(call add_define,ERRATA_A57_826974))
+
+# Process ERRATA_A57_826977 flag
+$(eval $(call assert_boolean,ERRATA_A57_826977))
+$(eval $(call add_define,ERRATA_A57_826977))
+
+# Process ERRATA_A57_828024 flag
+$(eval $(call assert_boolean,ERRATA_A57_828024))
+$(eval $(call add_define,ERRATA_A57_828024))
+
+# Process ERRATA_A57_829520 flag
+$(eval $(call assert_boolean,ERRATA_A57_829520))
+$(eval $(call add_define,ERRATA_A57_829520))
+
+# Process ERRATA_A57_833471 flag
+$(eval $(call assert_boolean,ERRATA_A57_833471))
+$(eval $(call add_define,ERRATA_A57_833471))
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
new file mode 100644
index 0000000..051e46a
--- /dev/null
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <cassert.h>
+#include <platform_def.h>
+#include <xlat_tables.h>
+#include "../xlat_tables_private.h"
+
+#define IS_POWER_OF_TWO(x) (((x) & ((x) - 1)) == 0)
+
+/*
+ * The virtual address space size must be a power of two (as set in TCR.T0SZ).
+ * As we start the initial lookup at level 1, it must also be between 2 GB and
+ * 512 GB (with the virtual address size therefore 31 to 39 bits). See section
+ * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.i) for more
+ * information.
+ */
+CASSERT(ADDR_SPACE_SIZE >= (1ull << 31) && ADDR_SPACE_SIZE <= (1ull << 39) &&
+ IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size);
+
+#define UNSET_DESC ~0ul
+#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
+
+static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
+ __aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
+
+static unsigned long long tcr_ps_bits;
+
+static unsigned long long calc_physical_addr_size_bits(
+ unsigned long long max_addr)
+{
+ /* Physical address can't exceed 48 bits */
+ assert((max_addr & ADDR_MASK_48_TO_63) == 0);
+
+ /* 48 bits address */
+ if (max_addr & ADDR_MASK_44_TO_47)
+ return TCR_PS_BITS_256TB;
+
+ /* 44 bits address */
+ if (max_addr & ADDR_MASK_42_TO_43)
+ return TCR_PS_BITS_16TB;
+
+ /* 42 bits address */
+ if (max_addr & ADDR_MASK_40_TO_41)
+ return TCR_PS_BITS_4TB;
+
+ /* 40 bits address */
+ if (max_addr & ADDR_MASK_36_TO_39)
+ return TCR_PS_BITS_1TB;
+
+ /* 36 bits address */
+ if (max_addr & ADDR_MASK_32_TO_35)
+ return TCR_PS_BITS_64GB;
+
+ return TCR_PS_BITS_4GB;
+}
+
+void init_xlat_tables(void)
+{
+ unsigned long long max_pa;
+ uintptr_t max_va;
+ print_mmap();
+ init_xlation_table(0, l1_xlation_table, 1, &max_va, &max_pa);
+ tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
+ assert(max_va < ADDR_SPACE_SIZE);
+}
+
+/*******************************************************************************
+ * Macro generating the code for the function enabling the MMU in the given
+ * exception level, assuming that the pagetables have already been created.
+ *
+ * _el: Exception level at which the function will run
+ * _tcr_extra: Extra bits to set in the TCR register. This mask will
+ * be OR'ed with the default TCR value.
+ * _tlbi_fct: Function to invalidate the TLBs at the current
+ * exception level
+ ******************************************************************************/
+#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
+ void enable_mmu_el##_el(unsigned int flags) \
+ { \
+ uint64_t mair, tcr, ttbr; \
+ uint32_t sctlr; \
+ \
+ assert(IS_IN_EL(_el)); \
+ assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
+ \
+ /* Set attributes in the right indices of the MAIR */ \
+ mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
+ mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
+ ATTR_IWBWA_OWBWA_NTR_INDEX); \
+ mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
+ ATTR_NON_CACHEABLE_INDEX); \
+ write_mair_el##_el(mair); \
+ \
+ /* Invalidate TLBs at the current exception level */ \
+ _tlbi_fct(); \
+ \
+ /* Set TCR bits as well. */ \
+ /* Inner & outer WBWA & shareable + T0SZ = 32 */ \
+ tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
+ TCR_RGN_INNER_WBA | \
+ (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \
+ tcr |= _tcr_extra; \
+ write_tcr_el##_el(tcr); \
+ \
+ /* Set TTBR bits as well */ \
+ ttbr = (uint64_t) l1_xlation_table; \
+ write_ttbr0_el##_el(ttbr); \
+ \
+ /* Ensure all translation table writes have drained */ \
+ /* into memory, the TLB invalidation is complete, */ \
+ /* and translation register writes are committed */ \
+ /* before enabling the MMU */ \
+ dsb(); \
+ isb(); \
+ \
+ sctlr = read_sctlr_el##_el(); \
+ sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
+ \
+ if (flags & DISABLE_DCACHE) \
+ sctlr &= ~SCTLR_C_BIT; \
+ else \
+ sctlr |= SCTLR_C_BIT; \
+ \
+ write_sctlr_el##_el(sctlr); \
+ \
+ /* Ensure the MMU enable takes effect immediately */ \
+ isb(); \
+ }
+
+/* Define EL1 and EL3 variants of the function enabling the MMU */
+DEFINE_ENABLE_MMU_EL(1,
+ (tcr_ps_bits << TCR_EL1_IPS_SHIFT),
+ tlbivmalle1)
+DEFINE_ENABLE_MMU_EL(3,
+ TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
+ tlbialle3)
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c
new file mode 100644
index 0000000..fd10084
--- /dev/null
+++ b/lib/xlat_tables/xlat_tables_common.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <bl_common.h>
+#include <cassert.h>
+#include <debug.h>
+#include <platform_def.h>
+#include <string.h>
+#include <xlat_tables.h>
+
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+#define LVL0_SPACER ""
+#define LVL1_SPACER " "
+#define LVL2_SPACER " "
+#define LVL3_SPACER " "
+#define get_level_spacer(level) \
+ (((level) == 0) ? LVL0_SPACER : \
+ (((level) == 1) ? LVL1_SPACER : \
+ (((level) == 2) ? LVL2_SPACER : LVL3_SPACER)))
+#define debug_print(...) tf_printf(__VA_ARGS__)
+#else
+#define debug_print(...) ((void)0)
+#endif
+
+#define UNSET_DESC ~0ul
+
+static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+ __aligned(XLAT_TABLE_SIZE) __section("xlat_table");
+
+static unsigned next_xlat;
+static unsigned long long xlat_max_pa;
+static uintptr_t xlat_max_va;
+
+/*
+ * Array of all memory regions stored in order of ascending base address.
+ * The list is terminated by the first entry with size == 0.
+ */
+static mmap_region_t mmap[MAX_MMAP_REGIONS + 1];
+
+
+void print_mmap(void)
+{
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ debug_print("mmap:\n");
+ mmap_region_t *mm = mmap;
+ while (mm->size) {
+ debug_print(" VA:%p PA:0x%llx size:0x%zx attr:0x%x\n",
+ (void *)mm->base_va, mm->base_pa,
+ mm->size, mm->attr);
+ ++mm;
+ };
+ debug_print("\n");
+#endif
+}
+
+void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
+ size_t size, unsigned int attr)
+{
+ mmap_region_t *mm = mmap;
+ mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1;
+ unsigned long long end_pa = base_pa + size - 1;
+ uintptr_t end_va = base_va + size - 1;
+
+ assert(IS_PAGE_ALIGNED(base_pa));
+ assert(IS_PAGE_ALIGNED(base_va));
+ assert(IS_PAGE_ALIGNED(size));
+
+ if (!size)
+ return;
+
+ assert(base_pa < end_pa); /* Check for overflows */
+ assert(base_va < end_va);
+
+#if DEBUG
+
+ /* Check for PAs and VAs overlaps with all other regions */
+ for (mm = mmap; mm->size; ++mm) {
+
+ uintptr_t mm_end_va = mm->base_va + mm->size - 1;
+
+ /*
+ * Check if one of the regions is completely inside the other
+ * one.
+ */
+ int fully_overlapped_va =
+ ((base_va >= mm->base_va) && (end_va <= mm_end_va)) ||
+ ((mm->base_va >= base_va) && (mm_end_va <= end_va));
+
+ /*
+ * Full VA overlaps are only allowed if both regions are
+ * identity mapped (zero offset) or have the same VA to PA
+ * offset. Also, make sure that it's not the exact same area.
+ */
+ if (fully_overlapped_va) {
+ assert((mm->base_va - mm->base_pa) ==
+ (base_va - base_pa));
+ assert((base_va != mm->base_va) || (size != mm->size));
+ } else {
+ /*
+ * If the regions do not have fully overlapping VAs,
+ * then they must have fully separated VAs and PAs.
+ * Partial overlaps are not allowed
+ */
+
+ unsigned long long mm_end_pa =
+ mm->base_pa + mm->size - 1;
+
+ int separated_pa =
+ (end_pa < mm->base_pa) || (base_pa > mm_end_pa);
+ int separated_va =
+ (end_va < mm->base_va) || (base_va > mm_end_va);
+
+ assert(separated_va && separated_pa);
+ }
+ }
+
+ mm = mmap; /* Restore pointer to the start of the array */
+
+#endif /* DEBUG */
+
+ /* Find correct place in mmap to insert new region */
+ while (mm->base_va < base_va && mm->size)
+ ++mm;
+
+ /*
+ * If a section is contained inside another one with the same base
+ * address, it must be placed after the one it is contained in:
+ *
+ * 1st |-----------------------|
+ * 2nd |------------|
+ * 3rd |------|
+ *
+ * This is required for mmap_region_attr() to get the attributes of the
+ * small region correctly.
+ */
+ while ((mm->base_va == base_va) && (mm->size > size))
+ ++mm;
+
+ /* Make room for new region by moving other regions up by one place */
+ memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
+
+ /* Check we haven't lost the empty sentinal from the end of the array */
+ assert(mm_last->size == 0);
+
+ mm->base_pa = base_pa;
+ mm->base_va = base_va;
+ mm->size = size;
+ mm->attr = attr;
+
+ if (end_pa > xlat_max_pa)
+ xlat_max_pa = end_pa;
+ if (end_va > xlat_max_va)
+ xlat_max_va = end_va;
+}
+
+void mmap_add(const mmap_region_t *mm)
+{
+ while (mm->size) {
+ mmap_add_region(mm->base_pa, mm->base_va, mm->size, mm->attr);
+ ++mm;
+ }
+}
+
+static uint64_t mmap_desc(unsigned attr, unsigned long long addr_pa,
+ int level)
+{
+ uint64_t desc = addr_pa;
+ int mem_type;
+
+ desc |= level == 3 ? TABLE_DESC : BLOCK_DESC;
+
+ desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0;
+
+ desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
+
+ desc |= LOWER_ATTRS(ACCESS_FLAG);
+
+ mem_type = MT_TYPE(attr);
+ if (mem_type == MT_MEMORY) {
+ desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH);
+ if (attr & MT_RW)
+ desc |= UPPER_ATTRS(XN);
+ } else if (mem_type == MT_NON_CACHEABLE) {
+ desc |= LOWER_ATTRS(ATTR_NON_CACHEABLE_INDEX | OSH);
+ if (attr & MT_RW)
+ desc |= UPPER_ATTRS(XN);
+ } else {
+ assert(mem_type == MT_DEVICE);
+ desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH);
+ desc |= UPPER_ATTRS(XN);
+ }
+
+ debug_print((mem_type == MT_MEMORY) ? "MEM" :
+ ((mem_type == MT_NON_CACHEABLE) ? "NC" : "DEV"));
+ debug_print(attr & MT_RW ? "-RW" : "-RO");
+ debug_print(attr & MT_NS ? "-NS" : "-S");
+
+ return desc;
+}
+
+/*
+ * Returns attributes of area at `base_va` with size `size`. It returns the
+ * attributes of the innermost region that contains it. If there are partial
+ * overlaps, it returns -1, as a smaller size is needed.
+ */
+static int mmap_region_attr(mmap_region_t *mm, uintptr_t base_va,
+ size_t size)
+{
+ /* Don't assume that the area is contained in the first region */
+ int attr = -1;
+
+ /*
+ * Get attributes from last (innermost) region that contains the
+ * requested area. Don't stop as soon as one region doesn't contain it
+ * because there may be other internal regions that contain this area:
+ *
+ * |-----------------------------1-----------------------------|
+ * |----2----| |-------3-------| |----5----|
+ * |--4--|
+ *
+ * |---| <- Area we want the attributes of.
+ *
+ * In this example, the area is contained in regions 1, 3 and 4 but not
+ * in region 2. The loop shouldn't stop at region 2 as inner regions
+ * have priority over outer regions, it should stop at region 5.
+ */
+ for (;; ++mm) {
+
+ if (!mm->size)
+ return attr; /* Reached end of list */
+
+ if (mm->base_va >= base_va + size)
+ return attr; /* Next region is after area so end */
+
+ if (mm->base_va + mm->size <= base_va)
+ continue; /* Next region has already been overtaken */
+
+ if (mm->attr == attr)
+ continue; /* Region doesn't override attribs so skip */
+
+ if (mm->base_va > base_va ||
+ mm->base_va + mm->size < base_va + size)
+ return -1; /* Region doesn't fully cover our area */
+
+ attr = mm->attr;
+ }
+}
+
+static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
+ uintptr_t base_va,
+ uint64_t *table,
+ int level)
+{
+ unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) *
+ XLAT_TABLE_ENTRIES_SHIFT;
+ unsigned level_size = 1 << level_size_shift;
+ unsigned long long level_index_mask =
+ ((unsigned long long) XLAT_TABLE_ENTRIES_MASK)
+ << level_size_shift;
+
+ assert(level > 0 && level <= 3);
+
+ debug_print("New xlat table:\n");
+
+ do {
+ uint64_t desc = UNSET_DESC;
+
+ if (!mm->size) {
+ /* Done mapping regions; finish zeroing the table */
+ desc = INVALID_DESC;
+ } else if (mm->base_va + mm->size <= base_va) {
+ /* This area is after the region so get next region */
+ ++mm;
+ continue;
+ }
+
+ debug_print("%s VA:%p size:0x%x ", get_level_spacer(level),
+ (void *)base_va, level_size);
+
+ if (mm->base_va >= base_va + level_size) {
+ /* Next region is after this area. Nothing to map yet */
+ desc = INVALID_DESC;
+ } else {
+ /*
+ * Try to get attributes of this area. It will fail if
+ * there are partially overlapping regions. On success,
+ * it will return the innermost region's attributes.
+ */
+ int attr = mmap_region_attr(mm, base_va, level_size);
+ if (attr >= 0) {
+ desc = mmap_desc(attr,
+ base_va - mm->base_va + mm->base_pa,
+ level);
+ }
+ }
+
+ if (desc == UNSET_DESC) {
+ /* Area not covered by a region so need finer table */
+ uint64_t *new_table = xlat_tables[next_xlat++];
+ assert(next_xlat <= MAX_XLAT_TABLES);
+ desc = TABLE_DESC | (uint64_t)new_table;
+
+ /* Recurse to fill in new table */
+ mm = init_xlation_table_inner(mm, base_va,
+ new_table, level+1);
+ }
+
+ debug_print("\n");
+
+ *table++ = desc;
+ base_va += level_size;
+ } while ((base_va & level_index_mask) && (base_va < ADDR_SPACE_SIZE));
+
+ return mm;
+}
+
+void init_xlation_table(uintptr_t base_va, uint64_t *table,
+ int level, uintptr_t *max_va,
+ unsigned long long *max_pa)
+{
+
+ init_xlation_table_inner(mmap, base_va, table, level);
+ *max_va = xlat_max_va;
+ *max_pa = xlat_max_pa;
+}
diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h
new file mode 100644
index 0000000..389bb0b
--- /dev/null
+++ b/lib/xlat_tables/xlat_tables_private.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __XLAT_TABLES_PRIVATE_H__
+#define __XLAT_TABLES_PRIVATE_H__
+
+void print_mmap(void);
+void init_xlation_table(uintptr_t base_va, uint64_t *table,
+ int level, uintptr_t *max_va,
+ unsigned long long *max_pa);
+
+#endif /* __XLAT_TABLES_PRIVATE_H__ */
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 5171ff0..c963b7a 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -208,11 +208,11 @@
$(OBJ): $(2)
@echo " CC $$<"
- $$(Q)$$(CC) $$(CFLAGS) -D$(IMAGE) -c $$< -o $$@
+ $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) -c $$< -o $$@
$(PREREQUISITES): $(2) | bl$(3)_dirs
@echo " DEPS $$@"
- $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+ $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$<
ifdef IS_ANYTHING_TO_BUILD
-include $(PREREQUISITES)
@@ -351,7 +351,7 @@
else
@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); \
const char version_string[] = "${VERSION_STRING}";' | \
- $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o
+ $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o
endif
$$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \
$(BUILD_DIR)/build_message.o $(OBJS)
diff --git a/make_helpers/windows.mk b/make_helpers/windows.mk
index 8ac8246..fe5e8c1 100644
--- a/make_helpers/windows.mk
+++ b/make_helpers/windows.mk
@@ -104,6 +104,6 @@
VERSION_STRING_MESSAGE = const char version_string[] = "${VERSION_STRING}";
define MAKE_BUILD_STRINGS
@echo $$(BUILT_TIME_DATE_STRING) $$(VERSION_STRING_MESSAGE) | \
- $$(CC) $$(CFLAGS) -x c - -o $1
+ $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -x c - -o $1
endef
diff --git a/plat/arm/board/fvp/aarch64/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
similarity index 88%
rename from plat/arm/board/fvp/aarch64/fvp_common.c
rename to plat/arm/board/fvp/fvp_common.c
index 1de9999..78782d4 100644
--- a/plat/arm/board/fvp/aarch64/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -37,10 +37,6 @@
#include <v2m_def.h>
#include "../fvp_def.h"
-#if (FVP_USE_GIC_DRIVER == FVP_GICV2)
-extern gicv2_driver_data_t arm_gic_data;
-#endif
-
/* Defines for GIC Driver build time selection */
#define FVP_GICV2 1
#define FVP_GICV3 2
@@ -159,26 +155,9 @@
*/
switch (bld) {
case BLD_GIC_VE_MMAP:
-#if IMAGE_BL31 || IMAGE_BL32
-#if FVP_USE_GIC_DRIVER == FVP_GICV2
- /*
- * If the FVP implements the VE compatible memory map, then the
- * GICv2 driver must be included in the build. Update the platform
- * data with the correct GICv2 base addresses before it is used
- * to initialise the driver.
- *
- * This update of platform data is temporary and will be removed
- * once VE memory map for FVP is no longer supported by Trusted
- * Firmware.
- */
- arm_gic_data.gicd_base = VE_GICD_BASE;
- arm_gic_data.gicc_base = VE_GICC_BASE;
-
-#else
- ERROR("Only GICv2 driver supported for VE memory map\n");
+ ERROR("Legacy Versatile Express memory map for GIC peripheral"
+ " is not supported\n");
panic();
-#endif /* __FVP_USE_GIC_DRIVER == FVP_GICV2__ */
-#endif /* __IMAGE_BL31 || IMAGE_BL32__ */
break;
case BLD_GIC_A53A57_MMAP:
break;
diff --git a/plat/arm/board/fvp/include/plat_macros.S b/plat/arm/board/fvp/include/plat_macros.S
index df66a52..e43c7ac 100644
--- a/plat/arm/board/fvp/include/plat_macros.S
+++ b/plat/arm/board/fvp/include/plat_macros.S
@@ -37,12 +37,13 @@
/* ---------------------------------------------
* The below required platform porting macro
- * prints out relevant GIC registers whenever an
- * unhandled exception is taken in BL31.
+ * prints out relevant GIC and CCI registers
+ * whenever an unhandled exception is taken in
+ * BL31.
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
- .macro plat_print_gic_regs
+ .macro plat_crash_print_regs
/*
* Detect if we're using the base memory map or
* the legacy VE memory map
@@ -63,6 +64,7 @@
mov_imm x16, VE_GICD_BASE
print_gic_regs:
arm_print_gic_regs
+ print_cci_regs
.endm
#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index afd939d..eecb597 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -28,8 +28,8 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-# Use the Legacy GICv3 driver on the FVP by default to maintain compatibility.
-FVP_USE_GIC_DRIVER := FVP_GICV3_LEGACY
+# Use the GICv3 driver on the FVP by default
+FVP_USE_GIC_DRIVER := FVP_GICV3
# The FVP platform depends on this macro to build with correct GIC driver.
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
@@ -73,7 +73,7 @@
PLAT_INCLUDES := -Iplat/arm/board/fvp/include
-PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/aarch64/fvp_common.c
+PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c
FVP_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a35.S \
diff --git a/plat/arm/board/juno/include/plat_macros.S b/plat/arm/board/juno/include/plat_macros.S
index d2a88ed..bb42bca 100644
--- a/plat/arm/board/juno/include/plat_macros.S
+++ b/plat/arm/board/juno/include/plat_macros.S
@@ -33,10 +33,16 @@
#include <cci_macros.S>
#include <css_macros.S>
-/*
- * Required platform porting macros
- * (Provided by included headers)
- */
-
+ /* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ css_print_gic_regs
+ print_cci_regs
+ .endm
#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/arm/common/aarch64/arm_common.c b/plat/arm/common/aarch64/arm_common.c
index 78b75b4..cf1f3ba 100644
--- a/plat/arm/common/aarch64/arm_common.c
+++ b/plat/arm/common/aarch64/arm_common.c
@@ -29,6 +29,7 @@
*/
#include <arch.h>
#include <arch_helpers.h>
+#include <debug.h>
#include <mmio.h>
#include <plat_arm.h>
#include <platform_def.h>
@@ -39,7 +40,7 @@
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_get_ns_image_entrypoint
#pragma weak plat_arm_get_mmap
-
+#pragma weak plat_get_syscnt_freq
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
@@ -161,3 +162,19 @@
{
return plat_arm_mmap;
}
+
+#ifdef ARM_SYS_CNTCTL_BASE
+unsigned long long plat_get_syscnt_freq(void)
+{
+ unsigned long long counter_base_frequency;
+
+ /* Read the frequency from Frequency modes table */
+ counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
+
+ /* The first entry of the frequency modes table must not be 0 */
+ if (counter_base_frequency == 0)
+ panic();
+
+ return counter_base_frequency;
+}
+#endif /* ARM_SYS_CNTCTL_BASE */
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 8fcfa77..8eb6818 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -34,7 +34,6 @@
#include <assert.h>
#include <bl_common.h>
#include <console.h>
-#include <debug.h>
#include <mmio.h>
#include <plat_arm.h>
#include <platform.h>
@@ -76,7 +75,6 @@
#pragma weak bl31_platform_setup
#pragma weak bl31_plat_arch_setup
#pragma weak bl31_plat_get_next_image_ep_info
-#pragma weak plat_get_syscnt_freq
/*******************************************************************************
@@ -268,17 +266,3 @@
{
arm_bl31_plat_arch_setup();
}
-
-uint64_t plat_get_syscnt_freq(void)
-{
- uint64_t counter_base_frequency;
-
- /* Read the frequency from Frequency modes table */
- counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
-
- /* The first entry of the frequency modes table must not be 0 */
- if (counter_base_frequency == 0)
- panic();
-
- return counter_base_frequency;
-}
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 973e583..0b28861 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -87,7 +87,8 @@
-Iinclude/plat/arm/common/aarch64
-PLAT_BL_COMMON_SOURCES += lib/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
plat/arm/common/aarch64/arm_common.c \
plat/arm/common/aarch64/arm_helpers.S \
plat/common/aarch64/plat_common.c
diff --git a/plat/arm/common/arm_gicv2.c b/plat/arm/common/arm_gicv2.c
index 76f04cd..2636d1c 100644
--- a/plat/arm/common/arm_gicv2.c
+++ b/plat/arm/common/arm_gicv2.c
@@ -47,17 +47,12 @@
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
+static const unsigned int g0_interrupt_array[] = {
PLAT_ARM_G1S_IRQS,
PLAT_ARM_G0_IRQS
};
-/*
- * Ideally `arm_gic_data` structure definition should be a `const` but it is
- * kept as modifiable for overwriting with different GICD and GICC base when
- * running on FVP with VE memory map.
- */
-gicv2_driver_data_t arm_gic_data = {
+static const gicv2_driver_data_t arm_gic_data = {
.gicd_base = PLAT_ARM_GICD_BASE,
.gicc_base = PLAT_ARM_GICC_BASE,
.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 33f8018..a20fd56 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -45,15 +45,15 @@
#pragma weak plat_arm_gic_pcpu_init
/* The GICv3 driver only needs to be initialized in EL3 */
-uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
/* Array of Group1 secure interrupts to be configured by the gic driver */
-const unsigned int g1s_interrupt_array[] = {
+static const unsigned int g1s_interrupt_array[] = {
PLAT_ARM_G1S_IRQS
};
/* Array of Group0 interrupts to be configured by the gic driver */
-const unsigned int g0_interrupt_array[] = {
+static const unsigned int g0_interrupt_array[] = {
PLAT_ARM_G0_IRQS
};
diff --git a/plat/arm/common/arm_gicv3_legacy.c b/plat/arm/common/arm_gicv3_legacy.c
index 6170933..8396b60 100644
--- a/plat/arm/common/arm_gicv3_legacy.c
+++ b/plat/arm/common/arm_gicv3_legacy.c
@@ -48,7 +48,7 @@
* In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group
* 0 interrupts.
*/
-const unsigned int irq_sec_array[] = {
+static const unsigned int irq_sec_array[] = {
PLAT_ARM_G0_IRQS,
PLAT_ARM_G1S_IRQS
};
diff --git a/plat/mediatek/mt8173/aarch64/platform_common.c b/plat/mediatek/mt8173/aarch64/platform_common.c
index 23116f5..d83e147 100644
--- a/plat/mediatek/mt8173/aarch64/platform_common.c
+++ b/plat/mediatek/mt8173/aarch64/platform_common.c
@@ -84,7 +84,7 @@
/* Define EL3 variants of the function initialising the MMU */
DEFINE_CONFIGURE_MMU_EL(3)
-uint64_t plat_get_syscnt_freq(void)
+unsigned long long plat_get_syscnt_freq(void)
{
return SYS_COUNTER_FREQ_IN_TICKS;
}
diff --git a/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c b/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c
index 265685f..5640fb3 100644
--- a/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c
+++ b/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c
@@ -181,17 +181,17 @@
mtcmos_ctrl_little_off(3);
}
-uint32_t wait_mtcmos_ack(uint32_t on, uint32_t mtcmos_sta, uint32_t spm_pwr_sta)
+uint32_t wait_mtcmos_ack(uint32_t on, uint32_t pwr_ctrl, uint32_t spm_pwr_sta)
{
int i = 0;
uint32_t cmp, pwr_sta, pwr_sta_2nd;
while (1) {
- cmp = (mmio_read_32(SPM_PCM_PASR_DPD_3) >> mtcmos_sta) & 1;
+ cmp = mmio_read_32(SPM_PCM_PASR_DPD_3) & pwr_ctrl;
pwr_sta = (mmio_read_32(SPM_PWR_STATUS) >> spm_pwr_sta) & 1;
pwr_sta_2nd =
(mmio_read_32(SPM_PWR_STATUS_2ND) >> spm_pwr_sta) & 1;
- if ((cmp == on) && (pwr_sta == on) && (pwr_sta_2nd == on)) {
+ if (cmp && (pwr_sta == on) && (pwr_sta_2nd == on)) {
mmio_write_32(SPM_PCM_RESERVE2, 0);
return MTCMOS_CTRL_SUCCESS;
}
@@ -218,6 +218,7 @@
uint32_t ret = MTCMOS_CTRL_SUCCESS;
uint32_t power_on;
uint32_t power_off;
+ uint32_t power_ctrl;
uint32_t power_status;
spm_lock_get();
@@ -280,13 +281,12 @@
INFO("No mapping MTCMOS(%d), ret = %d\n", mtcmos_num, ret);
break;
}
-
if (ret == MTCMOS_CTRL_SUCCESS) {
- mmio_setbits_32(SPM_PCM_RESERVE2, on ?
- (1 << power_on) : (1 << power_off));
- ret = wait_mtcmos_ack(on, power_on, power_status);
+ power_ctrl = on ? (1 << power_on) : (1 << power_off);
+ mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl);
+ ret = wait_mtcmos_ack(on, power_ctrl, power_status);
VERBOSE("0x%x(%d), PWR_STATUS(0x%x), ret(%d)\n",
- power_on, on, mmio_read_32(SPM_PWR_STATUS), ret);
+ power_ctrl, on, mmio_read_32(SPM_PWR_STATUS), ret);
}
mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN);
diff --git a/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c b/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
index 3043327..7aacdec 100644
--- a/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
+++ b/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
@@ -62,57 +62,56 @@
static const unsigned int mcdi_binary[] = {
0x1a10001f, 0x10006b04, 0x1890001f, 0x10006b6c, 0x1a40001f, 0x10006210,
0x18d0001f, 0x10006210, 0x81002001, 0xd82001c4, 0x17c07c1f, 0xa0900402,
- 0xc2401520, 0x17c07c1f, 0x81052001, 0xd8200284, 0x17c07c1f, 0x80b00402,
- 0xc2401b60, 0x17c07c1f, 0x1a40001f, 0x10006230, 0x18d0001f, 0x10006230,
- 0x8100a001, 0xd82003c4, 0x17c07c1f, 0xa0908402, 0xc2401520, 0x17c07c1f,
- 0x8105a001, 0xd8200484, 0x17c07c1f, 0x80b08402, 0xc2401b60, 0x17c07c1f,
+ 0xc2401540, 0x17c07c1f, 0x81052001, 0xd8200284, 0x17c07c1f, 0xa0950402,
+ 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x10006230, 0x18d0001f, 0x10006230,
+ 0x8100a001, 0xd82003c4, 0x17c07c1f, 0xa0908402, 0xc2401540, 0x17c07c1f,
+ 0x8105a001, 0xd8200484, 0x17c07c1f, 0xa0958402, 0xc2401b80, 0x17c07c1f,
0x1a40001f, 0x10006238, 0x18d0001f, 0x10006238, 0x81012001, 0xd82005c4,
- 0x17c07c1f, 0xa0910402, 0xc2401520, 0x17c07c1f, 0x81062001, 0xd8200684,
- 0x17c07c1f, 0x80b10402, 0xc2401b60, 0x17c07c1f, 0x1a40001f, 0x1000623c,
+ 0x17c07c1f, 0xa0910402, 0xc2401540, 0x17c07c1f, 0x81062001, 0xd8200684,
+ 0x17c07c1f, 0xa0960402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x1000623c,
0x18d0001f, 0x1000623c, 0x8101a001, 0xd82007c4, 0x17c07c1f, 0xa0918402,
- 0xc2401520, 0x17c07c1f, 0x8106a001, 0xd8200884, 0x17c07c1f, 0x80b18402,
- 0xc2401b60, 0x17c07c1f, 0x1a40001f, 0x10006298, 0x18d0001f, 0x10006298,
- 0x81022001, 0xd82009c4, 0x17c07c1f, 0xa0920402, 0xc2401520, 0x17c07c1f,
- 0x81072001, 0xd8200a84, 0x17c07c1f, 0x80b20402, 0xc2401b60, 0x17c07c1f,
+ 0xc2401540, 0x17c07c1f, 0x8106a001, 0xd8200884, 0x17c07c1f, 0xa0968402,
+ 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x10006298, 0x18d0001f, 0x10006298,
+ 0x81022001, 0xd82009c4, 0x17c07c1f, 0xa0920402, 0xc2401540, 0x17c07c1f,
+ 0x81072001, 0xd8200a84, 0x17c07c1f, 0xa0970402, 0xc2401b80, 0x17c07c1f,
0x1a40001f, 0x1000629c, 0x18d0001f, 0x1000629c, 0x8102a001, 0xd8200bc4,
- 0x17c07c1f, 0xa0928402, 0xc2401520, 0x17c07c1f, 0x8107a001, 0xd8200c84,
- 0x17c07c1f, 0x80b28402, 0xc2401b60, 0x17c07c1f, 0x1a40001f, 0x100062c4,
+ 0x17c07c1f, 0xa0928402, 0xc2401540, 0x17c07c1f, 0x8107a001, 0xd8200c84,
+ 0x17c07c1f, 0xa0978402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062c4,
0x18d0001f, 0x100062c4, 0x81032001, 0xd8200dc4, 0x17c07c1f, 0xa0930402,
- 0xc2401520, 0x17c07c1f, 0x81082001, 0xd8200e84, 0x17c07c1f, 0x80b30402,
- 0xc2401b60, 0x17c07c1f, 0x1a40001f, 0x100062c0, 0x18d0001f, 0x100062c0,
- 0x8103a001, 0xd8200fc4, 0x17c07c1f, 0xa0938402, 0xc2401520, 0x17c07c1f,
- 0x8108a001, 0xd8201084, 0x17c07c1f, 0x80b38402, 0xc2401b60, 0x17c07c1f,
+ 0xc2401540, 0x17c07c1f, 0x81082001, 0xd8200e84, 0x17c07c1f, 0xa0980402,
+ 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062c0, 0x18d0001f, 0x100062c0,
+ 0x8103a001, 0xd8200fc4, 0x17c07c1f, 0xa0938402, 0xc2401540, 0x17c07c1f,
+ 0x8108a001, 0xd8201084, 0x17c07c1f, 0xa0988402, 0xc2401b80, 0x17c07c1f,
0x1a40001f, 0x10006214, 0x18d0001f, 0x10006214, 0x81042001, 0xd82011c4,
- 0x17c07c1f, 0xa0940402, 0xc2401520, 0x17c07c1f, 0x81092001, 0xd8201284,
- 0x17c07c1f, 0x80b40402, 0xc2401b60, 0x17c07c1f, 0x1a40001f, 0x100062cc,
+ 0x17c07c1f, 0xa0940402, 0xc2401540, 0x17c07c1f, 0x81092001, 0xd8201284,
+ 0x17c07c1f, 0xa0990402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062cc,
0x18d0001f, 0x100062cc, 0x8104a001, 0xd82013c4, 0x17c07c1f, 0xa0948402,
- 0xc2401520, 0x17c07c1f, 0x8109a001, 0xd8201484, 0x17c07c1f, 0x80b48402,
- 0xc2401b60, 0x17c07c1f, 0x1900001f, 0x10006b6c, 0xe1000002, 0xf0000000,
- 0x17c07c1f, 0xa8c00003, 0x00000004, 0xe2400003, 0xa8c00003, 0x00000008,
- 0xe2400003, 0x1b80001f, 0x00000020, 0x88c00003, 0xffffffef, 0xe2400003,
- 0x88c00003, 0xfffffffd, 0xe2400003, 0xa8c00003, 0x00000001, 0xe2400003,
- 0x88c00003, 0xfffff0ff, 0xe2400003, 0x1b80001f, 0x20000080, 0x1a90001f,
- 0x10001220, 0x69200009, 0x1000623c, 0xd8001964, 0x17c07c1f, 0x69200009,
- 0x10006214, 0xd8001a44, 0x17c07c1f, 0xd0001ae0, 0x17c07c1f, 0x1900001f,
- 0x10001220, 0x8a80000a, 0xfffffff9, 0xe100000a, 0xd0001ae0, 0x17c07c1f,
- 0x1900001f, 0x10001220, 0x8a80000a, 0xff1fbfff, 0xe100000a, 0x1b80001f,
- 0x20000080, 0xf0000000, 0x17c07c1f, 0x1a90001f, 0x10001220, 0x69200009,
- 0x1000623c, 0xd8001ce4, 0x17c07c1f, 0x69200009, 0x10006214, 0xd8001dc4,
- 0x17c07c1f, 0xd0001e60, 0x17c07c1f, 0x1900001f, 0x10001220, 0xaa80000a,
- 0x00000006, 0xe100000a, 0xd0001e60, 0x17c07c1f, 0x1900001f, 0x10001220,
- 0xaa80000a, 0x00e04000, 0xe100000a, 0x1b80001f, 0x20000080, 0x69200009,
- 0x10006214, 0xd8001fc4, 0x17c07c1f, 0xa8c00003, 0x00000f00, 0xe2400003,
- 0xd0002020, 0x17c07c1f, 0xa8c00003, 0x00003f00, 0xe2400003, 0x1b80001f,
- 0x20000080, 0xa8c00003, 0x00000002, 0xe2400003, 0x88c00003, 0xfffffffe,
- 0xe2400003, 0xa8c00003, 0x00000010, 0xe2400003, 0x88c00003, 0xfffffffb,
- 0xe2400003, 0x88c00003, 0xfffffff7, 0xe2400003, 0xf0000000, 0x17c07c1f,
- 0xe2e00036, 0xe2e0003e, 0x1b80001f, 0x00000020, 0xe2e0003c, 0xe8208000,
- 0x10006244, 0x00000000, 0x1b80001f, 0x20000080, 0xe2e0007c, 0x1b80001f,
- 0x20000003, 0xe2e0005c, 0xe2e0004c, 0xe2e0004d, 0xf0000000, 0x17c07c1f,
- 0xe2e0004f, 0xe2e0006f, 0xe2e0002f, 0xe8208000, 0x10006244, 0x00000001,
- 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e0003a, 0xe2e00032,
- 0x1b80001f, 0x00000020, 0x1910001f, 0x10006b6c, 0x09000004, 0x00100000,
- 0x1a10001f, 0x10006b6c, 0xe2000004, 0xf0000000, 0x17c07c1f, 0xe2e00036,
+ 0xc2401540, 0x17c07c1f, 0x8109a001, 0xd8201484, 0x17c07c1f, 0xa0998402,
+ 0xc2401b80, 0x17c07c1f, 0x1900001f, 0x10006b6c, 0x80802002, 0xe1000002,
+ 0xf0000000, 0x17c07c1f, 0xa8c00003, 0x00000004, 0xe2400003, 0xa8c00003,
+ 0x00000008, 0xe2400003, 0x1b80001f, 0x00000020, 0x88c00003, 0xffffffef,
+ 0xe2400003, 0x88c00003, 0xfffffffd, 0xe2400003, 0xa8c00003, 0x00000001,
+ 0xe2400003, 0x88c00003, 0xfffff0ff, 0xe2400003, 0x1b80001f, 0x20000080,
+ 0x1a90001f, 0x10001220, 0x69200009, 0x1000623c, 0xd8001984, 0x17c07c1f,
+ 0x69200009, 0x10006214, 0xd8001a64, 0x17c07c1f, 0xd0001b00, 0x17c07c1f,
+ 0x1900001f, 0x10001220, 0x8a80000a, 0xfffffff9, 0xe100000a, 0xd0001b00,
+ 0x17c07c1f, 0x1900001f, 0x10001220, 0x8a80000a, 0xff1fbfff, 0xe100000a,
+ 0x1b80001f, 0x20000080, 0xf0000000, 0x17c07c1f, 0x1a90001f, 0x10001220,
+ 0x69200009, 0x1000623c, 0xd8001d04, 0x17c07c1f, 0x69200009, 0x10006214,
+ 0xd8001de4, 0x17c07c1f, 0xd0001e80, 0x17c07c1f, 0x1900001f, 0x10001220,
+ 0xaa80000a, 0x00000006, 0xe100000a, 0xd0001e80, 0x17c07c1f, 0x1900001f,
+ 0x10001220, 0xaa80000a, 0x00e04000, 0xe100000a, 0x1b80001f, 0x20000080,
+ 0x69200009, 0x10006214, 0xd8001fe4, 0x17c07c1f, 0xa8c00003, 0x00000f00,
+ 0xe2400003, 0xd0002040, 0x17c07c1f, 0xa8c00003, 0x00003f00, 0xe2400003,
+ 0x1b80001f, 0x20000080, 0xa8c00003, 0x00000002, 0xe2400003, 0x88c00003,
+ 0xfffffffe, 0xe2400003, 0xa8c00003, 0x00000010, 0xe2400003, 0x88c00003,
+ 0xfffffffb, 0xe2400003, 0x88c00003, 0xfffffff7, 0xe2400003, 0xf0000000,
+ 0x17c07c1f, 0xe2e00036, 0xe2e0003e, 0x1b80001f, 0x00000020, 0xe2e0003c,
+ 0xe8208000, 0x10006244, 0x00000000, 0x1b80001f, 0x20000080, 0xe2e0007c,
+ 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, 0xe2e0004d, 0xf0000000,
+ 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f, 0xe8208000, 0x10006244,
+ 0x00000001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e0003a,
+ 0xe2e00032, 0x1b80001f, 0x00000020, 0xf0000000, 0x17c07c1f, 0xe2e00036,
0xe2e0003e, 0x1b80001f, 0x00000020, 0xe2e0003c, 0xe2a00000, 0x1b80001f,
0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c,
0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f,
@@ -123,117 +122,115 @@
0xe2e0000c, 0xe2e0000d, 0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f,
0x100062b4, 0x1910001f, 0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804,
0xe2000004, 0x1b80001f, 0x20000080, 0xe2e0002f, 0xe2e0002b, 0xe2e00023,
- 0x1b80001f, 0x00000020, 0xe2e00022, 0xf0000000, 0x17c07c1f, 0x1900001f,
+ 0x1b80001f, 0x00000020, 0xe2e00022, 0xf0000000, 0x17c07c1f, 0x1910001f,
+ 0x1000660c, 0x1a10001f, 0x10006610, 0xa2002004, 0x89000008, 0x00030000,
+ 0xd80036c4, 0x17c07c1f, 0x8207a001, 0xd82036c8, 0x17c07c1f, 0x1900001f,
0x1020020c, 0x1a10001f, 0x1020020c, 0xaa000008, 0x00000001, 0xe1000008,
- 0x1910001f, 0x10006720, 0x820c9001, 0xd82030c8, 0x17c07c1f, 0x1900001f,
- 0x10001220, 0x1a10001f, 0x10001220, 0xa21f0408, 0xe1000008, 0x1b80001f,
- 0x20000080, 0xe2e0006d, 0xe2e0002d, 0x1a00001f, 0x100062b8, 0x1910001f,
- 0x100062b8, 0xa9000004, 0x00000001, 0xe2000004, 0x1b80001f, 0x20000080,
- 0xe2e0002c, 0xe2e0003c, 0xe2e0003e, 0xe2e0003a, 0xe2e00032, 0x1b80001f,
- 0x00000020, 0x1900001f, 0x10006404, 0x1a10001f, 0x10006404, 0xa2168408,
- 0xe1000008, 0xf0000000, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8a000008,
- 0x00003030, 0xb900010c, 0x01000001, 0xd8203bc4, 0x17c07c1f, 0x1900001f,
- 0x10006404, 0x1a10001f, 0x10006404, 0x8a000008, 0x0000dfff, 0xe1000008,
- 0xe2e00036, 0xe2e0003e, 0x1b80001f, 0x00000020, 0xe2e0002e, 0x1a00001f,
- 0x100062b8, 0x1910001f, 0x100062b8, 0x89000004, 0x0000fffe, 0xe2000004,
- 0x1b80001f, 0x20000080, 0xe2e0006e, 0xe2e0004e, 0xe2e0004c, 0xe2e0004d,
- 0x1900001f, 0x10001220, 0x1a10001f, 0x10001220, 0x8a000008, 0xbfffffff,
- 0xe1000008, 0x1b80001f, 0x20000080, 0x1900001f, 0x1020020c, 0x1a10001f,
- 0x1020020c, 0x8a000008, 0xfffffffe, 0xe1000008, 0xf0000000, 0x17c07c1f,
- 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
- 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
- 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
- 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
+ 0x1910001f, 0x1020020c, 0x81001001, 0xd8203184, 0x17c07c1f, 0x1910001f,
+ 0x10006720, 0x820c9001, 0xd8203228, 0x17c07c1f, 0x1900001f, 0x10001220,
+ 0x1a10001f, 0x10001220, 0xa21f0408, 0xe1000008, 0x1b80001f, 0x20000080,
+ 0xe2e0006d, 0xe2e0002d, 0x1a00001f, 0x100062b8, 0x1910001f, 0x100062b8,
+ 0xa9000004, 0x00000001, 0xe2000004, 0x1b80001f, 0x20000080, 0xe2e0002c,
+ 0xe2e0003c, 0xe2e0003e, 0xe2e0003a, 0xe2e00032, 0x1b80001f, 0x00000020,
+ 0x1900001f, 0x10006404, 0x1a10001f, 0x10006404, 0xa2168408, 0xe1000008,
+ 0xf0000000, 0x17c07c1f, 0x1a10001f, 0x10006610, 0x8207a001, 0xd8003e68,
+ 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8a000008, 0x00003030, 0xb900010c,
+ 0x01000001, 0xd8203e64, 0x17c07c1f, 0x1900001f, 0x10006404, 0x1a10001f,
+ 0x10006404, 0x8a000008, 0x0000dfff, 0xe1000008, 0xe2e00036, 0xe2e0003e,
+ 0x1b80001f, 0x00000020, 0xe2e0002e, 0x1a00001f, 0x100062b8, 0x1910001f,
+ 0x100062b8, 0x89000004, 0x0000fffe, 0xe2000004, 0x1b80001f, 0x20000080,
+ 0xe2e0006e, 0xe2e0004e, 0xe2e0004c, 0xe2e0004d, 0x1900001f, 0x10001220,
+ 0x1a10001f, 0x10001220, 0x8a000008, 0xbfffffff, 0xe1000008, 0x1b80001f,
+ 0x20000080, 0x1900001f, 0x1020020c, 0x1a10001f, 0x1020020c, 0x8a000008,
+ 0xfffffffe, 0xe1000008, 0x1910001f, 0x1020020c, 0x81001001, 0xd8003dc4,
+ 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x11407c1f, 0xe8208000,
- 0x10006b6c, 0xa0000000, 0xe8208000, 0x10006310, 0x0b160008, 0x1900001f,
- 0x000f7bde, 0x1a00001f, 0x10200268, 0xe2000004, 0xe8208000, 0x10006600,
- 0x00000000, 0x69200006, 0xbeefbeef, 0xd82045e4, 0x17c07c1f, 0x1910001f,
- 0x10006358, 0x810b1001, 0xd80042a4, 0x17c07c1f, 0x1980001f, 0xdeaddead,
- 0x69200006, 0xabcdabcd, 0xd8204384, 0x17c07c1f, 0x88900001, 0x10006814,
- 0x1910001f, 0x10006400, 0x81271002, 0x1880001f, 0x10006600, 0xe0800004,
- 0x1910001f, 0x10006358, 0x810b1001, 0xd8004504, 0x17c07c1f, 0x1980001f,
- 0x12345678, 0x60a07c05, 0x89100002, 0x10006600, 0x80801001, 0xd8007e02,
- 0x17c07c1f, 0x1890001f, 0x10006b00, 0x82090801, 0xc8800008, 0x17c07c1f,
- 0x1b00001f, 0x3fffe7ff, 0x8a00000c, 0x3fffe7ff, 0xd8204228, 0x17c07c1f,
- 0x1b80001f, 0xd0010000, 0x1a10001f, 0x10006720, 0x82002001, 0x82201408,
- 0xd82049e8, 0x17c07c1f, 0x1a40001f, 0x10006200, 0x1a80001f, 0x1000625c,
- 0xc24029a0, 0x17c07c1f, 0xa1400405, 0x1a10001f, 0x10006720, 0x8200a001,
- 0x82209408, 0xd8204b88, 0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f,
- 0x10006264, 0xc24029a0, 0x17c07c1f, 0xa1508405, 0x1a10001f, 0x10006720,
- 0x82012001, 0x82211408, 0xd8204d28, 0x17c07c1f, 0x1a40001f, 0x1000621c,
- 0x1a80001f, 0x1000626c, 0xc24029a0, 0x17c07c1f, 0xa1510405, 0x1a10001f,
- 0x10006720, 0x8201a001, 0x82219408, 0xd8204ec8, 0x17c07c1f, 0x1a40001f,
- 0x10006220, 0x1a80001f, 0x10006274, 0xc24029a0, 0x17c07c1f, 0xa1518405,
- 0x1a10001f, 0x10006720, 0x82022001, 0x82221408, 0xd8205048, 0x17c07c1f,
- 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2402d80, 0x17c07c1f, 0xa1520405,
- 0x1a10001f, 0x10006720, 0x8202a001, 0x82229408, 0xd82051c8, 0x17c07c1f,
- 0x1a40001f, 0x100062a4, 0x1290841f, 0xc2402d80, 0x17c07c1f, 0xa1528405,
- 0x1a10001f, 0x10006720, 0x82032001, 0x82231408, 0xd82052a8, 0x17c07c1f,
- 0xa1530405, 0x1a10001f, 0x10006720, 0x8203a001, 0x82239408, 0xd8205388,
- 0x17c07c1f, 0xa1538405, 0x1a10001f, 0x10006b00, 0x8108a001, 0xd8205ec4,
- 0x17c07c1f, 0x1a10001f, 0x10006610, 0x8104a001, 0xb1052081, 0xb105a081,
- 0xb1062081, 0xd8005984, 0x17c07c1f, 0x81042001, 0xd8205984, 0x17c07c1f,
- 0x1900001f, 0x1020002c, 0x1a10001f, 0x1020002c, 0xaa000008, 0x00000010,
- 0xe1000008, 0x1910001f, 0x10006720, 0x820c1001, 0xd8205668, 0x17c07c1f,
- 0x1900001f, 0x10001250, 0x1a10001f, 0x10001250, 0xa2110408, 0xe1000008,
+ 0x10006310, 0x0b160008, 0x1900001f, 0x000f7bde, 0x1a00001f, 0x10200268,
+ 0xe2000004, 0xe8208000, 0x10006600, 0x00000000, 0x69200006, 0xbeefbeef,
+ 0xd8204584, 0x17c07c1f, 0x1910001f, 0x10006358, 0x810b1001, 0xd8004244,
+ 0x17c07c1f, 0x1980001f, 0xdeaddead, 0x69200006, 0xabcdabcd, 0xd8204324,
+ 0x17c07c1f, 0x88900001, 0x10006814, 0x1910001f, 0x10006400, 0x81271002,
+ 0x1880001f, 0x10006600, 0xe0800004, 0x1910001f, 0x10006358, 0x810b1001,
+ 0xd80044a4, 0x17c07c1f, 0x1980001f, 0x12345678, 0x60a07c05, 0x89100002,
+ 0x10006600, 0x80801001, 0xd8007bc2, 0x17c07c1f, 0x1890001f, 0x10006b00,
+ 0x82090801, 0xc8800008, 0x17c07c1f, 0x1b00001f, 0x3fffe7ff, 0x8a00000c,
+ 0x3fffe7ff, 0xd82041c8, 0x17c07c1f, 0x1b80001f, 0xd0010000, 0x1a10001f,
+ 0x10006720, 0x82002001, 0x82201408, 0xd8204988, 0x17c07c1f, 0x1a40001f,
+ 0x10006200, 0x1a80001f, 0x1000625c, 0xc24028e0, 0x17c07c1f, 0xa1400405,
+ 0x1a10001f, 0x10006720, 0x8200a001, 0x82209408, 0xd8204b28, 0x17c07c1f,
+ 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc24028e0, 0x17c07c1f,
+ 0xa1508405, 0x1a10001f, 0x10006720, 0x82012001, 0x82211408, 0xd8204cc8,
+ 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c, 0xc24028e0,
+ 0x17c07c1f, 0xa1510405, 0x1a10001f, 0x10006720, 0x8201a001, 0x82219408,
+ 0xd8204e68, 0x17c07c1f, 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274,
+ 0xc24028e0, 0x17c07c1f, 0xa1518405, 0x1a10001f, 0x10006720, 0x82022001,
+ 0x82221408, 0xd8204fe8, 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f,
+ 0xc2402cc0, 0x17c07c1f, 0xa1520405, 0x1a10001f, 0x10006720, 0x8202a001,
+ 0x82229408, 0xd8205168, 0x17c07c1f, 0x1a40001f, 0x100062a4, 0x1290841f,
+ 0xc2402cc0, 0x17c07c1f, 0xa1528405, 0x1a10001f, 0x10006720, 0x82032001,
+ 0x82231408, 0xd8205248, 0x17c07c1f, 0xa1530405, 0x1a10001f, 0x10006720,
+ 0x8203a001, 0x82239408, 0xd8205328, 0x17c07c1f, 0xa1538405, 0x1a10001f,
+ 0x10006b00, 0x8108a001, 0xd8205e84, 0x17c07c1f, 0x1910001f, 0x1000660c,
+ 0x1a10001f, 0x10006610, 0xa2002004, 0x89000008, 0x00001e00, 0xd8005944,
+ 0x17c07c1f, 0x82042001, 0xd8205948, 0x17c07c1f, 0x1900001f, 0x1020002c,
+ 0x1a10001f, 0x1020002c, 0xaa000008, 0x00000010, 0xe1000008, 0x1910001f,
+ 0x10006720, 0x820c1001, 0xd8205628, 0x17c07c1f, 0x1900001f, 0x10001250,
+ 0x1a10001f, 0x10001250, 0xa2110408, 0xe1000008, 0x1b80001f, 0x20000080,
+ 0x1900001f, 0x10001220, 0x1a10001f, 0x10001220, 0xa21e8408, 0xe1000008,
+ 0x1b80001f, 0x20000080, 0x1a40001f, 0x10006208, 0xc24024e0, 0x17c07c1f,
+ 0x1a10001f, 0x10006610, 0x82042001, 0xd8005e88, 0x17c07c1f, 0x1a10001f,
+ 0x10006918, 0x8a000008, 0x00000f0f, 0xba00010c, 0x1fffe7ff, 0xd8205e88,
+ 0x17c07c1f, 0x1a40001f, 0x10006208, 0xc24022a0, 0x17c07c1f, 0x1900001f,
+ 0x10001250, 0x1a10001f, 0x10001250, 0x8a000008, 0xfffffffb, 0xe1000008,
0x1b80001f, 0x20000080, 0x1900001f, 0x10001220, 0x1a10001f, 0x10001220,
- 0xa21e8408, 0xe1000008, 0x1b80001f, 0x20000080, 0x1a40001f, 0x10006208,
- 0xc24024c0, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81041001, 0xd8005ec4,
- 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8a000008, 0x00000f0f, 0xb900010c,
- 0x1fffe7ff, 0xd8205ec4, 0x17c07c1f, 0x1a40001f, 0x10006208, 0xc2402280,
- 0x17c07c1f, 0x1900001f, 0x10001250, 0x1a10001f, 0x10001250, 0x8a000008,
- 0xfffffffb, 0xe1000008, 0x1b80001f, 0x20000080, 0x1900001f, 0x10001220,
- 0x1a10001f, 0x10001220, 0x8a000008, 0xdfffffff, 0xe1000008, 0x1b80001f,
- 0x20000080, 0x1900001f, 0x1020002c, 0x1a10001f, 0x1020002c, 0x8a000008,
- 0xffffffef, 0xe1000008, 0x1a10001f, 0x10006b00, 0x81082001, 0xd8206144,
- 0x17c07c1f, 0x1a10001f, 0x10006610, 0x81082001, 0xb108a081, 0xd8006144,
- 0x17c07c1f, 0x1a10001f, 0x10006610, 0x8107a001, 0xd8206144, 0x17c07c1f,
- 0x1a40001f, 0x100062b0, 0xc2402fe0, 0x17c07c1f, 0x1b80001f, 0x20000208,
- 0xd8207dcc, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81079001, 0xd80062e4,
- 0x17c07c1f, 0x1a40001f, 0x100062b0, 0xc24035a0, 0x17c07c1f, 0x81001401,
- 0xd8206664, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x81002001, 0xb1042081,
- 0xb900008c, 0x1fffe7ff, 0xd8206664, 0x17c07c1f, 0x1a40001f, 0x10006200,
- 0x1a80001f, 0x1000625c, 0xc24027a0, 0x17c07c1f, 0x89400005, 0xfffffffe,
+ 0x8a000008, 0xdfffffff, 0xe1000008, 0x1b80001f, 0x20000080, 0x1900001f,
+ 0x1020002c, 0x1a10001f, 0x1020002c, 0x8a000008, 0xffffffef, 0xe1000008,
+ 0x1a10001f, 0x10006b00, 0x81082001, 0xd8205fa4, 0x17c07c1f, 0x1a40001f,
+ 0x100062b0, 0xc2402f20, 0x17c07c1f, 0x1b80001f, 0x20000208, 0xd8207b8c,
+ 0x17c07c1f, 0x1a40001f, 0x100062b0, 0xc2403700, 0x17c07c1f, 0x81001401,
+ 0xd8206424, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x81002001, 0xb1042081,
+ 0xb900008c, 0x1fffe7ff, 0xd8206424, 0x17c07c1f, 0x1a40001f, 0x10006200,
+ 0x1a80001f, 0x1000625c, 0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffffe,
0xe8208000, 0x10006f00, 0x00000000, 0xe8208000, 0x10006b30, 0x00000000,
- 0xe8208000, 0x100063e0, 0x00000001, 0x81009401, 0xd82069e4, 0x17c07c1f,
+ 0xe8208000, 0x100063e0, 0x00000001, 0x81009401, 0xd82067a4, 0x17c07c1f,
0x1a10001f, 0x10006918, 0x8100a001, 0xb104a081, 0xb900008c, 0x01000001,
- 0xd82069e4, 0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264,
- 0xc24027a0, 0x17c07c1f, 0x89400005, 0xfffffffd, 0xe8208000, 0x10006f04,
+ 0xd82067a4, 0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264,
+ 0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffffd, 0xe8208000, 0x10006f04,
0x00000000, 0xe8208000, 0x10006b34, 0x00000000, 0xe8208000, 0x100063e0,
- 0x00000002, 0x81011401, 0xd8206d64, 0x17c07c1f, 0x1a10001f, 0x10006918,
- 0x81012001, 0xb1052081, 0xb900008c, 0x01000001, 0xd8206d64, 0x17c07c1f,
- 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c, 0xc24027a0, 0x17c07c1f,
+ 0x00000002, 0x81011401, 0xd8206b24, 0x17c07c1f, 0x1a10001f, 0x10006918,
+ 0x81012001, 0xb1052081, 0xb900008c, 0x01000001, 0xd8206b24, 0x17c07c1f,
+ 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c, 0xc24026e0, 0x17c07c1f,
0x89400005, 0xfffffffb, 0xe8208000, 0x10006f08, 0x00000000, 0xe8208000,
0x10006b38, 0x00000000, 0xe8208000, 0x100063e0, 0x00000004, 0x81019401,
- 0xd82070e4, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8101a001, 0xb105a081,
- 0xb900008c, 0x01000001, 0xd82070e4, 0x17c07c1f, 0x1a40001f, 0x10006220,
- 0x1a80001f, 0x10006274, 0xc24027a0, 0x17c07c1f, 0x89400005, 0xfffffff7,
+ 0xd8206ea4, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8101a001, 0xb105a081,
+ 0xb900008c, 0x01000001, 0xd8206ea4, 0x17c07c1f, 0x1a40001f, 0x10006220,
+ 0x1a80001f, 0x10006274, 0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffff7,
0xe8208000, 0x10006f0c, 0x00000000, 0xe8208000, 0x10006b3c, 0x00000000,
- 0xe8208000, 0x100063e0, 0x00000008, 0x1910001f, 0x10006610, 0x81079001,
- 0xd8207844, 0x17c07c1f, 0x81021401, 0xd82074e4, 0x17c07c1f, 0x1a10001f,
- 0x10006918, 0x81022001, 0xb1062081, 0xb900008c, 0x01000001, 0xd82074e4,
- 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2402b20, 0x17c07c1f,
+ 0xe8208000, 0x100063e0, 0x00000008, 0x1a10001f, 0x10006610, 0x8207a001,
+ 0xd8207608, 0x17c07c1f, 0x81021401, 0xd82072a4, 0x17c07c1f, 0x1a10001f,
+ 0x10006918, 0x81022001, 0xb1062081, 0xb900008c, 0x01000001, 0xd82072a4,
+ 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2402a60, 0x17c07c1f,
0x89400005, 0xffffffef, 0xe8208000, 0x10006f10, 0x00000000, 0xe8208000,
0x10006b40, 0x00000000, 0xe8208000, 0x100063e0, 0x00000010, 0x81029401,
- 0xd8207844, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8102a001, 0xb106a081,
- 0xb900008c, 0x01000001, 0xd8207844, 0x17c07c1f, 0x1a40001f, 0x100062a4,
- 0x1290841f, 0xc2402b20, 0x17c07c1f, 0x89400005, 0xffffffdf, 0xe8208000,
+ 0xd8207604, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8102a001, 0xb106a081,
+ 0xb900008c, 0x01000001, 0xd8207604, 0x17c07c1f, 0x1a40001f, 0x100062a4,
+ 0x1290841f, 0xc2402a60, 0x17c07c1f, 0x89400005, 0xffffffdf, 0xe8208000,
0x10006f14, 0x00000000, 0xe8208000, 0x10006b44, 0x00000000, 0xe8208000,
- 0x100063e0, 0x00000020, 0x81031401, 0xd8207b04, 0x17c07c1f, 0x1a10001f,
- 0x10006918, 0x81032001, 0xb1072081, 0xb900008c, 0x01000001, 0xd8207b04,
+ 0x100063e0, 0x00000020, 0x81031401, 0xd82078c4, 0x17c07c1f, 0x1a10001f,
+ 0x10006918, 0x81032001, 0xb1072081, 0xb900008c, 0x01000001, 0xd82078c4,
0x17c07c1f, 0x89400005, 0xffffffbf, 0xe8208000, 0x10006f18, 0x00000000,
0xe8208000, 0x10006b48, 0x00000000, 0xe8208000, 0x100063e0, 0x00000040,
- 0x81039401, 0xd8207dc4, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8103a001,
- 0xb107a081, 0xb900008c, 0x01000001, 0xd8207dc4, 0x17c07c1f, 0x89400005,
+ 0x81039401, 0xd8207b84, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8103a001,
+ 0xb107a081, 0xb900008c, 0x01000001, 0xd8207b84, 0x17c07c1f, 0x89400005,
0xffffff7f, 0xe8208000, 0x10006f1c, 0x00000000, 0xe8208000, 0x10006b4c,
- 0x00000000, 0xe8208000, 0x100063e0, 0x00000080, 0xd0004220, 0x17c07c1f,
+ 0x00000000, 0xe8208000, 0x100063e0, 0x00000080, 0xd00041c0, 0x17c07c1f,
0xe8208000, 0x10006600, 0x00000000, 0x1ac0001f, 0x55aa55aa, 0x1940001f,
0xaa55aa55, 0x1b80001f, 0x00001000, 0xf0000000, 0x17c07c1f
};
static const struct pcm_desc mcdi_pcm = {
- .version = "pcm_mcdi_mt8173_20151203_v6",
+ .version = "pcm_mcdi_mt8173_20160401_v1",
.base = mcdi_binary,
.size = 1019,
.sess = 2,
diff --git a/plat/mediatek/mt8173/include/plat_macros.S b/plat/mediatek/mt8173/include/plat_macros.S
index 0e34b19..018a790 100644
--- a/plat/mediatek/mt8173/include/plat_macros.S
+++ b/plat/mediatek/mt8173/include/plat_macros.S
@@ -43,14 +43,18 @@
spacer:
.asciz ":\t\t0x"
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+ .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
/* ---------------------------------------------
- * The below macro prints out relevant GIC
- * registers whenever an unhandled exception is
- * taken in BL3-1.
+ * The below macro prints out relevant GIC and
+ * CCI registers whenever an unhandled exception
+ * is taken in BL3-1.
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
- .macro plat_print_gic_regs
+ .macro plat_crash_print_regs
mov_imm x16, BASE_GICD_BASE
mov_imm x17, BASE_GICC_BASE
/* Load the gicc reg list to x6 */
@@ -82,20 +86,7 @@
bl asm_print_str
b gicd_ispendr_loop
exit_print_gic_regs:
- .endm
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
- .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
- /* ------------------------------------------------
- * The below macro prints out relevant interconnect
- * registers whenever an unhandled exception is
- * taken in BL3-1.
- * Clobbers: x0 - x9, sp
- * ------------------------------------------------
- */
- .macro plat_print_interconnect_regs
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index ba9c13b..ab1d5d7 100644
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk
@@ -40,7 +40,8 @@
-I${MTK_PLAT_SOC}/drivers/uart/ \
-I${MTK_PLAT_SOC}/include/
-PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/aarch64/plat_common.c \
plat/common/plat_gic.c
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index fcebde3..2ecf5f5 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -40,7 +40,8 @@
-Iplat/nvidia/tegra/include \
-Iplat/nvidia/tegra/include/${TARGET_SOC}
-PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/aarch64/plat_common.c
COMMON_DIR := plat/nvidia/tegra/common
diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S
index 0868b41..1afe454 100644
--- a/plat/nvidia/tegra/include/plat_macros.S
+++ b/plat/nvidia/tegra/include/plat_macros.S
@@ -50,7 +50,7 @@
* taken in BL31.
* ---------------------------------------------
*/
-.macro plat_print_gic_regs
+.macro plat_crash_print_regs
mov_imm x16, TEGRA_GICC_BASE
cbz x16, 1f
/* gicc base address is now in x16 */
@@ -81,14 +81,4 @@
1:
.endm
-/* ------------------------------------------------
- * The below required platform porting macro prints
- * out relevant interconnect registers whenever an
- * unhandled exception is taken in BL3-1.
- * ------------------------------------------------
- */
-.macro plat_print_interconnect_regs
- nop
-.endm
-
#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index 6fa943f..fb47f48 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -52,7 +52,7 @@
/* Declarations for plat_setup.c */
const mmap_region_t *plat_get_mmio_map(void);
-uint64_t plat_get_syscnt_freq(void);
+unsigned long long plat_get_syscnt_freq(void);
/* Declarations for plat_secondary.c */
void plat_secondary_setup(void);
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index 6ff2831..5b10505 100644
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -74,7 +74,7 @@
return tegra_mmap;
}
-uint64_t plat_get_syscnt_freq(void)
+unsigned long long plat_get_syscnt_freq(void)
{
return 12000000;
}
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index 3fce8a2..eecedb3 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -80,7 +80,7 @@
/*******************************************************************************
* Handler to get the System Counter Frequency
******************************************************************************/
-uint64_t plat_get_syscnt_freq(void)
+unsigned long long plat_get_syscnt_freq(void)
{
return 19200000;
}
diff --git a/plat/rockchip/common/aarch64/platform_common.c b/plat/rockchip/common/aarch64/platform_common.c
index 3f912a4..ba4d1a4 100644
--- a/plat/rockchip/common/aarch64/platform_common.c
+++ b/plat/rockchip/common/aarch64/platform_common.c
@@ -75,7 +75,7 @@
/* Define EL3 variants of the function initialising the MMU */
DEFINE_CONFIGURE_MMU_EL(3)
-uint64_t plat_get_syscnt_freq(void)
+unsigned long long plat_get_syscnt_freq(void)
{
return SYS_COUNTER_FREQ_IN_TICKS;
}
diff --git a/plat/rockchip/common/include/plat_macros.S b/plat/rockchip/common/include/plat_macros.S
index ce68cf1..dcc959f 100644
--- a/plat/rockchip/common/include/plat_macros.S
+++ b/plat/rockchip/common/include/plat_macros.S
@@ -54,15 +54,19 @@
spacer:
.asciz ":\t\t0x"
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+ .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
/* ---------------------------------------------
* The below utility macro prints out relevant GIC
- * registers whenever an unhandled exception is
- * taken in BL31 on ARM standard platforms.
+ * and CCI registers whenever an unhandled
+ * exception is taken in BL31.
* Expects: GICD base in x16, GICC base in x17
* Clobbers: x0 - x10, sp
* ---------------------------------------------
*/
- .macro plat_print_gic_regs
+ .macro plat_crash_print_regs
mov_imm x16, PLAT_RK_GICD_BASE
mov_imm x17, PLAT_RK_GICC_BASE
@@ -119,20 +123,7 @@
bl asm_print_str
b gicd_ispendr_loop
exit_print_gic_regs:
- .endm
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
- .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
- /* ------------------------------------------------
- * The below macro prints out relevant interconnect
- * registers whenever an unhandled exception is
- * taken in BL3-1.
- * Clobbers: x0 - x9, sp
- * ------------------------------------------------
- */
- .macro plat_print_interconnect_regs
#if PLATFORM_CLUSTER_COUNT > 1
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h
index 876cbfb..299704d 100644
--- a/plat/rockchip/rk3368/include/platform_def.h
+++ b/plat/rockchip/rk3368/include/platform_def.h
@@ -101,7 +101,7 @@
/*
* Put BL3-1 at the top of the Trusted RAM
*/
-#define BL31_BASE (TZRAM_BASE + 0x8000)
+#define BL31_BASE (TZRAM_BASE + 0x10000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index 4fadf21..0d34cf4 100644
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -48,7 +48,8 @@
plat/common/plat_gicv2.c \
${RK_PLAT}/common/rockchip_gicv2.c
-PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/aarch64/plat_common.c \
plat/common/aarch64/plat_psci_common.c
diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h
index 13f3d50..f7da0e7 100644
--- a/plat/rockchip/rk3399/include/platform_def.h
+++ b/plat/rockchip/rk3399/include/platform_def.h
@@ -101,7 +101,7 @@
/*
* Put BL3-1 at the top of the Trusted RAM
*/
-#define BL31_BASE (TZRAM_BASE + 0x8000)
+#define BL31_BASE (TZRAM_BASE + 0x10000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index 7851726..6d7e134 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -47,7 +47,8 @@
plat/common/plat_gicv3.c \
${RK_PLAT}/common/rockchip_gicv3.c
-PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/aarch64/plat_common.c \
plat/common/aarch64/plat_psci_common.c
diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h
index 8562148..4ddb0dd 100644
--- a/plat/rockchip/rk3399/rk3399_def.h
+++ b/plat/rockchip/rk3399/rk3399_def.h
@@ -79,7 +79,7 @@
#define RK3399_UART2_BASE (0xff1a0000)
#define RK3399_UART2_SIZE SIZE_K(64)
-#define RK3399_BAUDRATE (1500000)
+#define RK3399_BAUDRATE (115200)
#define RK3399_UART_CLOCK (24000000)
/******************************************************************************
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 0a878c3..6e5cee3 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -297,9 +297,9 @@
mmio_write_32(IOU_SCNTRS_CONTROL, IOU_SCNTRS_CONTROL_EN);
}
-uint64_t plat_get_syscnt_freq(void)
+unsigned long long plat_get_syscnt_freq(void)
{
- uint64_t counter_base_frequency;
+ unsigned long long counter_base_frequency;
/* FIXME: Read the frequency from Frequency modes table */
counter_base_frequency = zynqmp_get_system_timer_freq();
diff --git a/plat/xilinx/zynqmp/include/plat_macros.S b/plat/xilinx/zynqmp/include/plat_macros.S
index e6c39bb..f40beba 100644
--- a/plat/xilinx/zynqmp/include/plat_macros.S
+++ b/plat/xilinx/zynqmp/include/plat_macros.S
@@ -36,16 +36,17 @@
/* ---------------------------------------------
* The below required platform porting macro
- * prints out relevant GIC registers whenever an
- * unhandled exception is taken in BL31.
- * Clobbers: x0 - x10, x16, sp
+ * prints out relevant GIC and CCI registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
- .macro plat_print_gic_regs
+ .macro plat_crash_print_regs
mov_imm x17, BASE_GICC_BASE
mov_imm x16, BASE_GICD_BASE
arm_print_gic_regs
- mov x0, x1
+ print_cci_regs
.endm
#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 0ffc0a9..febff29 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -60,7 +60,8 @@
-Iplat/xilinx/zynqmp/include/ \
-Iplat/xilinx/zynqmp/pm_service/
-PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
diff --git a/services/std_svc/psci/psci_main.c b/services/std_svc/psci/psci_main.c
index e6cd3a3..68ad5f6 100644
--- a/services/std_svc/psci/psci_main.c
+++ b/services/std_svc/psci/psci_main.c
@@ -47,7 +47,6 @@
{
int rc;
- unsigned int end_pwrlvl;
entry_point_info_t ep;
/* Determine if the cpu exists of not */
@@ -64,11 +63,7 @@
* To turn this cpu on, specify which power
* levels need to be turned on
*/
- end_pwrlvl = PLAT_MAX_PWR_LVL;
- rc = psci_cpu_on_start(target_cpu,
- &ep,
- end_pwrlvl);
- return rc;
+ return psci_cpu_on_start(target_cpu, &ep);
}
unsigned int psci_version(void)
diff --git a/services/std_svc/psci/psci_on.c b/services/std_svc/psci/psci_on.c
index 200e622..c8c36cd 100644
--- a/services/std_svc/psci/psci_on.c
+++ b/services/std_svc/psci/psci_on.c
@@ -67,13 +67,16 @@
* platform handler as it can return error.
******************************************************************************/
int psci_cpu_on_start(u_register_t target_cpu,
- entry_point_info_t *ep,
- unsigned int end_pwrlvl)
+ entry_point_info_t *ep)
{
int rc;
unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu);
aff_info_state_t target_aff_state;
+ /* Calling function must supply valid input arguments */
+ assert((int) target_idx >= 0);
+ assert(ep != NULL);
+
/*
* This function must only be called on platforms where the
* CPU_ON platform hooks have been implemented.
diff --git a/services/std_svc/psci/psci_private.h b/services/std_svc/psci/psci_private.h
index 4b91ad5..8a671b3 100644
--- a/services/std_svc/psci/psci_private.h
+++ b/services/std_svc/psci/psci_private.h
@@ -203,8 +203,7 @@
/* Private exported functions from psci_on.c */
int psci_cpu_on_start(unsigned long target_cpu,
- entry_point_info_t *ep,
- unsigned int end_pwrlvl);
+ entry_point_info_t *ep);
void psci_cpu_on_finish(unsigned int cpu_idx,
psci_power_state_t *state_info);
diff --git a/tools/fip_create/fip_create.c b/tools/fip_create/fip_create.c
index 7bce348..48cb3f6 100644
--- a/tools/fip_create/fip_create.c
+++ b/tools/fip_create/fip_create.c
@@ -811,7 +811,7 @@
if (fip_filename == NULL) {
printf("ERROR: Missing FIP filename\n");
print_usage();
- return 0;
+ return EINVAL;
}
/* Unpack images from FIP always takes precedence over packaging. In