Merge pull request #382 from vikramkanigiri/vk/tf-issues-312
Configure all secure interrupts on ARM platforms
diff --git a/drivers/arm/gic/arm_gic.c b/drivers/arm/gic/arm_gic.c
index 90fc8b5..ecd5a93 100644
--- a/drivers/arm/gic/arm_gic.c
+++ b/drivers/arm/gic/arm_gic.c
@@ -62,7 +62,7 @@
******************************************************************************/
static void gicv3_cpuif_setup(void)
{
- unsigned int scr_val, val;
+ unsigned int val;
uintptr_t base;
/*
@@ -93,35 +93,9 @@
while (val & WAKER_CA)
val = gicr_read_waker(base);
- /*
- * We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
- * Restore SCR_EL3.NS again before exit.
- */
- scr_val = read_scr();
- write_scr(scr_val | SCR_NS_BIT);
- isb(); /* ensure NS=1 takes effect before accessing ICC_SRE_EL2 */
-
- /*
- * By default EL2 and NS-EL1 software should be able to enable GICv3
- * System register access without any configuration at EL3. But it turns
- * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So
- * we need to set it here again. In order to do that we need to enable
- * register access. We leave it enabled as it should be fine and might
- * prevent problems with later software trying to access GIC System
- * Registers.
- */
val = read_icc_sre_el3();
write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
-
- val = read_icc_sre_el2();
- write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
-
- write_icc_pmr_el1(GIC_PRI_MASK);
- isb(); /* commit ICC_* changes before setting NS=0 */
-
- /* Restore SCR_EL3 */
- write_scr(scr_val);
- isb(); /* ensure NS=0 takes effect immediately */
+ isb();
}
/*******************************************************************************
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 6e71f9c..169d8f4 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -34,6 +34,15 @@
/* Cortex-A53 midr for revision 0 */
#define CORTEX_A53_MIDR 0x410FD030
+/* Retention timer tick definitions */
+#define RETENTION_ENTRY_TICKS_2 0x1
+#define RETENTION_ENTRY_TICKS_8 0x2
+#define RETENTION_ENTRY_TICKS_32 0x3
+#define RETENTION_ENTRY_TICKS_64 0x4
+#define RETENTION_ENTRY_TICKS_128 0x5
+#define RETENTION_ENTRY_TICKS_256 0x6
+#define RETENTION_ENTRY_TICKS_512 0x7
+
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
@@ -41,6 +50,12 @@
#define CPUECTLR_SMP_BIT (1 << 6)
+#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
+#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
+
+#define CPUECTLR_FPU_RET_CTRL_SHIFT 3
+#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
+
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
@@ -56,4 +71,12 @@
#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
+/*******************************************************************************
+ * L2 Extended Control register specific definitions.
+ ******************************************************************************/
+#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */
+
+#define L2ECTLR_RET_CTRL_SHIFT 0
+#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
+
#endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 6128b16..c81259c 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -34,6 +34,15 @@
/* Cortex-A57 midr for revision 0 */
#define CORTEX_A57_MIDR 0x410FD070
+/* Retention timer tick definitions */
+#define RETENTION_ENTRY_TICKS_2 0x1
+#define RETENTION_ENTRY_TICKS_8 0x2
+#define RETENTION_ENTRY_TICKS_32 0x3
+#define RETENTION_ENTRY_TICKS_64 0x4
+#define RETENTION_ENTRY_TICKS_128 0x5
+#define RETENTION_ENTRY_TICKS_256 0x6
+#define RETENTION_ENTRY_TICKS_512 0x7
+
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
@@ -44,6 +53,9 @@
#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
+#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
+#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
+
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
@@ -63,4 +75,12 @@
#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
+/*******************************************************************************
+ * L2 Extended Control register specific definitions.
+ ******************************************************************************/
+#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */
+
+#define L2ECTLR_RET_CTRL_SHIFT 0
+#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
+
#endif /* __CORTEX_A57_H__ */
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 2979b32..d9f287c 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -57,6 +57,28 @@
*/
.macro cpu_init_common
+#if ENABLE_L2_DYNAMIC_RETENTION
+ /* ---------------------------
+ * Enable processor retention
+ * ---------------------------
+ */
+ mrs x0, L2ECTLR_EL1
+ mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT
+ bic x0, x0, #L2ECTLR_RET_CTRL_MASK
+ orr x0, x0, x1
+ msr L2ECTLR_EL1, x0
+ isb
+#endif
+
+#if ENABLE_CPU_DYNAMIC_RETENTION
+ mrs x0, CPUECTLR_EL1
+ mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT
+ bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK
+ orr x0, x0, x1
+ msr CPUECTLR_EL1, x0
+ isb
+#endif
+
#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
/* -------------------------------------------------------
* Enable L2 and CPU ECTLR RW access from non-secure world
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c
index fff8951..0d8e370 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c
@@ -118,6 +118,7 @@
uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20);
uintptr_t vmem_end_new = phys_base + size_in_bytes;
uint32_t regval;
+ uint64_t size;
/*
* The GPU is the user of the Video Memory region. In order to
@@ -153,12 +154,18 @@
INFO("Cleaning previous Video Memory Carveout\n");
disable_mmu_el3();
- if (phys_base > vmem_end_old || video_mem_base > vmem_end_new)
+ if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) {
zeromem16((void *)video_mem_base, video_mem_size << 20);
- else if (video_mem_base < phys_base)
- zeromem16((void *)video_mem_base, phys_base - video_mem_base);
- else if (vmem_end_old > vmem_end_new)
- zeromem16((void *)vmem_end_new, vmem_end_old - vmem_end_new);
+ } else {
+ if (video_mem_base < phys_base) {
+ size = phys_base - video_mem_base;
+ zeromem16((void *)video_mem_base, size);
+ }
+ if (vmem_end_old > vmem_end_new) {
+ size = vmem_end_old - vmem_end_new;
+ zeromem16((void *)vmem_end_new, size);
+ }
+ }
enable_mmu_el3(0);
done:
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index ca7718c..5001629 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -40,6 +40,12 @@
ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1
$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
+ENABLE_L2_DYNAMIC_RETENTION := 1
+$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION))
+
+ENABLE_CPU_DYNAMIC_RETENTION := 1
+$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION))
+
PLATFORM_CLUSTER_COUNT := 2
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))