tree 01b019470b10c2eacf5375673a71b080894cdd74
parent 7052d9d0334266c15e0757211a8eca31058df291
author Lin Huang <hl@rock-chips.com> 1487759095 +0800
committer Caesar Wang <wxt@rock-chips.com> 1496887174 +0800

rockchip/rk3399: fix DRAM gate training issue

The differential signal of DQS need keep low level
before gate training. It need enable RPULL and disable
PHY side ODT to ensure it when do gate training.
But it can not access the PHY registers to do it when
perform DFS.So the workaroud as below: It is ensure that
the PHY's read gate is landing somewhere in the incoming
DQS's pulses before it starts searching for pre-amble window.
It need get the rddqs_delay_ps to calculate the start point
of gate training for DFS.

Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe
Signed-off-by: Lin Huang <hl@rock-chips.com>