feat(st-ddr): add read valid training support
Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
diff --git a/include/drivers/st/stm32mp1_ddr_regs.h b/include/drivers/st/stm32mp1_ddr_regs.h
index 01d6638..e821206 100644
--- a/include/drivers/st/stm32mp1_ddr_regs.h
+++ b/include/drivers/st/stm32mp1_ddr_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -353,6 +353,7 @@
#define DDRPHYC_PIR_DRAMRST BIT(5)
#define DDRPHYC_PIR_DRAMINIT BIT(6)
#define DDRPHYC_PIR_QSTRN BIT(7)
+#define DDRPHYC_PIR_RVTRN BIT(8)
#define DDRPHYC_PIR_ICPC BIT(16)
#define DDRPHYC_PIR_ZCALBYP BIT(30)
#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)