tree 3bbdff926dcaefa762ff621451ca430a389ee60f
parent 94f1c2aec328c817efdad98fa3939495f6da01df
author Manish V Badarkhe <Manish.Badarkhe@arm.com> 1624474959 +0100
committer Manish V Badarkhe <Manish.Badarkhe@arm.com> 1629910876 +0100

feat(trbe): initialize trap settings of trace buffer control registers access

Trap bits of trace buffer control registers access are in
architecturally UNKNOWN state at boot hence

1. Initialized these bits to zero to prohibit trace buffer control
   registers accesses in lower ELs (EL2, EL1) in all security states
   when FEAT_TRBE is implemented
2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and
   hence setting it to zero also aligns with the Arm ARM reference
   recommendation, that mentions software must writes RES0 bits with
   all 0s

Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>