Remove coherent stack usage from the warm boot path
This patch uses stacks allocated in normal memory to enable the MMU early in the
warm boot path thus removing the dependency on stacks allocated in coherent
memory. Necessary cache and stack maintenance is performed when a cpu is being
powered down and up. This avoids any coherency issues that can arise from
reading speculatively fetched stale stack memory from another CPUs cache. These
changes affect the warm boot path in both BL3-1 and BL3-2.
The EL3 system registers responsible for preserving the MMU state are not saved
and restored any longer. Static values are used to program these system
registers when a cpu is powered on or resumed from suspend.
Change-Id: I8357e2eb5eb6c5f448492c5094b82b8927603784
diff --git a/services/std_svc/psci/psci_afflvl_suspend.c b/services/std_svc/psci/psci_afflvl_suspend.c
index 0977198..ab731fb 100644
--- a/services/std_svc/psci/psci_afflvl_suspend.c
+++ b/services/std_svc/psci/psci_afflvl_suspend.c
@@ -126,8 +126,7 @@
unsigned int power_state)
{
unsigned int plat_state;
- unsigned long psci_entrypoint, sctlr;
- el3_state_t *saved_el3_state;
+ unsigned long psci_entrypoint;
uint32_t ns_scr_el3 = read_scr_el3();
uint32_t ns_sctlr_el1 = read_sctlr_el1();
int rc;
@@ -170,39 +169,16 @@
*/
cm_el3_sysregs_context_save(NON_SECURE);
- /*
- * The EL3 state to PoC since it will be accessed after a
- * reset with the caches turned off
- */
- saved_el3_state = get_el3state_ctx(cm_get_context(NON_SECURE));
- flush_dcache_range((uint64_t) saved_el3_state, sizeof(*saved_el3_state));
-
/* Set the secure world (EL3) re-entry point after BL1 */
psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry;
/*
* Arch. management. Perform the necessary steps to flush all
* cpu caches.
- *
- * TODO: This power down sequence varies across cpus so it needs to be
- * abstracted out on the basis of the MIDR like in cpu_reset_handler().
- * Do the bare minimal for the time being. Fix this before porting to
- * Cortex models.
*/
- sctlr = read_sctlr_el3();
- sctlr &= ~SCTLR_C_BIT;
- write_sctlr_el3(sctlr);
- isb(); /* ensure MMU disable takes immediate effect */
+ psci_do_pwrdown_cache_maintenance(MPIDR_AFFLVL0);
/*
- * CAUTION: This flush to the level of unification makes an assumption
- * about the cache hierarchy at affinity level 0 (cpu) in the platform.
- * Ideally the platform should tell psci which levels to flush to exit
- * coherency.
- */
- dcsw_op_louis(DCCISW);
-
- /*
* Plat. management: Allow the platform to perform the
* necessary actions to turn off this cpu e.g. set the
* platform defined mailbox with the psci entrypoint,
@@ -467,9 +443,11 @@
/* Get the index for restoring the re-entry information */
/*
- * Arch. management: Restore the stashed EL3 architectural
- * context from the 'cpu_context' structure for this cpu.
+ * Arch. management: Enable the data cache, manage stack memory and
+ * restore the stashed EL3 architectural context from the 'cpu_context'
+ * structure for this cpu.
*/
+ psci_do_pwrup_cache_maintenance();
cm_el3_sysregs_context_restore(NON_SECURE);
/*
@@ -575,4 +553,3 @@
psci_afflvl1_suspend_finish,
psci_afflvl2_suspend_finish,
};
-