commit e0b757d293f16f056f2ea1c80ebad96ca4174796
author Antonio Nino Diaz <antonio.ninodiaz@arm.com> Fri Aug 24 16:30:29 2018 +0100
committer Antonio Nino Diaz <antonio.ninodiaz@arm.com> Thu Aug 30 09:22:33 2018 +0100
tree 9eacb4a8d992cf64f1bd719134baf8eb31292251
parent 8cdabb246b0ce37bb7e183d7a0503fca538f4d9b

Fix MISRA defects in BL31 common code

Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

plat/socionext/uniphier/uniphier_bl31_setup.c

diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index d9c87bd..9e28eec 100644
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +17,6 @@
 
 #include "uniphier.h"
 
-#define BL31_END		(unsigned long)(&__BL31_END__)
 #define BL31_SIZE		((BL31_END) - (BL31_BASE))
 
 static entry_point_info_t bl32_image_ep_info;
@@ -70,7 +69,7 @@
 
 	/* Enable and initialize the System level generic timer */
 	mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
-			CNTCR_FCREQ(0) | CNTCR_EN);
+			CNTCR_FCREQ(0U) | CNTCR_EN);
 }
 
 void bl31_plat_arch_setup(void)