Fix MISRA defects in BL31 common code
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 0664741..650181d 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -103,9 +103,14 @@
/*
* If SPD had registerd an init hook, invoke it.
*/
- if (bl32_init) {
+ if (bl32_init != NULL) {
INFO("BL31: Initializing BL32\n");
- (*bl32_init)();
+
+ int32_t rc = (*bl32_init)();
+
+ if (rc != 0) {
+ ERROR("BL31: BL32 initialization failed (rc = %d)", rc);
+ }
}
/*
* We are ready to enter the next EL. Prepare entry into the image
@@ -167,7 +172,7 @@
/* Program EL3 registers to enable entry into the next EL */
next_image_info = bl31_plat_get_next_image_ep_info(image_type);
- assert(next_image_info);
+ assert(next_image_info != NULL);
assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr));
INFO("BL31: Preparing for EL3 exit to %s world\n",
diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c
index b885a66..0df50b6 100644
--- a/bl31/interrupt_mgmt.c
+++ b/bl31/interrupt_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,6 @@
#include <errno.h>
#include <interrupt_mgmt.h>
#include <platform.h>
-#include <stdio.h>
/*******************************************************************************
* Local structure and corresponding array to keep track of the state of the
@@ -47,8 +46,8 @@
******************************************************************************/
static int32_t validate_interrupt_type(uint32_t type)
{
- if (type == INTR_TYPE_S_EL1 || type == INTR_TYPE_NS ||
- type == INTR_TYPE_EL3)
+ if ((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_NS) ||
+ (type == INTR_TYPE_EL3))
return 0;
return -EINVAL;
@@ -59,17 +58,16 @@
******************************************************************************/
static int32_t validate_routing_model(uint32_t type, uint32_t flags)
{
- flags >>= INTR_RM_FLAGS_SHIFT;
- flags &= INTR_RM_FLAGS_MASK;
+ uint32_t rm_flags = (flags >> INTR_RM_FLAGS_SHIFT) & INTR_RM_FLAGS_MASK;
if (type == INTR_TYPE_S_EL1)
- return validate_sel1_interrupt_rm(flags);
+ return validate_sel1_interrupt_rm(rm_flags);
if (type == INTR_TYPE_NS)
- return validate_ns_interrupt_rm(flags);
+ return validate_ns_interrupt_rm(rm_flags);
if (type == INTR_TYPE_EL3)
- return validate_el3_interrupt_rm(flags);
+ return validate_el3_interrupt_rm(rm_flags);
return -EINVAL;
}
@@ -106,10 +104,12 @@
bit_pos = plat_interrupt_type_to_line(type, security_state);
intr_type_descs[type].scr_el3[security_state] = flag << bit_pos;
- /* Update scr_el3 only if there is a context available. If not, it
+ /*
+ * Update scr_el3 only if there is a context available. If not, it
* will be updated later during context initialization which will obtain
- * the scr_el3 value to be used via get_scr_el3_from_routing_model() */
- if (cm_get_context(security_state))
+ * the scr_el3 value to be used via get_scr_el3_from_routing_model()
+ */
+ if (cm_get_context(security_state) != NULL)
cm_write_scr_el3_bit(security_state, bit_pos, flag);
}
@@ -124,11 +124,11 @@
int32_t rc;
rc = validate_interrupt_type(type);
- if (rc)
+ if (rc != 0)
return rc;
rc = validate_routing_model(type, flags);
- if (rc)
+ if (rc != 0)
return rc;
/* Update the routing model in internal data structures */
@@ -149,7 +149,7 @@
{
uint32_t bit_pos, flag;
- assert(intr_type_descs[type].handler);
+ assert(intr_type_descs[type].handler != NULL);
flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state);
@@ -167,7 +167,7 @@
{
uint32_t bit_pos, flag;
- assert(intr_type_descs[type].handler);
+ assert(intr_type_descs[type].handler != NULL);
flag = get_interrupt_rm_flag(intr_type_descs[type].flags,
security_state);
@@ -190,19 +190,19 @@
int32_t rc;
/* Validate the 'handler' parameter */
- if (!handler)
+ if (handler == NULL)
return -EINVAL;
/* Validate the 'flags' parameter */
- if (flags & INTR_TYPE_FLAGS_MASK)
+ if ((flags & INTR_TYPE_FLAGS_MASK) != 0U)
return -EINVAL;
/* Check if a handler has already been registered */
- if (intr_type_descs[type].handler)
+ if (intr_type_descs[type].handler != NULL)
return -EALREADY;
rc = set_routing_model(type, flags);
- if (rc)
+ if (rc != 0)
return rc;
/* Save the handler */
@@ -218,7 +218,7 @@
******************************************************************************/
interrupt_type_handler_t get_interrupt_type_handler(uint32_t type)
{
- if (validate_interrupt_type(type))
+ if (validate_interrupt_type(type) != 0)
return NULL;
return intr_type_descs[type].handler;
diff --git a/include/bl31/ehf.h b/include/bl31/ehf.h
index c60b04c..f35d810 100644
--- a/include/bl31/ehf.h
+++ b/include/bl31/ehf.h
@@ -14,7 +14,7 @@
#include <utils_def.h>
/* Valid priorities set bit 0 of the priority handler. */
-#define EHF_PRI_VALID_ (((uintptr_t) 1) << 0)
+#define EHF_PRI_VALID_ BIT(0)
/* Marker for no handler registered for a valid priority */
#define EHF_NO_HANDLER_ (0U | EHF_PRI_VALID_)
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 49ba9f7..0cdbda0 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -8,6 +8,7 @@
#define __INTERRUPT_MGMT_H__
#include <arch.h>
+#include <utils_def.h>
/*******************************************************************************
* Constants for the types of interrupts recognised by the IM framework
@@ -66,34 +67,6 @@
#define set_interrupt_rm_flag(flag, ss) ((flag) |= U(1) << (ss))
#define clr_interrupt_rm_flag(flag, ss) ((flag) &= ~(U(1) << (ss)))
-
-/*******************************************************************************
- * Macros to validate the routing model bits in the 'flags' for a type
- * of interrupt. If the model does not match one of the valid masks
- * -EINVAL is returned.
- ******************************************************************************/
-#define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \
- ((x) == INTR_SEL1_VALID_RM1 ? 0 :\
- -EINVAL))
-
-#define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \
- ((x) == INTR_NS_VALID_RM1 ? 0 :\
- -EINVAL))
-
-#if EL3_EXCEPTION_HANDLING
-/*
- * With EL3 exception handling, EL3 interrupts are always routed to EL3 from
- * both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is the only
- * valid routing model.
- */
-#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM1 ? 0 : \
- -EINVAL)
-#else
-#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \
- ((x) == INTR_EL3_VALID_RM1 ? 0 :\
- -EINVAL))
-#endif
-
/*******************************************************************************
* Macros to set the 'flags' parameter passed to an interrupt type handler. Only
* the flag to indicate the security state when the exception was generated is
@@ -108,9 +81,51 @@
#ifndef __ASSEMBLY__
+#include <errno.h>
#include <stdint.h>
+/*******************************************************************************
+ * Helpers to validate the routing model bits in the 'flags' for a type
+ * of interrupt. If the model does not match one of the valid masks
+ * -EINVAL is returned.
+ ******************************************************************************/
+static inline int32_t validate_sel1_interrupt_rm(uint32_t x)
+{
+ if ((x == INTR_SEL1_VALID_RM0) || (x == INTR_SEL1_VALID_RM1))
+ return 0;
+
+ return -EINVAL;
+}
+
+static inline int32_t validate_ns_interrupt_rm(uint32_t x)
+{
+ if ((x == INTR_NS_VALID_RM0) || (x == INTR_NS_VALID_RM1))
+ return 0;
+
+ return -EINVAL;
+}
+
-/* Prototype for defining a handler for an interrupt type */
+static inline int32_t validate_el3_interrupt_rm(uint32_t x)
+{
+#if EL3_EXCEPTION_HANDLING
+ /*
+ * With EL3 exception handling, EL3 interrupts are always routed to EL3
+ * from both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is
+ * the only valid routing model.
+ */
+ if (x == INTR_EL3_VALID_RM1)
+ return 0;
+#else
+ if ((x == INTR_EL3_VALID_RM0) || (x == INTR_EL3_VALID_RM1))
+ return 0;
+#endif
+
+ return -EINVAL;
+}
+
+/*******************************************************************************
+ * Prototype for defining a handler for an interrupt type
+ ******************************************************************************/
typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
uint32_t flags,
void *handle,
diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index bcba60a..ea11708 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -34,6 +34,6 @@
fvp_interconnect_enable();
/* On FVP RevC, intialize SMMUv3 */
- if (arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3)
+ if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
smmuv3_init(PLAT_FVP_SMMUV3_BASE);
}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index c7c45b0..4e16e3b 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -16,8 +16,6 @@
#include <platform.h>
#include <ras.h>
-#define BL31_END (uintptr_t)(&__BL31_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
@@ -152,7 +150,7 @@
* Copy BL33 and BL32 (if present), entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
- while (bl_params) {
+ while (bl_params != NULL) {
if (bl_params->image_id == BL32_IMAGE_ID)
bl32_image_ep_info = *bl_params->ep_info;
@@ -162,7 +160,7 @@
bl_params = bl_params->next_params_info;
}
- if (bl33_image_ep_info.pc == 0)
+ if (bl33_image_ep_info.pc == 0U)
panic();
# else /* LOAD_IMAGE_V2 */
@@ -175,8 +173,8 @@
assert(from_bl2->h.version >= VERSION_1);
/* Dynamic Config is not supported for LOAD_IMAGE_V1 */
- assert(soc_fw_config == 0);
- assert(hw_config == 0);
+ assert(soc_fw_config == 0U);
+ assert(hw_config == 0U);
/*
* Copy BL32 (if populated by BL2) and BL33 entry point information.
@@ -236,7 +234,7 @@
/* Enable and initialize the System level generic timer */
mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0) | CNTCR_EN);
+ CNTCR_FCREQ(0U) | CNTCR_EN);
/* Allow access to the System counter timer module */
arm_configure_sys_timer();
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index 5191d69..10c1914 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -5,6 +5,7 @@
*/
#include <assert.h>
+#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <mmio.h>
@@ -13,8 +14,6 @@
#include <platform_def.h>
#include <platform_sp_min.h>
-#define BL32_END (uintptr_t)(&__BL32_END__)
-
static entry_point_info_t bl33_image_ep_info;
/* Weak definitions may be overridden in specific ARM standard platform */
@@ -181,7 +180,7 @@
/* Enable and initialize the System level generic timer */
mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0) | CNTCR_EN);
+ CNTCR_FCREQ(0U) | CNTCR_EN);
/* Allow access to the System counter timer module */
arm_configure_sys_timer();
diff --git a/plat/layerscape/common/ls_bl31_setup.c b/plat/layerscape/common/ls_bl31_setup.c
index 3016f58..25fe407 100644
--- a/plat/layerscape/common/ls_bl31_setup.c
+++ b/plat/layerscape/common/ls_bl31_setup.c
@@ -5,6 +5,7 @@
*/
#include <assert.h>
+#include <bl_common.h>
#include <console.h>
#include <mmio.h>
#include <gicv2.h>
@@ -12,8 +13,6 @@
#include "plat_ls.h"
#include "soc.h"
-#define BL31_END (uintptr_t)(&__BL31_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
@@ -168,7 +167,7 @@
/* Enable and initialize the System level generic timer */
mmio_write_32(LS1043_SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0) | CNTCR_EN);
+ CNTCR_FCREQ(0U) | CNTCR_EN);
VERBOSE("Leave arm_bl31_platform_setup\n");
}
diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c
index 30d06e9..26b8ff1 100644
--- a/plat/socionext/synquacer/sq_bl31_setup.c
+++ b/plat/socionext/synquacer/sq_bl31_setup.c
@@ -137,7 +137,7 @@
/* Enable and initialize the System level generic timer */
mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0) | CNTCR_EN);
+ CNTCR_FCREQ(0U) | CNTCR_EN);
/* Allow access to the System counter timer module */
sq_configure_sys_timer();
diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index d9c87bd..9e28eec 100644
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,7 +17,6 @@
#include "uniphier.h"
-#define BL31_END (unsigned long)(&__BL31_END__)
#define BL31_SIZE ((BL31_END) - (BL31_BASE))
static entry_point_info_t bl32_image_ep_info;
@@ -70,7 +69,7 @@
/* Enable and initialize the System level generic timer */
mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0) | CNTCR_EN);
+ CNTCR_FCREQ(0U) | CNTCR_EN);
}
void bl31_plat_arch_setup(void)