diff --git a/plat/arm/board/morello/morello_bl31_setup.c b/plat/arm/board/morello/morello_bl31_setup.c
index 0eedfaf..05a6f4b 100644
--- a/plat/arm/board/morello/morello_bl31_setup.c
+++ b/plat/arm/board/morello/morello_bl31_setup.c
@@ -23,12 +23,14 @@
  *	- Remote DDR size in bytes, DDR memory in slave board
  *	- slave_count
  *	- multichip mode
+ *	- scc configuration
  */
 struct morello_plat_info {
 	uint64_t local_ddr_size;
 	uint64_t remote_ddr_size;
 	uint8_t slave_count;
 	bool multichip_mode;
+	uint32_t scc_config;
 } __packed;
 
 /* Compile time assertion to ensure the size of structure is 18 bytes */
@@ -79,6 +81,8 @@
 {
 	uint64_t dram2_size;
 	uint32_t val;
+	uint64_t tag_mem_base;
+	uint64_t usable_mem_size;
 
 	INFO("Total DIMM size: %uGB\n",
 			(uint32_t)(plat_info->local_ddr_size / 0x40000000));
@@ -115,6 +119,63 @@
 		continue;
 	}
 
+	/* Configure Bing client/server mode based on SCC configuration */
+	if (plat_info->scc_config & MORELLO_SCC_CLIENT_MODE_MASK) {
+		INFO("Configuring DMC Bing in client mode\n");
+		usable_mem_size = plat_info->local_ddr_size -
+			(plat_info->local_ddr_size / 128ULL);
+
+		/* Linear DDR address */
+		tag_mem_base = usable_mem_size;
+		tag_mem_base = tag_mem_base / 4;
+
+		/* Reverse translation */
+		if (tag_mem_base < ARM_DRAM1_BASE) {
+			tag_mem_base += ARM_DRAM1_BASE;
+		} else {
+			tag_mem_base = tag_mem_base - ARM_DRAM1_BASE +
+				ARM_DRAM2_BASE;
+		}
+
+		mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x1);
+		mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x1);
+		mmio_write_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x1);
+		mmio_write_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x1);
+
+		if (plat_info->scc_config & MORELLO_SCC_C1_TAG_CACHE_EN_MASK) {
+			mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2);
+			mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2);
+			INFO("C1 Tag Cache Enabled\n");
+		}
+
+		if (plat_info->scc_config & MORELLO_SCC_C2_TAG_CACHE_EN_MASK) {
+			mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4);
+			mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4);
+			INFO("C2 Tag Cache Enabled\n");
+		}
+
+		mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL,
+				(uint32_t)tag_mem_base);
+		mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL,
+				(uint32_t)tag_mem_base);
+		mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL2,
+				(uint32_t)(tag_mem_base >> 32));
+		mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL2,
+				(uint32_t)(tag_mem_base >> 32));
+
+		mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL,
+				MORELLO_DMC_MEM_ACCESS_DIS);
+		mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL,
+				MORELLO_DMC_MEM_ACCESS_DIS);
+
+		INFO("Tag base set to 0x%lx\n", tag_mem_base);
+		plat_info->local_ddr_size = usable_mem_size;
+	} else {
+		INFO("Configuring DMC Bing in server mode\n");
+		mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x0);
+		mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x0);
+	}
+
 	INFO("Enabling ECC on DMCs\n");
 	/* Enable ECC in DMCs */
 	mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG,
diff --git a/plat/arm/board/morello/morello_def.h b/plat/arm/board/morello/morello_def.h
index 326789c..1be7c00 100644
--- a/plat/arm/board/morello/morello_def.h
+++ b/plat/arm/board/morello/morello_def.h
@@ -18,7 +18,7 @@
 /* SDS Platform information defines */
 #define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID	U(8)
 #define MORELLO_SDS_PLATFORM_INFO_OFFSET	U(0)
-#define MORELLO_SDS_PLATFORM_INFO_SIZE		U(18)
+#define MORELLO_SDS_PLATFORM_INFO_SIZE		U(22)
 #define MORELLO_MAX_DDR_CAPACITY		U(0x1000000000)
 #define MORELLO_MAX_SLAVE_COUNT			U(16)
 
@@ -27,29 +27,64 @@
 #define MORELLO_SDS_BL33_INFO_OFFSET		U(0)
 #define MORELLO_SDS_BL33_INFO_SIZE		U(12)
 
+#define MORELLO_SCC_SERVER_MODE			U(0)
+#define MORELLO_SCC_CLIENT_MODE_MASK		U(1)
+#define MORELLO_SCC_C1_TAG_CACHE_EN_MASK	U(4)
+#define MORELLO_SCC_C2_TAG_CACHE_EN_MASK	U(8)
+
 /* Base address of non-secure SRAM where Platform information will be filled */
 #define MORELLO_PLATFORM_INFO_BASE		UL(0x06000000)
 
 /* DMC memory status registers */
-#define MORELLO_DMC0_MEMC_STATUS_REG		0x4E000000
-#define MORELLO_DMC1_MEMC_STATUS_REG		0x4E100000
+#define MORELLO_DMC0_MEMC_STATUS_REG		UL(0x4E000000)
+#define MORELLO_DMC1_MEMC_STATUS_REG		UL(0x4E100000)
 
 #define MORELLO_DMC_MEMC_STATUS_MASK		U(7)
 
 /* DMC memory command registers */
-#define MORELLO_DMC0_MEMC_CMD_REG		0x4E000008
-#define MORELLO_DMC1_MEMC_CMD_REG		0x4E100008
+#define MORELLO_DMC0_MEMC_CMD_REG		UL(0x4E000008)
+#define MORELLO_DMC1_MEMC_CMD_REG		UL(0x4E100008)
+
+/* DMC capability control register */
+#define MORELLO_DMC0_CAP_CTRL_REG		UL(0x4E000D00)
+#define MORELLO_DMC1_CAP_CTRL_REG		UL(0x4E100D00)
+
+/* DMC tag cache control register */
+#define MORELLO_DMC0_TAG_CACHE_CTL		UL(0x4E000D04)
+#define MORELLO_DMC1_TAG_CACHE_CTL		UL(0x4E100D04)
+
+/* DMC tag cache config register */
+#define MORELLO_DMC0_TAG_CACHE_CFG		UL(0x4E000D08)
+#define MORELLO_DMC1_TAG_CACHE_CFG		UL(0x4E100D08)
+
+/* DMC memory access control register */
+#define MORELLO_DMC0_MEM_ACCESS_CTL		UL(0x4E000D0C)
+#define MORELLO_DMC1_MEM_ACCESS_CTL		UL(0x4E100D0C)
+
+#define MORELLO_DMC_MEM_ACCESS_DIS		(1UL << 16)
+
+/* DMC memory address control register */
+#define MORELLO_DMC0_MEM_ADDR_CTL		UL(0x4E000D10)
+#define MORELLO_DMC1_MEM_ADDR_CTL		UL(0x4E100D10)
+
+/* DMC memory address control 2 register */
+#define MORELLO_DMC0_MEM_ADDR_CTL2		UL(0x4E000D14)
+#define MORELLO_DMC1_MEM_ADDR_CTL2		UL(0x4E100D14)
+
+/* DMC special control register */
+#define MORELLO_DMC0_SPL_CTL_REG		UL(0x4E000D18)
+#define MORELLO_DMC1_SPL_CTL_REG		UL(0x4E100D18)
 
 /* DMC ERR0CTLR0 registers */
-#define MORELLO_DMC0_ERR0CTLR0_REG		0x4E000708
-#define MORELLO_DMC1_ERR0CTLR0_REG		0x4E100708
+#define MORELLO_DMC0_ERR0CTLR0_REG		UL(0x4E000708)
+#define MORELLO_DMC1_ERR0CTLR0_REG		UL(0x4E100708)
 
 /* DMC ECC in ERR0CTLR0 register */
 #define MORELLO_DMC_ERR0CTLR0_ECC_EN		U(9)
 
 /* DMC ERR2STATUS register */
-#define MORELLO_DMC0_ERR2STATUS_REG		0x4E000790
-#define MORELLO_DMC1_ERR2STATUS_REG		0x4E100790
+#define MORELLO_DMC0_ERR2STATUS_REG		UL(0x4E000790)
+#define MORELLO_DMC1_ERR2STATUS_REG		UL(0x4E100790)
 
 /* DMC memory commands */
 #define MORELLO_DMC_MEMC_CMD_CONFIG		U(0)