diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 3a75dbd..287d32b 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -771,6 +771,10 @@
   CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of
   the CPU and is still open.
 
+- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3
+  CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
+  is fixed in r1p1.
+
 - ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3
   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is
   fixed in r1p2.
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index 4a3ac77..5429078 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,6 +26,11 @@
 #define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT	U(7)
 
 /*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_X3_CPUACTLR_EL1			S3_0_C15_C1_0
+
+/*******************************************************************************
  * CPU Auxiliary Control register 2 specific definitions.
  ******************************************************************************/
 #define CORTEX_X3_CPUACTLR2_EL1			S3_0_C15_C1_1
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index bd19269..ea89267 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -33,6 +33,12 @@
 
 check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2)
 
+workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875
+        sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22)
+workaround_reset_end cortex_x3, ERRATUM(2266875)
+
+check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0)
+
 workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506
 	sysreg_bit_set	CORTEX_X3_CPUACTLR2_EL1, BIT(0)
 workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index c134c03..f83fe19 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -774,6 +774,10 @@
 # still open.
 CPU_FLAG_LIST += ERRATA_X3_2070301
 
+# Flag to apply erratum 2266875 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
+CPU_FLAG_LIST += ERRATA_X3_2266875
+
 # Flag to apply erratum 2302506 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
 CPU_FLAG_LIST += ERRATA_X3_2302506
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 8255d33..18c0c88 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -446,13 +446,14 @@
 	.cpu_partnumber = CORTEX_X3_MIDR,
 	.cpu_errata_list = {
 		[0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301},
-		[1] = {2302506, 0x00, 0x11, ERRATA_X3_2302506},
-		[2] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
-		[3] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
-		[4] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
-		[5] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
-		[6] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
-		[7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[1] = {2266875, 0x00, 0x10, ERRATA_X3_2266875},
+		[2] = {2302506, 0x00, 0x11, ERRATA_X3_2302506},
+		[3] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
+		[4] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
+		[5] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
+		[6] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
+		[7] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
+		[8 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* CORTEX_X3_H_INC */