diff --git a/plat/mediatek/drivers/apusys/apusys.c b/plat/mediatek/drivers/apusys/apusys.c
index e3a986e..948bd9a 100644
--- a/plat/mediatek/drivers/apusys/apusys.c
+++ b/plat/mediatek/drivers/apusys/apusys.c
@@ -11,6 +11,7 @@
 #include "apusys.h"
 #include "apusys_devapc.h"
 #include "apusys_power.h"
+#include "apusys_security_ctrl_plat.h"
 #include <lib/mtk_init/mtk_init.h>
 #include <mtk_sip_svc.h>
 
@@ -52,6 +53,8 @@
 		return -1;
 	}
 
+	apusys_security_ctrl_init();
+
 	return 0;
 }
 MTK_PLAT_SETUP_1_INIT(apusys_init);
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.c b/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.c
new file mode 100644
index 0000000..86bebe5
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+/* Vendor header */
+#include "apusys_security_ctrl_plat.h"
+
+static void apusys_domain_remap_init(void)
+{
+	const uint32_t remap_domains[] = {
+		D0_REMAP_DOMAIN,  D1_REMAP_DOMAIN,  D2_REMAP_DOMAIN,  D3_REMAP_DOMAIN,
+		D4_REMAP_DOMAIN,  D5_REMAP_DOMAIN,  D6_REMAP_DOMAIN,  D7_REMAP_DOMAIN,
+		D8_REMAP_DOMAIN,  D9_REMAP_DOMAIN,  D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
+		D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN
+	};
+	uint32_t lower_domain = 0;
+	uint32_t higher_domain = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
+		if (i < REG_DOMAIN_NUM) {
+			lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
+		} else {
+			higher_domain |= (remap_domains[i] <<
+					  ((i - REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
+		}
+	}
+
+	mmio_write_32(SOC2APU_SET1_0, lower_domain);
+	mmio_write_32(SOC2APU_SET1_1, higher_domain);
+	mmio_setbits_32(APU_SEC_CON, DOMAIN_REMAP_SEL);
+}
+
+void apusys_security_ctrl_init(void)
+{
+	apusys_domain_remap_init();
+}
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.h b/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.h
new file mode 100644
index 0000000..f9181ae
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_SECURITY_CTRL_PLAT_H
+#define APUSYS_SECURITY_CTRL_PLAT_H
+
+#include <platform_def.h>
+
+#define SOC2APU_SET1_0	(APU_SEC_CON + 0x0c)
+#define SOC2APU_SET1_1	(APU_SEC_CON + 0x10)
+
+#define REG_DOMAIN_NUM		(8)
+#define REG_DOMAIN_BITS		(4)
+#define DOMAIN_REMAP_SEL	BIT(6)
+
+#define D0_REMAP_DOMAIN		(0)
+#define D1_REMAP_DOMAIN		(1)
+#define D2_REMAP_DOMAIN		(2)
+#define D3_REMAP_DOMAIN		(3)
+#define D4_REMAP_DOMAIN		(4)
+#define D5_REMAP_DOMAIN		(14)
+#define D6_REMAP_DOMAIN		(6)
+#define D7_REMAP_DOMAIN		(14)
+#define D8_REMAP_DOMAIN		(8)
+#define D9_REMAP_DOMAIN		(9)
+#define D10_REMAP_DOMAIN	(10)
+#define D11_REMAP_DOMAIN	(11)
+#define D12_REMAP_DOMAIN	(12)
+#define D13_REMAP_DOMAIN	(13)
+#define D14_REMAP_DOMAIN	(14)
+#define D15_REMAP_DOMAIN	(15)
+
+void apusys_security_ctrl_init(void);
+
+#endif /* APUSYS_SECURITY_CTRL_PLAT_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/rules.mk b/plat/mediatek/drivers/apusys/mt8188/rules.mk
index 1e6d9b4..c358067 100644
--- a/plat/mediatek/drivers/apusys/mt8188/rules.mk
+++ b/plat/mediatek/drivers/apusys/mt8188/rules.mk
@@ -10,5 +10,6 @@
 
 LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_devapc.c
 LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_security_ctrl_plat.c
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 7138c7a..43d12da 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -36,6 +36,7 @@
 #define APU_AO_CTRL		(IO_PHYS + 0x090f2000)
 #define APU_PLL			(IO_PHYS + 0x090f3000)
 #define APU_ACC			(IO_PHYS + 0x090f4000)
+#define APU_SEC_CON		(IO_PHYS + 0x090f5000)
 #define APU_ARETOP_ARE0		(IO_PHYS + 0x090f6000)
 #define APU_ARETOP_ARE1		(IO_PHYS + 0x090f7000)
 #define APU_ARETOP_ARE2		(IO_PHYS + 0x090f8000)