tree aacd6b760a02e7deab2a8c9972b9d09b1238dfe9
parent 46b6535549f9031c461874fd4d70be09b77c5168
author Marcin Wojtas <mw@semihalf.com> 1521622547 +0100
committer Konstantin Porotchkin <kostap@marvell.com> 1535978774 +0300

gicv2: enable configuring IRQ trigger type

This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.

Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>