arm_fpga: Read UART address from DT
The arm_fpga port requires a DTB, to launch a BL33 payload.
To make this port more flexible, we can also use the information in the
DT to configure the console driver.
For a start, find the DT node pointed to by the stdout-path property, and
read the base address from there.
This assumes for now that the stdout-path points to a PL011 UART.
This allows to remove platform specific addresses from the image. We
keep the original base address for the crash console.
Change-Id: I46a990de2315f81cae4d7913ae99a07b0bec5cb1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/plat/arm/board/arm_fpga/fpga_console.c b/plat/arm/board/arm_fpga/fpga_console.c
index a1fdb78..8c1da62 100644
--- a/plat/arm/board/arm_fpga/fpga_console.c
+++ b/plat/arm/board/arm_fpga/fpga_console.c
@@ -4,8 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <drivers/console.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <common/fdt_wrappers.h>
#include <drivers/arm/pl011.h>
+#include <drivers/console.h>
#include <platform_def.h>
@@ -13,8 +17,21 @@
void fpga_console_init(void)
{
- (void)console_pl011_register(PLAT_FPGA_BOOT_UART_BASE, 0, 0,
- &console);
+ const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
+ uintptr_t base_addr = PLAT_FPGA_CRASH_UART_BASE;
+ int node;
+
+ /*
+ * Try to read the UART base address from the DT, by chasing the
+ * stdout-path property of the chosen node.
+ * If this does not work, use the crash console address as a fallback.
+ */
+ node = fdt_get_stdout_node_offset(fdt);
+ if (node >= 0) {
+ fdt_get_reg_props_by_index(fdt, node, 0, &base_addr, NULL);
+ }
+
+ (void)console_pl011_register(base_addr, 0, 0, &console);
console_set_scope(&console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME);
diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h
index 0bb2b22..0378729 100644
--- a/plat/arm/board/arm_fpga/fpga_def.h
+++ b/plat/arm/board/arm_fpga/fpga_def.h
@@ -27,9 +27,11 @@
* FPGA image memory map related constants
******************************************************************************/
-/* UART base address, as configured by the image */
-#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
-#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
+/*
+ * UART base address, just for the crash console, as a fallback.
+ * The actual console UART address is taken from the DT.
+ */
+#define PLAT_FPGA_CRASH_UART_BASE 0x7ff80000
#define FPGA_DEFAULT_TIMER_FREQUENCY 10000000