commit db5a75f1d1a9223e2dd98e4317327bd1638ac993
author Igor Podgainõi <igor.podgainoi@arm.com> Fri Nov 15 15:20:50 2024 +0100
committer Igor Podgainõi <igor.podgainoi@arm.com> Wed Feb 05 21:19:15 2025 +0100
tree a50b9d24e2bf856b738c4d8ddec0a0f7f2bec683
parent e52c4016ec29c0a16472c932fde1fc1902f481a7

fix: add support for 128-bit sysregs to EL3 crash handler

The following changes have been made:
* Add new sysreg definitions and ASM macro is_feat_sysreg128_present_asm
* Add registers TTBR0_EL2 and VTTBR_EL2 to EL3 crash handler output
* Use MRRS instead of MRS for registers TTBR0_EL1, TTBR0_EL2, TTBR1_EL1,
  VTTBR_EL2 and PAR_EL1

Change-Id: I0e20b2c35251f3afba2df794c1f8bc0c46c197ff
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>

lib/extensions/sysreg128/sysreg128.S

diff --git a/lib/extensions/sysreg128/sysreg128.S b/lib/extensions/sysreg128/sysreg128.S
index 08cff2f..c8f304e 100644
--- a/lib/extensions/sysreg128/sysreg128.S
+++ b/lib/extensions/sysreg128/sysreg128.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -37,15 +37,14 @@
  */
 .macro _mrrs regins:req
 #if ENABLE_FEAT_D128 == 2
-        mrs     x0, ID_AA64MMFR3_EL1
-        tst     x0, #(ID_AA64MMFR3_EL1_D128_MASK << ID_AA64MMFR3_EL1_D128_SHIFT)
+        is_feat_sysreg128_present_asm x0
         bne     1f
-        /* If FEAT_D128 is not implemented then use mrs */
-        .inst   0xD5300000 | (\regins)
+        /* If FEAT_SYSREG128 is not implemented then use mrs */
+        .inst   0xD5300000 | (\regins)  /* mrs  x0, \regins */
         ret
 #endif
 1:
-        .inst   0xD5700000 | (\regins)
+        .inst   0xD5700000 | (\regins)  /* mrrs x0, x1, \regins */
         ret
 .endm
 
@@ -59,18 +58,16 @@
  * Clobbers: x0,x1,x2
  */
 .macro _msrr regins:req
-        /* If FEAT_D128 is not implemented use msr, dont tamper
-         * x0, x1 as they maybe used for mrrs */
 #if ENABLE_FEAT_D128 == 2
-        mrs     x2, ID_AA64MMFR3_EL1
-        tst     x2, #(ID_AA64MMFR3_EL1_D128_MASK << ID_AA64MMFR3_EL1_D128_SHIFT)
+        /* Don't tamper x0 and x1 as they may be used for msrr */
+        is_feat_sysreg128_present_asm x2
         bne     1f
-        /* If FEAT_D128 is not implemented then use msr */
-        .inst   0xD5100000 | (\regins)
+        /* If FEAT_SYSREG128 is not implemented then use msr */
+        .inst   0xD5100000 | (\regins)  /* msr  \regins, x0 */
         ret
 #endif
 1:
-        .inst   0xD5500000 | (\regins)
+        .inst   0xD5500000 | (\regins)  /* msrr \regins, x0, x1 */
         ret
 .endm