tree 2201c624aa44b6f4948ea0adffecbbda848becb6
parent 4f84cc182bd5b6f699ec27970b9daf9ecc79ce3e
author Nicolas Le Bayon <nicolas.le.bayon@st.com> 1573641991 +0100
committer Yann Gautier <yann.gautier@st.com> 1642521825 +0100

refactor(st-clock): improve DT parsing for PLL nodes

Add a function to get PLL settings from DT:
"cfg" property is mandatory, an error is generated if not found.
"frac" is optional, default value is returned if not found.
"csg" is optional too, a boolean value indicates if it has been
found, and its value is updated.

Store each PLL node validity information, this avoids parsing DT
several times.

Change-Id: I039466fbe1e67d160f7112814e7bb63b661804d0
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>