diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 3d3a51b..489cd1d 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -53,12 +53,11 @@
 #define PLL_LOCK_BIT			BIT(8)
 #define REF_FREF_SEL_OFFSET		0
 #define REF_FREF_SEL_MASK		(0x1F << REF_FREF_SEL_OFFSET)
-#define REF_CLOCK_SPEED_25M		(0x1 << REF_FREF_SEL_OFFSET)
-#define REF_CLOCK_SPEED_30M		(0x2 << REF_FREF_SEL_OFFSET)
-#define PCIE_REF_CLOCK_SPEED_25M	REF_CLOCK_SPEED_30M
-#define USB3_REF_CLOCK_SPEED_25M	REF_CLOCK_SPEED_30M
-#define REF_CLOCK_SPEED_40M		(0x3 << REF_FREF_SEL_OFFSET)
-#define REF_CLOCK_SPEED_50M		(0x4 << REF_FREF_SEL_OFFSET)
+#define REF_FREF_SEL_SERDES_25MHZ	(0x1 << REF_FREF_SEL_OFFSET)
+#define REF_FREF_SEL_SERDES_40MHZ	(0x3 << REF_FREF_SEL_OFFSET)
+#define REF_FREF_SEL_SERDES_50MHZ	(0x4 << REF_FREF_SEL_OFFSET)
+#define REF_FREF_SEL_PCIE_USB3_25MHZ	(0x2 << REF_FREF_SEL_OFFSET)
+#define REF_FREF_SEL_PCIE_USB3_40MHZ	(0x3 << REF_FREF_SEL_OFFSET)
 #define PHY_MODE_OFFSET			5
 #define PHY_MODE_MASK			(7 << PHY_MODE_OFFSET)
 #define PHY_MODE_SATA			(0x0 << PHY_MODE_OFFSET)