refactor(msm8916): handle single core platforms
Some Qualcomm modem platforms (MDM*) are quite similar to MSM8916
except that there is just a single CPU core. This requires some special
handling:
- There is no GPU so the GPU SMMU also does not exist.
- Looking closely at dumps of the MMIO register regions reveals that
some of the register addresses are slightly different.
Add the necessary checks for this to allow building for those
platforms.
No functional change for existing platforms.
Change-Id: I0380ac3734876243e970a55d8bec5a8247175343
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
diff --git a/plat/qti/msm8916/aarch32/msm8916_helpers.S b/plat/qti/msm8916/aarch32/msm8916_helpers.S
index c3acba7..dc35043 100644
--- a/plat/qti/msm8916/aarch32/msm8916_helpers.S
+++ b/plat/qti/msm8916/aarch32/msm8916_helpers.S
@@ -10,7 +10,11 @@
#include <msm8916_mmap.h>
+#if PLATFORM_CORE_COUNT > 1
#define APCS_TCM_START_ADDR 0x10
+#else
+#define APCS_TCM_START_ADDR 0x34
+#endif
#define APCS_TCM_REDIRECT_EN_0 BIT_32(0)
.globl plat_crash_console_init
@@ -80,12 +84,17 @@
* -------------------------------------------------
*/
func plat_my_core_pos
- ldcopr r1, MPIDR
- and r0, r1, #MPIDR_CPU_MASK
- .if PLATFORM_CLUSTER_COUNT > 1
- and r1, r1, #MPIDR_CLUSTER_MASK
- orr r0, r0, r1, LSR #(MPIDR_AFFINITY_BITS - \
- PLATFORM_CPU_PER_CLUSTER_SHIFT)
+ .if PLATFORM_CORE_COUNT > 1
+ ldcopr r1, MPIDR
+ and r0, r1, #MPIDR_CPU_MASK
+ .if PLATFORM_CLUSTER_COUNT > 1
+ and r1, r1, #MPIDR_CLUSTER_MASK
+ orr r0, r0, r1, LSR #(MPIDR_AFFINITY_BITS - \
+ PLATFORM_CPU_PER_CLUSTER_SHIFT)
+ .endif
+ .else
+ /* There is just a single core so always 0 */
+ mov r0, #0
.endif
bx lr
endfunc plat_my_core_pos
diff --git a/plat/qti/msm8916/aarch64/msm8916_helpers.S b/plat/qti/msm8916/aarch64/msm8916_helpers.S
index c2d0813..de9438a 100644
--- a/plat/qti/msm8916/aarch64/msm8916_helpers.S
+++ b/plat/qti/msm8916/aarch64/msm8916_helpers.S
@@ -10,7 +10,11 @@
#include <msm8916_mmap.h>
+#if PLATFORM_CORE_COUNT > 1
#define APCS_TCM_START_ADDR 0x10
+#else
+#define APCS_TCM_START_ADDR 0x34
+#endif
#define APCS_TCM_REDIRECT_EN_0 BIT_32(0)
.globl plat_crash_console_init
@@ -79,12 +83,17 @@
* -------------------------------------------------
*/
func plat_my_core_pos
- mrs x1, mpidr_el1
- and x0, x1, #MPIDR_CPU_MASK
- .if PLATFORM_CLUSTER_COUNT > 1
- and x1, x1, #MPIDR_CLUSTER_MASK
- orr x0, x0, x1, LSR #(MPIDR_AFFINITY_BITS - \
- PLATFORM_CPU_PER_CLUSTER_SHIFT)
+ .if PLATFORM_CORE_COUNT > 1
+ mrs x1, mpidr_el1
+ and x0, x1, #MPIDR_CPU_MASK
+ .if PLATFORM_CLUSTER_COUNT > 1
+ and x1, x1, #MPIDR_CLUSTER_MASK
+ orr x0, x0, x1, LSR #(MPIDR_AFFINITY_BITS - \
+ PLATFORM_CPU_PER_CLUSTER_SHIFT)
+ .endif
+ .else
+ /* There is just a single core so always 0 */
+ mov x0, #0
.endif
ret
endfunc plat_my_core_pos
diff --git a/plat/qti/msm8916/msm8916_config.c b/plat/qti/msm8916/msm8916_config.c
index b37fd19..0ac604b 100644
--- a/plat/qti/msm8916/msm8916_config.c
+++ b/plat/qti/msm8916/msm8916_config.c
@@ -41,9 +41,13 @@
*/
#define APCS_GLB_SECURE_STS_NS BIT_32(0)
#define APCS_GLB_SECURE_PWR_NS BIT_32(1)
+#if PLATFORM_CORE_COUNT > 1
#define APCS_BOOT_START_ADDR_SEC 0x04
-#define REMAP_EN BIT_32(0)
#define APCS_AA64NAA32_REG 0x0c
+#else
+#define APCS_BOOT_START_ADDR_SEC 0x18
+#endif
+#define REMAP_EN BIT_32(0)
static void msm8916_configure_apcs_cluster(unsigned int cluster)
{
@@ -62,13 +66,19 @@
mmio_write_32(APCS_GLB(cluster),
APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS);
- /* Disallow non-secure access to L2 SAW2 */
- mmio_write_32(APCS_L2_SAW2(cluster), 0);
+ if (PLATFORM_CORE_COUNT > 1) {
+ /* Disallow non-secure access to L2 SAW2 */
+ mmio_write_32(APCS_L2_SAW2(cluster), 0);
- /* Disallow non-secure access to CPU ACS and SAW2 */
- for (cpu = 0; cpu < PLATFORM_CPUS_PER_CLUSTER; cpu++) {
- mmio_write_32(APCS_ALIAS_ACS(cluster, cpu), 0);
- mmio_write_32(APCS_ALIAS_SAW2(cluster, cpu), 0);
+ /* Disallow non-secure access to CPU ACS and SAW2 */
+ for (cpu = 0; cpu < PLATFORM_CPUS_PER_CLUSTER; cpu++) {
+ mmio_write_32(APCS_ALIAS_ACS(cluster, cpu), 0);
+ mmio_write_32(APCS_ALIAS_SAW2(cluster, cpu), 0);
+ }
+ } else {
+ /* There is just one core so no aliases exist */
+ mmio_write_32(APCS_BANKED_ACS, 0);
+ mmio_write_32(APCS_BANKED_SAW2, 0);
}
#ifdef __aarch64__
@@ -145,9 +155,15 @@
static void msm8916_configure_smmu(void)
{
+ uint32_t ena_bits = APSS_TCU_CLK_ENA | SMMU_CFG_CLK_ENA;
+
+ /* Single core (MDM) platforms do not have a GPU */
+ if (PLATFORM_CORE_COUNT > 1) {
+ ena_bits |= GFX_TCU_CLK_ENA | GFX_TBU_CLK_ENA;
+ }
+
/* Enable SMMU clocks to enable register access */
- mmio_write_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA |
- APSS_TCU_CLK_ENA | GFX_TCU_CLK_ENA | GFX_TBU_CLK_ENA);
+ mmio_write_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, ena_bits);
/* Wait for configuration clock */
while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF) {
@@ -158,7 +174,9 @@
/* Clear sACR.CACHE_LOCK bit if needed for MMU-500 r2p0+ */
msm8916_smmu_cache_unlock(APPS_SMMU_BASE, GCC_APSS_TCU_CBCR);
- msm8916_smmu_cache_unlock(GPU_SMMU_BASE, GCC_GFX_TCU_CBCR);
+ if (PLATFORM_CORE_COUNT > 1) {
+ msm8916_smmu_cache_unlock(GPU_SMMU_BASE, GCC_GFX_TCU_CBCR);
+ }
/*
* Keep APCS vote for SMMU clocks for rest of booting process, but make
diff --git a/plat/qti/msm8916/msm8916_pm.c b/plat/qti/msm8916/msm8916_pm.c
index 7b44d60..fd44f04 100644
--- a/plat/qti/msm8916/msm8916_pm.c
+++ b/plat/qti/msm8916/msm8916_pm.c
@@ -4,6 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
+
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
@@ -34,6 +36,12 @@
static int msm8916_pwr_domain_on(u_register_t mpidr)
{
+ /* Should be never called on single-core platforms */
+ if (PLATFORM_CORE_COUNT == 1) {
+ assert(false);
+ return PSCI_E_ALREADY_ON;
+ }
+
/* Power on L2 cache and secondary CPU core for the first time */
if (PLATFORM_CLUSTER_COUNT > 1) {
msm8916_l2_boot(APCS_GLB(MPIDR_APCS_CLUSTER(mpidr)));
@@ -45,6 +53,12 @@
static void msm8916_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
+ /* Should be never called on single-core platforms */
+ if (PLATFORM_CORE_COUNT == 1) {
+ assert(false);
+ return;
+ }
+
if (PLATFORM_CLUSTER_COUNT > 1 &&
CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));