diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h
index f3180e9..3feae9d 100644
--- a/plat/xilinx/zynqmp/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/zynqmp_def.h
@@ -35,6 +35,7 @@
 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
 #define CRF_APB_BASE		0xFD1A0000
 #define CRF_APB_SIZE		0x00600000
+#define CRF_APB_CLK_BASE	0xFD1A0020
 
 /* CRF registers and bitfields */
 #define CRF_APB_RST_FPD_APU	(CRF_APB_BASE + 0X00000104)
@@ -44,10 +45,10 @@
 
 /* CRL registers and bitfields */
 #define CRL_APB_BASE			0xFF5E0000
-#define CRL_APB_RPLL_CTRL		(CRL_APB_BASE + 0x30)
 #define CRL_APB_BOOT_MODE_USER		(CRL_APB_BASE + 0x200)
 #define CRL_APB_RESET_CTRL		(CRL_APB_BASE + 0x218)
 #define CRL_APB_RST_LPD_TOP		(CRL_APB_BASE + 0x23C)
+#define CRL_APB_CLK_BASE		0xFF5E0020
 
 #define CRL_APB_RPU_AMBA_RESET		(1 << 2)
 #define CRL_APB_RPLL_CTRL_BYPASS	(1 << 3)
@@ -225,4 +226,81 @@
 #define ZYNQMP_SD_OTAPDLYENA_MASK		0x40
 #define ZYNQMP_SD_OTAPDLYENA			0x40
 
+/* Clock control registers */
+/* Full power domain clocks */
+#define CRF_APB_APLL_CTRL		(CRF_APB_CLK_BASE + 0x00)
+#define CRF_APB_DPLL_CTRL		(CRF_APB_CLK_BASE + 0x0c)
+#define CRF_APB_VPLL_CTRL		(CRF_APB_CLK_BASE + 0x18)
+#define CRF_APB_PLL_STATUS		(CRF_APB_CLK_BASE + 0x24)
+#define CRF_APB_APLL_TO_LPD_CTRL	(CRF_APB_CLK_BASE + 0x28)
+#define CRF_APB_DPLL_TO_LPD_CTRL	(CRF_APB_CLK_BASE + 0x2c)
+#define CRF_APB_VPLL_TO_LPD_CTRL	(CRF_APB_CLK_BASE + 0x30)
+/* Peripheral clocks */
+#define CRF_APB_ACPU_CTRL		(CRF_APB_CLK_BASE + 0x40)
+#define CRF_APB_DBG_TRACE_CTRL		(CRF_APB_CLK_BASE + 0x44)
+#define CRF_APB_DBG_FPD_CTRL		(CRF_APB_CLK_BASE + 0x48)
+#define CRF_APB_DP_VIDEO_REF_CTRL	(CRF_APB_CLK_BASE + 0x50)
+#define CRF_APB_DP_AUDIO_REF_CTRL	(CRF_APB_CLK_BASE + 0x54)
+#define CRF_APB_DP_STC_REF_CTRL		(CRF_APB_CLK_BASE + 0x5c)
+#define CRF_APB_DDR_CTRL		(CRF_APB_CLK_BASE + 0x60)
+#define CRF_APB_GPU_REF_CTRL		(CRF_APB_CLK_BASE + 0x64)
+#define CRF_APB_SATA_REF_CTRL		(CRF_APB_CLK_BASE + 0x80)
+#define CRF_APB_PCIE_REF_CTRL		(CRF_APB_CLK_BASE + 0x94)
+#define CRF_APB_GDMA_REF_CTRL		(CRF_APB_CLK_BASE + 0x98)
+#define CRF_APB_DPDMA_REF_CTRL		(CRF_APB_CLK_BASE + 0x9c)
+#define CRF_APB_TOPSW_MAIN_CTRL		(CRF_APB_CLK_BASE + 0xa0)
+#define CRF_APB_TOPSW_LSBUS_CTRL	(CRF_APB_CLK_BASE + 0xa4)
+#define CRF_APB_GTGREF0_REF_CTRL	(CRF_APB_CLK_BASE + 0xa8)
+#define CRF_APB_DBG_TSTMP_CTRL		(CRF_APB_CLK_BASE + 0xd8)
+
+/* Low power domain clocks */
+#define CRL_APB_IOPLL_CTRL		(CRL_APB_CLK_BASE + 0x00)
+#define CRL_APB_RPLL_CTRL		(CRL_APB_CLK_BASE + 0x10)
+#define CRL_APB_PLL_STATUS		(CRL_APB_CLK_BASE + 0x20)
+#define CRL_APB_IOPLL_TO_FPD_CTRL	(CRL_APB_CLK_BASE + 0x24)
+#define CRL_APB_RPLL_TO_FPD_CTRL	(CRL_APB_CLK_BASE + 0x28)
+/* Peripheral clocks */
+#define CRL_APB_USB3_DUAL_REF_CTRL	(CRL_APB_CLK_BASE + 0x2c)
+#define CRL_APB_GEM0_REF_CTRL		(CRL_APB_CLK_BASE + 0x30)
+#define CRL_APB_GEM1_REF_CTRL		(CRL_APB_CLK_BASE + 0x34)
+#define CRL_APB_GEM2_REF_CTRL		(CRL_APB_CLK_BASE + 0x38)
+#define CRL_APB_GEM3_REF_CTRL		(CRL_APB_CLK_BASE + 0x3c)
+#define CRL_APB_USB0_BUS_REF_CTRL	(CRL_APB_CLK_BASE + 0x40)
+#define CRL_APB_USB1_BUS_REF_CTRL	(CRL_APB_CLK_BASE + 0x44)
+#define CRL_APB_QSPI_REF_CTRL		(CRL_APB_CLK_BASE + 0x48)
+#define CRL_APB_SDIO0_REF_CTRL		(CRL_APB_CLK_BASE + 0x4c)
+#define CRL_APB_SDIO1_REF_CTRL		(CRL_APB_CLK_BASE + 0x50)
+#define CRL_APB_UART0_REF_CTRL		(CRL_APB_CLK_BASE + 0x54)
+#define CRL_APB_UART1_REF_CTRL		(CRL_APB_CLK_BASE + 0x58)
+#define CRL_APB_SPI0_REF_CTRL		(CRL_APB_CLK_BASE + 0x5c)
+#define CRL_APB_SPI1_REF_CTRL		(CRL_APB_CLK_BASE + 0x60)
+#define CRL_APB_CAN0_REF_CTRL		(CRL_APB_CLK_BASE + 0x64)
+#define CRL_APB_CAN1_REF_CTRL		(CRL_APB_CLK_BASE + 0x68)
+#define CRL_APB_CPU_R5_CTRL		(CRL_APB_CLK_BASE + 0x70)
+#define CRL_APB_IOU_SWITCH_CTRL		(CRL_APB_CLK_BASE + 0x7c)
+#define CRL_APB_CSU_PLL_CTRL		(CRL_APB_CLK_BASE + 0x80)
+#define CRL_APB_PCAP_CTRL		(CRL_APB_CLK_BASE + 0x84)
+#define CRL_APB_LPD_SWITCH_CTRL		(CRL_APB_CLK_BASE + 0x88)
+#define CRL_APB_LPD_LSBUS_CTRL		(CRL_APB_CLK_BASE + 0x8c)
+#define CRL_APB_DBG_LPD_CTRL		(CRL_APB_CLK_BASE + 0x90)
+#define CRL_APB_NAND_REF_CTRL		(CRL_APB_CLK_BASE + 0x94)
+#define CRL_APB_ADMA_REF_CTRL		(CRL_APB_CLK_BASE + 0x98)
+#define CRL_APB_PL0_REF_CTRL		(CRL_APB_CLK_BASE + 0xa0)
+#define CRL_APB_PL1_REF_CTRL		(CRL_APB_CLK_BASE + 0xa4)
+#define CRL_APB_PL2_REF_CTRL		(CRL_APB_CLK_BASE + 0xa8)
+#define CRL_APB_PL3_REF_CTRL		(CRL_APB_CLK_BASE + 0xac)
+#define CRL_APB_PL0_THR_CNT		(CRL_APB_CLK_BASE + 0xb4)
+#define CRL_APB_PL1_THR_CNT		(CRL_APB_CLK_BASE + 0xbc)
+#define CRL_APB_PL2_THR_CNT		(CRL_APB_CLK_BASE + 0xc4)
+#define CRL_APB_PL3_THR_CNT		(CRL_APB_CLK_BASE + 0xdc)
+#define CRL_APB_GEM_TSU_REF_CTRL	(CRL_APB_CLK_BASE + 0xe0)
+#define CRL_APB_DLL_REF_CTRL		(CRL_APB_CLK_BASE + 0xe4)
+#define CRL_APB_AMS_REF_CTRL		(CRL_APB_CLK_BASE + 0xe8)
+#define CRL_APB_I2C0_REF_CTRL		(CRL_APB_CLK_BASE + 0x100)
+#define CRL_APB_I2C1_REF_CTRL		(CRL_APB_CLK_BASE + 0x104)
+#define CRL_APB_TIMESTAMP_REF_CTRL	(CRL_APB_CLK_BASE + 0x108)
+#define IOU_SLCR_GEM_CLK_CTRL		(IOU_SLCR_BASEADDR + 0x308)
+#define IOU_SLCR_CAN_MIO_CTRL		(IOU_SLCR_BASEADDR + 0x304)
+#define IOU_SLCR_WDT_CLK_SEL		(IOU_SLCR_BASEADDR + 0x300)
+
 #endif /* __ZYNQMP_DEF_H__ */