fix(intel): add in missing ECC register
This patch is to add in missing ECC register (INITSTAT)
Change-Id: Iecf03dc9597ec2884901c132fb9cef7e90ab06a0
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 46596bf..53dcd13 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -147,6 +148,7 @@
/* QSPI ECC from SDM register */
#define SOCFPGA_ECC_QSPI_CTRL 0x08
+#define SOCFPGA_ECC_QSPI_INITSTAT 0x0C
#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 2f88c86..5dfbc14 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -419,6 +419,7 @@
case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */
case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */
+ case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */
case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */
case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */
case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */