Merge "style(xilinx): replace ARM by Arm in copyrights" into integration
diff --git a/.husky/prepare-commit-msg b/.husky/prepare-commit-msg
index 593dfa8..617400a 100755
--- a/.husky/prepare-commit-msg
+++ b/.husky/prepare-commit-msg
@@ -3,4 +3,6 @@
# shellcheck source=./_/husky.sh
. "$(dirname "$0")/_/husky.sh"
-"$(dirname "$0")/prepare-commit-msg.cz" "$@"
+if ! git config --get tf-a.disableCommitizen > /dev/null; then
+ "$(dirname "$0")/prepare-commit-msg.cz" "$@"
+fi
diff --git a/docs/Makefile b/docs/Makefile
index 3dd7ebc..5bc24db 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+# Copyright (c) 2019-2023, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -13,13 +13,20 @@
SOURCEDIR = .
BUILDDIR = build
+V ?= 0
+ifeq ($(V),0)
+ Q := @
+else
+ Q :=
+endif
+
# Put it first so that "make" without argument is like "make help".
help:
- @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+ ${Q}$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
- @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+ ${Q}$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
diff --git a/docs/components/measured_boot/event_log.rst b/docs/components/measured_boot/event_log.rst
index 0881248..c102bea 100644
--- a/docs/components/measured_boot/event_log.rst
+++ b/docs/components/measured_boot/event_log.rst
@@ -33,3 +33,11 @@
- tpm_event_log_size [mandatory]
- value type: <u32>
- Event Log size.
+
+- tpm_event_log_max_size [mandatory]
+ - value type: <u32>
+ - Event Log maximum size.
+
+--------------
+
+*Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.*
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 34f913b..ffbd4ca 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -267,8 +267,10 @@
uintptr_t log_addr,
#endif
size_t log_size, uintptr_t *ns_log_addr);
-int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size);
-int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size);
+int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size,
+ size_t log_max_size);
+int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size,
+ size_t *log_max_size);
#endif /* MEASURED_BOOT */
/*
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 886e1f3..e10ebb0 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -382,7 +382,11 @@
bl check_errata_2684597
cbz x0, 2f
- tsb csync
+ /*
+ * Many assemblers do not yet understand the "tsb csync" mnemonic,
+ * so use the equivalent hint instruction.
+ */
+ hint #18 /* tsb csync */
2:
ret x17
endfunc errata_cortex_a510_2684597_wa
diff --git a/plat/arm/board/fvp/fdts/event_log.dtsi b/plat/arm/board/fvp/fdts/event_log.dtsi
index 47af672..8e26542 100644
--- a/plat/arm/board/fvp/fdts/event_log.dtsi
+++ b/plat/arm/board/fvp/fdts/event_log.dtsi
@@ -9,4 +9,5 @@
compatible = "arm,tpm_event_log";
tpm_event_log_addr = <0x0 0x0>;
tpm_event_log_size = <0x0>;
+ tpm_event_log_max_size = <0x0>;
};
diff --git a/plat/arm/board/fvp/fvp_bl1_measured_boot.c b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
index 76cd918..72fdfef 100644
--- a/plat/arm/board/fvp/fvp_bl1_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
@@ -63,7 +63,8 @@
event_log_cur_size = event_log_get_cur_size(event_log);
int rc = arm_set_tb_fw_info((uintptr_t)event_log,
- event_log_cur_size);
+ event_log_cur_size,
+ PLAT_ARM_EVENT_LOG_MAX_SIZE);
if (rc != 0) {
/*
* It is a fatal error because on FVP platform, BL2 software
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index 7b0673a..e6b9192 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -90,9 +90,11 @@
uint8_t *event_log_start;
uint8_t *event_log_finish;
size_t bl1_event_log_size;
+ size_t event_log_max_size;
int rc;
- rc = arm_get_tb_fw_info(&event_log_base, &bl1_event_log_size);
+ rc = arm_get_tb_fw_info(&event_log_base, &bl1_event_log_size,
+ &event_log_max_size);
if (rc != 0) {
ERROR("%s(): Unable to get Event Log info from TB_FW_CONFIG\n",
__func__);
@@ -111,7 +113,7 @@
event_log_start = (uint8_t *)((uintptr_t)event_log_base +
bl1_event_log_size);
event_log_finish = (uint8_t *)((uintptr_t)event_log_base +
- PLAT_ARM_EVENT_LOG_MAX_SIZE);
+ event_log_max_size);
event_log_init((uint8_t *)event_log_start, event_log_finish);
diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c
index e88ea65..5dc1115 100644
--- a/plat/arm/common/arm_dyn_cfg_helpers.c
+++ b/plat/arm/common/arm_dyn_cfg_helpers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,12 +28,15 @@
* Currently OP-TEE does not support reading DTBs from Secure memory
* and this property should be removed when this feature is supported.
*/
-#define DTB_PROP_HW_SM_LOG_ADDR "tpm_event_log_sm_addr"
+#define DTB_PROP_HW_SM_LOG_ADDR "tpm_event_log_sm_addr"
#endif /* SPD_opteed */
-#define DTB_PROP_HW_LOG_ADDR "tpm_event_log_addr"
-#define DTB_PROP_HW_LOG_SIZE "tpm_event_log_size"
+#define DTB_PROP_HW_LOG_ADDR "tpm_event_log_addr"
+#define DTB_PROP_HW_LOG_SIZE "tpm_event_log_size"
+#define DTB_PROP_HW_LOG_MAX_SIZE "tpm_event_log_max_size"
#endif /* MEASURED_BOOT */
+static size_t event_log_max_size __unused;
+
/*******************************************************************************
* Validate the tb_fw_config is a valid DTB file and returns the node offset
* to "arm,tb_fw" property.
@@ -180,6 +183,16 @@
return err;
}
+ assert(event_log_max_size != 0U);
+ err = fdtw_write_inplace_cells(dtb, node,
+ DTB_PROP_HW_LOG_MAX_SIZE, 1,
+ &event_log_max_size);
+ if (err < 0) {
+ ERROR("%sDTB property '%s'\n",
+ "Unable to write ", DTB_PROP_HW_LOG_MAX_SIZE);
+ return err;
+ }
+
err = fdtw_write_inplace_cells(dtb, node,
DTB_PROP_HW_LOG_SIZE, 1, &log_size);
if (err < 0) {
@@ -294,7 +307,7 @@
* 0 = success
* < 0 = error
*/
-int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size)
+int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, size_t log_max_size)
{
/*
* Read tb_fw_config device tree for Event Log properties
@@ -309,6 +322,8 @@
tb_fw_cfg_dtb = tb_fw_config_info->config_addr;
+ event_log_max_size = log_max_size;
+
err = arm_set_event_log_info(tb_fw_cfg_dtb,
#ifdef SPD_opteed
0UL,
@@ -329,7 +344,8 @@
* Alongside returns Event Log address and its size.
*/
-int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size)
+int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size,
+ size_t *log_max_size)
{
/* As libfdt uses void *, we can't avoid this cast */
const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
@@ -362,6 +378,17 @@
if (rc != 0) {
ERROR("%s%s", DTB_PROP_HW_LOG_SIZE,
" not specified in TB_FW config.\n");
+ return rc;
+ }
+
+ rc = fdt_read_uint32(dtb, node, DTB_PROP_HW_LOG_MAX_SIZE,
+ (uint32_t *)log_max_size);
+ if (rc != 0) {
+ ERROR("%s%s", DTB_PROP_HW_LOG_MAX_SIZE,
+ " not specified in TB_FW config.\n");
+ return rc;
+ } else {
+ event_log_max_size = *log_max_size;
}
return rc;
diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c
index 1da8d29..13e80fb 100644
--- a/plat/imx/imx8qx/imx8qx_bl31_setup.c
+++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c
@@ -51,6 +51,16 @@
#define IMX_PAD_UART_RX SC_P_UART0_RX
#define IMX_PAD_UART_TX SC_P_UART0_TX
+#elif defined(IMX_USE_UART1)
+#define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \
+ (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
+#define IMX_RES_UART SC_R_UART_1
+#define IMX_PAD_UART_RX SC_P_UART1_RX
+#define IMX_PAD_UART_TX SC_P_UART1_TX
+
/*
* On Toradex Colibri i.MX8QXP UART3 on the FLEXCAN2.
* Use custom pad control for this
diff --git a/plat/imx/imx8qx/include/platform_def.h b/plat/imx/imx8qx/include/platform_def.h
index b880e1b..29f6f7c 100644
--- a/plat/imx/imx8qx/include/platform_def.h
+++ b/plat/imx/imx8qx/include/platform_def.h
@@ -41,6 +41,8 @@
#if defined(IMX_USE_UART0)
#define IMX_BOOT_UART_BASE 0x5a060000
+#elif defined(IMX_USE_UART1)
+#define IMX_BOOT_UART_BASE 0x5a070000
#elif defined(IMX_USE_UART3)
#define IMX_BOOT_UART_BASE 0x5a090000
#else
diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h
index f39d475..ee22241 100644
--- a/plat/intel/soc/agilex/include/agilex_clock_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h
@@ -127,5 +127,7 @@
uint32_t get_wdt_clk(void);
uint32_t get_uart_clk(void);
uint32_t get_mmc_clk(void);
+uint32_t get_mpu_clk(void);
+uint32_t get_cpu_clk(void);
#endif
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index b216ab1..4d7198c 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -35,6 +35,4 @@
/* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
-uint32_t get_cpu_clk(void);
-
#endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index 76b9937..10ef11b 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -388,12 +388,22 @@
return mmc_clk;
}
+/* Return MPU clock */
+uint32_t get_mpu_clk(void)
+{
+ uint32_t mpu_clk;
+
+ mpu_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC0,
+ CLKMGR_PERPLL_PLLC0);
+ return mpu_clk;
+}
+
/* Get cpu freq clock */
uint32_t get_cpu_clk(void)
{
uint32_t cpu_clk;
- cpu_clk = get_l3_clk()/PLAT_SYS_COUNTER_CONVERT_TO_MHZ;
+ cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
return cpu_clk;
}
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 2b3f144..4e50156 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -191,7 +191,7 @@
* System counter frequency related constants
******************************************************************************/
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
-#define PLAT_SYS_COUNTER_CONVERT_TO_MHZ (1000000)
+#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE
#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE
diff --git a/plat/intel/soc/common/socfpga_delay_timer.c b/plat/intel/soc/common/socfpga_delay_timer.c
index dcd51e2..8fce5cf 100644
--- a/plat/intel/soc/common/socfpga_delay_timer.c
+++ b/plat/intel/soc/common/socfpga_delay_timer.c
@@ -10,6 +10,15 @@
#include <lib/mmio.h>
#include "socfpga_plat_def.h"
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
+#include "agilex_clock_manager.h"
+#elif PLATFORM_MODEL == PLAT_SOCFPGA_N5X
+#include "n5x_clock_manager.h"
+#elif PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
+#include "s10_clock_manager.h"
+#endif
+
#define SOCFPGA_GLOBAL_TIMER 0xffd01000
#define SOCFPGA_GLOBAL_TIMER_EN 0x3
@@ -43,6 +52,8 @@
socfpga_delay_timer_init_args();
mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
+ NOTICE("BL31 CLK freq = %d MHz\n", PLAT_SYS_COUNTER_FREQ_IN_MHZ);
+
asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));
diff --git a/plat/intel/soc/n5x/include/n5x_clock_manager.h b/plat/intel/soc/n5x/include/n5x_clock_manager.h
new file mode 100644
index 0000000..14a5717
--- /dev/null
+++ b/plat/intel/soc/n5x/include/n5x_clock_manager.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CLOCKMANAGER_H
+#define CLOCKMANAGER_H
+
+#include "socfpga_handoff.h"
+
+/* MACRO DEFINITION */
+#define SOCFPGA_GLOBAL_TIMER 0xffd01000
+#define SOCFPGA_GLOBAL_TIMER_EN 0x3
+
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
+#define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8)
+#define CLKMGR_PLLDIV_FDIV_OFFSET 8
+#define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0)
+#define CLKMGR_PLLDIV_REFCLKDIV_OFFSET 0
+#define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
+#define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24
+
+#define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
+#define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
+#define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8)
+#define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8
+#define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
+#define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24
+#define CLKMGR_CLKSRC_MASK GENMASK(18, 16)
+#define CLKMGR_CLKSRC_OFFSET 16
+#define CLKMGR_NOCDIV_DIVIDER_MASK GENMASK(1, 0)
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
+
+#define CLKMGR_INTOSC_HZ 400000000
+#define CLKMGR_VCO_PSRC_EOSC1 0
+#define CLKMGR_VCO_PSRC_INTOSC 1
+#define CLKMGR_VCO_PSRC_F2S 2
+#define CLKMGR_CLKSRC_MAIN 0
+#define CLKMGR_CLKSRC_PER 1
+
+#define CLKMGR_N5X_BASE 0xffd10000
+#define CLKMGR_MAINPLL_NOCCLK 0x40
+#define CLKMGR_MAINPLL_NOCDIV 0x44
+#define CLKMGR_MAINPLL_PLLGLOB 0x48
+#define CLKMGR_MAINPLL_PLLOUTDIV 0x54
+#define CLKMGR_MAINPLL_PLLDIV 0x50
+#define CLKMGR_PERPLL_PLLGLOB 0x9c
+#define CLKMGR_PERPLL_PLLDIV 0xa4
+#define CLKMGR_PERPLL_PLLOUTDIV 0xa8
+
+/* FUNCTION DEFINITION */
+uint64_t clk_get_pll_output_hz(void);
+uint64_t get_l4_clk(void);
+uint32_t get_clk_freq(uint32_t psrc_reg);
+uint32_t get_mpu_clk(void);
+uint32_t get_cpu_clk(void);
+
+#endif
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index 4c36f91..eec8411 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -32,11 +32,6 @@
#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
-/* Platform specific system counter */
-/*
- * In N5X the clk init is done in Uboot SPL.
- * BL31 shall bypass the clk init and only provides other APIs.
- */
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
#endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk
index 4f3da4e..7afeb74 100644
--- a/plat/intel/soc/n5x/platform.mk
+++ b/plat/intel/soc/n5x/platform.mk
@@ -36,6 +36,7 @@
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
plat/intel/soc/n5x/bl31_plat_setup.c \
+ plat/intel/soc/n5x/soc/n5x_clock_manager.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_sip_svc_v2.c \
diff --git a/plat/intel/soc/n5x/soc/n5x_clock_manager.c b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
new file mode 100644
index 0000000..f8ff2c5
--- /dev/null
+++ b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include "n5x_clock_manager.h"
+#include "socfpga_system_manager.h"
+
+
+uint64_t clk_get_pll_output_hz(void)
+{
+ uint32_t clksrc;
+ uint32_t scr_reg;
+ uint32_t divf;
+ uint32_t divr;
+ uint32_t divq;
+ uint32_t power = 1;
+ uint64_t clock = 0;
+
+ clksrc = ((get_clk_freq(CLKMGR_PERPLL_PLLGLOB)) &
+ CLKMGR_PLLGLOB_VCO_PSRC_MASK) >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
+
+ switch (clksrc) {
+ case CLKMGR_VCO_PSRC_EOSC1:
+ scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
+ clock = mmio_read_32(scr_reg);
+ break;
+
+ case CLKMGR_VCO_PSRC_INTOSC:
+ clock = CLKMGR_INTOSC_HZ;
+ break;
+
+ case CLKMGR_VCO_PSRC_F2S:
+ scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
+ clock = mmio_read_32(scr_reg);
+ break;
+ }
+
+ divf = ((get_clk_freq(CLKMGR_PERPLL_PLLDIV)) &
+ CLKMGR_PLLDIV_FDIV_MASK) >> CLKMGR_PLLDIV_FDIV_OFFSET;
+ divr = ((get_clk_freq(CLKMGR_PERPLL_PLLDIV)) &
+ CLKMGR_PLLDIV_REFCLKDIV_MASK) >> CLKMGR_PLLDIV_REFCLKDIV_OFFSET;
+ divq = ((get_clk_freq(CLKMGR_PERPLL_PLLDIV)) &
+ CLKMGR_PLLDIV_OUTDIV_QDIV_MASK) >> CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET;
+
+ while (divq) {
+ power *= 2;
+ divq--;
+ }
+
+ return ((clock * 2 * (divf + 1)) / ((divr + 1) * power));
+}
+
+uint64_t get_l4_clk(void)
+{
+ uint32_t clock = 0;
+ uint32_t mainpll_c1cnt;
+ uint32_t perpll_c1cnt;
+ uint32_t clksrc;
+
+ mainpll_c1cnt = ((get_clk_freq(CLKMGR_MAINPLL_PLLOUTDIV)) &
+ CLKMGR_PLLOUTDIV_C1CNT_MASK) >> CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
+
+ perpll_c1cnt = ((get_clk_freq(CLKMGR_PERPLL_PLLOUTDIV)) &
+ CLKMGR_PLLOUTDIV_C1CNT_MASK) >> CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
+
+ clksrc = ((get_clk_freq(CLKMGR_MAINPLL_NOCCLK)) & CLKMGR_CLKSRC_MASK) >>
+ CLKMGR_CLKSRC_OFFSET;
+
+ switch (clksrc) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_pll_output_hz();
+ clock /= 1 + mainpll_c1cnt;
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_pll_output_hz();
+ clock /= 1 + perpll_c1cnt;
+ break;
+
+ default:
+ return 0;
+ }
+
+ clock /= BIT(((get_clk_freq(CLKMGR_MAINPLL_NOCDIV)) >>
+ CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_NOCDIV_DIVIDER_MASK);
+
+ return clock;
+}
+
+/* Return MPU clock */
+uint32_t get_mpu_clk(void)
+{
+ uint32_t clock = 0;
+ uint32_t mainpll_c0cnt;
+ uint32_t perpll_c0cnt;
+ uint32_t clksrc;
+
+ mainpll_c0cnt = ((get_clk_freq(CLKMGR_MAINPLL_PLLOUTDIV)) &
+ CLKMGR_PLLOUTDIV_C0CNT_MASK) >> CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
+
+ perpll_c0cnt = ((get_clk_freq(CLKMGR_PERPLL_PLLOUTDIV)) &
+ CLKMGR_PLLOUTDIV_C0CNT_MASK) >> CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
+
+ clksrc = ((get_clk_freq(CLKMGR_MAINPLL_NOCCLK)) & CLKMGR_CLKSRC_MASK) >>
+ CLKMGR_CLKSRC_OFFSET;
+
+ switch (clksrc) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_pll_output_hz();
+ clock /= 1 + mainpll_c0cnt;
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_pll_output_hz();
+ clock /= 1 + perpll_c0cnt;
+ break;
+
+ default:
+ return 0;
+ }
+
+ clock /= BIT(((get_clk_freq(CLKMGR_MAINPLL_NOCDIV)) >>
+ CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_NOCDIV_DIVIDER_MASK);
+
+ return clock;
+}
+
+/* Calculate clock frequency based on parameter */
+uint32_t get_clk_freq(uint32_t psrc_reg)
+{
+ uint32_t clk_psrc;
+
+ clk_psrc = mmio_read_32(CLKMGR_N5X_BASE + psrc_reg);
+
+ return clk_psrc;
+}
+
+/* Get cpu freq clock */
+uint32_t get_cpu_clk(void)
+{
+ uint32_t cpu_clk = 0;
+
+ cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
+
+ return cpu_clk;
+}
diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h
index cf57df3..661e204 100644
--- a/plat/intel/soc/stratix10/include/s10_clock_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h
@@ -95,5 +95,6 @@
uint32_t get_mmc_clk(void);
uint32_t get_l3_clk(uint32_t ref_clk);
uint32_t get_ref_clk(uint32_t pllglob);
+uint32_t get_cpu_clk(void);
#endif
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index 516cc75..da6414f 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -34,7 +34,5 @@
/* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
-uint32_t get_cpu_clk(void);
-
#endif /* PLATSOCFPGA_DEF_H */
diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
index 30009f7..416d359 100644
--- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
@@ -316,7 +316,7 @@
data32 = mmio_read_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB);
ref_clk = get_ref_clk(data32);
- cpu_clk = get_l3_clk(ref_clk)/PLAT_SYS_COUNTER_CONVERT_TO_MHZ;
+ cpu_clk = get_l3_clk(ref_clk)/PLAT_HZ_CONVERT_TO_MHZ;
return cpu_clk;
}
diff --git a/plat/mediatek/drivers/apusys/apusys.c b/plat/mediatek/drivers/apusys/apusys.c
index 1d34627..c82b3a7 100644
--- a/plat/mediatek/drivers/apusys/apusys.c
+++ b/plat/mediatek/drivers/apusys/apusys.c
@@ -11,6 +11,35 @@
#include "apusys.h"
#include "apusys_power.h"
#include <lib/mtk_init/mtk_init.h>
+#include <mtk_sip_svc.h>
+
+static u_register_t apusys_kernel_handler(u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *handle,
+ struct smccc_res *smccc_ret)
+{
+ uint32_t request_ops;
+ int32_t ret = -1;
+
+ request_ops = (uint32_t)x1;
+
+ switch (request_ops) {
+ case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON:
+ ret = apusys_kernel_apusys_pwr_top_on();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF:
+ ret = apusys_kernel_apusys_pwr_top_off();
+ break;
+ default:
+ ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
+ break;
+ }
+
+ return ret;
+}
+DECLARE_SMC_HANDLER(MTK_SIP_APUSYS_CONTROL, apusys_kernel_handler);
int apusys_init(void)
{
diff --git a/plat/mediatek/drivers/apusys/apusys.h b/plat/mediatek/drivers/apusys/apusys.h
index 5fdd2ec..1592cff 100644
--- a/plat/mediatek/drivers/apusys/apusys.h
+++ b/plat/mediatek/drivers/apusys/apusys.h
@@ -9,4 +9,10 @@
#define MODULE_TAG "[APUSYS]"
+enum MTK_APUSYS_KERNEL_OP {
+ MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF,/* 1 */
+ MTK_APUSYS_KERNEL_OP_NUM,
+};
+
#endif
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
index d7b0d24..ac62f2f 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
@@ -10,6 +10,7 @@
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
+#include <lib/spinlock.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
@@ -18,6 +19,9 @@
#include "apusys_power.h"
#include <mtk_mmap_pool.h>
+static spinlock_t apu_lock;
+static bool apusys_top_on;
+
static int apu_poll(uintptr_t reg, uint32_t mask, uint32_t value, uint32_t timeout_us)
{
uint32_t reg_val, count;
@@ -43,6 +47,135 @@
return -1;
}
+static void apu_xpu2apusys_d4_slv_en(enum APU_D4_SLV_CTRL en)
+{
+ switch (en) {
+ case D4_SLV_OFF:
+ mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0,
+ INFRA_FMEM_BUS_u_SI21_CTRL_EN);
+ mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0,
+ INFRA_FMEM_BUS_u_SI22_CTRL_EN);
+ mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0,
+ INFRA_FMEM_BUS_u_SI11_CTRL_EN);
+ mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0,
+ INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN);
+ break;
+ case D4_SLV_ON:
+ mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0,
+ INFRA_FMEM_BUS_u_SI21_CTRL_EN);
+ mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0,
+ INFRA_FMEM_BUS_u_SI22_CTRL_EN);
+ mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0,
+ INFRA_FMEM_BUS_u_SI11_CTRL_EN);
+ mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0,
+ INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN);
+ break;
+ default:
+ ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, en);
+ break;
+ }
+}
+
+static void apu_pwr_flow_remote_sync(uint32_t cfg)
+{
+ mmio_write_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG, (cfg & 0x1));
+}
+
+int apusys_kernel_apusys_pwr_top_on(void)
+{
+ int ret;
+
+ spin_lock(&apu_lock);
+
+ if (apusys_top_on == true) {
+ INFO(MODULE_TAG "%s: APUSYS already powered on!\n", __func__);
+ spin_unlock(&apu_lock);
+ return 0;
+ }
+
+ apu_pwr_flow_remote_sync(1);
+
+ mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, AFC_ENA);
+
+ mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_SET);
+
+ ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY,
+ PWR_RDY, PWR_RDY, APU_TOP_ON_POLLING_TIMEOUT_US);
+ if (ret != 0) {
+ ERROR(MODULE_TAG "%s polling RPC RDY timeout, ret %d\n", __func__, ret);
+ spin_unlock(&apu_lock);
+ return ret;
+ }
+
+ ret = apu_poll(APU_RPC_BASE + APU_RPC_STATUS,
+ RPC_STATUS_RDY, RPC_STATUS_RDY, APU_TOP_ON_POLLING_TIMEOUT_US);
+ if (ret != 0) {
+ ERROR(MODULE_TAG "%s polling ARE FSM timeout, ret %d\n", __func__, ret);
+ spin_unlock(&apu_lock);
+ return ret;
+ }
+
+ mmio_write_32(APU_VCORE_BASE + APUSYS_VCORE_CG_CLR, CG_CLR);
+ mmio_write_32(APU_RCX_BASE + APU_RCX_CG_CLR, CG_CLR);
+
+ apu_xpu2apusys_d4_slv_en(D4_SLV_OFF);
+
+ apusys_top_on = true;
+
+ spin_unlock(&apu_lock);
+ return ret;
+}
+
+static void apu_sleep_rpc_rcx(void)
+{
+ mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_CLR);
+ udelay(10);
+
+ mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, (RPC_CTRL | RSV10));
+ udelay(10);
+
+ mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, CLR_IRQ);
+ udelay(10);
+
+ mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, SLEEP_REQ);
+ udelay(100);
+}
+
+int apusys_kernel_apusys_pwr_top_off(void)
+{
+ int ret;
+
+ spin_lock(&apu_lock);
+
+ if (apusys_top_on == false) {
+ INFO(MODULE_TAG "%s: APUSYS already powered off!\n", __func__);
+ spin_unlock(&apu_lock);
+ return 0;
+ }
+
+ apu_xpu2apusys_d4_slv_en(D4_SLV_ON);
+
+ if (mmio_read_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG) == 0) {
+ apu_pwr_flow_remote_sync(1);
+ } else {
+ apu_sleep_rpc_rcx();
+ }
+
+ ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY,
+ PWR_RDY, PWR_OFF, APU_TOP_OFF_POLLING_TIMEOUT_US);
+ if (ret != 0) {
+ ERROR(MODULE_TAG "%s timeout to wait RPC sleep (val:%d), ret %d\n",
+ __func__, APU_TOP_OFF_POLLING_TIMEOUT_US, ret);
+ spin_unlock(&apu_lock);
+ return ret;
+ }
+
+ apusys_top_on = false;
+
+ spin_unlock(&apu_lock);
+ return ret;
+}
+
static void get_pll_pcw(const uint32_t clk_rate, uint32_t *r1, uint32_t *r2)
{
unsigned int fvco = clk_rate;
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.h b/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
index 1f68bd2..b4968d6 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
@@ -24,6 +24,11 @@
APU_ARE_NUM,
};
+enum APU_D4_SLV_CTRL {
+ D4_SLV_OFF = 0,
+ D4_SLV_ON,
+};
+
#define APU_POLL_STEP_US (5)
#define OUT_CLK_FREQ_MIN (1500)
@@ -40,20 +45,26 @@
#define APU_ARE_POLLING_TIMEOUT_US (10000)
/* APU related reg */
+#define APU_VCORE_BASE (APU_RCX_VCORE_CONFIG)
+#define APU_RCX_BASE (APU_RCX_CONFIG)
#define APU_RPC_BASE (APU_RPCTOP)
#define APU_PCU_BASE (APU_PCUTOP)
#define APU_ARE0_BASE (APU_ARETOP_ARE0)
#define APU_ARE1_BASE (APU_ARETOP_ARE1)
#define APU_ARE2_BASE (APU_ARETOP_ARE2)
+#define APU_MBOX0_BASE (APU_MBOX0)
#define APU_AO_CTL_BASE (APU_AO_CTRL)
#define APU_PLL_BASE (APU_PLL)
#define APU_ACC_BASE (APU_ACC)
#define APU_ACX0_RPC_LITE_BASE (APU_ACX0_RPC_LITE)
/* RPC offset define */
+#define APU_RPC_TOP_CON (0x0000)
#define APU_RPC_TOP_SEL (0x0004)
+#define APU_RPC_STATUS (0x0014)
#define APU_RPC_TOP_SEL_1 (0x0018)
#define APU_RPC_HW_CON (0x001c)
+#define APU_RPC_INTF_PWR_RDY (0x0044)
#define APU_RPC_SW_TYPE0 (0x0200)
/* RPC control */
@@ -68,6 +79,15 @@
#define RPC_CTRL (0x0000009e)
#define RPC_TOP_CTRL (0x0800501e)
#define RPC_TOP_CTRL1 BIT(20)
+#define AFC_ENA BIT(16)
+#define REG_WAKEUP_SET BIT(8)
+#define REG_WAKEUP_CLR BIT(12)
+#define PWR_RDY BIT(0)
+#define PWR_OFF (0)
+#define RPC_STATUS_RDY BIT(29)
+#define RSV10 BIT(10)
+#define CLR_IRQ (0x6)
+#define SLEEP_REQ BIT(0)
/* PLL offset define */
#define PLL4H_PLL1_CON1 (0x000c)
@@ -137,6 +157,12 @@
#define ARE_ENTRY1_SRAM_L_INIT (0x76543210)
#define ARE_CONFG_INI BIT(2)
+/* VCORE offset define */
+#define APUSYS_VCORE_CG_CLR (0x0008)
+
+/* RCX offset define */
+#define APU_RCX_CG_CLR (0x0008)
+
/* SPM offset define */
#define APUSYS_BUCK_ISOLATION (0x03ec)
@@ -149,6 +175,18 @@
/* apu_rcx_ao_ctrl control */
#define VCORE_ARE_REQ BIT(2)
+/* xpu2apusys */
+#define INFRA_FMEM_BUS_u_SI21_CTRL_0 (0x002c)
+#define INFRA_FMEM_BUS_u_SI22_CTRL_0 (0x0044)
+#define INFRA_FMEM_BUS_u_SI11_CTRL_0 (0x0048)
+#define INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0 (0x01d0)
+
+/* xpu2apusys */
+#define INFRA_FMEM_BUS_u_SI21_CTRL_EN BIT(12)
+#define INFRA_FMEM_BUS_u_SI22_CTRL_EN BIT(13)
+#define INFRA_FMEM_BUS_u_SI11_CTRL_EN BIT(11)
+#define INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN BIT(15)
+
/* PCU offset define */
#define APU_PCU_CTRL_SET (0x0000)
#define APU_PCU_BUCK_STEP_SEL (0x0030)
@@ -188,6 +226,13 @@
#define APU_RPC_SW_TYPE8 (0x0220)
#define APU_RPC_SW_TYPE9 (0x0224)
+/* power flow sync */
+#define PWR_FLOW_SYNC_REG (0x0440)
+
+#define CG_CLR (0xffffffff)
+
int apusys_power_init(void);
+int apusys_kernel_apusys_pwr_top_on(void);
+int apusys_kernel_apusys_pwr_top_off(void);
#endif /* APUSYS_POWER_H */
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 576dc3d..fc9725e 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -28,6 +28,9 @@
* APUSYS related constants
******************************************************************************/
#define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000)
+#define APU_RCX_CONFIG (IO_PHYS + 0x09020000)
+#define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090e0000)
+#define APU_MBOX0 (IO_PHYS + 0x090e1000)
#define APU_RPCTOP (IO_PHYS + 0x090f0000)
#define APU_PCUTOP (IO_PHYS + 0x090f1000)
#define APU_AO_CTRL (IO_PHYS + 0x090f2000)
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index 803f8e2..98b8254 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -23,15 +23,14 @@
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
#else
-#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
/*
* Define the number of cores per cluster used in calculating core position.
* The cluster number is shifted by this value and added to the core ID,
* so its value represents log2(cores/cluster).
- * Default is 2**(2) = 4 cores per cluster.
+ * Default is 2**(4) = 16 cores per cluster.
*/
-#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2)
-
+#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(4)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER (U(1) << PLATFORM_CPU_PER_CLUSTER_SHIFT)
#define PLATFORM_CLUSTER_COUNT U(2)
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c
index 2e99ae8..2abf794 100644
--- a/plat/xilinx/versal/aarch64/versal_common.c
+++ b/plat/xilinx/versal/aarch64/versal_common.c
@@ -23,7 +23,7 @@
MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(FPD_MAINCCI_BASE, FPD_MAINCCI_SIZE, MT_DEVICE | MT_RW |
+ MAP_REGION_FLAT(PLAT_ARM_CCI_BASE, PLAT_ARM_CCI_SIZE, MT_DEVICE | MT_RW |
MT_SECURE),
{ 0 }
};
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 2a9e9ad..fb90aa0 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -50,6 +50,7 @@
* CCI-400 related constants
******************************************************************************/
#define PLAT_ARM_CCI_BASE 0xFD000000
+#define PLAT_ARM_CCI_SIZE 0x00100000
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
@@ -110,9 +111,6 @@
#define CRF_RST_APU_ACPU_RESET (1 << 0)
#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
-#define FPD_MAINCCI_BASE 0xFD000000
-#define FPD_MAINCCI_SIZE 0x00100000
-
/* APU registers and bitfields */
#define FPD_APU_BASE 0xFD5C0000U
#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)