diff --git a/.cz.json b/.cz.json
new file mode 100644
index 0000000..cb500ba
--- /dev/null
+++ b/.cz.json
@@ -0,0 +1,5 @@
+{
+    "path": "./node_modules/cz-conventional-changelog",
+    "maxHeaderWidth": 50,
+    "maxLineWidth": 72
+}
\ No newline at end of file
diff --git a/.gitignore b/.gitignore
index 79c5104..f524658 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,3 +42,5 @@
 # Ctags
 tags
 
+# Node.js
+node_modules/
diff --git a/.husky/.gitignore b/.husky/.gitignore
new file mode 100644
index 0000000..31354ec
--- /dev/null
+++ b/.husky/.gitignore
@@ -0,0 +1 @@
+_
diff --git a/.husky/commit-msg b/.husky/commit-msg
new file mode 100755
index 0000000..c1c9600
--- /dev/null
+++ b/.husky/commit-msg
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# shellcheck source=./_/husky.sh
+. "$(dirname "$0")/_/husky.sh"
+
+"$(dirname "$0")/commit-msg.gerrit" "$@"
+"$(dirname "$0")/commit-msg.commitlint" "$@"
diff --git a/.husky/commit-msg.commitlint b/.husky/commit-msg.commitlint
new file mode 100755
index 0000000..ca25ce1
--- /dev/null
+++ b/.husky/commit-msg.commitlint
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+npx --no-install commitlint --edit "$1"
diff --git a/.husky/commit-msg.gerrit b/.husky/commit-msg.gerrit
new file mode 100755
index 0000000..b8ce477
--- /dev/null
+++ b/.husky/commit-msg.gerrit
@@ -0,0 +1,194 @@
+#!/bin/sh
+# From Gerrit Code Review 2.14.20
+#
+# Part of Gerrit Code Review (https://www.gerritcodereview.com/)
+#
+# Copyright (C) 2009 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+unset GREP_OPTIONS
+
+CHANGE_ID_AFTER="Bug|Depends-On|Issue|Test|Feature|Fixes|Fixed"
+MSG="$1"
+
+# Check for, and add if missing, a unique Change-Id
+#
+add_ChangeId() {
+	clean_message=`sed -e '
+		/^diff --git .*/{
+			s///
+			q
+		}
+		/^Signed-off-by:/d
+		/^#/d
+	' "$MSG" | git stripspace`
+	if test -z "$clean_message"
+	then
+		return
+	fi
+
+	# Do not add Change-Id to temp commits
+	if echo "$clean_message" | head -1 | grep -q '^\(fixup\|squash\)!'
+	then
+		return
+	fi
+
+	if test "false" = "`git config --bool --get gerrit.createChangeId`"
+	then
+		return
+	fi
+
+	# Does Change-Id: already exist? if so, exit (no change).
+	if grep -i '^Change-Id:' "$MSG" >/dev/null
+	then
+		return
+	fi
+
+	id=`_gen_ChangeId`
+	T="$MSG.tmp.$$"
+	AWK=awk
+	if [ -x /usr/xpg4/bin/awk ]; then
+		# Solaris AWK is just too broken
+		AWK=/usr/xpg4/bin/awk
+	fi
+
+	# Get core.commentChar from git config or use default symbol
+	commentChar=`git config --get core.commentChar`
+	commentChar=${commentChar:-#}
+
+	# How this works:
+	# - parse the commit message as (textLine+ blankLine*)*
+	# - assume textLine+ to be a footer until proven otherwise
+	# - exception: the first block is not footer (as it is the title)
+	# - read textLine+ into a variable
+	# - then count blankLines
+	# - once the next textLine appears, print textLine+ blankLine* as these
+	#   aren't footer
+	# - in END, the last textLine+ block is available for footer parsing
+	$AWK '
+	BEGIN {
+		if (match(ENVIRON["OS"], "Windows")) {
+			RS="\r?\n" # Required on recent Cygwin
+		}
+		# while we start with the assumption that textLine+
+		# is a footer, the first block is not.
+		isFooter = 0
+		footerComment = 0
+		blankLines = 0
+	}
+
+	# Skip lines starting with commentChar without any spaces before it.
+	/^'"$commentChar"'/ { next }
+
+	# Skip the line starting with the diff command and everything after it,
+	# up to the end of the file, assuming it is only patch data.
+	# If more than one line before the diff was empty, strip all but one.
+	/^diff --git / {
+		blankLines = 0
+		while (getline) { }
+		next
+	}
+
+	# Count blank lines outside footer comments
+	/^$/ && (footerComment == 0) {
+		blankLines++
+		next
+	}
+
+	# Catch footer comment
+	/^\[[a-zA-Z0-9-]+:/ && (isFooter == 1) {
+		footerComment = 1
+	}
+
+	/]$/ && (footerComment == 1) {
+		footerComment = 2
+	}
+
+	# We have a non-blank line after blank lines. Handle this.
+	(blankLines > 0) {
+		print lines
+		for (i = 0; i < blankLines; i++) {
+			print ""
+		}
+
+		lines = ""
+		blankLines = 0
+		isFooter = 1
+		footerComment = 0
+	}
+
+	# Detect that the current block is not the footer
+	(footerComment == 0) && (!/^\[?[a-zA-Z0-9-]+:/ || /^[a-zA-Z0-9-]+:\/\//) {
+		isFooter = 0
+	}
+
+	{
+		# We need this information about the current last comment line
+		if (footerComment == 2) {
+			footerComment = 0
+		}
+		if (lines != "") {
+			lines = lines "\n";
+		}
+		lines = lines $0
+	}
+
+	# Footer handling:
+	# If the last block is considered a footer, splice in the Change-Id at the
+	# right place.
+	# Look for the right place to inject Change-Id by considering
+	# CHANGE_ID_AFTER. Keys listed in it (case insensitive) come first,
+	# then Change-Id, then everything else (eg. Signed-off-by:).
+	#
+	# Otherwise just print the last block, a new line and the Change-Id as a
+	# block of its own.
+	END {
+		unprinted = 1
+		if (isFooter == 0) {
+			print lines "\n"
+			lines = ""
+		}
+		changeIdAfter = "^(" tolower("'"$CHANGE_ID_AFTER"'") "):"
+		numlines = split(lines, footer, "\n")
+		for (line = 1; line <= numlines; line++) {
+			if (unprinted && match(tolower(footer[line]), changeIdAfter) != 1) {
+				unprinted = 0
+				print "Change-Id: I'"$id"'"
+			}
+			print footer[line]
+		}
+		if (unprinted) {
+			print "Change-Id: I'"$id"'"
+		}
+	}' "$MSG" > "$T" && mv "$T" "$MSG" || rm -f "$T"
+}
+_gen_ChangeIdInput() {
+	echo "tree `git write-tree`"
+	if parent=`git rev-parse "HEAD^0" 2>/dev/null`
+	then
+		echo "parent $parent"
+	fi
+	echo "author `git var GIT_AUTHOR_IDENT`"
+	echo "committer `git var GIT_COMMITTER_IDENT`"
+	echo
+	printf '%s' "$clean_message"
+}
+_gen_ChangeId() {
+	_gen_ChangeIdInput |
+	git hash-object -t commit --stdin
+}
+
+
+add_ChangeId
diff --git a/.husky/prepare-commit-msg b/.husky/prepare-commit-msg
new file mode 100755
index 0000000..593dfa8
--- /dev/null
+++ b/.husky/prepare-commit-msg
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+# shellcheck source=./_/husky.sh
+. "$(dirname "$0")/_/husky.sh"
+
+"$(dirname "$0")/prepare-commit-msg.cz" "$@"
diff --git a/.husky/prepare-commit-msg.cz b/.husky/prepare-commit-msg.cz
new file mode 100755
index 0000000..724527d
--- /dev/null
+++ b/.husky/prepare-commit-msg.cz
@@ -0,0 +1,28 @@
+#!/bin/bash
+
+file="$1"
+type="$2"
+
+if [ -z "$type" ]; then # only run on new commits
+    #
+    # Save any commit message trailers generated by Git.
+    #
+
+    trailers=$(git interpret-trailers --parse "$file")
+
+    #
+    # Execute the Commitizen hook.
+    #
+
+    (exec < "/dev/tty" && npx --no-install git-cz --hook) || true
+
+    #
+    # Restore any trailers that Commitizen might have overwritten.
+    #
+
+    printf "\n" >> "$file"
+
+    while IFS= read -r trailer; do
+        git interpret-trailers --in-place --trailer "$trailer" "$file"
+    done <<< "$trailers"
+fi
diff --git a/Makefile b/Makefile
index b6c8b21..4dbc2be 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
 # Trusted Firmware Version
 #
 VERSION_MAJOR			:= 2
-VERSION_MINOR			:= 4
+VERSION_MINOR			:= 5
 
 # Default goal is build all images
 .DEFAULT_GOAL			:= all
@@ -245,6 +245,13 @@
 # Determine if FEAT_RNG is supported
 ENABLE_FEAT_RNG		=	$(if $(findstring rng,${arch-features}),1,0)
 
+# Determine if FEAT_SB is supported
+ENABLE_FEAT_SB		=	$(if $(findstring sb,${arch-features}),1,0)
+
+ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_SB		= 	1
+endif
+
 ifneq ($(findstring armclang,$(notdir $(CC))),)
 TF_CFLAGS_aarch32	=	-target arm-arm-none-eabi $(march32-directive)
 TF_CFLAGS_aarch64	=	-target aarch64-arm-none-eabi $(march64-directive)
@@ -327,7 +334,7 @@
 
 # General warnings
 WARNINGS		:=	-Wall -Wmissing-include-dirs -Wunused	\
-				-Wdisabled-optimization	-Wvla -Wshadow	\
+				-Wdisabled-optimization -Wvla -Wshadow	\
 				-Wno-unused-parameter -Wredundant-decls
 
 # Additional warnings
@@ -514,6 +521,10 @@
         ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
             DTC_CPPFLAGS	+=	-DOPTEE_SP_FW_CONFIG
         endif
+
+        ifeq ($(TS_SP_FW_CONFIG),1)
+            DTC_CPPFLAGS	+=	-DTS_SP_FW_CONFIG
+        endif
     else
         # All other SPDs in spd directory
         SPD_DIR := spd
@@ -572,11 +583,9 @@
 endif
 	BL31_CFLAGS	+=	-fpie
 	BL31_LDFLAGS	+=	$(PIE_LDFLAGS)
-ifeq ($(ARCH),aarch64)
 	BL32_CFLAGS	+=	-fpie
 	BL32_LDFLAGS	+=	$(PIE_LDFLAGS)
 endif
-endif
 
 ifeq (${ARCH},aarch64)
 BL1_CPPFLAGS += -DIMAGE_AT_EL3
@@ -726,6 +735,9 @@
     endif
 endif
 
+# Trusted Boot is a prerequisite for Measured Boot. It provides trust that the
+# code taking the measurements and recording them has not been tampered
+# with. This is referred to as the Root of Trust for Measurement.
 ifeq ($(MEASURED_BOOT),1)
     ifneq (${TRUSTED_BOARD_BOOT},1)
         $(error MEASURED_BOOT requires TRUSTED_BOARD_BOOT=1)
@@ -904,6 +916,7 @@
         ENABLE_RUNTIME_INSTRUMENTATION \
         ENABLE_SPE_FOR_LOWER_ELS \
         ENABLE_SVE_FOR_NS \
+        ENABLE_SVE_FOR_SWD \
         ERROR_DEPRECATED \
         FAULT_INJECTION_SUPPORT \
         GENERATE_COT \
@@ -945,6 +958,7 @@
         COT_DESC_IN_DTB \
         USE_SP804_TIMER \
         ENABLE_FEAT_RNG \
+        ENABLE_FEAT_SB \
 )))
 
 $(eval $(call assert_numerics,\
@@ -996,6 +1010,7 @@
         ENABLE_RUNTIME_INSTRUMENTATION \
         ENABLE_SPE_FOR_LOWER_ELS \
         ENABLE_SVE_FOR_NS \
+        ENABLE_SVE_FOR_SWD \
         ENCRYPT_BL31 \
         ENCRYPT_BL32 \
         ERROR_DEPRECATED \
@@ -1038,6 +1053,7 @@
         COT_DESC_IN_DTB \
         USE_SP804_TIMER \
         ENABLE_FEAT_RNG \
+        ENABLE_FEAT_SB \
 )))
 
 ifeq (${SANITIZE_UB},trap)
@@ -1298,8 +1314,6 @@
 fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME}
 
 ${FIPTOOL}: FORCE
-	@${ECHO_BLANK_LINE}
-	@echo "Building $@"
 ifdef UNIX_MK
 	${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH}
 else
@@ -1307,7 +1321,6 @@
 # to pass the gnumake flags to nmake.
 	${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL))
 endif
-	@${ECHO_BLANK_LINE}
 
 sptool: ${SPTOOL}
 ${SPTOOL}: FORCE
diff --git a/bl1/aarch32/bl1_entrypoint.S b/bl1/aarch32/bl1_entrypoint.S
index 6a15566..94dfd37 100644
--- a/bl1/aarch32/bl1_entrypoint.S
+++ b/bl1/aarch32/bl1_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -49,7 +49,8 @@
 		_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU	\
 		_init_memory=1					\
 		_init_c_runtime=1				\
-		_exception_vectors=bl1_vector_table
+		_exception_vectors=bl1_vector_table		\
+		_pie_fixup_size=0
 
 	/* -----------------------------------------------------
 	 * Perform BL1 setup
diff --git a/bl2/aarch32/bl2_el3_entrypoint.S b/bl2/aarch32/bl2_el3_entrypoint.S
index 2e851e6..7e85551 100644
--- a/bl2/aarch32/bl2_el3_entrypoint.S
+++ b/bl2/aarch32/bl2_el3_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,7 +26,8 @@
                 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU      \
                 _init_memory=1                                  \
                 _init_c_runtime=1                               \
-                _exception_vectors=bl2_vector_table
+                _exception_vectors=bl2_vector_table		\
+		_pie_fixup_size=0
 
 	/*
 	 * Restore parameters of boot rom
diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S
index 102fd2f..6e8e2c1 100644
--- a/bl2/aarch32/bl2_entrypoint.S
+++ b/bl2/aarch32/bl2_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -80,12 +80,14 @@
 	 * ---------------------------------------------
 	 */
 	ldr	r0, =__BSS_START__
-	ldr	r1, =__BSS_SIZE__
+	ldr	r1, =__BSS_END__
+	sub 	r1, r1, r0
 	bl	zeromem
 
 #if USE_COHERENT_MEM
 	ldr	r0, =__COHERENT_RAM_START__
-	ldr	r1, =__COHERENT_RAM_UNALIGNED_SIZE__
+	ldr	r1, =__COHERENT_RAM_END_UNALIGNED__
+	sub 	r1, r1, r0
 	bl	zeromem
 #endif
 
diff --git a/bl2u/aarch32/bl2u_entrypoint.S b/bl2u/aarch32/bl2u_entrypoint.S
index 6391f53..e4dd03d 100644
--- a/bl2u/aarch32/bl2u_entrypoint.S
+++ b/bl2u/aarch32/bl2u_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -79,7 +79,8 @@
 	 * ---------------------------------------------
 	 */
 	ldr	r0, =__BSS_START__
-	ldr	r1, =__BSS_SIZE__
+	ldr	r1, =__BSS_END__
+	sub 	r1, r1, r0
 	bl	zeromem
 
 	/* --------------------------------------------
diff --git a/bl2u/aarch64/bl2u_entrypoint.S b/bl2u/aarch64/bl2u_entrypoint.S
index 3e37b44..15978b6 100644
--- a/bl2u/aarch64/bl2u_entrypoint.S
+++ b/bl2u/aarch64/bl2u_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -69,8 +69,11 @@
 	 *   - the coherent memory section.
 	 * ---------------------------------------------
 	 */
-	ldr	x0, =__BSS_START__
-	ldr	x1, =__BSS_SIZE__
+	adrp	x0, __BSS_START__
+	add	x0, x0, :lo12:__BSS_START__
+	adrp	x1, __BSS_END__
+	add	x1, x1, :lo12:__BSS_END__
+	sub	x1, x1, x0
 	bl	zeromem
 
 	/* --------------------------------------------
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 2088533..1fdf545 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -95,6 +95,10 @@
 				lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
 endif
 
+ifeq ($(SMC_PCI_SUPPORT),1)
+BL31_SOURCES		+=	services/std_svc/pci_svc.c
+endif
+
 BL31_LINKERFILE		:=	bl31/bl31.ld.S
 
 # Flag used to indicate if Crash reporting via console should be included
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index f3a1e44..39f1065 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,6 +23,8 @@
 	.globl	sp_min_handle_smc
 	.globl	sp_min_handle_fiq
 
+#define FIXUP_SIZE	((BL32_LIMIT) - (BL32_BASE))
+
 	.macro route_fiq_to_sp_min reg
 		/* -----------------------------------------------------
 		 * FIQs are secure interrupts trapped by Monitor and non
@@ -87,7 +89,8 @@
 		_secondary_cold_boot=0				\
 		_init_memory=0					\
 		_init_c_runtime=1				\
-		_exception_vectors=sp_min_vector_table
+		_exception_vectors=sp_min_vector_table		\
+		_pie_fixup_size=FIXUP_SIZE
 
 	/* ---------------------------------------------------------------------
 	 * Relay the previous bootloader's arguments to the platform layer
@@ -106,7 +109,8 @@
 		_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU	\
 		_init_memory=1					\
 		_init_c_runtime=1				\
-		_exception_vectors=sp_min_vector_table
+		_exception_vectors=sp_min_vector_table		\
+		_pie_fixup_size=FIXUP_SIZE
 
 	/* ---------------------------------------------------------------------
 	 * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
@@ -306,7 +310,8 @@
 		_secondary_cold_boot=0				\
 		_init_memory=0					\
 		_init_c_runtime=0				\
-		_exception_vectors=sp_min_vector_table
+		_exception_vectors=sp_min_vector_table		\
+		_pie_fixup_size=0
 
 	/*
 	 * We're about to enable MMU and participate in PSCI state coordination.
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S
index f202c7a..475affa 100644
--- a/bl32/sp_min/sp_min.ld.S
+++ b/bl32/sp_min/sp_min.ld.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -92,6 +92,7 @@
     __RW_START__ = . ;
 
     DATA_SECTION >RAM
+    RELA_SECTION >RAM
 
 #ifdef BL32_PROGBITS_LIMIT
     ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
@@ -141,5 +142,9 @@
 
     __BL32_END__ = .;
 
+    /DISCARD/ : {
+        *(.dynsym .dynstr .hash .gnu.hash)
+    }
+
     ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
 }
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index a007bab..795c586 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -114,13 +114,19 @@
 	 *   - the coherent memory section.
 	 * ---------------------------------------------
 	 */
-	ldr	x0, =__BSS_START__
-	ldr	x1, =__BSS_SIZE__
+	adrp	x0, __BSS_START__
+	add	x0, x0, :lo12:__BSS_START__
+	adrp	x1, __BSS_END__
+	add	x1, x1, :lo12:__BSS_END__
+	sub	x1, x1, x0
 	bl	zeromem
 
 #if USE_COHERENT_MEM
-	ldr	x0, =__COHERENT_RAM_START__
-	ldr	x1, =__COHERENT_RAM_UNALIGNED_SIZE__
+	adrp	x0, __COHERENT_RAM_START__
+	add	x0, x0, :lo12:__COHERENT_RAM_START__
+	adrp	x1, __COHERENT_RAM_END_UNALIGNED__
+	add	x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
+	sub	x1, x1, x0
 	bl	zeromem
 #endif
 
diff --git a/commitlint.config.js b/commitlint.config.js
new file mode 100644
index 0000000..94cad8f
--- /dev/null
+++ b/commitlint.config.js
@@ -0,0 +1,14 @@
+/* eslint-env node */
+
+"use strict";
+
+const config = require("./.cz.json");
+
+module.exports = {
+    extends: ["@commitlint/config-conventional"],
+    rules: {
+        "header-max-length": [1, "always", config.maxHeaderWidth], /* Warning */
+        "body-max-line-length": [1, "always", config.maxLineWidth], /* Warning */
+        "signed-off-by": [0, "always", "Signed-off-by:"] /* Disabled - buggy */
+    }
+};
diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index 5aad14e..dd7a0fa 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,12 +7,14 @@
 /* Helper functions to offer easier navigation of Device Tree Blob */
 
 #include <assert.h>
+#include <errno.h>
 #include <string.h>
 
 #include <libfdt.h>
 
 #include <common/debug.h>
 #include <common/fdt_wrappers.h>
+#include <common/uuid.h>
 
 /*
  * Read cells from a given property of the given node. Any number of 32-bit
@@ -152,6 +154,39 @@
 }
 
 /*
+ * Read UUID from a given property of the given node. Returns 0 on success,
+ * and a negative value upon error.
+ */
+int fdtw_read_uuid(const void *dtb, int node, const char *prop,
+		   unsigned int length, uint8_t *uuid)
+{
+	/* Buffer for UUID string (plus NUL terminator) */
+	char uuid_string[UUID_STRING_LENGTH + 1U];
+	int err;
+
+	assert(dtb != NULL);
+	assert(prop != NULL);
+	assert(uuid != NULL);
+	assert(node >= 0);
+
+	if (length < UUID_BYTES_LENGTH) {
+		return -EINVAL;
+	}
+
+	err = fdtw_read_string(dtb, node, prop, uuid_string,
+			       UUID_STRING_LENGTH + 1U);
+	if (err != 0) {
+		return err;
+	}
+
+	if (read_uuid(uuid, uuid_string) != 0) {
+		return -FDT_ERR_BADVALUE;
+	}
+
+	return 0;
+}
+
+/*
  * Write cells in place to a given property of the given node. At most 2 cells
  * of the property are written. Returns 0 on success, and -1 upon error.
  */
diff --git a/common/hw_crc32.c b/common/hw_crc32.c
new file mode 100644
index 0000000..a8731da
--- /dev/null
+++ b/common/hw_crc32.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include <arm_acle.h>
+#include <common/debug.h>
+
+/* hw_crc32 - compute CRC using Arm intrinsic function
+ *
+ * This function is useful for the platforms with the CPU ARMv8.0
+ * (with CRC instructions supported), and onwards.
+ * Platforms with CPU ARMv8.0 should make sure to add a compile switch
+ * '-march=armv8-a+crc" for successful compilation of this file.
+ *
+ * @crc: previous accumulated CRC
+ * @buf: buffer base address
+ * @size: the size of the buffer
+ *
+ * Return calculated CRC value
+ */
+uint32_t hw_crc32(uint32_t crc, const unsigned char *buf, size_t size)
+{
+	assert(buf != NULL);
+
+	uint32_t calc_crc = ~crc;
+	const unsigned char *local_buf = buf;
+	size_t local_size = size;
+
+	/*
+	 * calculate CRC over byte data
+	 */
+	while (local_size != 0UL) {
+		calc_crc = __crc32b(calc_crc, *local_buf);
+		local_buf++;
+		local_size--;
+	}
+
+	return ~calc_crc;
+}
diff --git a/common/uuid.c b/common/uuid.c
new file mode 100644
index 0000000..ac6db50
--- /dev/null
+++ b/common/uuid.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <common/uuid.h>
+
+/* Return the hex nibble value of a char */
+static int8_t hex_val(char hex)
+{
+	int8_t val = 0;
+
+	if ((hex >= '0') && (hex <= '9')) {
+		val = (int8_t)(hex - '0');
+	} else if ((hex >= 'a') && (hex <= 'f')) {
+		val = (int8_t)(hex - 'a' + 0xa);
+	} else if ((hex >= 'A') && (hex <= 'F')) {
+		val = (int8_t)(hex - 'A' + 0xa);
+	} else {
+		val = -1;
+	}
+
+	return val;
+}
+
+/*
+ * Read hex_src_len hex characters from hex_src, convert to bytes and
+ * store in buffer pointed to by dest
+ */
+static int read_hex(uint8_t *dest, char *hex_src, unsigned int hex_src_len)
+{
+	int8_t nibble;
+	uint8_t byte;
+
+	/*
+	 * The string length must be a multiple of 2 to represent an
+	 * exact number of bytes.
+	 */
+	assert((hex_src_len % 2U) == 0U);
+
+	for (unsigned int i = 0U; i < (hex_src_len / 2U); i++) {
+		nibble = 0;
+		byte = 0U;
+
+		nibble = hex_val(hex_src[2U * i]);
+		if (nibble < 0) {
+			return -1;
+		}
+		byte = (uint8_t)nibble;
+		byte <<= 4U;
+
+		nibble = hex_val(hex_src[(2U * i) + 1U]);
+		if (nibble < 0) {
+			return -1;
+		}
+		byte |= (uint8_t)nibble;
+
+		*dest = byte;
+		dest++;
+	}
+
+	return 0;
+}
+
+/* Parse UUIDs of the form aabbccdd-eeff-4099-8877-665544332211 */
+int read_uuid(uint8_t *dest, char *uuid)
+{
+	int err;
+	uint8_t *dest_start = dest;
+
+	/* Check that we have enough characters */
+	if (strnlen(uuid, UUID_STRING_LENGTH) != UUID_STRING_LENGTH) {
+		WARN("UUID string is too short\n");
+		return -EINVAL;
+	}
+
+	/* aabbccdd */
+	err = read_hex(dest, uuid, 8);
+	uuid += 8;
+	dest += 4;
+
+	/* Check for '-' */
+	err |= ((*uuid == '-') ? 0 : -1);
+	uuid++;
+
+	/* eeff */
+	err |= read_hex(dest, uuid, 4);
+	uuid += 4;
+	dest += 2;
+
+	/* Check for '-' */
+	err |= ((*uuid == '-') ? 0 : -1);
+	uuid++;
+
+	/* 4099 */
+	err |= read_hex(dest, uuid, 4);
+	uuid += 4;
+	dest += 2;
+
+	/* Check for '-' */
+	err |= ((*uuid == '-') ? 0 : -1);
+	uuid++;
+
+	/* 8877 */
+	err |= read_hex(dest, uuid, 4);
+	uuid += 4;
+	dest += 2;
+
+	/* Check for '-' */
+	err |= ((*uuid == '-') ? 0 : -1);
+	uuid++;
+
+	/* 665544332211 */
+	err |= read_hex(dest, uuid, 12);
+	uuid += 12;
+	dest += 6;
+
+	if (err < 0) {
+		WARN("Error parsing UUID\n");
+		/* Clear the buffer on error */
+		memset((void *)dest_start, '\0', UUID_BYTES_LENGTH * sizeof(uint8_t));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
diff --git a/docs/_static/css/custom.css b/docs/_static/css/custom.css
new file mode 100644
index 0000000..f6f5fa0
--- /dev/null
+++ b/docs/_static/css/custom.css
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * Set the white-space property of tables to normal.
+ * With this setting sequences of whitespace inside
+ * a table will collapse into a single whitespace,
+ * and text will wrap when necessary.
+ */
+.wy-table-responsive table td {
+white-space: normal;
+}
diff --git a/docs/about/features.rst b/docs/about/features.rst
index 964cb25..f5fc1e0 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -108,7 +108,7 @@
 
 -  Refinements to Position Independent Executable (PIE) support.
 
--  Continued support for the PSA FF-A v1.0 (formally known as SPCI) specification, to enable the
+-  Continued support for the FF-A v1.0 (formally known as SPCI) specification, to enable the
    use of secure partition management in the secure world.
 
 -  Documentation enhancements.
@@ -126,4 +126,4 @@
 
 --------------
 
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 0b3f782..725e96b 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -142,6 +142,15 @@
 :|F|: include/drivers/ufs.h
 :|F|: include/drivers/synopsys/dw_mmc.h
 
+JTAG DCC console driver
+^^^^^^^^^^^^^^^^^^^^^^^
+:M: Michal Simek <michal.simek@xilinx.com>
+:G: `michalsimek`_
+:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
+:G: `venkatesh`_
+:F: drivers/arm/dcc/
+:F: include/drivers/arm/dcc.h
+
 Power State Coordination Interface (PSCI)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
@@ -390,6 +399,7 @@
 :|G|: `vishnu-banavath`_
 :|F|: plat/arm/board/corstone700
 :|F|: plat/arm/board/a5ds
+:|F|: plat/arm/board/diphda
 
 Arm Reference Design platform ports
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -440,8 +450,8 @@
 
 MediaTek platform ports
 ^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Yidi Lin (林以廸) <yidi.lin@mediatek.com>
-:|G|: `mtk09422`_
+:|M|: Rex-BC Chen <rex-bc.chen@mediatek.com>
+:|G|: `mtk-rex-bc-chen`_
 :|F|: plat/mediatek/
 
 Marvell platform ports and SoC drivers
@@ -484,8 +494,8 @@
 
 NXP i.MX 8 platform port
 ^^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Anson Huang <Anson.Huang@nxp.com>
-:|G|: `Anson-Huang`_
+:|M|: Peng Fan <peng.fan@nxp.com>
+:|G|: `MrVan`_
 :|F|: docs/plat/imx8.rst
 :|F|: plat/imx/
 
@@ -496,6 +506,24 @@
 :|F|: docs/plat/imx8m.rst
 :|F|: plat/imx/imx8m/
 
+NXP QorIQ Layerscape common code for platform ports
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
+:|G|: `pangupta`_
+:|F|: docs/plat/nxp/
+:|F|: plat/nxp/
+:|F|: drivers/nxp/
+:|F|: tools/nxp/
+
+NXP SoC Part LX2160A and its platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
+:|G|: `pangupta`_
+:|F|: plat/nxp/soc-lx2160a
+:|F|: plat/nxp/soc-lx2160a/lx2162aqds
+:|F|: plat/nxp/soc-lx2160a/lx2160aqds
+:|F|: plat/nxp/soc-lx2160a/lx2160ardb
+
 QEMU platform port
 ^^^^^^^^^^^^^^^^^^
 :|M|: Jens Wiklander <jens.wiklander@linaro.org>
@@ -567,6 +595,8 @@
 :|G|: `rockchip-linux`_
 :|M|: Heiko Stuebner <heiko@sntech.de>
 :|G|: `mmind`_
+:|M|: Julius Werner <jwerner@chromium.org>
+:|G|: `jwerner-chromium`_
 :|F|: plat/rockchip/
 
 STM32MP1 platform port
@@ -672,6 +702,20 @@
 :|F|: Makefile
 :|F|: make_helpers/
 
+Threat Model
+~~~~~~~~~~~~~
+:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com>
+:|G|: `zelalem-aweke`_
+:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
+:|G|: `sandrine-bailleux-arm`_
+:|M|: Joanna Farley <joanna.farley@arm.com>
+:|G|: `joannafarley-arm`_
+:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
+:|G|: `raghuncstate`_
+:|M|: Varun Wadekar <vwadekar@nvidia.com>
+:|G|: `vwadekar`_
+:|F|: docs/threat_model/
+
 .. _AlexeiFedorov: https://github.com/AlexeiFedorov
 .. _Andre-ARM: https://github.com/Andre-ARM
 .. _Anson-Huang: https://github.com/Anson-Huang
@@ -694,7 +738,7 @@
 .. _michalsimek: https://github.com/michalsimek
 .. _mmind: https://github.com/mmind
 .. _MrVan: https://github.com/MrVan
-.. _mtk09422: https://github.com/mtk09422
+.. _mtk-rex-bc-chen: https://github.com/mtk-rex-bc-chen
 .. _niej: https://github.com/niej
 .. _npoushin: https://github.com/npoushin
 .. _prabhakarlad: https://github.com/prabhakarlad
@@ -736,5 +780,6 @@
 .. _vijayenthiran-arm: https://github.com/vijayenthiran-arm
 .. _arugan02: https://github.com/arugan02
 .. _uarif1: https://github.com/uarif1
+.. _pangupta: https://github.com/pangupta
 
 .. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index 55c8bda..3e8dd91 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -44,7 +44,9 @@
 +-----------------+---------------------------+------------------------------+
 | v2.4            | 2nd week of Nov '20       | 4th week of Oct '20          |
 +-----------------+---------------------------+------------------------------+
-| v2.5            | 2nd week of May '21       | 4th week of Apr '21          |
+| v2.5            | 3rd week of May '21       | 5th week of Apr '21          |
++-----------------+---------------------------+------------------------------+
+| v2.6            | 4th week of Oct '21       | 1st week of Oct '21          |
 +-----------------+---------------------------+------------------------------+
 
 Removal of Deprecated Interfaces
@@ -64,4 +66,4 @@
 
 --------------
 
-*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst
deleted file mode 100644
index 03806d9..0000000
--- a/docs/change-log-upcoming.rst
+++ /dev/null
@@ -1,149 +0,0 @@
-Change Log for Upcoming Release
-===============================
-
-This document contains a summary of the new features, changes, fixes and known
-issues to be included in the upcoming release of Trusted Firmware-A. The contents
-of this file will be moved to the collective change-log.rst file at the time of
-release code freeze.
-
-
-Upcoming Release Version 2.4
-----------------------------
-
-**Trusted Firmware-A Contributors,
-Please log all relevant new features, changes, fixes, and known issues for the
-upcoming release.  For the CPU support, drivers, and tools sections please preface
-the log description with the relevant key word, example: "<CPU>: <CPU Support
-addition>".  Use the RST format convention already used in the Change Log.**
-
-New Features
-^^^^^^^^^^^^
-
-- Arm Architecture
-   - Example: "Add support for Branch Target Identification (BTI)"
-
-- BL-specific
-   - Example: "Enhanced BL2 bootloader flow to load secure partitions based
-     on firmware configuration data (fconf)."
-
-- Build System
-   - Example: "Modify FVP makefile for CPUs that support both AArch64/32"
-
-- CPU Support
-   - Example: "cortex-a55: Workaround for erratum 1221012"
-
-- Drivers
-   - Example: "console: Allow the console to register multiple times"
-
-- Libraries
-   - Example: "Introduce BTI support in Library at ROM (romlib)"
-
-- New Platforms Support
-   - Example: "qemu/qemu_sbsa: New platform support added for QEMU SBSA platform"
-
-- Platforms
-   - Example: "arm/common: Introduce wrapper functions to setup secure watchdog"
-
-- PSCI
-   - Example: "Adding new optional PSCI hook ``pwr_domain_on_finish_late``"
-
-- Security
-   - Example: "UBSAN support and handlers"
-
-- Tools
-   - Example: "fiptool: Add support to build fiptool on Windows."
-
-
-Changed
-^^^^^^^
-
-- Arm Architecture
-   - Example: "Refactor ARMv8.3 Pointer Authentication support code"
-
-- BL-Specific
-   - Example: "BL2: Invalidate dcache build option for BL2 entry at EL3"
-
-- Boot Flow
-   - Example: "Add helper to parse BL31 parameters (both versions)"
-
-- Drivers
-   - Example: "gicv3: Prevent pending G1S interrupt from becoming G0 interrupt"
-
-- Platforms
-   - Example: "arm/common: Shorten the Firmware Update (FWU) process"
-
-- PSCI
-   - Example: "PSCI: Lookup list of parent nodes to lock only once"
-
-- Secure Partition Manager (SPM)
-   - Example: "Move shim layer to TTBR1_EL1"
-
-- Security
-   - Example: "Refactor SPSR initialisation code"
-
-- Tools
-   - Example: "cert_create: Remove RSA PKCS#1 v1.5 support"
-
-
-Resolved Issues
-^^^^^^^^^^^^^^^
-
-- Arm Architecture
-   - Example: "Fix restoration of PAuth context"
-
-- BL-Specific
-   - Example: "Fix BL31 crash reporting on AArch64 only platforms"
-
-- Build System
-   - Example: "Remove several warnings reported with W=2 and W=1"
-
-- Code Quality
-   - Example: "Unify type of "cpu_idx" across PSCI module"
-
-- CPU Support
-   - Example: "cortex-a12: Fix MIDR mask"
-
-- Drivers
-   - Example: "scmi: Fix wrong payload length"
-
-- Library Code
-   - Example: "libc: Fix memchr implementation"
-
-- Platforms
-   - Example: "rpi: rpi3: Fix compilation error when stack protector is enabled"
-
-- Security
-   - Example: "AArch32: Disable Secure Cycle Counter"
-
-Deprecations
-^^^^^^^^^^^^
-
-- Common Code
-   - Example: "Remove MULTI_CONSOLE_API flag and references to it"
-
-- Drivers
-   - Example: "console: Remove deprecated finish_console_register"
-
-- Secure Partition Manager (SPM):
-   - Example: "Prototype SPCI-based SPM (services/std_svc/spm) will be replaced
-     with alternative methods of secure partitioning support."
-
-Known Issues
-^^^^^^^^^^^^
-
-- Build System
-   - dtb: DTB creation not supported when building on a Windows host.
-
-     This step in the build process is skipped when running on a Windows host. A
-     known issue from the 1.6 release.
-
-- Platforms
-   - arm/juno: System suspend from Linux does not function as documented in the
-     user guide
-
-     Following the instructions provided in the user guide document does not
-     result in the platform entering system suspend state as expected. A message
-     relating to the hdlcd driver failing to suspend will be emitted on the
-     Linux terminal.
-
-   - mediatek/mt6795: This platform does not build in this release
diff --git a/docs/change-log.rst b/docs/change-log.rst
index ec88df9..9c47568 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -4,6 +4,675 @@
 This document contains a summary of the new features, changes, fixes and known
 issues in each release of Trusted Firmware-A.
 
+Version 2.5
+-----------
+
+New Features
+^^^^^^^^^^^^
+
+- Architecture support
+    - Added support for speculation barrier(``FEAT_SB``) for non-Armv8.5
+      platforms starting from Armv8.0
+    - Added support for Activity Monitors Extension version 1.1(``FEAT_AMUv1p1``)
+    - Added helper functions for Random number generator(``FEAT_RNG``) registers
+    - Added support for Armv8.6 Multi-threaded PMU extensions (``FEAT_MTPMU``)
+    - Added support for MTE Asymmetric Fault Handling extensions(``FEAT_MTE3``)
+    - Added support for Privileged Access Never extensions(``FEAT_PANx``)
+
+- Bootloader images
+    - Added PIE support for AArch32 builds
+    - Enable Trusted Random Number Generator service for BL32(sp_min)
+
+- Build System
+    - Added build option for Arm Feature Modifiers
+
+- Drivers
+    - Added support for interrupts in TZC-400 driver
+
+    - Broadcom
+        - Added support for I2C, MDIO and USB drivers
+
+    - Marvell
+        - Added support for secure read/write of dfc register-set
+        - Added support for thermal sensor driver
+        - Implement a3700_core_getc API in console driver
+        - Added rx training on 10G port
+
+    - Marvell Mochi
+        - Added support for cn913x in PCIe mode
+
+    - Marvell Armada A8K
+        - Added support for TRNG-IP-76 driver and accessing RNG register
+
+    - Mediatek MT8192
+        - Added support for following drivers
+            - MPU configuration for SCP/PCIe
+            - SPM suspend
+            - Vcore DVFS
+            - LPM
+            - PTP3
+            - UART save and restore
+            - Power-off
+            - PMIC
+            - CPU hotplug and MCDI support
+            - SPMC
+            - MPU
+
+    - Mediatek MT8195
+        - Added support for following drivers
+            - GPIO, NCDI, SPMC drivers
+            - Power-off
+            - CPU hotplug, reboot and MCDI
+            - Delay timer and sys timer
+            - GIC
+
+    - NXP
+        - Added support for
+            - non-volatile storage API
+            - chain of trust and trusted board boot using two modes: MBEDTLS and CSF
+            - fip-handler necessary for DDR initialization
+            - SMMU and console drivers
+            - crypto hardware accelerator driver
+            - following drivers: SD, EMMC, QSPI, FLEXSPI, GPIO, GIC, CSU, PMU, DDR
+            - NXP Security Monitor and SFP driver
+            - interconnect config APIs using ARM CCN-CCI driver
+            - TZC APIs to configure DDR region
+            - generic timer driver
+            - Device configuration driver
+
+    - IMX
+        - Added support for image loading and io-storage driver for TBBR fip booting
+
+    - Renesas
+        - Added support for PFC and EMMC driver
+
+        - RZ Family:
+            - G2N, G2E and G2H SoCs
+                - Added support for watchdog, QoS, PFC and DRAM initialization
+
+        - RZG Family:
+            - G2M
+                - Added support for QoS and DRAM initialization
+
+    - Xilinx
+        - Added JTAG DCC support for Versal and ZynqMP SoC family.
+
+- Libraries
+    - C standard library
+        - Added support to print ``%`` in ``snprintf()`` and ``printf()`` APIs
+        - Added support for strtoull, strtoll, strtoul, strtol APIs from FreeBSD project
+
+    - CPU support
+        - Added support for
+            - Cortex_A78C CPU
+            - Makalu ELP CPU
+            - Makalu CPU
+            - Matterhorn ELP CPU
+            - Neoverse-N2 CPU
+
+    - CPU Errata
+        - Arm Cortex-A76: Added workaround for erratum 1946160
+
+        - Arm Cortex-A77: Added workaround for erratum 1946167
+
+        - Arm Cortex-A78: Added workaround for erratum 1941498 and 1951500
+
+        - Arm Neoverse-N1: Added workaround for erratum 1946160
+
+    - Flattened device tree(libfdt)
+        - Added support for wrapper function to read UUIDs in string format from dtb
+
+- Platforms
+    - Added support for MediaTek MT8195
+    - Added support for Arm RD-N2 board
+
+    - Allwinner
+        - Added support for H616 SoC
+
+    - Arm
+        - Added support for GPT parser
+        - Protect GICR frames for fused/unused cores
+
+    - Arm Morello
+        - Added VirtIO network device to Morello FVP fdts
+
+    - Arm RD-N2
+        - Added support for variant 1 of RD-N2 platform
+        - Enable AMU support
+
+    - Arm RD-V1
+        - Enable AMU support
+
+    - Arm SGI
+        - Added support for platform variant build option
+
+    - Arm TC0
+        - Added Matterhorn ELP CPU support
+        - Added support for opteed
+
+    - Arm Juno
+        - Added support to use hw_config in BL31
+        - Use TRNG entropy source for SMCCC TRNG interface
+        - Condition Juno entropy source with CRC instructions
+
+    - Marvell Mochi
+        - Added support for detection of secure mode
+
+    - Marvell ARMADA
+        - Added support for new compile option A3720_DB_PM_WAKEUP_SRC
+        - Added support doing system reset via CM3 secure coprocessor
+        - Made several makefile enhancements required to build WTMI_MULTI_IMG and TIMDDRTOOL
+        - Added support for building DOIMAGETOOL tool
+        - Added new target mrvl_bootimage
+
+    - Mediatek MT8192
+        - Added support for rtc power off sequence
+
+    - Mediatek MT8195
+        - Added support for SiP service
+
+    - STM32MP1
+        - Added support for
+            - Seeed ODYSSEY SoM and board
+            - SDMMC2 and I2C2 pins in pinctrl
+            - I2C2 peripheral in DTS
+            - PIE for BL32
+            - TZC-400 interrupt managament
+            - Linux Automation MC-1 board
+
+    - Renesas RZG
+        - Added support for identifying EK874 RZ/G2E board
+        - Added support for identifying HopeRun HiHope RZ/G2H and RZ/G2H boards
+
+    - Rockchip
+        - Added support for stack protector
+
+    - QEMU
+        - Added support for ``max`` CPU
+        - Added Cortex-A72 support to ``virt`` platform
+        - Enabled trigger reboot from secure pl061
+
+    - QEMU SBSA
+        - Added support for sbsa-ref Embedded Controller
+
+    - NXP
+        - Added support for warm reset to retain ddr content
+        - Added support for image loader necessary for loading fip image
+
+        - lx2160a SoC Family
+            - Added support for
+                - new platform lx2160a-aqds
+                - new platform lx2160a-rdb
+                - new platform lx2162a-aqds
+                - errata handling
+
+    - IMX imx8mm
+        - Added support for trusted board boot
+
+    - TI K3
+        - Added support for lite device board
+        - Enabled Cortex-A72 erratum 1319367
+        - Enabled Cortex-A53 erratum 1530924
+
+    - Xilinx ZynqMP
+        - Added support for PS and system reset on WDT restart
+        - Added support for error management
+        - Enable support for log messages necessary for debug
+        - Added support for PM API SMC call for efuse and register access
+
+- Processes
+    - Introduced process for platform deprecation
+    - Added documentation for TF-A threat model
+    - Provided a copy of the MIT license to comply with the license
+      requirements of the arm-gic.h source file (originating from the Linux
+      kernel project and re-distributed in TF-A).
+
+- Services
+    - Added support for TRNG firmware interface service
+
+    - Arm
+        - Added SiP service to configure Ethos-N NPU
+
+    - SPMC
+        - Added documentation for SPM(Hafnium) SMMUv3 driver
+
+    - SPMD
+        - Added support for
+            - FFA_INTERRUPT forwading ABI
+            - FFA_SECONDARY_EP_REGISTER ABI
+            - FF-A v1.0 boot time power management, SPMC secondary core boot and
+              early run-time power management
+
+- Tools
+
+    - FIPTool
+        - Added mechanism to allow platform specific image UUID
+
+    - git hooks
+        - Added support for conventional commits through commitlint hook,
+          commitizen hook and husky configuration files.
+
+    - NXP tool
+        - Added support for a tool that creates pbl file from BL2
+
+    - Renesas RZ/G2
+        - Added tool support for creating bootparam and cert_header images
+
+    - CertCreate
+        - Added support for platform-defined certificates, keys, and extensions using
+          the platform's makefile
+
+    - shared tools
+        - Added EFI_GUID representation to uuid helper data structure
+
+Changed
+^^^^^^^
+
+- Common components
+    - Print newline after hex address in aarch64 el3_panic function
+    - Use proper ``#address-cells`` and ``#size-cells`` for reserved-memory in dtbs
+
+- Drivers
+
+    - Move SCMI driver from ST platform directory and make it common to all platforms
+
+    - Arm GICv3
+        - Shift eSPI register offset in GICD_OFFSET_64()
+        - Use mpidr to probe GICR for current CPU
+
+    - Arm TZC-400
+        - Adjust filter tag if it set to FILTER_BIT_ALL
+
+    - Cadence
+        - Enhance UART driver APIs to put characters to fifo
+
+    - Mediatek MT8192
+        - Move timer driver to common folder
+        - Enhanced sys_cirq driver to add more IC services
+
+    - Renesas
+        - Move ddr and delay driver to common directory
+
+    - Renesas rcar
+        - Treat log as device memory in console driver
+
+    - Renesas RZ Family:
+        - G2N and G2H SoCs
+             - Select MMC_CH1 for eMMC channel
+
+    - Marvell
+        - Added support for checking if TRNG unit is present
+
+    - Marvell A3K
+        - Set TXDCLK_2X_SEL bit during PCIe initialization
+        - Set mask parameter for every reg_set call
+
+    - Marvell Mochi
+        - Added missing stream IDs configurations
+
+    - MbedTLS
+        - Migrated to Mbed TLS v2.26.0
+
+    - IMX imx8mp
+        - Change the bl31 physical load address
+
+    - QEMU SBSA
+        - Enable secure variable storage
+
+    - SCMI
+        - Update power domain protocol version to 2.0
+
+    - STM32
+        - Remove dead code from nand FMC driver
+
+- Libraries
+    - C Standard Library
+        - Use macros to reduce duplicated code between snprintf and printf
+
+    - CPU support
+        - Sanity check pointers before use in AArch32 builds
+
+        - Arm Cortex-A78
+            - Remove rainier cpu workaround for errata 1542319
+
+        - Arm Makalu ELP
+            - Added "_arm" suffix to Makalu ELP CPU lib
+
+
+- Miscellaneous
+    - Editorconfig
+        - set max line length to 100
+
+- Platforms
+    - Allwinner
+        - Added reserved-memory node to DT
+        - Express memmap more dynamically
+        - Move SEPARATE_NOBITS_REGION to platforms
+        - Limit FDT checks to reduce code size
+        - Use CPUIDLE hardware when available
+        - Allow conditional compilation of SCPI and native PSCI ops
+        - Always use a 3MHz RSB bus clock
+        - Enable workaround for Cortex-A53 erratum 1530924
+        - Fixed non-default PRELOADED_BL33_BASE
+        - Leave CPU power alone during BL31 setup
+        - Added several psci hooks enhancements to improve system shutdown/reset
+          sequence
+        - Return the PMIC to I2C mode after use
+        - Separate code to power off self and other CPUs
+        - Split native and SCPI-based PSCI implementations
+
+    - Allwinner H6
+        - Added R_PRCM security setup for H6 board
+        - Added SPC security setup for H6 board
+        - Use RSB for the PMIC connection on H6
+
+    - Arm
+        - Store UUID as a string, rather than ints
+        - Replace FIP base and size macro with a generic name
+        - Move compile time switch from source to dt file
+        - Don't provide NT_FW_CONFIG when booting hafnium
+        - Do not setup 'disabled' regulator
+        - Increase SP max size
+        - Remove false dependency of ARM_LINUX_KERNEL_AS_BL33 on RESET_TO_BL31
+          and allow it to be enabled independently
+
+    - Arm FVP
+        - Do not map GIC region in BL1 and BL2
+
+    - Arm Juno
+        - Refactor juno_getentropy() to return 64 bits on each call
+
+    - Arm Morello
+        - Remove "virtio-rng" from Morello FVP
+        - Enable virtIO P9 device for Morello fvp
+
+    - Arm RDV1
+        - Allow all PSCI callbacks on RD-V1
+        - Rename rddaniel to rdv1
+
+    - Arm RDV1MC
+        - Rename rddanielxlr to rdv1mc
+        - Initialize TZC-400 controllers
+
+    - Arm TC0
+        - Updated GICR base address
+        - Use scmi_dvfs clock index 1 for cores 4-7 through fdt
+        - Added reserved-memory node for OP-TEE fdts
+        - Enabled Theodul DSU in TC platform
+        - OP-TEE as S-EL1 SP with SPMC at S-EL2
+        - Update Matterhorm ELP DVFS clock index
+
+    - Arm SGI
+        - Allow access to TZC controller on all chips
+        - Define memory regions for multi-chip platforms
+        - Allow access to nor2 flash and system registers from S-EL0
+        - Define default list of memory regions for DMC-620 TZC
+        - Improve macros defining cper buffer memory region
+        - Refactor DMC-620 error handling SMC function id
+        - Refactor SDEI specific macros
+        - Added platform id value for RDN2 platform
+        - Refactored header file inclusions and inclusion of memory mapping
+
+    - Arm RDN2
+        - Allow usage of secure partitions on RDN2 platform
+        - Update GIC redistributor and TZC base address
+
+    - Arm SGM775
+        - Deprecate Arm sgm775 FVP platform
+
+    - Marvell
+        - Increase TX FIFO EMPTY timeout from 2ms to 3ms
+        - Update delay code to be compatible with 1200 MHz CPU
+
+    - Marvell ARMADA
+        - Postpone MSS CPU startup to BL31 stage
+        - Allow builds without MSS support
+        - Use MSS SRAM in secure mode
+        - Added missing FORCE, .PHONY and clean targets
+        - Cleanup MSS SRAM if used for copy
+        - Move definition of mrvl_flash target to common marvell_common.mk file
+        - Show informative build messages and blank lines
+
+    - Marvell ARMADA A3K
+        - Added a new target mrvl_uart which builds UART image
+        - Added checks that WTP, MV_DDR_PATH and CRYPTOPP_PATH are correctly defined
+        - Allow use of the system Crypto++ library
+        - Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
+        - Build intermediate files in $(BUILD_PLAT) directory
+        - Build UART image files directly in $(BUILD_UART) subdirectory
+        - Correctly set DDR_TOPOLOGY and CLOCKSPRESET for WTMI
+        - Do not use 'echo -e' in Makefile
+        - Improve 4GB DRAM usage from 3.375 GB to 3.75 GB
+        - Remove unused variable WTMI_SYSINIT_IMG from Makefile
+        - Simplify check if WTP variable is defined
+        - Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
+
+    - Marvell ARMADA A8K
+        - Allow CP1/CP2 mapping at BLE stage
+
+    - Mediatek MT8183
+        - Added timer V20 compensation
+
+    - Nvidia Tegra
+        - Rename SMC API
+
+    - TI K3
+        - Make plat_get_syscnt_freq2 helper check CNT_FID0 register
+        - Fill non-message data fields in sec_proxy with 0x0
+        - Update ti_sci_msg_req_reboot ABI to include domain
+        - Enable USE_COHERENT_MEM only for the generic board
+        - Explicitly map SEC_SRAM_BASE to 0x0
+        - Use BL31_SIZE instead of computing
+        - Define the correct number of max table entries and increase SRAM size
+          to account for additional table
+
+    - Raspberry Pi4
+        - Switch to gicv2.mk and GICV2_SOURCES
+
+    - Renesas
+        - Move headers and assembly files to common folder
+
+    - Renesas rzg
+        - Added device tree memory node enhancements
+
+    - Rockchip
+        - Switch to using common gicv3.mk
+
+    - STM32MP1
+        - Set BL sizes regardless of flags
+
+    - QEMU
+        - Include gicv2.mk for compiling GICv2 source files
+        - Change DEVICE2 definition for MMU
+        - Added helper to calculate the position shift from MPIDR
+
+    - QEMU SBSA
+        - Include libraries for Cortex-A72
+        - Increase SHARED_RAM_SIZE
+        - Addes support in spm_mm for upto 512 cores
+        - Added support for topology handling
+
+    - QTI
+        - Mandate SMC implementation
+
+    - Xilinx
+        - Rename the IPI CRC checksum macro
+        - Use fno-jump-tables flag in CPPFLAGS
+
+    - Xilinx versal
+        - Added the IPI CRC checksum macro support
+        - Mark IPI calls secure/non-secure
+        - Enable sgi to communicate with linux using IPI
+        - Remove Cortex-A53 compilation
+
+    - Xilinx ZynqMP
+        - Configure counter frequency during initialization
+        - Filter errors related to clock gate permissions
+        - Implement pinctrl request/release EEMI API
+        - Reimplement pinctrl get/set config parameter EEMI API calls
+        - Reimplement pinctrl set/get function EEMI API
+        - Update error codes to match Linux and PMU Firmware
+        - Update PM version and support PM version check
+        - Update return type in query functions
+        - Added missing ids for 43/46/47dr devices
+        - Checked for DLL status before doing reset
+        - Disable ITAPDLYENA bit for zero ITAP delay
+        - Include GICv2 makefile
+        - Remove the custom crash implementation
+
+- Services
+
+    - SPMD
+        - Lock the g_spmd_pm structure
+        - Declare third cactus instance as UP SP
+        - Provide number of vCPUs and VM size for first SP
+        - Remove ``chosen`` node from SPMC manifests
+        - Move OP-TEE SP manifest DTS to FVP platform
+        - Update OP-TEE SP manifest with device-regions node
+        - Remove device-memory node from SPMC manifests
+
+    - SPM_MM
+        - Use sp_boot_info to set SP context
+
+    - SDEI
+        - Updata the affinity of shared event
+
+- Tools
+    - FIPtool
+        - Do not print duplicate verbose lines about building fiptool
+
+    - CertCreate
+        - Updated tool for platform defined certs, keys & extensions
+        - Create only requested certificates
+        - Avoid duplicates in extension stack
+
+Resolved Issues
+^^^^^^^^^^^^^^^
+- Several fixes for typos and mis-spellings in documentation
+
+- Build system
+    - Fixed ${FIP_NAME} to be rebuilt only when needed in Makefile
+    - Do not mark file targets as .PHONY target in Makefile
+
+- Drivers
+    - Authorization
+        - Avoid NV counter upgrade without certificate validation
+
+    - Arm GICv3
+        - Fixed logical issue for num_eints
+        - Limit SPI ID to avoid misjudgement in GICD_OFFSET()
+        - Fixed potential GICD context override with ESPI enabled
+
+    - Marvell A3700
+        - Fixed configuring polarity invert bits
+
+    - Arm TZC-400
+        - Correct FAIL_CONTROL Privileged bit
+        - Fixed logical error in FILTER_BIT definitions
+
+    - Renesas rcar
+        - Fixed several coding style violations reported by checkpatch
+
+- Libraries
+    - Arch helpers
+        - Fixed assertions in processing dynamic relocations for AArch64 builds
+
+    - C standard library
+        - Fixed MISRA issues in memset() ABI
+
+    - RAS
+        - Fixed bug of binary search in RAS interrupt handler
+
+- Platforms
+
+    - Arm
+        - Fixed missing copyrights in arm-gic.h file
+        - Fixed the order of header files in several dts files
+        - Fixed error message printing in board makefile
+        - Fixed bug of overriding the last node in image load helper API
+        - Fixed stdout-path in fdts files of TC0 and N1SDP platforms
+        - Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF for css platforms
+
+    - Arm FVP
+        - Fixed Generic Timer interrupt types in platform dts files
+
+    - Arm Juno
+        - Fixed parallel build issue for romlib config
+
+    - Arm SGI
+        - Fixed bug in SDEI receive event of RAS handler
+
+    - Intel Agilex
+        - Fixed PLAT_MAX_PWR_LVL value
+
+    - Marvell
+        - Fixed SPD handling in dram port
+
+    - Marvell ARMADA
+        - Fixed TRNG return SMC handling
+        - Fixed the logic used for LD selector mask
+        - Fixed MSS firmware loader for A8K family
+
+    - ST
+        - Fixed few violations reported by coverity static checks
+
+    - STM32MP1
+        - Fixed SELFREF_TO_X32 mask in ddr driver
+        - Do not keep mmc_device_info in stack
+        - Correct plat_crash_console_flush()
+
+    - QEMU SBSA
+        - Fixed memory type of secure NOR flash
+
+    - QTI
+        - Fixed NUM_APID and REG_APID_MAP() argument in SPMI driver
+
+    - Intel
+        - Do not keep mmc_device_info in stack
+
+    - Hisilicon
+        - Do not keep mmc_device_info in stack
+
+
+- Services
+
+    - EL3 runtime
+        - Fixed the EL2 context save/restore routine by removing EL2 generic
+          timer system registers
+        - Added fix for exception handler in BL31 by synchronizing pending EA
+          using DSB barrier
+
+    - SPMD
+        - Fixed error codes to use int32_t type
+
+    - TSPD
+        - Added bug fix in tspd interrupt handling when TSP_NS_INTR_ASYNC_PREEMPT is enabled
+
+    - TRNG
+        - Fixed compilation errors with -O0 compile option
+
+    - DebugFS
+        - Checked channel index before calling clone function
+
+    - PSCI
+        - Fixed limit of 256 CPUs caused by cast to unsigned char
+
+    - TSP
+        - Fixed compilation erros when built with GCC 11.0.0 toolchain
+
+- Tools
+    - FIPtool
+        - Do not call ``make clean`` for ``all`` target
+
+    - CertCreate
+        - Fixed bug to avoid cleaning when building the binary
+        - Used preallocated parts of the HASH struct to avoid leaking HASH struct fields
+        - Free arguments copied with strdup
+        - Free keys after use
+        - Free X509_EXTENSION structures on stack to avoid leaking them
+        - Optimized the code to avoid unnecessary attempts to create non-requested
+          certificates
+
 Version 2.4
 -----------
 
@@ -89,7 +758,7 @@
             - Added workaround for erratum 1800714
             - Added workaround for erratum 1925769
 
-        - Arm Neoverse N1
+        - Arm Neoverse-N1
             - Added workaround for erratum 1868343
 
     - EL3 Runtime
diff --git a/docs/components/psa-ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst
similarity index 94%
rename from docs/components/psa-ffa-manifest-binding.rst
rename to docs/components/ffa-manifest-binding.rst
index af79074..9e3919d 100644
--- a/docs/components/psa-ffa-manifest-binding.rst
+++ b/docs/components/ffa-manifest-binding.rst
@@ -1,8 +1,8 @@
-PSA FF-A manifest binding to device tree
+FF-A manifest binding to device tree
 ========================================
 
 This document defines the nodes and properties used to define a partition,
-according to the PSA FF-A specification.
+according to the FF-A specification.
 
 Version 1.0
 -----------
@@ -25,9 +25,9 @@
    - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X,
      15:0 -> Y, where:
 
-      - X is the major version of PSA-FF-A expected by the partition at the FFA
+      - X is the major version of FF-A expected by the partition at the FFA
         instance it will execute.
-      - Y is the minor version of PSA-FF-A expected by the partition at the FFA
+      - Y is the minor version of FF-A expected by the partition at the FFA
         instance it will execute.
 
 - uuid [mandatory]
@@ -112,6 +112,8 @@
       - 0x0: direct messaging method
       - 0x1: indirect messaging method
       - 0x2: both direct and indirect messaging methods
+      - 0x3: direct messaging method with managed exit support
+      - 0x4: both messaging methods with managed exit support
 
 - has-primary-scheduler
    - value type: <empty>
@@ -244,4 +246,4 @@
 
 --------------
 
-*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/components/index.rst b/docs/components/index.rst
index ffeef80..2409f96 100644
--- a/docs/components/index.rst
+++ b/docs/components/index.rst
@@ -19,6 +19,6 @@
    sdei
    secure-partition-manager
    secure-partition-manager-mm
-   psa-ffa-manifest-binding
+   ffa-manifest-binding
    xlat-tables-lib-v2-design
    cot-binding
diff --git a/docs/components/secure-partition-manager-mm.rst b/docs/components/secure-partition-manager-mm.rst
index d532901..30312ee 100644
--- a/docs/components/secure-partition-manager-mm.rst
+++ b/docs/components/secure-partition-manager-mm.rst
@@ -6,7 +6,7 @@
 
 Two implementations of a Secure Partition Manager co-exist in the TF-A codebase:
 
--  SPM based on the PSA FF-A specification (:ref:`Secure Partition Manager`).
+-  SPM based on the FF-A specification (:ref:`Secure Partition Manager`).
 -  SPM based on the MM interface.
 
 Both implementations differ in their architectures and only one can be selected
@@ -822,7 +822,7 @@
 
 --------------
 
-*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.*
 
 .. _Armv8-A ARM: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
 .. _instructions in the EDK2 repository: https://github.com/tianocore/edk2-staging/blob/AArch64StandaloneMm/HowtoBuild.MD
diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst
index 9a65e64..a5e7e8e 100644
--- a/docs/components/secure-partition-manager.rst
+++ b/docs/components/secure-partition-manager.rst
@@ -7,6 +7,10 @@
 ========
 
 +--------+-----------------------------------+
+| CoT    | Chain of Trust                    |
++--------+-----------------------------------+
+| DMA    | Direct Memory Access              |
++--------+-----------------------------------+
 | DTB    | Device Tree Blob                  |
 +--------+-----------------------------------+
 | DTS    | Device Tree Source                |
@@ -15,7 +19,7 @@
 +--------+-----------------------------------+
 | FIP    | Firmware Image Package            |
 +--------+-----------------------------------+
-| FF-A   | Firmware Framework for A-class    |
+| FF-A   | Firmware Framework for Armv8-A    |
 +--------+-----------------------------------+
 | IPA    | Intermediate Physical Address     |
 +--------+-----------------------------------+
@@ -29,12 +33,16 @@
 +--------+-----------------------------------+
 | PE     | Processing Element                |
 +--------+-----------------------------------+
+| PM     | Power Management                  |
++--------+-----------------------------------+
 | PVM    | Primary VM                        |
 +--------+-----------------------------------+
-| PSA    | Platform Security Architecture    |
+| SMMU   | System Memory Management Unit     |
 +--------+-----------------------------------+
 | SP     | Secure Partition                  |
 +--------+-----------------------------------+
+| SPD    | Secure Payload Dispatcher         |
++--------+-----------------------------------+
 | SPM    | Secure Partition Manager          |
 +--------+-----------------------------------+
 | SPMC   | SPM Core                          |
@@ -57,111 +65,117 @@
 
 Two implementations of a Secure Partition Manager co-exist in the TF-A codebase:
 
--  SPM based on the PSA FF-A specification `[1]`_.
--  SPM based on the MM interface to communicate with an S-EL0 partition `[2]`_.
+- SPM based on the FF-A specification `[1]`_.
+- SPM based on the MM interface to communicate with an S-EL0 partition `[2]`_.
 
 Both implementations differ in their architectures and only one can be selected
 at build time.
 
 This document:
 
--  describes the PSA FF-A implementation where the Secure Partition Manager
-   resides at EL3 and S-EL2 (or EL3 and S-EL1).
--  is not an architecture specification and it might provide assumptions
-   on sections mandated as implementation-defined in the specification.
--  covers the implications to TF-A used as a bootloader, and Hafnium
-   used as a reference code base for an S-EL2 secure firmware on
-   platforms implementing Armv8.4-SecEL2.
+- describes the FF-A implementation where the Secure Partition Manager
+  resides at EL3 and S-EL2 (or EL3 and S-EL1).
+- is not an architecture specification and it might provide assumptions
+  on sections mandated as implementation-defined in the specification.
+- covers the implications to TF-A used as a bootloader, and Hafnium
+  used as a reference code base for an S-EL2 secure firmware on
+  platforms implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2)
+  architecture extension.
 
 Terminology
 -----------
 
--  Hypervisor refers to the NS-EL2 component managing Virtual Machines (or
-   partitions) in the Normal World.
--  SPMC refers to the S-EL2 component managing Virtual Machines (or Secure
-   Partitions) in the Secure World when Armv8.4-SecEL2 extension is implemented.
--  Alternatively, SPMC can refer to an S-EL1 component, itself being a Secure
-   Partition and implementing the FF-A ABI on pre-Armv8.4 platforms.
--  VM refers to a Normal World Virtual Machine managed by an Hypervisor.
--  SP refers to a Secure World "Virtual Machine" managed by the SPMC component.
+- The term Hypervisor refers to the NS-EL2 component managing Virtual Machines
+  (or partitions) in the normal world.
+- The term SPMC refers to the S-EL2 component managing secure partitions in
+  the secure world when the FEAT_SEL2 architecture extension is implemented.
+- Alternatively, SPMC can refer to an S-EL1 component, itself being a secure
+  partition and implementing the FF-A ABI on platforms not implementing the
+  FEAT_SEL2 architecture extension.
+- The term VM refers to a normal world Virtual Machine managed by an Hypervisor.
+- The term SP refers to a secure world "Virtual Machine" managed by an SPMC.
 
 Support for legacy platforms
 ----------------------------
 
-In the implementation, the SPM is split into SPMD and SPMC components
-(although not strictly mandated by the specification). SPMD is located
-at EL3 and principally relays FF-A messages from NWd (Hypervisor or OS
-kernel) to SPMC located either at S-EL1 or S-EL2.
+In the implementation, the SPM is split into SPMD and SPMC components.
+The SPMD is located at EL3 and mainly relays FF-A messages from
+NWd (Hypervisor or OS kernel) to SPMC located either at S-EL1 or S-EL2.
 
-Hence TF-A must support both cases where SPMC is either located at:
+Hence TF-A supports both cases where the SPMC is located either at:
 
--  S-EL1 supporting pre-Armv8.4 platforms. SPMD conveys FF-A protocol
-   from EL3 to S-EL1.
--  S-EL2 supporting platforms implementing Armv8.4-SecEL2 extension.
-   SPMD conveys FF-A protocol from EL3 to S-EL2.
+- S-EL1 supporting platforms not implementing the FEAT_SEL2 architecture
+  extension. The SPMD relays the FF-A protocol from EL3 to S-EL1.
+- or S-EL2 supporting platforms implementing the FEAT_SEL2 architecture
+  extension. The SPMD relays the FF-A protocol from EL3 to S-EL2.
 
-The same SPMD component is used to support both configurations. The SPMC
-execution level is a build time choice.
+The same TF-A SPMD component is used to support both configurations.
+The SPMC exception level is a build time choice.
 
 Sample reference stack
 ======================
 
-The following diagram illustrates a possible configuration with SPMD and SPMC,
-one or multiple Secure Partitions, with or without an optional Hypervisor:
+The following diagram illustrates a possible configuration when the
+FEAT_SEL2 architecture extension is implemented, showing the SPMD
+and SPMC, one or multiple secure partitions, with an optional
+Hypervisor:
 
 .. image:: ../resources/diagrams/ff-a-spm-sel2.png
 
 TF-A build options
 ==================
 
-The following TF-A build options are provisioned:
+This section explains the TF-A build options involved in building with
+support for an FF-A based SPM where the SPMD is located at EL3 and the
+SPMC located at S-EL1 or S-EL2:
 
--  **SPD=spmd**: this option selects the SPMD component to relay FF-A
-   protocol from NWd to SWd back and forth. It is not possible to
-   enable another Secure Payload Dispatcher when this option is chosen.
--  **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC execution
-   level to being S-EL1 or S-EL2. It defaults to enabled (value 1) when
-   SPD=spmd is chosen.
--  **CTX_INCLUDE_EL2_REGS**: this option permits saving (resp.
-   restoring) the EL2 system register context before entering (resp.
-   after leaving) the SPMC. It is mandatory when ``SPMD_SPM_AT_SEL2`` is
-   enabled. The context save/restore routine and exhaustive list of
-   registers is visible at `[4]`_.
--  **SP_LAYOUT_FILE**: this option provides a text description file
-   providing paths to SP binary images and DTS format manifests
-   (see `Specifying partition binary image and DT`_). It
-   is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple
-   secure partitions are to be loaded on behalf of SPMC.
+- **SPD=spmd**: this option selects the SPMD component to relay the FF-A
+  protocol from NWd to SWd back and forth. It is not possible to
+  enable another Secure Payload Dispatcher when this option is chosen.
+- **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC exception
+  level to being S-EL1 or S-EL2. It defaults to enabled (value 1) when
+  SPD=spmd is chosen.
+- **CTX_INCLUDE_EL2_REGS**: this option permits saving (resp.
+  restoring) the EL2 system register context before entering (resp.
+  after leaving) the SPMC. It is mandatorily enabled when
+  ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
+  and exhaustive list of registers is visible at `[4]`_.
+- **SP_LAYOUT_FILE**: this option specifies a text description file
+  providing paths to SP binary images and manifests in DTS format
+  (see `Describing secure partitions`_). It
+  is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple
+  secure partitions are to be loaded on behalf of the SPMC.
 
-+------------------------------+----------------------+------------------+
-|                              | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 |
-+------------------------------+----------------------+------------------+
-| SPMC at S-EL1 (e.g. OP-TEE)  |           0          |        0         |
-+------------------------------+----------------------+------------------+
-| SPMC at S-EL2 (e.g. Hafnium) |           1          | 1 (default when  |
-|                              |                      |    SPD=spmd)     |
-+------------------------------+----------------------+------------------+
++---------------+----------------------+------------------+
+|               | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 |
++---------------+----------------------+------------------+
+| SPMC at S-EL1 |         0            |        0         |
++---------------+----------------------+------------------+
+| SPMC at S-EL2 |         1            | 1 (default when  |
+|               |                      |    SPD=spmd)     |
++---------------+----------------------+------------------+
 
 Other combinations of such build options either break the build or are not
 supported.
 
-Note, the ``CTX_INCLUDE_EL2_REGS`` option provides the generic support for
-barely saving/restoring EL2 registers from an Arm arch perspective. As such
-it is decoupled from the ``SPD=spmd`` option.
+Notes:
 
-BL32 option is re-purposed to specify the SPMC image. It can specify either the
-Hafnium binary path (built for the secure world) or the path to a TEE binary
-implementing the FF-A protocol.
-
-BL33 option can specify either:
-
--  the TFTF binary or
--  the Hafnium binary path (built for the normal world) if VMs were loaded by
-   TF-A beforehand or
--  a minimal loader performing the loading of VMs and Hafnium.
+- Only Arm's FVP platform is supported to use with the TF-A reference software
+  stack.
+- The reference software stack uses FEAT_PAuth (formerly Armv8.3-PAuth) and
+  FEAT_BTI (formerly Armv8.5-BTI) architecture extensions by default at EL3
+  and S-EL2.
+- The ``CTX_INCLUDE_EL2_REGS`` option provides the generic support for
+  barely saving/restoring EL2 registers from an Arm arch perspective. As such
+  it is decoupled from the ``SPD=spmd`` option.
+- BL32 option is re-purposed to specify the SPMC image. It can specify either
+  the Hafnium binary path (built for the secure world) or the path to a TEE
+  binary implementing FF-A interfaces.
+- BL33 option can specify the TFTF binary or a normal world loader
+  such as U-Boot or the UEFI framework.
 
 Sample TF-A build command line when SPMC is located at S-EL1
-(typically pre-Armv8.4):
+(e.g. when the FEAT_EL2 architecture extension is not implemented):
 
 .. code:: shell
 
@@ -170,67 +184,108 @@
     SPD=spmd \
     SPMD_SPM_AT_SEL2=0 \
     BL32=<path-to-tee-binary> \
-    BL33=<path-to-nwd-binary> \
+    BL33=<path-to-bl33-binary> \
     PLAT=fvp \
     all fip
 
-Sample TF-A build command line for an Armv8.4-SecEL2 enabled system
-where SPMC is located at S-EL2:
+Sample TF-A build command line for a FEAT_SEL2 enabled system where the SPMC is
+located at S-EL2:
 
 .. code:: shell
 
     make \
     CROSS_COMPILE=aarch64-none-elf- \
+    PLAT=fvp \
     SPD=spmd \
     CTX_INCLUDE_EL2_REGS=1 \
-    ARM_ARCH_MINOR=4 \
-    BL32=<path-to-swd-hafnium-binary>
-    BL33=<path-to-nwd-binary> \
+    ARM_ARCH_MINOR=5 \
+    BRANCH_PROTECTION=1 \
+    CTX_INCLUDE_PAUTH_REGS=1 \
+    BL32=<path-to-hafnium-binary> \
+    BL33=<path-to-bl33-binary> \
     SP_LAYOUT_FILE=sp_layout.json \
-    PLAT=fvp \
     all fip
 
-Build options to enable secure boot:
+Same as above with enabling secure boot in addition:
 
 .. code:: shell
 
     make \
     CROSS_COMPILE=aarch64-none-elf- \
+    PLAT=fvp \
     SPD=spmd \
     CTX_INCLUDE_EL2_REGS=1 \
-    ARM_ARCH_MINOR=4 \
-    BL32=<path-to-swd-hafnium-binary>
-    BL33=<path-to-nwd-binary> \
-    SP_LAYOUT_FILE=../tf-a-tests/build/fvp/debug/sp_layout.json \
+    ARM_ARCH_MINOR=5 \
+    BRANCH_PROTECTION=1 \
+    CTX_INCLUDE_PAUTH_REGS=1 \
+    BL32=<path-to-hafnium-binary> \
+    BL33=<path-to-bl33-binary> \
+    SP_LAYOUT_FILE=sp_layout.json \
     MBEDTLS_DIR=<path-to-mbedtls-lib> \
     TRUSTED_BOARD_BOOT=1 \
     COT=dualroot \
     ARM_ROTPK_LOCATION=devel_rsa \
     ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
     GENERATE_COT=1 \
-    PLAT=fvp \
     all fip
 
+FVP model invocation
+====================
+
+The FVP command line needs the following options to exercise the S-EL2 SPMC:
+
++---------------------------------------------------+------------------------------------+
+| - cluster0.has_arm_v8-5=1                         | Implements FEAT_SEL2, FEAT_PAuth,  |
+| - cluster1.has_arm_v8-5=1                         | and FEAT_BTI.                      |
++---------------------------------------------------+------------------------------------+
+| - pci.pci_smmuv3.mmu.SMMU_AIDR=2                  | Parameters required for the        |
+| - pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B         | SMMUv3.2 modeling.                 |
+| - pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002         |                                    |
+| - pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714             |                                    |
+| - pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472         |                                    |
+| - pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002       |                                    |
+| - pci.pci_smmuv3.mmu.SMMU_S_IDR2=0                |                                    |
+| - pci.pci_smmuv3.mmu.SMMU_S_IDR3=0                |                                    |
++---------------------------------------------------+------------------------------------+
+| - cluster0.has_branch_target_exception=1          | Implements FEAT_BTI.               |
+| - cluster1.has_branch_target_exception=1          |                                    |
++---------------------------------------------------+------------------------------------+
+| - cluster0.restriction_on_speculative_execution=2 | Required by the EL2 context        |
+| - cluster1.restriction_on_speculative_execution=2 | save/restore routine.              |
++---------------------------------------------------+------------------------------------+
+
+Sample FVP command line invocation:
+
+.. code:: shell
+
+    <path-to-fvp-model>/FVP_Base_RevC-2xAEMv8A -C pctl.startup=0.0.0.0
+    -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \
+    -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \
+    -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \
+    -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \
+    -C bp.pl011_uart2.out_file=fvp-uart2.log \
+    -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 \
+    -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 \
+    -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 \
+    -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 \
+    -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 \
+    -C cluster0.has_branch_target_exception=1 \
+    -C cluster1.has_branch_target_exception=1 \
+    -C cluster0.restriction_on_speculative_execution=2 \
+    -C cluster1.restriction_on_speculative_execution=2
+
 Boot process
 ============
 
-Loading Hafnium and Secure Partitions in the secure world
+Loading Hafnium and secure partitions in the secure world
 ---------------------------------------------------------
 
-The Hafnium implementation in normal world requires VMs to be loaded in
-memory prior to booting. The mechanism upon which VMs are loaded and
-exposed to Hafnium are either:
-
--  by supplying a ramdisk image where VM images are concatenated (1)
--  or by providing VM load addresses within Hafnium manifest (2)
+TF-A BL2 is the bootlader for the SPMC and SPs in the secure world.
 
-TF-A is the bootlader for the Hafnium and SPs in the secure world. TF-A
-does not provide tooling or libraries manipulating ramdisks as required
-by (1). Thus BL2 loads SPs payloads independently.
 SPs may be signed by different parties (SiP, OEM/ODM, TOS vendor, etc.).
-Thus they are supplied as distinct “self-contained” signed entities within
-the FIP flash image. The FIP image itself is not signed hence providing
-ability to upgrade SPs in the field.
+Thus they are supplied as distinct signed entities within the FIP flash
+image. The FIP image itself is not signed hence this provides the ability
+to upgrade SPs in the field.
 
 Booting through TF-A
 --------------------
@@ -239,26 +294,27 @@
 ~~~~~~~~~~~~
 
 An SP manifest describes SP attributes as defined in `[1]`_
-section 3.1 (partition manifest at virtual FF-A instance) in DTS text format. It
-is represented as a single file associated with the SP. A sample is
+(partition manifest at virtual FF-A instance) in DTS format. It is
+represented as a single file associated with the SP. A sample is
 provided by `[5]`_. A binding document is provided by `[6]`_.
 
 Secure Partition packages
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Secure Partitions are bundled as independent package files consisting
+Secure partitions are bundled as independent package files consisting
 of:
 
--  a header
--  a DTB
--  an image payload
+- a header
+- a DTB
+- an image payload
 
 The header starts with a magic value and offset values to SP DTB and
 image payload. Each SP package is loaded independently by BL2 loader
 and verified for authenticity and integrity.
 
-The SP package identified by its UUID (matching FF-A uuid) is inserted
-as a single entry into the FIP at end of the TF-A build flow as shown:
+The SP package identified by its UUID (matching FF-A uuid property) is
+inserted as a single entry into the FIP at end of the TF-A build flow
+as shown:
 
 .. code:: shell
 
@@ -276,18 +332,17 @@
 
 .. uml:: ../resources/diagrams/plantuml/fip-secure-partitions.puml
 
-Specifying partition binary image and DT
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Describing secure partitions
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-A description file (json format) is passed to the build flow specifying
-paths to the SP binary image and associated DTS partition manifest file.
-The latter is going through the dtc compiler to generate the dtb fed into
-the SP package.
-This file also specifies the owner of the SP, which is an optional field and
-identifies the signing domain in case of dualroot CoT.
-The possible owner of an SP could either be Silicon Provider or Platform, and
-the corresponding "owner" field value could either be "SiP" or "Plat".
-In absence of "owner" field, it defaults to "SiP".
+A json-formatted description file is passed to the build flow specifying paths
+to the SP binary image and associated DTS partition manifest file. The latter
+is processed by the dtc compiler to generate a DTB fed into the SP package.
+This file also specifies the SP owner (as an optional field) identifying the
+signing domain in case of dual root CoT.
+The SP owner can either be the silicon or the platform provider. The
+corresponding "owner" field value can either take the value of "SiP" or "Plat".
+In absence of "owner" field, it defaults to "SiP" owner.
 
 .. code:: shell
 
@@ -308,14 +363,16 @@
 SPMC manifest
 ~~~~~~~~~~~~~
 
-This manifest contains an SPMC attributes node consumed by SPMD at boot time. It
-is implementing the description from `[1]`_ section 3.2 (SP manifest at physical
-FF-A instance). The SP manifest at physical FF-A instance is used by the SPMD to
-setup a SP that co-resides with the SPMC and executes at S-EL1 or Secure
-Supervisor mode.
+This manifest contains the SPMC *attribute* node consumed by the SPMD at boot
+time. It implements `[1]`_ (SP manifest at physical FF-A instance) and serves
+two different cases:
 
-In this implementation its usage is extended to the secure physical FF-A
-instance where SPMC executes at S-EL2.
+- The SPMC resides at S-EL1: the SPMC manifest is used by the SPMD to setup a
+  SP that co-resides with the SPMC and executes at S-EL1 or Secure Supervisor
+  mode.
+- The SPMC resides at S-EL2: the SPMC manifest is used by the SPMD to setup
+  the environment required by the SPMC to run at S-EL2. SPs run at S-EL1 or
+  S-EL0.
 
 .. code:: shell
 
@@ -329,28 +386,28 @@
         binary_size = <0x60000>;
     };
 
--  *spmc_id* defines the endpoint ID value that SPMC can query through
-   ``FFA_ID_GET``.
--  *maj_ver/min_ver*. SPMD checks provided version versus its internal
-   version and aborts if not matching.
--  *exec_state* defines SPMC execution state (can be AArch64 for
-   Hafnium, or AArch64/AArch32 for OP-TEE at S-EL1).
--  *load_address* and *binary_size* are mostly used to verify secondary
-   entry points fit into the loaded binary image.
--  *entrypoint* defines the cold boot primary core entry point used by
-   SPMD (currently matches ``BL32_BASE``)
+- *spmc_id* defines the endpoint ID value that SPMC can query through
+  ``FFA_ID_GET``.
+- *maj_ver/min_ver*. SPMD checks provided version versus its internal
+  version and aborts if not matching.
+- *exec_state* defines the SPMC execution state (AArch64 or AArch32).
+  Notice Hafnium used as a SPMC only supports AArch64.
+- *load_address* and *binary_size* are mostly used to verify secondary
+  entry points fit into the loaded binary image.
+- *entrypoint* defines the cold boot primary core entry point used by
+  SPMD (currently matches ``BL32_BASE``) to enter the SPMC.
 
 Other nodes in the manifest are consumed by Hafnium in the secure world.
 A sample can be found at [7]:
 
--  The *chosen* node is currently unused in SWd. It is meant for NWd to
-   specify the init ramdisk image.
--  The *hypervisor* node describes SPs. *is_ffa_partition* boolean
-   attribute indicates an SP. Load-addr field specifies the load address
-   at which TF-A loaded the SP package.
--  *cpus* node provide the platform topology and allows MPIDR to VMPIDR
-   mapping. Notice with current implementation primary cpu is declared
-   first, then secondary cpus must be declared in reverse order.
+- The *hypervisor* node describes SPs. *is_ffa_partition* boolean attribute
+  indicates a FF-A compliant SP. The *load_address* field specifies the load
+  address at which TF-A loaded the SP package.
+- *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping.
+  Note the primary core is declared first, then secondary core are declared
+  in reverse order.
+- The *memory* node provides platform information on the ranges of memory
+  available to the SPMC.
 
 SPMC boot
 ~~~~~~~~~
@@ -361,134 +418,111 @@
 
 BL2 passes the SPMC manifest address to BL31 through a register.
 
-BL31(SPMD) runs from primary core, initializes the core contexts and
-launches BL32 passing the SPMC manifest address through a register.
+At boot time, the SPMD in BL31 runs from the primary core, initializes the core
+contexts and launches the SPMC (BL32) passing the SPMC manifest address through
+a register.
 
 Loading of SPs
 ~~~~~~~~~~~~~~
 
-.. uml:: ../resources/diagrams/plantuml/bl2-loading-sp.puml
+At boot time, BL2 loads SPs sequentially in addition to the SPMC as depicted
+below:
 
+.. uml:: ../resources/diagrams/plantuml/bl2-loading-sp.puml
 
-Notice this boot flow is an implementation sample on Arm's FVP platform. Platforms
-not using FW_CONFIG would adjust to a different implementation.
+Note this boot flow is an implementation sample on Arm's FVP platform.
+Platforms not using TF-A's *Firmware CONFiguration* framework would adjust to a
+different implementation.
 
 Secure boot
 ~~~~~~~~~~~
 
 The SP content certificate is inserted as a separate FIP item so that BL2 loads SPMC,
-SPMC manifest and Secure Partitions and verifies them for authenticity and integrity.
+SPMC manifest, secure partitions and verifies them for authenticity and integrity.
 Refer to TBBR specification `[3]`_.
 
-The multiple-signing domain feature (in current state dual signing domain) allows
-the use of two root keys namely S-ROTPK and NS-ROTPK (see `[8]`_):
+The multiple-signing domain feature (in current state dual signing domain `[8]`_) allows
+the use of two root keys namely S-ROTPK and NS-ROTPK:
 
--  SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK.
--  BL33 may be signed by the OEM using NS-ROTPK.
--  An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK).
+- SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK.
+- BL33 may be signed by the OEM using NS-ROTPK.
+- An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK).
 
-Longer term multiple signing domain will allow additional signing keys, e.g.
-if SPs originate from different parties.
-
-See `TF-A build options`_ for a sample build command line.
+Also refer to `Describing secure partitions`_ and `TF-A build options`_ sections.
 
 Hafnium in the secure world
 ===========================
 
-**NOTE: this section is work in progress. Descriptions and implementation choices
-are subject to evolve.**
-
 General considerations
 ----------------------
 
 Build platform for the secure world
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-The implementation might add specific code parts only relevant to the
-secure world. Such code parts might be isolated into different files
-and/or conditional code enclosed by a ``SECURE_WORLD`` macro.
+In the Hafnium reference implementation specific code parts are only relevant to
+the secure world. Such portions are isolated in architecture specific files
+and/or enclosed by a ``SECURE_WORLD`` macro.
 
-Secure Partitions CPU scheduling
+Secure partitions CPU scheduling
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-In the normal world, VMs are scheduled by the FFA_RUN ABI invoked from the
-primary scheduler (in the primary VM), or by a direct message request or
-response.
+The FF-A v1.0 specification `[1]`_ provides two ways to relinquinsh CPU time to
+secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of:
 
-With the FF-A EAC specification, Secure Partitions are scheduled by direct
-message invocations from a NWd VM or another SP.
+- the FFA_MSG_SEND_DIRECT_REQ interface.
+- the FFA_RUN interface.
 
 Platform topology
 ~~~~~~~~~~~~~~~~~
 
-As stated in `[1]`_ section 4.4.1 the SPMC implementation assumes the
+The *execution-ctx-count* SP manifest field can take the value of one or the
+total number of PEs. The FF-A v1.0 specification `[1]`_  recommends the
 following SP types:
 
--  Pinned MP SPs: an Execution Context id matches a physical PE id. MP
-   SPs must implement the same number of ECs as the number of PEs in the
-   platform. Hence the *execution-ctx-count* as defined by
-   `[1]`_ (or NWd-Hafnium *vcpu_count*) can only take the
-   value of one or the number of physical PEs.
--  Migratable UP SPs: a single execution context can run and be migrated
-   on any physical PE. It declares a single EC in its SP manifest. An UP
-   SP can receive a direct message request on any physical core.
-
-Usage of PSCI services in the secure world
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-- The normal world Hypervisor (optional) or OS kernel issues PSCI service
-  invocations e.g. to request PSCI version, wake-up a secondary core, or request
-  core suspend. This happens at the non-secure physical FF-A instance. In the
-  example case of Hafnium in the normal world, it boots on the primary core and
-  one of the first initialization step is to request the PSCI version. It then
-  launches the primary VM. The primary VM upon initializing performs PSCI service
-  calls (at non-secure virtual FF-A instance) which are trapped by the
-  Hypervisor. Invocation from OS Kernel ends straight at EL3. The PVM issues
-  ``PSCI_CPU_ON`` service calls to wake-up secondary cores by passing an
-  ``MPIDR``, entry point address and a CPU context address. The EL3 PSCI layer
-  then performs an exception return to the secondary core entry point on the
-  targeted core. Other PSCI calls can happen at run-time from the PVM e.g. to
-  request core suspend.
-- In the existing TF-A PSCI standard library, PSCI service calls are filtered at
-  EL3 to only originate from the NWd. Thus concerning the SPMC (at secure
-  physical FF-A instance) the PSCI service invocations cannot happen as in the
-  normal world. For example, a ``PSCI_CPU_ON`` service invocation from the SPMC
-  does not reach the PSCI layer.
+- Pinned MP SPs: an execution context matches a physical PE. MP SPs must
+  implement the same number of ECs as the number of PEs in the platform.
+- Migratable UP SPs: a single execution context can run and be migrated on any
+  physical PE. Such SP declares a single EC in its SP manifest. An UP SP can
+  receive a direct message request originating from any physical core targeting
+  the single execution context.
 
 Parsing SP partition manifests
 ------------------------------
 
-Hafnium must be able to consume SP manifests as defined in
-`[1]`_ section 3.1, at least for the mandatory fields.
+Hafnium consumes SP manifests as defined in `[1]`_ and `SP manifests`_.
+Note the current implementation may not implement all optional fields.
 
-The SP manifest may contain memory and device regions nodes.
+The SP manifest may contain memory and device regions nodes. In case of
+an S-EL2 SPMC:
 
--  Memory regions shall be mapped in the SP Stage-2 translation regime at
-   load time. A memory region node can specify RX/TX buffer regions in which
-   case it is not necessary for an SP to explicitly call the ``FFA_RXTX_MAP``
-   service.
--  Device regions shall be mapped in SP Stage-2 translation regime as
-   peripherals and possibly allocate additional resources (e.g. interrupts)
+- Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at
+  load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can
+  specify RX/TX buffer regions in which case it is not necessary for an SP
+  to explicitly invoke the ``FFA_RXTX_MAP`` interface.
+- Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or
+  EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate
+  additional resources (e.g. interrupts).
 
-Base addresses for memory and device region nodes are IPAs provided SPMC
-identity maps IPAs to PAs within SP Stage-2 translation regime.
+For the S-EL2 SPMC, base addresses for memory and device region nodes are IPAs
+provided the SPMC identity maps IPAs to PAs within SP EL1&0 Stage-2 translation
+regime.
 
-Note: currently both VTTBR_EL2 and VSTTBR_EL2 resolve to the same set of page
-tables. It is still open whether two sets of page tables shall be provided per
-SP. The memory region node as defined in the spec (section 3.1 Table 10)
+Note: in the current implementation both VTTBR_EL2 and VSTTBR_EL2 point to the
+same set of page tables. It is still open whether two sets of page tables shall
+be provided per SP. The memory region node as defined in the specification
 provides a memory security attribute hinting to map either to the secure or
-non-secure stage-2 table.
+non-secure EL1&0 Stage-2 table if it exists.
 
 Passing boot data to the SP
 ---------------------------
 
-`[1]`_ Section 3.4.2 “Protocol for passing data” defines a
-method to passing boot data to SPs (not currently implemented).
+In `[1]`_ , the "Protocol for passing data" section defines a method for passing
+boot data to SPs (not currently implemented).
 
-Provided that the whole Secure Partition package image (see `Secure
-Partition packages`_) is mapped to the SP's secure Stage-2 translation
-regime, an SP can access its own manifest DTB blob and extract its partition
-manifest properties.
+Provided that the whole secure partition package image (see
+`Secure Partition packages`_) is mapped to the SP secure EL1&0 Stage-2
+translation regime, an SP can access its own manifest DTB blob and extract its
+partition manifest properties.
 
 SP Boot order
 -------------
@@ -497,347 +531,396 @@
 dependencies such as an SP providing a service required to properly boot
 another SP.
 
+It is possible for an SP to call into another SP through a direct request
+provided the latter SP has already been booted.
+
 Boot phases
 -----------
 
 Primary core boot-up
 ~~~~~~~~~~~~~~~~~~~~
 
-The SPMC performs its platform initializations then loads and creates
-secure partitions based on SP packages and manifests. Then each secure
-partition is launched in sequence (see `SP Boot order`_) on their primary
-Execution Context.
-
-Notice the primary physical core may not be core 0. Hence if the primary
-core linear id is N, the 1:1 mapping requires MP SPs are launched using
-EC[N] on PE[N] (see `Platform topology`_).
-
-The SP's primary Execution Context (or the EC used when the partition is booted)
-exits through ``FFA_MSG_WAIT`` to indicate successful initialization.
-
-Secondary physical core boot-up
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Upon boot-up, BL31 hands over to the SPMC (BL32) on the primary boot physical
+core. The SPMC performs its platform initializations and registers the SPMC
+secondary physical core entry point physical address by the use of the
+FFA_SECONDARY_EP_REGISTER interface (SMC invocation from the SPMC to the SPMD
+at secure physical FF-A instance). This interface is implementation-defined in
+context of FF-A v1.0.
 
-Upon boot-up, the SPMC running on the primary core performs
-implementation-defined SPMD service calls at secure physical FF-A instance
-to register the secondary physical cores entry points and context information:
+The SPMC then creates secure partitions based on SP packages and manifests. Each
+secure partition is launched in sequence (`SP Boot order`_) on their "primary"
+execution context. If the primary boot physical core linear id is N, an MP SP is
+started using EC[N] on PE[N] (see `Platform topology`_). If the partition is a
+UP SP, it is started using its unique EC0 on PE[N].
 
--  This is done through a direct message request invocation to the SPMD
-   (``SET_ENTRY_POINT``). This service call does not wake-up the targeted
-   core immediately. The secondary core is woken up later by a NWd
-   ``PSCI_CPU_ON`` service invocation. A notification is passed from EL3
-   PSCI layer to the SPMD, and then to SPMC through an implementation-defined
-   interface.
--  The SPMC/SPMD interface can consist of FF-A direct message requests/responses
-   transporting PM events.
+The SP primary EC (or the EC used when the partition is booted as described
+above):
 
-If there is no Hypervisor in the normal world, the OS Kernel issues
-``PSCI_CPU_ON`` calls that are directly trapped to EL3.
+- Performs the overall SP boot time initialization, and in case of a MP SP,
+  prepares the SP environment for other execution contexts.
+- In the case of a MP SP, it invokes the FFA_SECONDARY_EP_REGISTER at secure
+  virtual FF-A instance (SMC invocation from SP to SPMC) to provide the IPA
+  entry point for other execution contexts.
+- Exits through ``FFA_MSG_WAIT`` to indicate successful initialization or
+  ``FFA_ERROR`` in case of failure.
 
-When a secondary physical core wakes-up the SPMD notifies the SPMC which updates
-its internal states reflecting current physical core is being turned on.
-It might then return straight to the SPMD and then to the NWd.
+Secondary cores boot-up
+~~~~~~~~~~~~~~~~~~~~~~~
 
-*(under discussion)* There may be possibility that an SP registers "PM events"
-(during primary EC boot stage) through an ad-hoc interface. Such events would
-be relayed by SPMC to one or more registered SPs on need basis
-(see `Power management`_).
+Once the system is started and NWd brought up, a secondary physical core is
+woken up by the ``PSCI_CPU_ON`` service invocation. The TF-A SPD hook mechanism
+calls into the SPMD on the newly woken up physical core. Then the SPMC is
+entered at the secondary physical core entry point.
 
-Secondary virtual core boot-up
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+In the current implementation, the first SP is resumed on the coresponding EC
+(the virtual CPU which matches the physical core). The implication is that the
+first SP must be a MP SP.
 
-In the example case where Hafnium exists in the normal world, secondary VMs
-issue a ``PSCI_CPU_ON`` service call which is trapped to the Hypervisor. The
-latter then enables the vCPU context for the targeted core, and switches to
-the PVM down to the kernel driver with an ``HF_WAKE_UP`` message. The NWd
-driver in PVM can then schedule the newly woken up vCPU context.
+In a linux based system, once secure and normal worlds are booted but prior to
+a NWd FF-A driver has been loaded:
 
-In the secure world the primary EC of a given SP passes the secondary EC entry
-point and context. The SMC service call is trapped into the SPMC. This can be
-either *(under discussion)*:
+- The first SP has initialized all its ECs in response to primary core boot up
+  (at system initialization) and secondary core boot up (as a result of linux
+  invoking PSCI_CPU_ON for all secondary cores).
+- Other SPs have their first execution context initialized as a result of secure
+  world initialization on the primary boot core. Other ECs for those SPs have to
+  be run first through ffa_run to complete their initialization (which results
+  in the EC completing with FFA_MSG_WAIT).
 
--  a specific interface registering the secondary EC entry point,
-   similarly to above ``SET_ENTRY_POINT`` service.
--  Re-purposing the ``PSCI_CPU_ON`` function id. It is
-   assumed that even if the input arguments are the same as the ones defined in
-   the PSCI standard, the usage deviates by the fact the secondary EC is not
-   woken up immediately. At least for the PSA-FF-A EAC where only
-   direct messaging is allowed, it is only after the first direct
-   message invocation that the secondary EC is entered. This option
-   might be preferred when the same code base is re-used for a VM or
-   an SP. The ABI to wake-up a secondary EC can remain similar.
-
-SPs are always scheduled from the NWd, this paradigm did not change from legacy
-TEEs. There must always be some logic (or driver) in the NWd to relinquish CPU
-cycles to the SWd. If primary core is 0, an SP EC[x>0] entry point is supplied
-by the SP EC[0] when the system boots in SWd. But this EC[x] is not immediately
-entered at boot. Later in the boot process when NWd is up, a direct message
-request issued from physical core 1 ends up in SP EC[1], and only at this stage
-this context is effectively scheduled.
-
-It should be possible for an SP to call into another SP through direct message
-provided the latter SP has been booted already. The "boot-order" field in
-partition manifests (`SP Boot order`_) fulfills the dependency towards availability
-of a service within an SP offered to another SP.
+Refer to `Power management`_ for further details.
 
 Mandatory interfaces
 --------------------
 
-The following interfaces must be exposed to any VM or SP:
+The following interfaces are exposed to SPs:
 
--  ``FFA_STATUS``
--  ``FFA_ERROR``
--  ``FFA_INTERRUPT``
 -  ``FFA_VERSION``
 -  ``FFA_FEATURES``
 -  ``FFA_RX_RELEASE``
 -  ``FFA_RXTX_MAP``
--  ``FFA_RXTX_UNMAP``
+-  ``FFA_RXTX_UNMAP`` (not implemented)
 -  ``FFA_PARTITION_INFO_GET``
 -  ``FFA_ID_GET``
+-  ``FFA_MSG_WAIT``
+-  ``FFA_MSG_SEND_DIRECT_REQ``
+-  ``FFA_MSG_SEND_DIRECT_RESP``
+-  ``FFA_MEM_DONATE``
+-  ``FFA_MEM_LEND``
+-  ``FFA_MEM_SHARE``
+-  ``FFA_MEM_RETRIEVE_REQ``
+-  ``FFA_MEM_RETRIEVE_RESP``
+-  ``FFA_MEM_RELINQUISH``
+-  ``FFA_MEM_RECLAIM``
+-  ``FFA_SECONDARY_EP_REGISTER``
 
 FFA_VERSION
 ~~~~~~~~~~~
 
-Per `[1]`_ section 8.1 ``FFA_VERSION`` requires a
-*requested_version* parameter from the caller.
+``FFA_VERSION`` requires a *requested_version* parameter from the caller.
+The returned value depends on the caller:
 
-In the current implementation when ``FFA_VERSION`` is invoked from:
-
--  Hypervisor in NS-EL2: the SPMD returns the SPMC version specified
-   in the SPMC manifest.
--  OS kernel in NS-EL1 when NS-EL2 is not present: the SPMD returns the
-   SPMC version specified in the SPMC manifest.
--  VM in NWd: the Hypervisor returns its implemented version.
--  SP in SWd: the SPMC returns its implemented version.
--  SPMC at S-EL1/S-EL2: the SPMD returns its implemented version.
+- Hypervisor or OS kernel in NS-EL1/EL2: the SPMD returns the SPMC version
+  specified in the SPMC manifest.
+- SP: the SPMC returns its own implemented version.
+- SPMC at S-EL1/S-EL2: the SPMD returns its own implemented version.
 
 FFA_FEATURES
 ~~~~~~~~~~~~
 
-FF-A features may be discovered by Secure Partitions while booting
-through the SPMC. However, SPMC cannot get features from Hypervisor
-early at boot time as NS world is not setup yet.
+FF-A features supported by the SPMC may be discovered by secure partitions at
+boot (that is prior to NWd is booted) or run-time.
 
-The Hypervisor may decide to gather FF-A features from SPMC through SPMD
-once at boot time and store the result. Later when a VM requests FF-A
-features, the Hypervisor can adjust its own set of features with what
-SPMC advertised, if necessary. Another approach is to always forward FF-A
-features to the SPMC when a VM requests it to the Hypervisor. Although
-the result is not supposed to change over time so there may not be added
-value doing the systematic forwarding.
+The SPMC calling FFA_FEATURES at secure physical FF-A instance always get
+FFA_SUCCESS from the SPMD.
+
+The request made by an Hypervisor or OS kernel is forwarded to the SPMC and
+the response relayed back to the NWd.
 
 FFA_RXTX_MAP/FFA_RXTX_UNMAP
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-VM mailboxes are re-purposed to serve as SP RX/TX buffers. The RX/TX
-map API maps the send and receive buffer IPAs to the SP Stage-2 translation regime.
+When invoked from a secure partition FFA_RXTX_MAP maps the provided send and
+receive buffers described by their IPAs to the SP EL1&0 Stage-2 translation
+regime as secure buffers in the MMU descriptors.
 
-Hafnium in the normal world defines VMs and their attributes as logical structures,
-including a mailbox used for FF-A indirect messaging, memory sharing, or the
-`FFA_PARTITION_INFO_GET`_  ABI.
-This same mailbox structure is re-used in the SPMC. `[1]`_ states only direct
-messaging is allowed to SPs. Thus mailbox usage is restricted to implementing
-`FFA_PARTITION_INFO_GET`_ and memory sharing ABIs.
+When invoked from the Hypervisor or OS kernel, the buffers are mapped into the
+SPMC EL2 Stage-1 translation regime and marked as NS buffers in the MMU
+descriptors.
+
+Note:
+
+- FFA_RXTX_UNMAP is not implemented.
 
 FFA_PARTITION_INFO_GET
 ~~~~~~~~~~~~~~~~~~~~~~
 
-Partition info get service call can originate:
+Partition info get call can originate:
 
--  from SP to SPM
--  from VM to Hypervisor
--  from Hypervisor to SPM
-
-For the latter case, the service call must be forwarded through the SPMD.
+- from SP to SPMC
+- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD.
 
 FFA_ID_GET
 ~~~~~~~~~~
 
-The SPMD returns:
+The FF-A id space is split into a non-secure space and secure space:
 
--  a default zero value on invocation from the Hypervisor.
--  The ``spmc_id`` value specified in the SPMC manifest on invocation from
-   the SPMC (see `SPMC manifest`_)
+- FF-A ID with bit 15 clear relates to VMs.
+- FF-A ID with bit 15 set related to SPs.
+- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor, SPMD
+  and SPMC.
 
-The FF-A id space is split into a non-secure space and secure space:
+The SPMD returns:
 
--  FF-A id with bit 15 clear refer to normal world VMs.
--  FF-A id with bit 15 set refer to secure world SPs
+- The default zero value on invocation from the Hypervisor.
+- The ``spmc_id`` value specified in the SPMC manifest on invocation from
+  the SPMC (see `SPMC manifest`_)
 
-Such convention helps the SPMC discriminating the origin and destination worlds
-in an FF-A service invocation. In particular the SPMC shall filter unauthorized
+This convention helps the SPMC to determine the origin and destination worlds in
+an FF-A ABI invocation. In particular the SPMC shall filter unauthorized
 transactions in its world switch routine. It must not be permitted for a VM to
-use a secure FF-A id as origin world through spoofing:
+use a secure FF-A ID as origin world by spoofing:
 
--  A VM-to-SP messaging passing shall have an origin world being non-secure
-   (FF-A id bit 15 clear) and destination world being secure (FF-A id bit 15
-   set).
--  Similarly, an SP-to-SP message shall have FF-A id bit 15 set for both origin
-   and destination ids.
+- A VM-to-SP direct request/response shall set the origin world to be non-secure
+  (FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15
+  set).
+- Similarly, an SP-to-SP direct request/response shall set the FF-A ID bit 15
+  for both origin and destination IDs.
 
 An incoming direct message request arriving at SPMD from NWd is forwarded to
 SPMC without a specific check. The SPMC is resumed through eret and "knows" the
 message is coming from normal world in this specific code path. Thus the origin
-endpoint id must be checked by SPMC for being a normal world id.
+endpoint ID must be checked by SPMC for being a normal world ID.
 
 An SP sending a direct message request must have bit 15 set in its origin
-endpoint id and this can be checked by the SPMC when the SP invokes the ABI.
+endpoint ID and this can be checked by the SPMC when the SP invokes the ABI.
 
 The SPMC shall reject the direct message if the claimed world in origin endpoint
-id is not consistent:
-
--  It is either forwarded by SPMD and thus origin endpoint id must be a "normal
-   world id",
--  or initiated by an SP and thus origin endpoint id must be a "secure world id".
+ID is not consistent:
 
-Direct messaging
-----------------
-
-This is a mandatory interface for Secure Partitions consisting in direct
-message request and responses.
+-  It is either forwarded by SPMD and thus origin endpoint ID must be a "normal
+   world ID",
+-  or initiated by an SP and thus origin endpoint ID must be a "secure world ID".
 
-The ``ffa_handler`` Hafnium function may:
 
--  trigger a world change e.g. when an SP invokes the direct message
-   response ABI to a VM.
--  handle multiple requests from the NWd without resuming an SP.
+FFA_MSG_SEND_DIRECT_REQ/FFA_MSG_SEND_DIRECT_RESP
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-SP-to-SP
-~~~~~~~~
+This is a mandatory interface for secure partitions consisting in direct request
+and responses with the following rules:
 
--  An SP can send a direct message request to another SP
--  An SP can receive a direct message response from another SP.
+- An SP can send a direct request to another SP.
+- An SP can receive a direct request from another SP.
+- An SP can send a direct response to another SP.
+- An SP cannot send a direct request to an Hypervisor or OS kernel.
+- An Hypervisor or OS kernel can send a direct request to an SP.
+- An SP can send a direct response to an Hypervisor or OS kernel.
 
-VM-to-SP
-~~~~~~~~
+SPMC-SPMD direct requests/responses
+-----------------------------------
 
--  A VM can send a direct message request to an SP
--  An SP can send a direct message response to a VM
+Implementation-defined FF-A IDs are allocated to the SPMC and SPMD.
+Using those IDs in source/destination fields of a direct request/response
+permits SPMD to SPMC communication and either way.
 
-SPMC-SPMD messaging
-~~~~~~~~~~~~~~~~~~~
+- SPMC to SPMD direct request/response uses SMC conduit.
+- SPMD to SPMC direct request/response uses ERET conduit.
 
-Specific implementation-defined endpoint IDs are allocated to the SPMC and SPMD.
-Referring those IDs in source/destination fields of a direct message
-request/response permits SPMD to SPMC messaging back and forth.
+PE MMU configuration
+--------------------
 
-Per `[1]`_ Table 114 Config No. 1 (physical FF-A instance):
+With secure virtualization enabled, two IPA spaces are output from the secure
+EL1&0 Stage-1 translation (secure and non-secure). The EL1&0 Stage-2 translation
+hardware is fed by:
 
--  SPMC=>SPMD direct message request uses SMC conduit
--  SPMD=>SPMC direct message request uses ERET conduit
+- A single secure IPA space when the SP EL1&0 Stage-1 MMU is disabled.
+- Two IPA spaces (secure and non-secure) when the SP EL1&0 Stage-1 MMU is
+  enabled.
 
-Per `[1]`_ Table 118 Config No. 1 (physical FF-A instance):
+``VTCR_EL2`` and ``VSTCR_EL2`` provide configuration bits for controlling the
+NS/S IPA translations.
+``VSTCR_EL2.SW`` = 0, ``VSTCR_EL2.SA`` = 0,``VTCR_EL2.NSW`` = 0, ``VTCR_EL2.NSA`` = 1:
 
--  SPMC=>SPMD direct message response uses SMC conduit
--  SPMD=>SPMC direct message response uses ERET conduit
+- Stage-2 translations for the NS IPA space access the NS PA space.
+- Stage-2 translation table walks for the NS IPA space are to the secure PA space.
 
-Memory management
------------------
+Secure and non-secure IPA regions use the same set of Stage-2 page tables within
+a SP.
 
-This section only deals with the PE MMU configuration.
+Interrupt management
+--------------------
 
-Hafnium in the normal world deals with NS buffers only and provisions
-a single root page table directory to VMs. In context of S-EL2 enabled
-firmware, two IPA spaces are output from Stage-1 translation (secure
-and non-secure). The Stage-2 translation handles:
+GIC ownership
+~~~~~~~~~~~~~
 
--  A single secure IPA space when an SP Stage-1 MMU is disabled.
--  Two IPA spaces (secure and non-secure) when Stage-1 MMU is enabled.
+The SPMC owns the GIC configuration. Secure and non-secure interrupts are
+trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt
+IDs based on SP manifests. The SPMC acknowledges physical interrupts and injects
+virtual interrupts by setting the use of vIRQ/vFIQ bits before resuming a SP.
 
-``VTCR_EL2`` and ``VSTCR_EL2`` provide additional bits for controlling the
-NS/S IPA translations (``VSTCR_EL2.SW``, ``VSTCR_EL2.SA``, ``VTCR_EL2.NSW``,
-``VTCR_EL2.NSA``). There may be two approaches:
+Non-secure interrupt handling
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
--  secure and non-secure mappings are rooted as two separate root page
-   tables
--  secure and non-secure mappings use the same root page table. Access
-   from S-EL1 to an NS region translates to a secure physical address
-   space access.
+The following illustrate the scenarios of non secure physical interrupts trapped
+by the SPMC:
 
-Interrupt management
---------------------
+- The SP handles a managed exit operation:
 
-Road to a para-virtualized interface
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. image:: ../resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png
 
-Current Hafnium implementation uses an ad-hoc mechanism for a VM to get
-a pending interrupt number through an hypercall. The PVM injects
-interrupts to VMs by delegation from the Hypervisor. The PVM probes a
-pending interrupt directly from the GIC distributor.
+- The SP is pre-empted without managed exit:
 
-The short-term plan is to have Hafnium/SPMC in the secure world owner
-of the GIC configuration.
+.. image:: ../resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png
 
-The SPMC fully owns the GIC configuration at S-EL2. The SPMC manages
-interrupt resources and allocates interrupt ID based on SP manifests.
-The SPMC acknowledges physical interrupts and injects virtual interrupts
-by setting the vIRQ bit when resuming an SP. A Secure Partition gathers
-the interrupt number through an hypercall.
+Secure interrupt handling
+~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Notice the SPMC/SPMD has to handle Group0 secure interrupts in addition
-to Group1 S/NS interrupts.
+The current implementation does not support handling of secure interrupts
+trapped by the SPMC at S-EL2. This is work in progress planned for future
+releases.
 
 Power management
 ----------------
 
+In platforms with or without secure virtualization:
+
+- The NWd owns the platform PM policy.
+- The Hypervisor or OS kernel is the component initiating PSCI service calls.
+- The EL3 PSCI library is in charge of the PM coordination and control
+  (eventually writing to platform registers).
+- While coordinating PM events, the PSCI library calls backs into the Secure
+  Payload Dispatcher for events the latter has statically registered to.
+
+When using the SPMD as a Secure Payload Dispatcher:
+
-Assumption on the Nwd:
+- A power management event is relayed through the SPD hook to the SPMC.
+- In the current implementation only cpu on (svc_on_finish) and cpu off
+  (svc_off) hooks are registered.
+- The behavior for the cpu on event is described in `Secondary cores boot-up`_.
+  The SPMC is entered through its secondary physical core entry point.
+- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The method by which
+  the PM event is conveyed to the SPMC is implementation-defined in context of
+  FF-A v1.0 (`SPMC-SPMD direct requests/responses`_). It consists in a SPMD-to-SPMC
+  direct request/response conveying the PM event details and SPMC response.
+  The SPMD performs a synchronous entry into the SPMC. The SPMC is entered and
+  updates its internal state to reflect the physical core is being turned off.
+  In the current implementation no SP is resumed as a consequence. This behavior
+  ensures a minimal support for CPU hotplug e.g. when initiated by the NWd linux
+  userspace.
 
--  NWd is the best candidate to own the platform Power Management
-   policy. It is master to invoking PSCI service calls from physical
-   CPUs.
--  EL3 monitor is in charge of the PM control part (its PSCI layer
-   actually writing to platform registers).
--  It is fine for the Hypervisor to trap PSCI calls and relay to EL3, or
-   OS kernel driver to emit PSCI service calls.
+SMMUv3 support in Hafnium
+=========================
 
-PSCI notification are relayed through the SPMD/SPD PM hooks to the SPMC.
-This can either be through re-use of PSCI FIDs or an FF-A direct message
-from SPMD to SPMC.
+An SMMU is analogous to an MMU in a CPU. It performs address translations for
+Direct Memory Access (DMA) requests from system I/O devices.
+The responsibilities of an SMMU include:
 
-The SPMD performs an exception return to the SPMC which is resumed to
-its ``eret_handler`` routine. It is then either consuming a PSCI FID or
-an FF-A FID. Depending on the servicing, the SPMC may return directly to
-the SPMD (and then NWd) without resuming an SP at this stage. An example
-of this is invocation of ``FFA_PARTITION_INFO_GET`` from NWd relayed by
-the SPMD to the SPMC. The SPMC returns the needed partition information
-to the SPMD (then NWd) without actually resuming a partition in secure world.
+-  Translation: Incoming DMA requests are translated from bus address space to
+   system physical address space using translation tables compliant to
+   Armv8/Armv7 VMSA descriptor format.
+-  Protection: An I/O device can be prohibited from read, write access to a
+   memory region or allowed.
+-  Isolation: Traffic from each individial device can be independently managed.
+   The devices are differentiated from each other using unique translation
+   tables.
 
-*(under discussion)*
-About using PSCI FIDs from SPMD to SPMC to notify of PM events, it is still
-questioned what to use as the return code from the SPMC.
-If the function ID used by the SPMC is not an FF-A ID when doing SMC, then the
-EL3 std svc handler won't route the response to the SPMD. That's where comes the
-idea to embed the notification into an FF-A message. The SPMC can discriminate
-this message as being a PSCI event, process it, and reply with an FF-A return
-message that the SPMD receives as an acknowledgement.
+The following diagram illustrates a typical SMMU IP integrated in a SoC with
+several I/O devices along with Interconnect and Memory system.
 
-SP notification
+.. image:: ../resources/diagrams/MMU-600.png
+
+SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides
+support for SMMUv3 driver in both normal and secure world. A brief introduction
+of SMMUv3 functionality and the corresponding software support in Hafnium is
+provided here.
+
+SMMUv3 features
 ---------------
 
+-  SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2)
+   translation support. It can either bypass or abort incoming translations as
+   well.
+-  Traffic (memory transactions) from each upstream I/O peripheral device,
+   referred to as Stream, can be independently managed using a combination of
+   several memory based configuration structures. This allows the SMMUv3 to
+   support a large number of streams with each stream assigned to a unique
+   translation context.
+-  Support for Armv8.1 VMSA where the SMMU shares the translation tables with
+   a Processing Element. AArch32(LPAE) and AArch64 translation table format
+   are supported by SMMUv3.
+-  SMMUv3 offers non-secure stream support with secure stream support being
+   optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU
+   instance for secure and non-secure stream support.
+-  It also supports sub-streams to differentiate traffic from a virtualized
+   peripheral associated with a VM/SP.
+-  Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A
+   extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2
+   for providing Secure Stage2 translation support to upstream peripheral
+   devices.
+
+SMMUv3 Programming Interfaces
+-----------------------------
+
-Power management notifications are conveyed from PSCI library to the
-SPMD / SPD hooks. A range of events can be relayed to SPMC.
+SMMUv3 has three software interfaces that are used by the Hafnium driver to
+configure the behaviour of SMMUv3 and manage the streams.
 
-SPs may need to be notified about specific PM events.
+-  Memory based data strutures that provide unique translation context for
+   each stream.
+-  Memory based circular buffers for command queue and event queue.
+-  A large number of SMMU configuration registers that are memory mapped during
+   boot time by Hafnium driver. Except a few registers, all configuration
+   registers have independent secure and non-secure versions to configure the
+   behaviour of SMMUv3 for translation of secure and non-secure streams
+   respectively.
 
--  SPs might register PM events to the SPMC
--  On SPMD to SPMC notification, a limited range of SPs may be notified
-   through a direct message.
--  This assumes the mentioned SPs supports managed exit.
+Peripheral device manifest
+--------------------------
 
-The SPMC is the first to be notified about PM events from the SPMD. It is up
-to the SPMC to arbitrate to which SP it needs to send PM events.
-An SP explicitly registers to receive notifications to specific PM events.
-The register operation can either be an implementation-defined service call
-to the SPMC when the primary SP EC boots, or be supplied through the SP
-manifest.
+Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices.
+These devices are dependent on PE endpoint to initiate and receive memory
+management transactions on their behalf. The acccess to the MMIO regions of
+any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver
+uses the same stage 2 translations for the device as those used by partition
+manager on behalf of the PE endpoint. This ensures that the peripheral device
+has the same visibility of the physical address space as the endpoint. The
+device node of the corresponding partition manifest (refer to `[1]`_ section 3.2
+) must specify these additional properties for each peripheral device in the
+system :
+
+-  smmu-id: This field helps to identify the SMMU instance that this device is
+   upstream of.
+-  stream-ids: List of stream IDs assigned to this device.
+
+.. code:: shell
+
+    smmuv3-testengine {
+        base-address = <0x00000000 0x2bfe0000>;
+        pages-count = <32>;
+        attributes = <0x3>;
+        smmu-id = <0>;
+        stream-ids = <0x0 0x1>;
+        interrupts = <0x2 0x3>, <0x4 0x5>;
+        exclusive-access;
+    };
+
+SMMUv3 driver limitations
+-------------------------
+
+The primary design goal for the Hafnium SMMU driver is to support secure
+streams.
+
+-  Currently, the driver only supports Stage2 translations. No support for
+   Stage1 or nested translations.
+-  Supports only AArch64 translation format.
+-  No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS,
+   Fault handling, Performance Monitor Extensions, Event Handling, MPAM.
+-  No support for independent peripheral devices.
 
 References
 ==========
 
 .. _[1]:
 
-[1] `Platform Security Architecture Firmware Framework for Arm® v8-A 1.0 Platform Design Document <https://developer.arm.com/docs/den0077/latest>`__
+[1] `Arm Firmware Framework for Armv8-A <https://developer.arm.com/docs/den0077/latest>`__
 
 .. _[2]:
 
@@ -846,7 +929,7 @@
 .. _[3]:
 
 [3] `Trusted Boot Board Requirements
-Client <https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a>`__
+Client <https://developer.arm.com/documentation/den0006/d/>`__
 
 .. _[4]:
 
@@ -854,11 +937,11 @@
 
 .. _[5]:
 
-[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/cactus.dts
+[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/plat/arm/fvp/fdts/cactus.dts
 
 .. _[6]:
 
-[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/psa-ffa-manifest-binding.html
+[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html
 
 .. _[7]:
 
@@ -866,8 +949,8 @@
 
 .. _[8]:
 
-[8] https://developer.trustedfirmware.org/w/tf_a/poc-multiple-signing-domains/
+[8] https://lists.trustedfirmware.org/pipermail/tf-a/2020-February/000296.html
 
 --------------
 
-*Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/conf.py b/docs/conf.py
index a100241..356be99 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -1,6 +1,6 @@
 # -*- coding: utf-8 -*-
 #
-# Copyright (c) 2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -76,6 +76,14 @@
     'style_external_links': True # Display an icon next to external links
 }
 
+# Path to _static directory
+html_static_path = ['_static']
+
+# Path to css file relative to html_static_path
+html_css_files = [
+    'css/custom.css',
+]
+
 # -- Options for autosectionlabel --------------------------------------------
 
 # Only generate automatic section labels for document titles
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 7c142d1..949845a 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -260,6 +260,12 @@
 -  ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
 
+-  ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
+   CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+-  ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
+   CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
+
 For Cortex-A78, the following errata build flags are defined :
 
 -  ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
@@ -272,6 +278,9 @@
    CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
    issue but there is no workaround for that revision.
 
+-  ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
+   CPU. This needs to be enabled for revisions r0p0 and r1p0.
+
 For Neoverse N1, the following errata build flags are defined :
 
 -  ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
@@ -314,6 +323,16 @@
    CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
    revisions r0p0, r1p0, and r2p0 there is no workaround.
 
+For Neoverse V1, the following errata build flags are defined :
+
+-  ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
+   CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
+   in r1p1.
+
+-  ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
+   CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
+   CPU.
+
 DSU Errata Workarounds
 ----------------------
 
@@ -385,7 +404,7 @@
 
 --------------
 
-*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.*
 
 .. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
 .. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 5935b4e..86618e4 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -252,7 +252,8 @@
 
 -  ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
    support within generic code in TF-A. This option is currently only supported
-   in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0.
+   in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32
+   (SP_min) for AARCH32. Default is 0.
 
 -  ``ENABLE_PMF``: Boolean option to enable support for optional Performance
    Measurement Framework(PMF). Default is 0.
@@ -277,7 +278,8 @@
 -  ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
    (SVE) for the Non-secure world only. SVE is an optional architectural feature
    for AArch64. Note that when SVE is enabled for the Non-secure world, access
-   to SIMD and floating-point functionality from the Secure world is disabled.
+   to SIMD and floating-point functionality from the Secure world is disabled by
+   default and controlled with ENABLE_SVE_FOR_SWD.
    This is to avoid corruption of the Non-secure world data in the Z-registers
    which are aliased by the SIMD and FP registers. The build option is not
    compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
@@ -285,6 +287,11 @@
    1. The default is 1 but is automatically disabled when the target
    architecture is AArch32.
 
+-  ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
+   SVE is an optional architectural feature for AArch64. Note that this option
+   requires ENABLE_SVE_FOR_NS to be enabled.  The default is 0 and it is
+   automatically disabled when the target architecture is AArch32.
+
 -  ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
    checks in GCC. Allowed values are "all", "strong", "default" and "none". The
    default value is set to "none". "strong" is the recommended stack protection
@@ -462,7 +469,10 @@
    the build. The default value is 40 in debug builds and 20 in release builds.
 
 -  ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
-   feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set.
+   feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well
+   in order to provide trust that the code taking the measurements and recording
+   them has not been tampered with.
+
    This option defaults to 0 and is an experimental feature in the stage of
    development.
 
@@ -578,6 +588,11 @@
    ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
    sections are placed in RAM immediately following the loaded firmware image.
 
+-  ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
+   access requests via a standard SMCCC defined in `DEN0115`_. When combined with
+   UEFI+ACPI this can provide a certain amount of OS forward compatibility
+   with newer platforms that aren't ECAM compliant.
+
 -  ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
    This build option is only valid if ``ARCH=aarch64``. The value should be
    the path to the directory containing the SPD source, relative to
@@ -847,4 +862,7 @@
 
 --------------
 
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+
+.. _DEN0115: https://developer.arm.com/docs/den0115/latest
+
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index be3f0bb..906daf8 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -1742,9 +1742,9 @@
     which is list of executable images following BL31,
 
     arg1 - Points to load address of SOC_FW_CONFIG if present
-           except in case of Arm FVP platform.
+           except in case of Arm FVP and Juno platform.
 
-           In case of Arm FVP platform, Points to load address
+           In case of Arm FVP and Juno platform, points to load address
            of FW_CONFIG.
 
     arg2 - Points to load address of HW_CONFIG if present
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 91ecdf3..aa1ae67 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@
 |TF-A| can be built with any of the following *cross-compiler* toolchains that
 target the Armv7-A or Armv8-A architectures:
 
-- GCC >= 9.2-2019.12 (from the `Arm Developer website`_)
+- GCC >= 10.2-2020.11 (from the `Arm Developer website`_)
 - Clang >= 4.0
 - Arm Compiler >= 6.0
 
@@ -60,7 +60,7 @@
 
 The following libraries are required for Trusted Board Boot support:
 
-- mbed TLS == 2.24.0 (tag: ``mbedtls-2.24.0``)
+- mbed TLS == 2.26.0 (tag: ``mbedtls-2.26.0``)
 
 These tools are optional:
 
@@ -75,6 +75,12 @@
    The standard software package used for debugging software on Arm development
    platforms and |FVP| models.
 
+- Node.js >= 14
+
+   Highly recommended, and necessary in order to install and use the packaged
+   Git hooks and helper tools. Without these tools you will need to rely on the
+   CI for feedback on commit message conformance.
+
 Package Installation (Linux)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -91,11 +97,22 @@
 
     sudo apt install device-tree-compiler
 
+Additionally, to install an up-to-date version of Node.js, you can use the `Node
+Version Manager`_ to install a version of your choosing (we recommend 14, but
+later LTS versions might offer a more stable experience):
+
+.. code:: shell
+
+    curl -o- https://raw.githubusercontent.com/nvm-sh/nvm/v0.38.0/install.sh | "$SHELL"
+    exec "$SHELL" -ic "nvm install 14; exec $SHELL"
+
+.. _Node Version Manager: https://github.com/nvm-sh/nvm#install--update-script
+
 Supporting Files
 ----------------
 
 TF-A has been tested with pre-built binaries and file systems from `Linaro
-Release 19.06`_. Alternatively, you can build the binaries from source using
+Release 20.01`_. Alternatively, you can build the binaries from source using
 instructions in :ref:`Performing an Initial Build`.
 
 .. _prerequisites_get_source:
@@ -109,28 +126,44 @@
 
 .. code:: shell
 
-    git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a" && (cd "trusted-firmware-a" && mkdir -p .git/hooks && curl -Lo `git rev-parse --git-dir`/hooks/commit-msg https://review.trustedfirmware.org/tools/hooks/commit-msg; chmod +x `git rev-parse --git-dir`/hooks/commit-msg)
+    git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
 
-This will clone the Git repository also install a *commit hook* that
-automatically inserts appropriate *Change-Id:* lines at the end of your
-commit messages. These change IDs are required when committing changes that you
-intend to push for review via our Gerrit system.
+Additional Steps for Contributors
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-You can read more about Git hooks in the *githooks* page of the Git documentation,
-available at: https://git-scm.com/docs/githooks
+If you are planning on contributing back to TF-A, there are some things you'll
+want to know.
 
-Alternatively, you can clone without the commit hook using:
+TF-A is hosted by a `Gerrit Code Review`_ server. Gerrit requires that all
+commits include a ``Change-Id`` footer, and this footer is typically
+automatically generated by a Git hook installed by you, the developer.
+
+If you have Node.js installed already, you can automatically install this hook,
+along with any additional hooks and Javascript-based tooling that we use, by
+running from within your newly-cloned repository:
 
 .. code:: shell
 
-    git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
+    npm install --no-save
+
+If you have opted **not** to install Node.js, you can install the Gerrit hook
+manually by running:
+
+.. code:: shell
+
+    curl -Lo $(git rev-parse --git-dir)/hooks/commit-msg https://review.trustedfirmware.org/tools/hooks/commit-msg
+    chmod +x $(git rev-parse --git-dir)/hooks/commit-msg
+
+You can read more about Git hooks in the *githooks* page of the Git
+documentation, available `here <https://git-scm.com/docs/githooks>`_.
 
 --------------
 
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
 
 .. _Arm Developer website: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
+.. _Gerrit Code Review: https://www.gerritcodereview.com/
 .. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
 .. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
 .. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
-.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
+.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
diff --git a/docs/index.rst b/docs/index.rst
index cb53127..29e5839 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -15,8 +15,8 @@
    perf/index
    security_advisories/index
    design_documents/index
+   threat_model/index
    change-log
-   change-log-upcoming
    glossary
    license
 
@@ -83,7 +83,7 @@
 
 --------------
 
-*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
 
 .. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
 .. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
diff --git a/docs/license.rst b/docs/license.rst
index 2f97043..80f1118 100644
--- a/docs/license.rst
+++ b/docs/license.rst
@@ -76,5 +76,15 @@
    BSD-3-Clause license. Any contributions to this code must be made under the
    terms of both licenses.
 
+-  Some source files originating from the Linux source tree, which are
+   disjunctively dual licensed (GPL-2.0 OR MIT), are redistributed under the
+   terms of the MIT license. These files are:
+
+   -  ``include/dt-bindings/interrupt-controller/arm-gic.h``
+   -  ``include/dt-bindings/interrupt-controller/irq.h``
+
+   See the original `Linux MIT license`_.
+
 .. _FreeBSD: http://www.freebsd.org
+.. _Linux MIT license: https://raw.githubusercontent.com/torvalds/linux/master/LICENSES/preferred/MIT
 .. _SCC: http://www.simple-cc.org/
diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst
index d82380d..b696989 100644
--- a/docs/plat/allwinner.rst
+++ b/docs/plat/allwinner.rst
@@ -5,16 +5,34 @@
 SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
 PSCI runtime services.
 
-U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot).
-Loading is done from SD card, eMMC or SPI flash, also via an USB debug
-interface (FEL).
+Building TF-A
+-------------
 
-BL31 lives in SRAM A2, which is documented to be accessible from secure
-world only.
+To build for machines with an A64 or H5 SoC:
+
+.. code:: shell
+
+    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
+
+To build for machines with an H6 SoC:
+
+.. code:: shell
+
+    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
+
+To build for machines with an H616 or H313 SoC:
+
+.. code:: shell
+
+    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h616 DEBUG=1 bl31
 
-Current limitations:
 
--  Missing PMIC support
+Installation
+------------
+
+U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot).
+Loading is done from SD card, eMMC or SPI flash, also via an USB debug
+interface (FEL).
 
 After building bl31.bin, the binary must be fed to the U-Boot build system
 to include it in the FIT image that the SPL loader will process.
@@ -22,19 +40,54 @@
 or the environment variable BL31 must contain the binary's path.
 See the respective `U-Boot documentation`_ for more details.
 
-To build for machines with an A64 or H5 SoC:
+.. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64
 
-.. code:: shell
+Memory layout
+-------------
 
-    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
+A64, H5 and H6 SoCs
+~~~~~~~~~~~~~~~~~~~
 
-To build for machines with an H6 SoC:
+BL31 lives in SRAM A2, which is documented to be accessible from secure
+world only. Since this SRAM region is very limited (48 KB), we take
+several measures to reduce memory consumption. One of them is to confine
+BL31 to only 28 bits of virtual address space, which reduces the number
+of required page tables (each occupying 4KB of memory).
+The mapping we use on those SoCs is as follows:
 
-.. code:: shell
+::
 
-    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
+   0 64K         16M             1GB         1G+160M     physical address
+   +-+------+-+---+------+--...---+-------+----+------+----------
+   |B|      |S|///|      |//...///|       |////|      |
+   |R| SRAM |C|///| dev  |//...///| (sec) |////| BL33 |  DRAM ...
+   |O|      |P|///| MMIO |//...///| DRAM  |////|      |
+   |M|      | |///|      |//...///| (32M) |////|      |
+   +-+------+-+---+------+--...---+-------+----+------+----------
+   | |      | |   |      |       /       /   /      /
+   | |      | |   |      |      /       /  /      /
+   | |      | |   |      |     /       / /      /
+   | |      | |   |      |    /       //      /
+   | |      | |   |      |   /       /      /
+   +-+------+-+---+------+--+-------+------+
+   |B|      |S|///|      |//|       |      |
+   |R| SRAM |C|///| dev  |//|  sec  | BL33 |
+   |O|      |P|///| MMIO |//| DRAM  |      |
+   |M|      | |///|      |//|       |      |
+   +-+------+-+---+------+--+-------+------+
+   0 64K         16M       160M    192M  256M             virtual address
 
-.. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64
+
+H616 SoC
+~~~~~~~~
+
+The H616 lacks the secure SRAM region present on the other SoCs, also
+lacks the "ARISC" management processor (SCP) we use. BL31 thus needs to
+run from DRAM, which prevents our compressed virtual memory map described
+above. Since running in DRAM also lifts the restriction of the limited
+SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
+address space. So the virtual addresses used in BL31 match the physical
+addresses as presented above.
 
 Trusted OS dispatcher
 ---------------------
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index a1d2313..d4fa98d 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -91,6 +91,12 @@
    platforms. If this option is specified, then the path to the CryptoCell
    SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
 
+-  ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
+   configure an Arm Ethos-N NPU. To use this service the target platform's
+   ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
+   the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
+   only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
+
 -  ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the
    SPMC Core manifest. Valid when ``SPD=spmd`` is selected.
 
@@ -98,6 +104,17 @@
    device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest
    file name contains pattern optee_sp.
 
+-  ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and
+   secure-storage) as SP in tb_fw_config device tree.
+
+-  ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of
+   the various partitions present in the GPT image. This support is available
+   only for the BL2 component, and it is disabled by default.
+   The following diagram shows the view of the FIP partition inside the GPT
+   image:
+
+   |FIP in a GPT image|
+
 For a better understanding of these options, the Arm development platform memory
 map is explained in the :ref:`Firmware Design`.
 
@@ -126,6 +143,14 @@
    valid value greater than 1, the platform code performs required configuration
    to support multi-chip operation.
 
+- ``CSS_SGI_PLATFORM_VARIANT``: Selects the variant of a SGI/RD platform. A
+    particular SGI/RD platform may have multiple variants which may differ in
+    core count, cluster count or other peripherals. This build option is used
+    to select the appropriate platform variant for the build. The range of
+    valid values is platform specific.
+
 --------------
 
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+.. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png
+
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/diphda/index.rst b/docs/plat/arm/diphda/index.rst
new file mode 100644
index 0000000..27afda4
--- /dev/null
+++ b/docs/plat/arm/diphda/index.rst
@@ -0,0 +1,61 @@
+Diphda Platform
+==========================
+
+Some of the features of the Diphda platform referenced in TF-A include:
+
+- Cortex-A35 application processor (64-bit mode)
+- Secure Enclave
+- GIC-400
+- Trusted Board Boot
+
+Boot Sequence
+-------------
+
+The board boot relies on CoT (chain of trust). The trusted-firmware-a
+BL2 is extracted from the FIP and verified by the Secure Enclave
+processor. BL2 verification relies on the signature area at the
+beginning of the BL2 image. This area is needed by the SecureEnclave
+bootloader.
+
+Then, the application processor is released from reset and starts by
+executing BL2.
+
+BL2 performs the actions described in the trusted-firmware-a TBB design
+document.
+
+Build Procedure (TF-A only)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Obtain AArch64 ELF bare-metal target `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
+   Set the CROSS_COMPILE environment variable to point to the toolchain folder.
+
+-  Build TF-A:
+
+   .. code:: shell
+
+      make LD=aarch64-none-elf-ld \
+      CC=aarch64-none-elf-gcc \
+      V=1 \
+      BUILD_BASE=<path to the build folder> \
+      PLAT=diphda \
+      SPD=spmd \
+      SPMD_SPM_AT_SEL2=0 \
+      DEBUG=1 \
+      MBEDTLS_DIR=mbedtls \
+      OPENSSL_DIR=<path to openssl usr folder> \
+      RUNTIME_SYSROOT=<path to the sysroot> \
+      ARCH=aarch64 \
+      TARGET_PLATFORM=<fpga or fvp> \
+      ENABLE_PIE=1 \
+      BL2_AT_EL3=1 \
+      CREATE_KEYS=1 \
+      GENERATE_COT=1 \
+      TRUSTED_BOARD_BOOT=1 \
+      COT=tbbr \
+      ARM_ROTPK_LOCATION=devel_rsa \
+      ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
+      BL32=<path to optee binary> \
+      BL33=<path to u-boot binary> \
+      bl2
+
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index c3ef07e..d41982f 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -12,13 +12,13 @@
 (64-bit host machine only).
 
 .. note::
-   The FVP models used are Version 11.12 Build 38, unless otherwise stated.
+   The FVP models used are Version 11.15 Build 14, unless otherwise stated.
 
 -  ``FVP_Base_AEMvA``
 -  ``FVP_Base_AEMv8A-AEMv8A``
 -  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
--  ``FVP_Base_RevC-2xAEMv8A``
--  ``FVP_Base_Cortex-A32x4``
+-  ``FVP_Base_RevC-2xAEMvA``
+-  ``FVP_Base_Cortex-A32x4`` (Version 11.12 build 38)
 -  ``FVP_Base_Cortex-A35x4``
 -  ``FVP_Base_Cortex-A53x4``
 -  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
@@ -39,10 +39,13 @@
 -  ``FVP_Base_Cortex-A76AEx8``
 -  ``FVP_Base_Cortex-A77x4``
 -  ``FVP_Base_Cortex-A78x4``
+-  ``FVP_Base_Cortex-A710x4``
+-  ``FVP_Morello``         (Version 0.10 build 542)
 -  ``FVP_Base_Neoverse-E1x1``
 -  ``FVP_Base_Neoverse-E1x2``
 -  ``FVP_Base_Neoverse-E1x4``
 -  ``FVP_Base_Neoverse-N1x4``
+-  ``FVP_Base_Neoverse-N2x4`` (Version 11.12 build 38)
 -  ``FVP_Base_Neoverse-V1x4``
 -  ``FVP_CSS_SGI-575``     (Version 11.10 build 36)
 -  ``FVP_CSS_SGM-775``
@@ -51,7 +54,7 @@
 -  ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36)
 -  ``FVP_RD_Daniel``       (Version 11.13 build 10)
 -  ``FVP_RD_N2``           (Version 11.13 build 10)
--  ``FVP_TC0``             (Version 0.0 build 6114)
+-  ``FVP_TC0``             (Version 0.0 build 6509)
 -  ``FVP_Base_AEMv8A-GIC600AE`` (Version 0.0 build 6415)
 -  ``Foundation_Platform``
 
@@ -98,7 +101,7 @@
    the models. The models can be launched with ``-Q 100`` option if they are
    required to match the run time characteristics of the older versions.
 
-All the above platforms have been tested with `Linaro Release 19.06`_.
+All the above platforms have been tested with `Linaro Release 20.01`_.
 
 .. _build_options_arm_fvp_platform:
 
@@ -523,8 +526,8 @@
 
 Notes:
 
--  If Position Independent Executable (PIE) support is enabled for BL31
-   in this config, it can be loaded at any valid address for execution.
+-  Position Independent Executable (PIE) support is enabled in this
+   config allowing BL31 to be loaded at any valid address for execution.
 
 -  Since a FIP is not loaded when using BL31 as reset entrypoint, the
    ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
@@ -585,8 +588,8 @@
     --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
 
 .. note::
-   The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
-   It should match the address programmed into the RVBAR register as well.
+   Position Independent Executable (PIE) support is enabled in this
+   config allowing SP_MIN to be loaded at any valid address for execution.
 
 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -641,10 +644,10 @@
 
 --------------
 
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
 
 .. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
 .. _Arm's website: `FVP models`_
 .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
+.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
 .. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
index f72992b..f50dab5 100644
--- a/docs/plat/arm/index.rst
+++ b/docs/plat/arm/index.rst
@@ -12,6 +12,7 @@
    arm_fpga/index
    arm-build-options
    morello/index
+   diphda/index
 
 This chapter holds documentation related to Arm's development platforms,
 including both software models (FVPs) and hardware development boards
@@ -19,4 +20,4 @@
 
 --------------
 
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index cf328fa..8b9d453 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -12,24 +12,21 @@
 
 This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
 
-To execute the software stack on Juno, the version of the Juno board recovery
-image indicated in the `Linaro Release Notes`_ must be installed. If you have an
-earlier version installed or are unsure which version is installed, please
-re-install the recovery image by following the
-`Instructions for using Linaro's deliverables on Juno`_.
+To run TF-A on Juno, you need to first prepare an SD card with Juno software
+stack that includes TF-A. This version of TF-A is tested with pre-built
+`Linaro release software stack`_ version 20.01. You can alternatively
+build the software stack yourself by following the
+`Juno platform software user guide`_. Once you prepare the software stack
+on an SD card, you can replace the ``bl1.bin`` and ``fip.bin``
+binaries in the ``SOFTWARE/`` directory with custom built TF-A binaries.
 
 Preparing TF-A images
 ---------------------
 
-After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
-``SOFTWARE/`` directory of the Juno SD card.
-
-Creating a Firmware Image Package (FIP)
----------------------------------------
-
 This section provides Juno and FVP specific instructions to build Trusted
 Firmware, obtain the additional required firmware, and pack it all together in
-a single FIP binary. It assumes that a Linaro release has been installed.
+a single FIP binary. It assumes that a Linaro release software stack has been
+installed.
 
 .. note::
    Pre-built binaries for AArch32 are available from Linaro Release 16.12
@@ -57,9 +54,16 @@
 
        make realclean
 
-#. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
+#. Obtain SCP binaries (Juno)
 
-   Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
+   This version of TF-A is tested with SCP version 2.8.0 on Juno. You can
+   download pre-built SCP binaries (``scp_bl1.bin`` and ``scp_bl2.bin``)
+   from `TF-A downloads page`_. Alternatively, you can `build
+   the binaries from source`_.
+
+#. Obtain BL33 (all platforms)
+
+   Use the fiptool to extract the BL33 image from the FIP
    package included in the Linaro release:
 
    .. code:: shell
@@ -71,8 +75,7 @@
        ./tools/fiptool/fiptool unpack <path-to-linaro-release>/[SOFTWARE]/fip.bin
 
    The unpack operation will result in a set of binary images extracted to the
-   current working directory. The SCP_BL2 image corresponds to
-   ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
+   current working directory. BL33 corresponds to ``nt-fw.bin``.
 
    .. note::
       The fiptool will complain if the images to be unpacked already
@@ -102,7 +105,7 @@
 
    .. code:: shell
 
-       make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
+       make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp_bl2.bin all fip
 
    For AArch32:
 
@@ -144,7 +147,7 @@
       .. code:: shell
 
           make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
-          BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
+          BL33=nt-fw.bin SCP_BL2=scp_bl2.bin \
           BL32=<path-to-temporary>/bl32.bin all fip
 
 The resulting BL1 and FIP images may be found in:
@@ -159,6 +162,8 @@
     ./build/fvp/release/bl1.bin
     ./build/fvp/release/fip.bin
 
+After building TF-A, the files ``bl1.bin``, ``fip.bin`` and ``scp_bl1.bin``
+need to be copied to the ``SOFTWARE/`` directory on the Juno SD card.
 
 Booting Firmware Update images
 ------------------------------
@@ -236,10 +241,12 @@
 
 --------------
 
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
 
-.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
-.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
+.. _Linaro release software stack: http://releases.linaro.org/members/arm/platforms/
+.. _Juno platform software user guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/juno/user-guide.rst
+.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.8.0/juno/
+.. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide
 .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
 .. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
diff --git a/docs/plat/deprecated.rst b/docs/plat/deprecated.rst
new file mode 100644
index 0000000..7cc4258
--- /dev/null
+++ b/docs/plat/deprecated.rst
@@ -0,0 +1,20 @@
+Deprecated platforms
+====================
+
+Process of deprecating a platform
+---------------------------------
+
+Platform can be deprecated and its source can be kept in repository for a cooling
+off period before deleting it or it can be deleted straight away. For later types
+Deprecated/Deleted version would be same.
+
+List of deprecated platforms
+----------------------------
+
++----------------+----------------+--------------------+--------------------+
+|    Platform    |     Vendor     | Deprecated version |  Deleted version   |
++================+================+====================+====================+
+|    sgm775      |      Arm       |        2.5         |       2.7          |
++----------------+----------------+--------------------+--------------------+
+|    mt6795      |      MTK       |        2.5         |       2.7          |
++----------------+----------------+--------------------+--------------------+
diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst
index f184b69..0fe15c9 100644
--- a/docs/plat/imx8m.rst
+++ b/docs/plat/imx8m.rst
@@ -6,6 +6,9 @@
 reliability and embedded security needed to drive the growth of fast-growing
 edge node computing, streaming multimedia, and machine learning applications.
 
+imx8mq is dropped in TF-A CI build due to the small OCRAM size, but still actively
+maintained in NXP official release.
+
 Boot Sequence
 -------------
 
@@ -43,3 +46,17 @@
 used to generate flash.bin, and flash.bin needs to be flashed into SD card
 with certain offset for BOOT ROM. the u-boot and imx-mkimage will be upstreamed
 soon, this doc will be updated once they are ready, and the link will be posted.
+
+TBBR Boot Sequence
+------------------
+
+When setting NEED_BL2=1 on imx8mm. We support an alternative way of
+boot sequence to support TBBR.
+
+Bootrom --> SPL --> BL2 --> BL31 --> BL33(u-boot with UEFI) --> grub
+
+This helps us to fulfill the SystemReady EBBR standard.
+BL2 will be in the FIT image and SPL will verify it.
+All of the BL3x will be put in the FIP image. BL2 will verify them.
+In U-boot we turn on the UEFI secure boot features so it can verify
+grub. And we use grub to verify linux kernel.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 3cbb552..4dc9ecd 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -9,6 +9,7 @@
 
    allwinner
    arm/index
+   deprecated
    meson-axg
    meson-gxbb
    meson-gxl
@@ -20,6 +21,7 @@
    marvell/index
    mt8183
    mt8192
+   mt8195
    nvidia-tegra
    warp7
    imx8
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index e55ce3c..09b4fa4 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -26,7 +26,7 @@
 
        *u-boot.bin* should be used and not *u-boot-spl.bin*
 
-Set MSS/SCP image path (mandatory only for A7K/8K/CN913x)
+Set MSS/SCP image path (mandatory only for A7K/8K/CN913x when MSS_SUPPORT=1)
 
     .. code:: shell
 
@@ -112,6 +112,11 @@
         This option is needed on Turris MOX as a workaround to a HW bug which causes reset to
         sometime hang the board.
 
+- A3720_DB_PM_WAKEUP_SRC
+
+        For Armada 3720 Develpment Board only, when ``A3720_DB_PM_WAKEUP_SRC=1``,
+        TF-A will setup PM wake up src configuration. This option is disabled by default.
+
 - MARVELL_SECURE_BOOT
 
         Build trusted(=1)/non trusted(=0) image, default is non trusted.
@@ -124,19 +129,16 @@
 
 - MV_DDR_PATH
 
-        For A7K/8K/CN913x, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
-        it is used for ddr_tool build.
+        This parameter is required for ``mrvl_flash`` and ``mrvl_uart`` targets.
+        For A7K/8K/CN913x it is used for BLE build and for Armada37x0 it used
+        for ddr_tool build.
 
-        Usage example: MV_DDR_PATH=path/to/mv_ddr
+        Specify path to the full checkout of Marvell mv-ddr-marvell git
+        repository. Checkout must contain also .git subdirectory because
+        mv-ddr build process calls git commands.
 
-        The parameter is optional for A7K/8K/CN913x, when this parameter is not set, the mv_ddr
-        sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
-        is necessary for A37x0.
-
-        For the mv_ddr source location, check the section "Tools and external components installation"
-
-        If MV_DDR_PATH source code is a git snapshot then provide path to the full git
-        repository (including .git subdir) because mv_ddr build process calls git commands.
+        Do not remove any parts of git checkout becuase build process and other
+        applications need them for correct building and version determination.
 
 - CP_NUM
 
@@ -219,14 +221,29 @@
         binary and sys-init code from the WTP directory which sets DDR and CPU
         clocks according to DDR_TOPOLOGY and CLOCKSPRESET options.
 
+        CZ.NIC as part of Turris project released free and open source WTMI
+        application firmware ``wtmi_app.bin`` for all Armada 3720 devices.
+        This firmware includes additional features like access to Hardware
+        Random Number Generator of Armada 3720 SoC which original Marvell's
+        ``fuse.bin`` image does not have.
+
+        CZ.NIC's Armada 3720 Secure Firmware is available at website:
+
+            https://gitlab.nic.cz/turris/mox-boot-builder/
+
 - WTP
 
-        For Armada37x0 only, use this parameter to point to wtptools source code
-        directory, which can be found as a3700_utils.zip in the release. Usage
-        example: ``WTP=/path/to/a3700_utils``
+        For Armada37x0 only.
 
-        If WTP source code is a git snapshot then provide path to the full git
-        repository (including .git subdir) because WTP build process calls git commands.
+        Specify path to the full checkout of Marvell A3700-utils-marvell git
+        repository. Checkout must contain also .git subdirectory because WTP
+        build process calls git commands.
+
+        WTP build process uses also Marvell mv-ddr-marvell git repository
+        specified in MV_DDR_PATH option.
+
+        Do not remove any parts of git checkout becuase build process and other
+        applications need them for correct building and version determination.
 
 - CRYPTOPP_PATH
 
@@ -274,21 +291,25 @@
         CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
 
 Here is full example how to build production release of Marvell firmware image (concatenated
-binary of Marvell secure firmware, TF-A and U-Boot) for EspressoBin board (PLAT=a3700) with
-1GHz CPU (CLOCKSPRESET=CPU_1000_DDR_800) and 1GB DDR4 RAM (DDR_TOPOLOGY=5):
+binary of Marvell's A3720 sys-init, CZ.NIC's Armada 3720 Secure Firmware, TF-A and U-Boot) for
+EspressoBin board (PLAT=a3700) with 1GHz CPU (CLOCKSPRESET=CPU_1000_DDR_800) and
+1GB DDR4 RAM (DDR_TOPOLOGY=5):
 
 .. code:: shell
 
-    > git clone https://review.trustedfirmware.org/TF-A/trusted-firmware-a
-    > git clone https://gitlab.denx.de/u-boot/u-boot.git
+    > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+    > git clone https://source.denx.de/u-boot/u-boot.git
     > git clone https://github.com/weidai11/cryptopp.git
-    > git clone https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git -b master
-    > git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git -b master
+    > git clone https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
+    > git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
+    > git clone https://gitlab.nic.cz/turris/mox-boot-builder.git
     > make -C u-boot CROSS_COMPILE=aarch64-linux-gnu- mvebu_espressobin-88f3720_defconfig u-boot.bin
+    > make -C mox-boot-builder CROSS_CM3=arm-linux-gnueabi- wtmi_app.bin
     > make -C trusted-firmware-a CROSS_COMPILE=aarch64-linux-gnu- CROSS_CM3=arm-linux-gnueabi- \
         USE_COHERENT_MEM=0 PLAT=a3700 CLOCKSPRESET=CPU_1000_DDR_800 DDR_TOPOLOGY=5 \
-        MV_DDR_PATH=$PWD/mv-ddr-marvell/ WTP=$PWD/A3700-utils-marvell/ CRYPTOPP_PATH=$PWD/cryptopp/ \
-        BL33=$PWD/u-boot/u-boot.bin mrvl_flash
+        MV_DDR_PATH=$PWD/mv-ddr-marvell/ WTP=$PWD/A3700-utils-marvell/ \
+        CRYPTOPP_PATH=$PWD/cryptopp/ BL33=$PWD/u-boot/u-boot.bin \
+        WTMI_IMG=$PWD/mox-boot-builder/wtmi_app.bin FIP_ALIGN=0x100 mrvl_flash
 
 Produced Marvell firmware flash image: ``trusted-firmware-a/build/a3700/release/flash-image.bin``
 
diff --git a/docs/plat/mt8195.rst b/docs/plat/mt8195.rst
new file mode 100644
index 0000000..b2aeea2
--- /dev/null
+++ b/docs/plat/mt8195.rst
@@ -0,0 +1,21 @@
+MediaTek 8195
+=============
+
+MediaTek 8195 (MT8195) is a 64-bit ARM SoC introduced by MediaTek in 2021.
+The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
+Cortex-A76 can operate at up to 2.2 GHz.
+Cortex-A55 can operate at up to 2.0 GHz.
+
+Boot Sequence
+-------------
+
+::
+
+    Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
+
+How to Build
+------------
+
+.. code:: shell
+
+    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8195 DEBUG=1 COREBOOT=1
diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst
index 57a363b..3d4c4a4 100644
--- a/docs/plat/xilinx-versal.rst
+++ b/docs/plat/xilinx-versal.rst
@@ -19,6 +19,11 @@
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal VERSAL_PLATFORM=versal_virt bl31
 ```
 
+To build TF-A for JTAG DCC console
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 VERSAL_CONSOLE=dcc
+```
+
 Xilinx Versal platform specific build options
 ---------------------------------------------
 
diff --git a/docs/plat/xilinx-zynqmp.rst b/docs/plat/xilinx-zynqmp.rst
index 5db4488..79c2535 100644
--- a/docs/plat/xilinx-zynqmp.rst
+++ b/docs/plat/xilinx-zynqmp.rst
@@ -22,6 +22,12 @@
 
     make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
 
+To build TF-A for JTAG DCC console:
+
+.. code:: bash
+
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc
+
 ZynqMP platform specific build options
 --------------------------------------
 
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index 15c2b45..c91903a 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -29,6 +29,20 @@
 -  Make commits of logical units. See these general `Git guidelines`_ for
    contributing to a project.
 
+-  Ensure your commit messages comply with the `Conventional Commits`_
+   specification:
+
+   .. code::
+
+       <type>[optional scope]: <description>
+
+       [optional body]
+
+       [optional footer(s)]
+
+   You can use the tooling installed by the optional steps in the
+   :ref:`prerequisites <Prerequisites>` guide to validate this locally.
+
 -  Keep the commits on topic. If you need to fix another bug or make another
    enhancement, please address it on a separate topic branch.
 
@@ -216,6 +230,7 @@
 
 *Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
 
+.. _Conventional Commits: https://www.conventionalcommits.org/en/v1.0.0
 .. _developer.trustedfirmware.org: https://developer.trustedfirmware.org
 .. _review.trustedfirmware.org: https://review.trustedfirmware.org
 .. _issue: https://developer.trustedfirmware.org/project/board/1/
diff --git a/docs/resources/diagrams/FIP_in_a_GPT_image.png b/docs/resources/diagrams/FIP_in_a_GPT_image.png
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+++ b/docs/resources/diagrams/ff-a-spm-sel2.png
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diff --git a/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png b/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png
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diff --git a/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png b/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png
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diff --git a/docs/resources/diagrams/plantuml/tfa_dfd.puml b/docs/resources/diagrams/plantuml/tfa_dfd.puml
new file mode 100644
index 0000000..0007911
--- /dev/null
+++ b/docs/resources/diagrams/plantuml/tfa_dfd.puml
@@ -0,0 +1,66 @@
+/'
+ ' Copyright (c) 2021, Arm Limited. All rights reserved.
+ '
+ ' SPDX-License-Identifier: BSD-3-Clause
+ '/
+
+/'
+TF-A Data Flow Diagram
+'/
+
+@startuml
+digraph tfa_dfd {
+
+    # Arrange nodes from left to right
+    rankdir="LR"
+
+    # Allow arrows to end on cluster boundaries
+    compound=true
+
+    # Default settings for edges and nodes
+    edge [minlen=2 color="#8c1b07"]
+    node [fillcolor="#ffb866" style=filled shape=box fixedsize=true width=1.6 height=0.7]
+
+    # Nodes outside of the trust boundary
+    nsec [label="Non-secure\nClients"]
+    sec [label="Secure\nClients"]
+    dbg [label="Debug & Trace"]
+    logs [label="Logs\n(UART)"]
+    nvm [label="Non-volatile\nMemory"]
+
+    # Trust boundary cluster
+    subgraph cluster_trusted{
+        graph [style=dashed color="#f22430"]
+
+        # HW IPs cluster
+        subgraph cluster_ip{
+            label ="Hardware IPs";
+            graph [style=filled color="#000000" fillcolor="#ffd29e"]
+
+            rank="same"
+            gic [label="GIC" width=1.2 height=0.5]
+            tzc [label="TZ\nController" width=1.2 height=0.5]
+            etc [label="..." shape=none style=none height=0.5]
+        }
+
+        # TF-A cluster
+        subgraph cluster_tfa{
+            label ="TF-A";
+            graph [style=filled color="#000000" fillcolor="#faf9cd"]
+
+            bl1 [label="Boot ROM\n(BL1)" fillcolor="#ddffb3"];
+            bl2 [label="Trusted Boot\nFirmware\n(BL2)" fillcolor="#ddffb3" height=1]
+            bl31 [label="TF-A Runtime\n(BL31)" fillcolor="#ddffb3"]
+        }
+    }
+
+    # Interactions between nodes
+    nvm -> bl31 [lhead=cluster_tfa label="DF1"]
+    logs -> bl31 [dir="back" lhead=cluster_tfa label="DF2"]
+    dbg -> bl2 [dir="both" lhead=cluster_tfa label="DF3"]
+    sec -> bl2 [dir="both" lhead=cluster_tfa label="DF4"]
+    nsec -> bl1 [dir="both" lhead=cluster_tfa, label="DF5"]
+    bl2 ->  tzc [dir="both" ltail=cluster_tfa lhead=cluster_ip label="DF6" minlen=1]
+}
+
+@enduml
diff --git a/docs/threat_model/index.rst b/docs/threat_model/index.rst
new file mode 100644
index 0000000..e8f09b9
--- /dev/null
+++ b/docs/threat_model/index.rst
@@ -0,0 +1,13 @@
+Threat Model
+=============
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents
+   :numbered:
+
+   threat_model
+
+--------------
+
+*Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/threat_model/threat_model.rst b/docs/threat_model/threat_model.rst
new file mode 100644
index 0000000..9cee104
--- /dev/null
+++ b/docs/threat_model/threat_model.rst
@@ -0,0 +1,784 @@
+*****************
+Introduction
+*****************
+Threat modeling is an important part of Secure Development Lifecycle (SDL)
+that helps us identify potential threats and mitigations affecting a system.
+
+This document provides a generic threat model for TF-A firmware. In the
+next sections, we first give a description of the target of evaluation
+using a data flow diagram. Then we provide a list of threats we have
+identified based on the data flow diagram and potential threat mitigations.
+
+************************
+Target of Evaluation
+************************
+In this threat model, the target of evaluation is the Trusted
+Firmware for A-class Processors (TF-A). This includes the boot ROM (BL1),
+the trusted boot firmware (BL2) and the runtime EL3 firmware (BL31) as
+shown on Figure 1. Everything else on Figure 1 is outside of the scope of
+the evaluation.
+
+TF-A can be configured in various ways. In this threat model we consider
+only the most basic configuration. To that end we make the following
+assumptions:
+
+- All TF-A images are run from either ROM or on-chip trusted SRAM. This means
+  TF-A is not vulnerable to an attacker that can probe or tamper with off-chip
+  memory.
+- Trusted boot is enabled. This means an attacker can't boot arbitrary images
+  that are not approved by platform providers.
+- There is no Secure-EL2. We don't consider threats that may come with
+  Secure-EL2 software.
+
+Data Flow Diagram
+======================
+Figure 1 shows a high-level data flow diagram for TF-A. The diagram
+shows a model of the different components of a TF-A-based system and
+their interactions with TF-A. A description of each diagram element
+is given on Table 1. On the diagram, the red broken lines indicate
+trust boundaries. Components outside of the broken lines
+are considered untrusted by TF-A.
+
+.. uml:: ../resources/diagrams/plantuml/tfa_dfd.puml
+  :caption: Figure 1: TF-A Data Flow Diagram
+
+.. table:: Table 1: TF-A Data Flow Diagram Description
+
+  +-----------------+--------------------------------------------------------+
+  | Diagram Element | Description                                            |
+  +=================+========================================================+
+  |       ``DF1``   | | At boot time, images are loaded from non-volatile    |
+  |                 |   memory and verified by TF-A boot firmware. These     |
+  |                 |   images include TF-A BL2 and BL31 images, as well as  |
+  |                 |   other secure and non-secure images.                  |
+  +-----------------+--------------------------------------------------------+
+  |       ``DF2``   | | TF-A log system framework outputs debug messages     |
+  |                 |   over a UART interface.                               |
+  +-----------------+--------------------------------------------------------+
+  |       ``DF3``   | | Debug and trace IP on a platform can allow access    |
+  |                 |   to registers and memory of TF-A.                     |
+  +-----------------+--------------------------------------------------------+
+  |       ``DF4``   | | Secure world software (e.g. trusted OS) interact     |
+  |                 |   with TF-A through SMC call interface and/or shared   |
+  |                 |   memory.                                              |
+  +-----------------+--------------------------------------------------------+
+  |       ``DF5``   | | Non-secure world software (e.g. rich OS) interact    |
+  |                 |   with TF-A through SMC call interface and/or shared   |
+  |                 |   memory.                                              |
+  +-----------------+--------------------------------------------------------+
+  |       ``DF6``   | | This path represents the interaction between TF-A and|
+  |                 |   various hardware IPs such as TrustZone controller    |
+  |                 |   and GIC. At boot time TF-A configures/initializes the|
+  |                 |   IPs and interacts with them at runtime through       |
+  |                 |   interrupts and registers.                            |
+  +-----------------+--------------------------------------------------------+
+
+
+*********************
+Threat Analysis
+*********************
+In this section we identify and provide assessment of potential threats to TF-A
+firmware. The threats are identified for each diagram element on the
+data flow diagram above.
+
+For each threat, we identify the *asset* that is under threat, the
+*threat agent* and the *threat type*. Each threat is given a *risk rating*
+that represents the impact and likelihood of that threat. We also discuss
+potential mitigations.
+
+Assets
+==================
+We have identified the following assets for TF-A:
+
+.. table:: Table 2: TF-A Assets
+
+  +--------------------+---------------------------------------------------+
+  | Asset              | Description                                       |
+  +====================+===================================================+
+  | ``Sensitive Data`` | | These include sensitive data that an attacker   |
+  |                    |   must not be able to tamper with (e.g. the Root  |
+  |                    |   of Trust Public Key) or see (e.g. secure logs,  |
+  |                    |   debugging information such as crash reports).   |
+  +--------------------+---------------------------------------------------+
+  | ``Code Execution`` | | This represents the requirement that the        |
+  |                    |   platform should run only TF-A code approved by  |
+  |                    |   the platform provider.                          |
+  +--------------------+---------------------------------------------------+
+  | ``Availability``   | | This represents the requirement that TF-A       |
+  |                    |   services should always be available for use.    |
+  +--------------------+---------------------------------------------------+
+
+Threat Agents
+=====================
+To understand the attack surface, it is important to identify potential
+attackers, i.e. attack entry points. The following threat agents are
+in scope of this threat model.
+
+.. table:: Table 3: Threat Agents
+
+  +-------------------+-------------------------------------------------------+
+  | Threat Agent      | Description                                           |
+  +===================+=======================================================+
+  |   ``NSCode``      | | Malicious or faulty code running in the Non-secure  |
+  |                   |   world, including NS-EL0 NS-EL1 and NS-EL2 levels    |
+  +-------------------+-------------------------------------------------------+
+  |   ``SecCode``     | | Malicious or faulty code running in the secure      |
+  |                   |   world, including S-EL0 and S-EL1 levels             |
+  +-------------------+-------------------------------------------------------+
+  |   ``AppDebug``    | | Physical attacker using  debug signals to access    |
+  |                   |   TF-A resources                                      |
+  +-------------------+-------------------------------------------------------+
+  | ``PhysicalAccess``| | Physical attacker having access to external device  |
+  |                   |   communication bus and to external flash             |
+  |                   |   communication bus using common hardware             |
+  +-------------------+-------------------------------------------------------+
+
+.. note::
+
+  In this threat model an advanced physical attacker that has the capability
+  to tamper with a hardware (e.g. "rewiring" a chip using a focused
+  ion beam (FIB) workstation or decapsulate the chip using chemicals) is
+  considered out-of-scope.
+
+Threat Types
+========================
+In this threat model we categorize threats using the `STRIDE threat
+analysis technique`_. In this technique a threat is categorized as one
+or more of these types: ``Spoofing``, ``Tampering``, ``Repudiation``,
+``Information disclosure``, ``Denial of service`` or
+``Elevation of privilege``.
+
+Threat Risk Ratings
+========================
+For each threat identified, a risk rating that ranges
+from *informational* to *critical* is given based on the likelihood of the
+threat occuring if a mitigation is not in place, and the impact of the
+threat (i.e. how severe the consequences could be). Table 4 explains each
+rating in terms of score, impact and likelihood.
+
+.. table:: Table 4: Rating and score as applied to impact and likelihood
+
+  +-----------------------+-------------------------+---------------------------+
+  | **Rating (Score)**    | **Impact**              | **Likelihood**            |
+  +=======================+=========================+===========================+
+  | ``Critical (5)``      | | Extreme impact to     | | Threat is almost        |
+  |                       |   entire organization   |   certain to be exploited.|
+  |                       |   if exploited.         |                           |
+  |                       |                         | | Knowledge of the threat |
+  |                       |                         |   and how to exploit it   |
+  |                       |                         |   are in the public       |
+  |                       |                         |   domain.                 |
+  +-----------------------+-------------------------+---------------------------+
+  | ``High (4)``          | | Major impact to entire| | Threat is relatively    |
+  |                       |   organization or single|   easy to detect and      |
+  |                       |   line of business if   |   exploit by an attacker  |
+  |                       |   exploited             |   with little skill.      |
+  +-----------------------+-------------------------+---------------------------+
+  | ``Medium (3)``        | | Noticeable impact to  | | A knowledgeable insider |
+  |                       |   line of business if   |   or expert attacker could|
+  |                       |   exploited.            |   exploit the threat      |
+  |                       |                         |   without much difficulty.|
+  +-----------------------+-------------------------+---------------------------+
+  | ``Low (2)``           | | Minor damage if       | | Exploiting the threat   |
+  |                       |   exploited or could    |   would require           |
+  |                       |   be used in conjunction|   considerable expertise  |
+  |                       |   with other            |   and resources           |
+  |                       |   vulnerabilities to    |                           |
+  |                       |   perform a more serious|                           |
+  |                       |   attack                |                           |
+  +-----------------------+-------------------------+---------------------------+
+  | ``Informational (1)`` | | Poor programming      | | Threat is not likely    |
+  |                       |   practice or poor      |   to be exploited on its  |
+  |                       |   design decision that  |   own, but may be used to |
+  |                       |   may not represent an  |   gain information for    |
+  |                       |   immediate risk on its |   launching another       |
+  |                       |   own, but may have     |   attack                  |
+  |                       |   security implications |                           |
+  |                       |   if multiplied and/or  |                           |
+  |                       |   combined with other   |                           |
+  |                       |   threats.              |                           |
+  +-----------------------+-------------------------+---------------------------+
+
+Aggregate risk scores are assigned to identified threats;
+specifically, the impact score multiplied by the likelihood score.
+For example, a threat with high likelihood and low impact would have an
+aggregate risk score of eight (8); that is, four (4) for high likelihood
+multiplied by two (2) for low impact. The aggregate risk score determines
+the finding's overall risk level, as shown in the following table.
+
+.. table:: Table 5: Overall risk levels and corresponding aggregate scores
+
+  +---------------------+-----------------------------------+
+  | Overall Risk Level  | Aggregate Risk Score              |
+  |                     | (Impact multiplied by Likelihood) |
+  +=====================+===================================+
+  | Critical            | 20–25                             |
+  +---------------------+-----------------------------------+
+  | High                | 12–19                             |
+  +---------------------+-----------------------------------+
+  | Medium              | 6–11                              |
+  +---------------------+-----------------------------------+
+  | Low                 | 2–5                               |
+  +---------------------+-----------------------------------+
+  | Informational       | 1                                 |
+  +---------------------+-----------------------------------+
+
+The likelihood and impact of a threat depends on the
+target environment in which TF-A is running. For example, attacks
+that require physical access are unlikely in server environments while
+they are more common in Internet of Things(IoT) environments.
+In this threat model we consider three target environments:
+``Internet of Things(IoT)``, ``Mobile`` and ``Server``.
+
+Threat Assessment
+============================
+The following threats were identified by applying STRIDE analysis on
+each diagram element of the data flow diagram.
+
++------------------------+----------------------------------------------------+
+| ID                     | 01                                                 |
++========================+====================================================+
+| ``Threat``             | | **An attacker can mangle firmware images to      |
+|                        |   execute arbitrary code**                         |
+|                        |                                                    |
+|                        | | Some TF-A images are loaded from external        |
+|                        |   storage. It is possible for an attacker to access|
+|                        |   the external flash memory and change its contents|
+|                        |   physically, through the Rich OS, or using the    |
+|                        |   updating mechanism to modify the non-volatile    |
+|                        |   images to execute arbitrary code.                |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements``   | DF1, DF4, DF5                                      |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A        | BL2, BL31                                          |
+| Components``           |                                                    |
++------------------------+----------------------------------------------------+
+| ``Assets``             | Code Execution                                     |
++------------------------+----------------------------------------------------+
+| ``Threat Agent``       | PhysicalAccess, NSCode, SecCode                    |
++------------------------+----------------------------------------------------+
+| ``Threat Type``        | Tampering, Elevation of Privilege                  |
++------------------------+------------------+-----------------+---------------+
+| ``Application``        | ``Server``       | ``IoT``         | ``Mobile``    |
++------------------------+------------------+-----------------+---------------+
+| ``Impact``             | Critical (5)     | Critical (5)    | Critical (5)  |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood``         | Critical (5)     | Critical (5)    | Critical (5)  |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating``  | Critical (25)    | Critical (25)   | Critical (25) |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations``        | | TF-A implements the `Trusted Board Boot (TBB)`_  |
+|                        |   feature which prevents malicious firmware from   |
+|                        |   running on the platform by authenticating all    |
+|                        |   firmware images. In addition to this, the TF-A   |
+|                        |   boot firmware performs extra checks on           |
+|                        |   unauthenticated data, such as FIP metadata, prior|
+|                        |   to use.                                          |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID                     | 02                                                 |
++========================+====================================================+
+| ``Threat``             | | **An attacker may attempt to boot outdated,      |
+|                        |   potentially vulnerable firmware image**          |
+|                        |                                                    |
+|                        | | When updating firmware, an attacker may attempt  |
+|                        |   to rollback to an older version that has unfixed |
+|                        |   vulnerabilities.                                 |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements``   | DF1, DF4, DF5                                      |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A        | BL2, BL31                                          |
+| Components``           |                                                    |
++------------------------+----------------------------------------------------+
+| ``Assets``             | Code Execution                                     |
++------------------------+----------------------------------------------------+
+| ``Threat Agent``       | PhysicalAccess, NSCode, SecCode                    |
++------------------------+----------------------------------------------------+
+| ``Threat Type``        | Tampering                                          |
++------------------------+------------------+-----------------+---------------+
+| ``Application``        | ``Server``       | ``IoT``         | ``Mobile``    |
++------------------------+------------------+-----------------+---------------+
+| ``Impact``             | Critical (5)     | Critical (5)    | Critical (5)  |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood``         | Critical (5)     | Critical (5)    | Critical (5)  |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating``  | Critical (25)    | Critical (25)   | Critical (25) |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations``        | | TF-A supports anti-rollback protection using     |
+|                        |   non-volatile counters (NV counters) as required  |
+|                        |   by `TBBR-Client specification`_. After a firmware|
+|                        |   image is validated, the image revision number    |
+|                        |   taken from a certificate extension field is      |
+|                        |   compared with the corresponding NV counter stored|
+|                        |   in hardware to make sure the new counter value is|
+|                        |   larger or equal to the current counter value.    |
+|                        |   Platforms must implement this protection using   |
+|                        |   platform specific hardware NV counters.          |
++------------------------+----------------------------------------------------+
+
++------------------------+-------------------------------------------------------+
+| ID                     | 03                                                    |
++========================+=======================================================+
+| ``Threat``             | |  **An attacker can use Time-of-Check-Time-of-Use    |
+|                        |   (TOCTOU) attack to bypass image authentication      |
+|                        |   during the boot process**                           |
+|                        |                                                       |
+|                        | | Time-of-Check-Time-of-Use (TOCTOU) threats occur    |
+|                        |   when the security check is produced before the time |
+|                        |   the resource is accessed. If an attacker is sitting |
+|                        |   in the middle of the off-chip images, they could    |
+|                        |   change the binary containing executable code right  |
+|                        |   after the integrity and authentication check has    |
+|                        |   been performed.                                     |
++------------------------+-------------------------------------------------------+
+| ``Diagram Elements``   | DF1                                                   |
++------------------------+-------------------------------------------------------+
+| ``Affected TF-A        | BL1, BL2                                              |
+| Components``           |                                                       |
++------------------------+-------------------------------------------------------+
+| ``Assets``             | Code Execution, Sensitive Data                        |
++------------------------+-------------------------------------------------------+
+| ``Threat Agent``       | PhysicalAccess                                        |
++------------------------+-------------------------------------------------------+
+| ``Threat Type``        | Elevation of Privilege                                |
++------------------------+---------------------+-----------------+---------------+
+| ``Application``        | ``Server``          | ``IoT``         | ``Mobile``    |
++------------------------+---------------------+-----------------+---------------+
+| ``Impact``             | N/A                 | Critical (5)    | Critical (5)  |
++------------------------+---------------------+-----------------+---------------+
+| ``Likelihood``         | N/A                 | Medium (3)      | Medium (3)    |
++------------------------+---------------------+-----------------+---------------+
+| ``Total Risk Rating``  | N/A                 | High (15)       | High (15)     |
++------------------------+---------------------+-----------------+---------------+
+| ``Mitigations``        | | TF-A boot firmware copies image to on-chip          |
+|                        |   memory before authenticating an image.              |
++------------------------+-------------------------------------------------------+
+
++------------------------+-------------------------------------------------------+
+| ID                     | 04                                                    |
++========================+=======================================================+
+| ``Threat``             | | **An attacker with physical access can execute      |
+|                        |   arbitrary image by bypassing the signature          |
+|                        |   verification stage using glitching techniques**     |
+|                        |                                                       |
+|                        | | Glitching (Fault injection) attacks attempt to put  |
+|                        |   a hardware into a undefined state by manipulating an|
+|                        |   environmental variable such as power supply.        |
+|                        |                                                       |
+|                        | | TF-A relies on a chain of trust that starts with the|
+|                        |   ROTPK, which is the key stored inside the chip and  |
+|                        |   the root of all validation processes. If an attacker|
+|                        |   can break this chain of trust, they could execute   |
+|                        |   arbitrary code on the device. This could be         |
+|                        |   achieved with physical access to the device by      |
+|                        |   attacking the normal execution flow of the          |
+|                        |   process using glitching techniques that target      |
+|                        |   points where the image is validated against the     |
+|                        |   signature.                                          |
++------------------------+-------------------------------------------------------+
+| ``Diagram Elements``   | DF1                                                   |
++------------------------+-------------------------------------------------------+
+| ``Affected TF-A        | BL1, BL2                                              |
+| Components``           |                                                       |
++------------------------+-------------------------------------------------------+
+| ``Assets``             | Code Execution                                        |
++------------------------+-------------------------------------------------------+
+| ``Threat Agent``       | PhysicalAccess                                        |
++------------------------+-------------------------------------------------------+
+| ``Threat Type``        | Tampering, Elevation of Privilege                     |
++------------------------+---------------------+-----------------+---------------+
+| ``Application``        | ``Server``          | ``IoT``         | ``Mobile``    |
++------------------------+---------------------+-----------------+---------------+
+| ``Impact``             | N/A                 | Critical (5)    | Critical (5)  |
++------------------------+---------------------+-----------------+---------------+
+| ``Likelihood``         | N/A                 | Medium (3)      | Medium (3)    |
++------------------------+---------------------+-----------------+---------------+
+| ``Total Risk Rating``  | N/A                 | High (15)       | High (15)     |
++------------------------+---------------------+-----------------+---------------+
+| ``Mitigations``        | | The most effective mitigation is adding glitching   |
+|                        |   detection and mitigation circuit at the hardware    |
+|                        |   level. However, software techniques,                |
+|                        |   such as adding redundant checks when performing     |
+|                        |   conditional branches that are security sensitive,   |
+|                        |   can be used to harden TF-A against such attacks.    |
+|                        |   **At the moment TF-A doesn't implement such         |
+|                        |   mitigations.**                                      |
++------------------------+-------------------------------------------------------+
+
++------------------------+---------------------------------------------------+
+| ID                     | 05                                                |
++========================+===================================================+
+| ``Threat``             | | **Information leak via UART logs such as        |
+|                        |   crashes**                                       |
+|                        |                                                   |
+|                        | | During the development stages of software it is |
+|                        |   common to include crash reports with detailed   |
+|                        |   information of the CPU state including current  |
+|                        |   values of the registers, privilege level and    |
+|                        |   stack dumps. This information is useful when    |
+|                        |   debugging problems before releasing the         |
+|                        |   production version, but it could be used by an  |
+|                        |   attacker to develop a working exploit if left   |
+|                        |   in the production version.                      |
++------------------------+---------------------------------------------------+
+| ``Diagram Elements``   | DF2                                               |
++------------------------+---------------------------------------------------+
+| ``Affected TF-A        | BL1, BL2, BL31                                    |
+| Components``           |                                                   |
++------------------------+---------------------------------------------------+
+| ``Assets``             | Sensitive Data                                    |
++------------------------+---------------------------------------------------+
+| ``Threat Agent``       | AppDebug                                          |
++------------------------+---------------------------------------------------+
+| ``Threat Type``        | Information Disclosure                            |
++------------------------+------------------+----------------+---------------+
+| ``Application``        | ``Server``       | ``IoT``        | ``Mobile``    |
++------------------------+------------------+----------------+---------------+
+| ``Impact``             | N/A              | Low (2)        | Low (2)       |
++------------------------+------------------+----------------+---------------+
+| ``Likelihood``         | N/A              | High (4)       | High (4)      |
++------------------------+------------------+----------------+---------------+
+| ``Total Risk Rating``  | N/A              | Medium (8)     | Medium (8)    |
++------------------------+------------------+----------------+---------------+
+| ``Mitigations``        | | In TF-A, crash reporting is only enabled for    |
+|                        |   debug builds by default. Alternatively, the log |
+|                        |   level can be tuned at build time (from verbose  |
+|                        |   to no output at all), independently of the      |
+|                        |   build type.                                     |
++------------------------+---------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID                     | 06                                                 |
++========================+====================================================+
+| ``Threat``             | | **An attacker can read sensitive data and        |
+|                        |   execute arbitrary code through the external      |
+|                        |   debug and trace interface**                      |
+|                        |                                                    |
+|                        | | Arm processors include hardware-assisted debug   |
+|                        |   and trace features that can be controlled without|
+|                        |   the need for software operating on the platform. |
+|                        |   If left enabled without authentication, this     |
+|                        |   feature can be used by an attacker to inspect and|
+|                        |   modify TF-A registers and memory allowing the    |
+|                        |   attacker to read sensitive data and execute      |
+|                        |   arbitrary code.                                  |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements``   | DF3                                                |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A        | BL1, BL2, BL31                                     |
+| Components``           |                                                    |
++------------------------+----------------------------------------------------+
+| ``Assets``             | Code Execution, Sensitive Data                     |
++------------------------+----------------------------------------------------+
+| ``Threat Agent``       | AppDebug                                           |
++------------------------+----------------------------------------------------+
+| ``Threat Type``        | Tampering, Information Disclosure,                 |
+|                        | Elevation of privilege                             |
++------------------------+------------------+---------------+-----------------+
+| ``Application``        | ``Server``       | ``IoT``       | ``Mobile``      |
++------------------------+------------------+---------------+-----------------+
+| ``Impact``             | N/A              | High (4)      | High (4)        |
++------------------------+------------------+---------------+-----------------+
+| ``Likelihood``         | N/A              | Critical (5)  | Critical (5)    |
++------------------------+------------------+---------------+-----------------+
+| ``Total Risk Rating``  | N/A              | Critical (20) | Critical (20)   |
++------------------------+------------------+---------------+-----------------+
+| ``Mitigations``        | | Configuration of debug and trace capabilities is |
+|                        |   platform specific. Therefore, platforms must     |
+|                        |   disable the debug and trace capability for       |
+|                        |   production releases or enable proper debug       |
+|                        |   authentication as recommended by [`DEN0034`_].   |
++------------------------+----------------------------------------------------+
+
++------------------------+------------------------------------------------------+
+| ID                     | 07                                                   |
++========================+======================================================+
+| ``Threat``             | | **An attacker can perform a denial-of-service      |
+|                        |   attack by using a broken SMC call that causes the  |
+|                        |   system to reboot or enter into unknown state.**    |
+|                        |                                                      |
+|                        | | Secure and non-secure clients access TF-A services |
+|                        |   through SMC calls. Malicious code can attempt to   |
+|                        |   place the TF-A runtime into an inconsistent state  |
+|                        |   by calling unimplemented SMC call or by passing    |
+|                        |   invalid arguments.                                 |
++------------------------+------------------------------------------------------+
+| ``Diagram Elements``   | DF4, DF5                                             |
++------------------------+------------------------------------------------------+
+| ``Affected TF-A        | BL31                                                 |
+| Components``           |                                                      |
++------------------------+------------------------------------------------------+
+| ``Assets``             | Availability                                         |
++------------------------+------------------------------------------------------+
+| ``Threat Agent``       | NSCode, SecCode                                      |
++------------------------+------------------------------------------------------+
+| ``Threat Type``        | Denial of Service                                    |
++------------------------+-------------------+----------------+-----------------+
+| ``Application``        | ``Server``        | ``IoT``        | ``Mobile``      |
++------------------------+-------------------+----------------+-----------------+
+| ``Impact``             | Medium (3)        | Medium (3)     | Medium (3)      |
++------------------------+-------------------+----------------+-----------------+
+| ``Likelihood``         | High (4)          | High (4)       | High (4)        |
++------------------------+-------------------+----------------+-----------------+
+| ``Total Risk Rating``  | High (12)         | High (12)      | High (12)       |
++------------------------+-------------------+----------------+-----------------+
+| ``Mitigations``        | | The generic TF-A code validates SMC function ids   |
+|                        |   and arguments before using them.                   |
+|                        |   Platforms that implement SiP services must also    |
+|                        |   validate SMC call arguments.                       |
++------------------------+------------------------------------------------------+
+
++------------------------+------------------------------------------------------+
+| ID                     | 08                                                   |
++========================+======================================================+
+| ``Threat``             | | **Memory corruption due to memory overflows and    |
+|                        |   lack of boundary checking when accessing resources |
+|                        |   could allow an attacker to execute arbitrary code, |
+|                        |   modify some state variable to change the normal    |
+|                        |   flow of the program, or leak sensitive             |
+|                        |   information**                                      |
+|                        |                                                      |
+|                        | | Like in other software, the Trusted Firmware has   |
+|                        |   multiple points where memory corruption security   |
+|                        |   errors can arise. Memory corruption is a dangerous |
+|                        |   security issue since it could allow an attacker    |
+|                        |   to execute arbitrary code, modify some state       |
+|                        |   variable to change the normal flow of the program, |
+|                        |   or leak sensitive information.                     |
+|                        |                                                      |
+|                        | | Some of the errors include integer overflow,       |
+|                        |   buffer overflow, incorrect array boundary checks,  |
+|                        |   and incorrect error management.                    |
+|                        |   Improper use of asserts instead of proper input    |
+|                        |   validations might also result in these kinds of    |
+|                        |   errors in release builds.                          |
++------------------------+------------------------------------------------------+
+| ``Diagram Elements``   | DF4, DF5                                             |
++------------------------+------------------------------------------------------+
+| ``Affected TF-A        | BL1, BL2, BL31                                       |
+| Components``           |                                                      |
++------------------------+------------------------------------------------------+
+| ``Assets``             | Code Execution, Sensitive Data                       |
++------------------------+------------------------------------------------------+
+| ``Threat Agent``       | NSCode, SecCode                                      |
++------------------------+------------------------------------------------------+
+| ``Threat Type``        | Tampering, Information Disclosure,                   |
+|                        | Elevation of Privilege                               |
++------------------------+-------------------+-----------------+----------------+
+| ``Application``        | ``Server``        | ``IoT``         | ``Mobile``     |
++------------------------+-------------------+-----------------+----------------+
+| ``Impact``             | Critical (5)      | Critical (5)    | Critical (5)   |
++------------------------+-------------------+-----------------+----------------+
+| ``Likelihood``         | Medium (3         | Medium (3)      | Medium (3)     |
++------------------------+-------------------+-----------------+----------------+
+| ``Total Risk Rating``  | High (15)         | High (15)       | High (15)      |
++------------------------+-------------------+-----------------+----------------+
+| ``Mitigations``        | | TF-A uses a combination of manual code reviews and |
+|                        |   automated program analysis and testing to detect   |
+|                        |   and fix memory corruption bugs. All TF-A code      |
+|                        |   including platform code go through manual code     |
+|                        |   reviews. Additionally, static code analysis is     |
+|                        |   performed using Coverity Scan on all TF-A code.    |
+|                        |   The code is also tested  with                      |
+|                        |   `Trusted Firmware-A Tests`_ on Juno and FVP        |
+|                        |   platforms.                                         |
+|                        |                                                      |
+|                        | | Data received from normal world, such as addresses |
+|                        |   and sizes identifying memory regions, are          |
+|                        |   sanitized before being used. These security checks |
+|                        |   make sure that the normal world software does not  |
+|                        |   access memory beyond its limit.                    |
+|                        |                                                      |
+|                        | | By default *asserts* are only used to check for    |
+|                        |   programming errors in debug builds. Other types of |
+|                        |   errors are handled through condition checks that   |
+|                        |   remain enabled in release builds. See              |
+|                        |   `TF-A error handling policy`_. TF-A provides an    |
+|                        |   option to use *asserts* in release builds, however |
+|                        |   we recommend using proper runtime checks instead   |
+|                        |   of relying on asserts in release builds.           |
++------------------------+------------------------------------------------------+
+
++------------------------+------------------------------------------------------+
+| ID                     | 09                                                   |
++========================+======================================================+
+| ``Threat``             | | **Improperly handled SMC calls can leak register   |
+|                        |   contents**                                         |
+|                        |                                                      |
+|                        | | When switching between secure and non-secure       |
+|                        |   states, register contents of Secure world or       |
+|                        |   register contents of other normal world clients    |
+|                        |   can be leaked.                                     |
++------------------------+------------------------------------------------------+
+| ``Diagram Elements``   | DF5                                                  |
++------------------------+------------------------------------------------------+
+| ``Affected TF-A        | BL31                                                 |
+| Components``           |                                                      |
++------------------------+------------------------------------------------------+
+| ``Assets``             | Sensitive Data                                       |
++------------------------+------------------------------------------------------+
+| ``Threat Agent``       | NSCode                                               |
++------------------------+------------------------------------------------------+
+| ``Threat Type``        | Information Disclosure                               |
++------------------------+-------------------+----------------+-----------------+
+| ``Application``        | ``Server``        | ``IoT``        | ``Mobile``      |
++------------------------+-------------------+----------------+-----------------+
+| ``Impact``             | Medium (3)        | Medium (3)     | Medium (3)      |
++------------------------+-------------------+----------------+-----------------+
+| ``Likelihood``         | High (4)          | High (4)       | High (4)        |
++------------------------+-------------------+----------------+-----------------+
+| ``Total Risk Rating``  | High (12)         | High (12)      | High (12)       |
++------------------------+-------------------+----------------+-----------------+
+| ``Mitigations``        | | TF-A saves and restores registers                  |
+|                        |   by default when switching contexts. Build options  |
+|                        |   are also provided to save/restore additional       |
+|                        |   registers such as floating-point registers.        |
++------------------------+------------------------------------------------------+
+
++------------------------+-----------------------------------------------------+
+| ID                     | 10                                                  |
++========================+=====================================================+
+| ``Threat``             | | **SMC calls can leak sensitive information from   |
+|                        |   TF-A memory via microarchitectural side channels**|
+|                        |                                                     |
+|                        | | Microarchitectural side-channel attacks such as   |
+|                        |   `Spectre`_ can be used to leak data across        |
+|                        |   security boundaries. An attacker might attempt to |
+|                        |   use this kind of attack to leak sensitive         |
+|                        |   data from TF-A memory.                            |
++------------------------+-----------------------------------------------------+
+| ``Diagram Elements``   | DF4, DF5                                            |
++------------------------+-----------------------------------------------------+
+| ``Affected TF-A        | BL31                                                |
+| Components``           |                                                     |
++------------------------+-----------------------------------------------------+
+| ``Assets``             | Sensitive Data                                      |
++------------------------+-----------------------------------------------------+
+| ``Threat Agent``       | SecCode, NSCode                                     |
++------------------------+-----------------------------------------------------+
+| ``Threat Type``        | Information Disclosure                              |
++------------------------+-------------------+----------------+----------------+
+| ``Application``        | ``Server``        | ``IoT``        | ``Mobile``     |
++------------------------+-------------------+----------------+----------------+
+| ``Impact``             | Medium (3)        | Medium (3)     | Medium (3)     |
++------------------------+-------------------+----------------+----------------+
+| ``Likelihood``         | Medium (3)        | Medium (3)     | Medium (3)     |
++------------------------+-------------------+----------------+----------------+
+| ``Total Risk Rating``  | Medium (9)        | Medium (9)     | Medium (9)     |
++------------------------+-------------------+----------------+----------------+
+| ``Mitigations``        | | TF-A implements software mitigations for Spectre  |
+|                        |   type attacks as recommended by `Cache Speculation |
+|                        |   Side-channels`_ for the generic code. SiPs should |
+|                        |   implement similar mitigations for code that is    |
+|                        |   deemed to be vulnerable to such attacks.          |
++------------------------+-----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID                     | 11                                                 |
++========================+====================================================+
+| ``Threat``             | | **Misconfiguration of the Memory Management Unit |
+|                        |   (MMU) may allow a normal world software to       |
+|                        |   access sensitive data or execute arbitrary       |
+|                        |   code**                                           |
+|                        |                                                    |
+|                        | | A misconfiguration of the MMU could              |
+|                        |   lead to an open door for software running in the |
+|                        |   normal world to access sensitive data or even    |
+|                        |   execute code if the proper security mechanisms   |
+|                        |   are not in place.                                |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements``   | DF5, DF6                                           |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A        | BL1, BL2, BL31                                     |
+| Components``           |                                                    |
++------------------------+----------------------------------------------------+
+| ``Assets``             | Sensitive Data, Code execution                     |
++------------------------+----------------------------------------------------+
+| ``Threat Agent``       | NSCode                                             |
++------------------------+----------------------------------------------------+
+| ``Threat Type``        | Information Disclosure, Elevation of Privilege     |
++------------------------+-----------------+-----------------+----------------+
+| ``Application``        | ``Server``      | ``IoT``         | ``Mobile``     |
++------------------------+-----------------+-----------------+----------------+
+| ``Impact``             | Critical (5)    | Critical (5)    | Critical (5)   |
++------------------------+-----------------+-----------------+----------------+
+| ``Likelihood``         | High (4)        | High (4)        | High (4)       |
++------------------------+-----------------+-----------------+----------------+
+| ``Total Risk Rating``  | Critical (20)   | Critical (20)   | Critical (20)  |
++------------------------+-----------------+-----------------+----------------+
+| ``Mitigations``        | | In TF-A, configuration of the MMU is done        |
+|                        |   through a translation tables library. The        |
+|                        |   library provides APIs to define memory regions   |
+|                        |   and assign attributes including memory types and |
+|                        |   access permissions. Memory configurations are    |
+|                        |   platform specific, therefore platforms need make |
+|                        |   sure the correct attributes are assigned to      |
+|                        |   memory regions. When assigning access            |
+|                        |   permissions, principle of least privilege ought  |
+|                        |   to be enforced, i.e. we should not grant more    |
+|                        |   privileges than strictly needed, e.g. code       |
+|                        |   should be read-only executable, RO data should   |
+|                        |   be read-only XN, and so on.                      |
++------------------------+----------------------------------------------------+
+
++------------------------+-----------------------------------------------------+
+| ID                     | 12                                                  |
++========================+=====================================================+
+| ``Threat``             | | **Incorrect configuration of Performance Monitor  |
+|                        |   Unit (PMU) counters can allow an attacker to      |
+|                        |   mount side-channel attacks using information      |
+|                        |   exposed by the counters**                         |
+|                        |                                                     |
+|                        | | Non-secure software can configure PMU registers   |
+|                        |   to count events at any exception level and in     |
+|                        |   both Secure and Non-secure states. This allows    |
+|                        |   a Non-secure software (or a lower-level Secure    |
+|                        |   software) to potentially  carry out               |
+|                        |   side-channel timing attacks against TF-A.         |
++------------------------+-----------------------------------------------------+
+| ``Diagram Elements``   | DF5, DF6                                            |
++------------------------+-----------------------------------------------------+
+| ``Affected TF-A        | BL31                                                |
+| Components``           |                                                     |
++------------------------+-----------------------------------------------------+
+| ``Assets``             | Sensitive Data                                      |
++------------------------+-----------------------------------------------------+
+| ``Threat Agent``       | NSCode                                              |
++------------------------+-----------------------------------------------------+
+| ``Threat Type``        | Information Disclosure                              |
++------------------------+-------------------+----------------+----------------+
+| ``Impact``             | Medium (3)        | Medium (3)     | Medium (3)     |
++------------------------+-------------------+----------------+----------------+
+| ``Likelihood``         | Low (2)           | Low (2)        | Low (2)        |
++------------------------+-------------------+----------------+----------------+
+| ``Total Risk Rating``  | Medium (6)        | Medium (6)     | Medium (6)     |
++------------------------+-------------------+----------------+----------------+
+| ``Mitigations``        | | TF-A follows mitigation strategies as described   |
+|                        |   in `Secure Development Guidelines`_. General      |
+|                        |   events and cycle counting in the Secure world is  |
+|                        |   prohibited by default when applicable. However,   |
+|                        |   on some implementations (e.g. PMUv3) Secure world |
+|                        |   event counting depends on external debug interface|
+|                        |   signals, i.e. Secure world event counting is      |
+|                        |   enabled if external debug is enabled.             |
+|                        |   Configuration of debug signals is platform        |
+|                        |   specific, therefore platforms need to make sure   |
+|                        |   that external debug is disabled in production or  |
+|                        |   proper debug authentication is in place.          |
++------------------------+-----------------------------------------------------+
+
+--------------
+
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
+
+
+.. _STRIDE threat analysis technique: https://docs.microsoft.com/en-us/azure/security/develop/threat-modeling-tool-threats#stride-model
+.. _DEN0034: https://developer.arm.com/documentation/den0034/latest
+.. _Cache Speculation Side-channels: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
+.. _Spectre: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
+.. _TBBR-Client specification: https://developer.arm.com/documentation/den0006/d/
+.. _Trusted Board Boot (TBB): https://trustedfirmware-a.readthedocs.io/en/latest/design/trusted-board-boot.html
+.. _TF-A error handling policy: https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#error-handling-and-robustness
+.. _Secure Development Guidelines: https://trustedfirmware-a.readthedocs.io/en/latest/process/security-hardening.html#secure-development-guidelines
+.. _Trusted Firmware-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/about/
\ No newline at end of file
diff --git a/drivers/arm/css/scmi/scmi_common.c b/drivers/arm/css/scmi/scmi_common.c
index 5b3724a..ec749fb 100644
--- a/drivers/arm/css/scmi/scmi_common.c
+++ b/drivers/arm/css/scmi/scmi_common.c
@@ -173,12 +173,12 @@
 
 	ret = scmi_proto_version(ch, SCMI_PWR_DMN_PROTO_ID, &version);
 	if (ret != SCMI_E_SUCCESS) {
-		WARN("SCMI power domain protocol version message failed");
+		WARN("SCMI power domain protocol version message failed\n");
 		goto error;
 	}
 
 	if (!is_scmi_version_compatible(SCMI_PWR_DMN_PROTO_VER, version)) {
-		WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x",
+		WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x\n",
 			version, SCMI_PWR_DMN_PROTO_VER);
 		goto error;
 	}
@@ -187,12 +187,12 @@
 
 	ret = scmi_proto_version(ch, SCMI_SYS_PWR_PROTO_ID, &version);
 	if ((ret != SCMI_E_SUCCESS)) {
-		WARN("SCMI system power protocol version message failed");
+		WARN("SCMI system power protocol version message failed\n");
 		goto error;
 	}
 
 	if (!is_scmi_version_compatible(SCMI_SYS_PWR_PROTO_VER, version)) {
-		WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x",
+		WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x\n",
 			version, SCMI_SYS_PWR_PROTO_VER);
 		goto error;
 	}
diff --git a/drivers/arm/dcc/dcc_console.c b/drivers/arm/dcc/dcc_console.c
new file mode 100644
index 0000000..0b7e541
--- /dev/null
+++ b/drivers/arm/dcc/dcc_console.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2015-2021, Xilinx Inc.
+ * Written by Michal Simek.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <errno.h>
+#include <stddef.h>
+#include <arch_helpers.h>
+#include <drivers/arm/dcc.h>
+#include <drivers/console.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+/* DCC Status Bits */
+#define DCC_STATUS_RX		BIT(30)
+#define DCC_STATUS_TX		BIT(29)
+#define TIMEOUT_COUNT_US	U(0x10624)
+
+struct dcc_console {
+	struct console console;
+};
+
+static inline uint32_t __dcc_getstatus(void)
+{
+	return read_mdccsr_el0();
+}
+
+static inline char __dcc_getchar(void)
+{
+	char c;
+
+	c = read_dbgdtrrx_el0();
+
+	return c;
+}
+
+static inline void __dcc_putchar(char c)
+{
+	/*
+	 * The typecast is to make absolutely certain that 'c' is
+	 * zero-extended.
+	 */
+	write_dbgdtrtx_el0((unsigned char)c);
+}
+
+static int32_t dcc_status_timeout(uint32_t mask)
+{
+	const unsigned int timeout_count = TIMEOUT_COUNT_US;
+	uint64_t timeout;
+	unsigned int status;
+
+	timeout = timeout_init_us(timeout_count);
+
+	do {
+		status = (__dcc_getstatus() & mask);
+		if (timeout_elapsed(timeout)) {
+			return -ETIMEDOUT;
+		}
+	} while ((status != 0U));
+
+	return 0;
+}
+
+static int32_t dcc_console_putc(int32_t ch, struct console *console)
+{
+	unsigned int status;
+
+	status = dcc_status_timeout(DCC_STATUS_TX);
+	if (status != 0U) {
+		return status;
+	}
+	__dcc_putchar(ch);
+
+	return ch;
+}
+
+static int32_t dcc_console_getc(struct console *console)
+{
+	unsigned int status;
+
+	status = dcc_status_timeout(DCC_STATUS_RX);
+	if (status != 0U) {
+		return status;
+	}
+
+	return __dcc_getchar();
+}
+
+int32_t dcc_console_init(unsigned long base_addr, uint32_t uart_clk,
+		      uint32_t baud_rate)
+{
+	return 0; /* No init needed */
+}
+
+/**
+ * dcc_console_flush() - Function to force a write of all buffered data
+ *		          that hasn't been output.
+ * @console		Console struct
+ *
+ */
+static void dcc_console_flush(struct console *console)
+{
+	unsigned int status;
+
+	status = dcc_status_timeout(DCC_STATUS_TX);
+	if (status != 0U) {
+		return;
+	}
+}
+
+static struct dcc_console dcc_console = {
+	.console = {
+		.flags = CONSOLE_FLAG_BOOT |
+			CONSOLE_FLAG_RUNTIME,
+		.putc = dcc_console_putc,
+		.getc = dcc_console_getc,
+		.flush = dcc_console_flush,
+	},
+};
+
+int console_dcc_register(void)
+{
+	return console_register(&dcc_console.console);
+}
diff --git a/drivers/arm/ethosn/ethosn_smc.c b/drivers/arm/ethosn/ethosn_smc.c
new file mode 100644
index 0000000..299d07c
--- /dev/null
+++ b/drivers/arm/ethosn/ethosn_smc.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <drivers/arm/ethosn.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <plat/arm/common/fconf_ethosn_getter.h>
+
+/* Arm Ethos-N NPU (NPU) status */
+#define ETHOSN_STATUS \
+	FCONF_GET_PROPERTY(hw_config, ethosn_config, status)
+
+/* Number of NPU cores available */
+#define ETHOSN_NUM_CORES \
+	FCONF_GET_PROPERTY(hw_config, ethosn_config, num_cores)
+
+/* Address to an NPU core  */
+#define ETHOSN_CORE_ADDR(core_idx) \
+	FCONF_GET_PROPERTY(hw_config, ethosn_core_addr, core_idx)
+
+/* NPU core sec registry address */
+#define ETHOSN_CORE_SEC_REG(core_addr, reg_offset) \
+	(core_addr + reg_offset)
+
+/* Reset timeout in us */
+#define ETHOSN_RESET_TIMEOUT_US		U(10 * 1000 * 1000)
+#define ETHOSN_RESET_WAIT_US		U(1)
+
+#define SEC_DEL_REG			U(0x0004)
+#define SEC_DEL_VAL			U(0x81C)
+#define SEC_DEL_EXCC_MASK		U(0x20)
+
+#define SEC_SECCTLR_REG			U(0x0010)
+#define SEC_SECCTLR_VAL			U(0x3)
+
+#define SEC_DEL_MMUSID_REG		U(0x2008)
+#define SEC_DEL_MMUSID_VAL		U(0x3FFFF)
+
+#define SEC_DEL_ADDR_EXT_REG		U(0x201C)
+#define SEC_DEL_ADDR_EXT_VAL		U(0x15)
+
+#define SEC_SYSCTRL0_REG		U(0x0018)
+#define SEC_SYSCTRL0_SOFT_RESET		U(3U << 29)
+#define SEC_SYSCTRL0_HARD_RESET		U(1U << 31)
+
+static void ethosn_delegate_to_ns(uintptr_t core_addr)
+{
+	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SECCTLR_REG),
+			SEC_SECCTLR_VAL);
+
+	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG),
+			SEC_DEL_VAL);
+
+	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_MMUSID_REG),
+			SEC_DEL_MMUSID_VAL);
+
+	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_ADDR_EXT_REG),
+			SEC_DEL_ADDR_EXT_VAL);
+}
+
+static int ethosn_is_sec(void)
+{
+	if ((mmio_read_32(ETHOSN_CORE_SEC_REG(ETHOSN_CORE_ADDR(0), SEC_DEL_REG))
+		& SEC_DEL_EXCC_MASK) != 0U) {
+		return 0;
+	}
+
+	return 1;
+}
+
+static bool ethosn_reset(uintptr_t core_addr, int hard_reset)
+{
+	unsigned int timeout;
+	const uintptr_t sysctrl0_reg =
+		ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
+	const uint32_t reset_val = (hard_reset != 0) ? SEC_SYSCTRL0_HARD_RESET
+						    : SEC_SYSCTRL0_SOFT_RESET;
+
+	mmio_write_32(sysctrl0_reg, reset_val);
+
+	/* Wait for reset to complete */
+	for (timeout = 0U; timeout < ETHOSN_RESET_TIMEOUT_US;
+			   timeout += ETHOSN_RESET_WAIT_US) {
+
+		if ((mmio_read_32(sysctrl0_reg) & reset_val) == 0U) {
+			break;
+		}
+
+		udelay(ETHOSN_RESET_WAIT_US);
+	}
+
+	return timeout < ETHOSN_RESET_TIMEOUT_US;
+}
+
+uintptr_t ethosn_smc_handler(uint32_t smc_fid,
+			     u_register_t core_idx,
+			     u_register_t x2,
+			     u_register_t x3,
+			     u_register_t x4,
+			     void *cookie,
+			     void *handle,
+			     u_register_t flags)
+{
+	uintptr_t core_addr;
+	int hard_reset = 0;
+
+	/* Only SiP fast calls are expected */
+	if ((GET_SMC_TYPE(smc_fid) != SMC_TYPE_FAST) ||
+		(GET_SMC_OEN(smc_fid) != OEN_SIP_START)) {
+		SMC_RET1(handle, SMC_UNK);
+	}
+
+	/* Truncate parameters to 32-bits for SMC32 */
+	if (GET_SMC_CC(smc_fid) == SMC_32) {
+		core_idx &= 0xFFFFFFFF;
+		x2 &= 0xFFFFFFFF;
+		x3 &= 0xFFFFFFFF;
+		x4 &= 0xFFFFFFFF;
+	}
+
+	if (!is_ethosn_fid(smc_fid)) {
+		SMC_RET1(handle, SMC_UNK);
+	}
+
+	if (ETHOSN_STATUS == ETHOSN_STATUS_DISABLED) {
+		WARN("ETHOSN: Arm Ethos-N NPU not available\n");
+		SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
+	}
+
+	switch (smc_fid & FUNCID_NUM_MASK) {
+	case ETHOSN_FNUM_VERSION:
+		SMC_RET2(handle, ETHOSN_VERSION_MAJOR, ETHOSN_VERSION_MINOR);
+	case ETHOSN_FNUM_IS_SEC:
+		SMC_RET1(handle, ethosn_is_sec());
+	case ETHOSN_FNUM_HARD_RESET:
+		hard_reset = 1;
+		/* Fallthrough */
+	case ETHOSN_FNUM_SOFT_RESET:
+		if (core_idx >= ETHOSN_NUM_CORES) {
+			WARN("ETHOSN: core index out of range\n");
+			SMC_RET1(handle, ETHOSN_CORE_IDX_OUT_OF_RANGE);
+		}
+
+		core_addr = ETHOSN_CORE_ADDR(core_idx);
+
+		if (!ethosn_reset(core_addr, hard_reset)) {
+			SMC_RET1(handle, ETHOSN_FAILURE);
+		}
+
+		ethosn_delegate_to_ns(core_addr);
+
+		SMC_RET1(handle, ETHOSN_SUCCESS);
+	default:
+		SMC_RET1(handle, SMC_UNK);
+	}
+}
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index 6bb66a0..a0f44e9 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -92,6 +92,47 @@
 }
 
 /*******************************************************************************
+ * Helper function to get the maximum SPI INTID + 1.
+ ******************************************************************************/
+unsigned int gicv3_get_spi_limit(uintptr_t gicd_base)
+{
+	unsigned int spi_limit;
+	unsigned int typer_reg = gicd_read_typer(gicd_base);
+
+	/* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */
+	spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
+
+	/* Filter out special INTIDs 1020-1023 */
+	if (spi_limit > (MAX_SPI_ID + 1U)) {
+		return MAX_SPI_ID + 1U;
+	}
+
+	return spi_limit;
+}
+
+#if GIC_EXT_INTID
+/*******************************************************************************
+ * Helper function to get the maximum ESPI INTID + 1.
+ ******************************************************************************/
+unsigned int gicv3_get_espi_limit(uintptr_t gicd_base)
+{
+	unsigned int typer_reg = gicd_read_typer(gicd_base);
+
+	/* Check if extended SPI range is implemented */
+	if ((typer_reg & TYPER_ESPI) != 0U) {
+		/*
+		 * (maximum ESPI INTID + 1) is equal to
+		 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096
+		 */
+		return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
+			TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
+	}
+
+	return 0U;
+}
+#endif /* GIC_EXT_INTID */
+
+/*******************************************************************************
  * Helper function to configure the default attributes of (E)SPIs.
  ******************************************************************************/
 void gicv3_spis_config_defaults(uintptr_t gicd_base)
@@ -100,19 +141,8 @@
 #if GIC_EXT_INTID
 	unsigned int num_eints;
 #endif
-	unsigned int typer_reg = gicd_read_typer(gicd_base);
 
-	/* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
-	num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
-
-	/*
-	 * The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
-	 * the maximum possible value for num_ints is 1024. Limit the value to
-	 * MAX_SPI_ID + 1 to avoid getting wrong address in GICD_OFFSET() macro.
-	 */
-	if (num_ints > MAX_SPI_ID + 1U) {
-		num_ints = MAX_SPI_ID + 1U;
-	}
+	num_ints = gicv3_get_spi_limit(gicd_base);
 	INFO("Maximum SPI INTID supported: %u\n", num_ints - 1);
 
 	/* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
@@ -121,13 +151,8 @@
 	}
 
 #if GIC_EXT_INTID
-	/* Check if extended SPI range is implemented */
-	if ((typer_reg & TYPER_ESPI) != 0U) {
-		/*
-		 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
-		 */
-		num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
-			TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
+	num_eints = gicv3_get_espi_limit(gicd_base);
+	if (num_eints != 0U) {
 		INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1);
 
 		for (i = MIN_ESPI_ID; i < num_eints;
@@ -135,7 +160,6 @@
 			gicd_write_igroupr(gicd_base, i, ~0U);
 		}
 	} else {
-		num_eints = 0U;
 		INFO("ESPI range is not implemented.\n");
 	}
 #endif
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 5a49b4f..668416c 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -728,40 +728,17 @@
  *****************************************************************************/
 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
 {
-	unsigned int typer_reg, num_ints;
-#if GIC_EXT_INTID
-	unsigned int num_eints;
-#endif
-
 	assert(gicv3_driver_data != NULL);
 	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(IS_IN_EL3());
 	assert(dist_ctx != NULL);
 
 	uintptr_t gicd_base = gicv3_driver_data->gicd_base;
-
-	typer_reg = gicd_read_typer(gicd_base);
-
-	/* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
-	num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
-
-	/* Filter out special INTIDs 1020-1023 */
-	if (num_ints > (MAX_SPI_ID + 1U)) {
-		num_ints = MAX_SPI_ID + 1U;
-	}
-
+	unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
 #if GIC_EXT_INTID
-	/* Check if extended SPI range is implemented */
-	if ((typer_reg & TYPER_ESPI) != 0U) {
-		/*
-		 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
-		 */
-		num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
-			TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
-	} else {
-		num_eints = 0U;
-	}
+	unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
 #endif
+
 	/* Wait for pending write to complete */
 	gicd_wait_for_pending_write(gicd_base);
 
@@ -838,11 +815,6 @@
  *****************************************************************************/
 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
 {
-	unsigned int typer_reg, num_ints;
-#if GIC_EXT_INTID
-	unsigned int num_eints;
-#endif
-
 	assert(gicv3_driver_data != NULL);
 	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(IS_IN_EL3());
@@ -864,27 +836,9 @@
 	/* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
 	gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
 
-	typer_reg = gicd_read_typer(gicd_base);
-
-	/* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
-	num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
-
-	/* Filter out special INTIDs 1020-1023 */
-	if (num_ints > (MAX_SPI_ID + 1U)) {
-		num_ints = MAX_SPI_ID + 1U;
-	}
-
+	unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
 #if GIC_EXT_INTID
-	/* Check if extended SPI range is implemented */
-	if ((typer_reg & TYPER_ESPI) != 0U) {
-		/*
-		 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
-		 */
-		num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
-			TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
-	} else {
-		num_eints = 0U;
-	}
+	unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
 #endif
 	/* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 416cdd0..93ee1a1 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -233,6 +233,8 @@
 /*******************************************************************************
  * Private GICv3 helper function prototypes
  ******************************************************************************/
+unsigned int gicv3_get_spi_limit(uintptr_t gicd_base);
+unsigned int gicv3_get_espi_limit(uintptr_t gicd_base);
 void gicv3_spis_config_defaults(uintptr_t gicd_base);
 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index 9798ed4..9fc1578 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -10,6 +10,7 @@
 #include <common/debug.h>
 #include <drivers/arm/tzc400.h>
 #include <lib/mmio.h>
+#include <lib/utils_def.h>
 
 #include "tzc_common_private.h"
 
@@ -70,6 +71,77 @@
 DEFINE_TZC_COMMON_CONFIGURE_REGION0(400)
 DEFINE_TZC_COMMON_CONFIGURE_REGION(400)
 
+static void _tzc400_clear_it(uintptr_t base, uint32_t filter)
+{
+	mmio_write_32(base + INT_CLEAR, BIT_32(filter));
+}
+
+static uint32_t _tzc400_get_int_by_filter(uintptr_t base, uint32_t filter)
+{
+	return mmio_read_32(base + INT_STATUS) & BIT_32(filter);
+}
+
+#if DEBUG
+static unsigned long _tzc400_get_fail_address(uintptr_t base, uint32_t filter)
+{
+	unsigned long fail_address;
+
+	fail_address = mmio_read_32(base + FAIL_ADDRESS_LOW_OFF +
+				    (filter * FILTER_OFFSET));
+#ifdef __aarch64__
+	fail_address += (unsigned long)mmio_read_32(base + FAIL_ADDRESS_HIGH_OFF +
+						    (filter * FILTER_OFFSET)) << 32;
+#endif
+
+	return fail_address;
+}
+
+static uint32_t _tzc400_get_fail_id(uintptr_t base, uint32_t filter)
+{
+	return mmio_read_32(base + FAIL_ID + (filter * FILTER_OFFSET));
+}
+
+static uint32_t _tzc400_get_fail_control(uintptr_t base, uint32_t filter)
+{
+	return mmio_read_32(base + FAIL_CONTROL_OFF + (filter * FILTER_OFFSET));
+}
+
+static void _tzc400_dump_fail_filter(uintptr_t base, uint32_t filter)
+{
+	uint32_t control_fail;
+	uint32_t fail_id;
+	unsigned long address_fail;
+
+	address_fail = _tzc400_get_fail_address(base, filter);
+	ERROR("Illegal access to 0x%lx:\n", address_fail);
+
+	fail_id = _tzc400_get_fail_id(base, filter);
+	ERROR("\tFAIL_ID = 0x%x\n", fail_id);
+
+	control_fail = _tzc400_get_fail_control(base, filter);
+	if (((control_fail & BIT_32(FAIL_CONTROL_NS_SHIFT)) >> FAIL_CONTROL_NS_SHIFT) ==
+	    FAIL_CONTROL_NS_NONSECURE) {
+		ERROR("\tNon-Secure\n");
+	} else {
+		ERROR("\tSecure\n");
+	}
+
+	if (((control_fail & BIT_32(FAIL_CONTROL_PRIV_SHIFT)) >> FAIL_CONTROL_PRIV_SHIFT) ==
+	    FAIL_CONTROL_PRIV_PRIV) {
+		ERROR("\tPrivilege\n");
+	} else {
+		ERROR("\tUnprivilege\n");
+	}
+
+	if (((control_fail & BIT_32(FAIL_CONTROL_DIR_SHIFT)) >> FAIL_CONTROL_DIR_SHIFT) ==
+	    FAIL_CONTROL_DIR_WRITE) {
+		ERROR("\tWrite\n");
+	} else {
+		ERROR("\tRead\n");
+	}
+}
+#endif /* DEBUG */
+
 static unsigned int _tzc400_get_gate_keeper(uintptr_t base,
 				unsigned int filter)
 {
@@ -108,11 +180,6 @@
 	assert(tzc400.base != 0U);
 	assert(action <= TZC_ACTION_ERR_INT);
 
-	/*
-	 * - Currently no handler is provided to trap an error via interrupt
-	 *   or exception.
-	 * - The interrupt action has not been tested.
-	 */
 	_tzc400_write_action(tzc400.base, action);
 }
 
@@ -245,3 +312,31 @@
 	for (filter = 0; filter < tzc400.num_filters; filter++)
 		_tzc400_set_gate_keeper(tzc400.base, filter, 0);
 }
+
+int tzc400_it_handler(void)
+{
+	uint32_t filter;
+	uint32_t filter_it_pending = tzc400.num_filters;
+
+	assert(tzc400.base != 0U);
+
+	for (filter = 0U; filter < tzc400.num_filters; filter++) {
+		if (_tzc400_get_int_by_filter(tzc400.base, filter) != 0U) {
+			filter_it_pending = filter;
+			break;
+		}
+	}
+
+	if (filter_it_pending == tzc400.num_filters) {
+		ERROR("TZC-400: No interrupt pending!\n");
+		return -1;
+	}
+
+#if DEBUG
+	_tzc400_dump_fail_filter(tzc400.base, filter_it_pending);
+#endif
+
+	_tzc400_clear_it(tzc400.base, filter_it_pending);
+
+	return 0;
+}
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 91ee1be..c7f84af 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -222,19 +222,25 @@
  * To protect the system against rollback, the platform includes a non-volatile
  * counter whose value can only be increased. All certificates include a counter
  * value that should not be lower than the value stored in the platform. If the
- * value is larger, the counter in the platform must be updated to the new
- * value.
+ * value is larger, the counter in the platform must be updated to the new value
+ * (provided it has been authenticated).
  *
  * Return: 0 = success, Otherwise = error
+ * Returns additionally,
+ * cert_nv_ctr -> NV counter value present in the certificate
+ * need_nv_ctr_upgrade = 0 -> platform NV counter upgrade is not needed
+ * need_nv_ctr_upgrade = 1 -> platform NV counter upgrade is needed
  */
 static int auth_nvctr(const auth_method_param_nv_ctr_t *param,
 		      const auth_img_desc_t *img_desc,
-		      void *img, unsigned int img_len)
+		      void *img, unsigned int img_len,
+		      unsigned int *cert_nv_ctr,
+		      bool *need_nv_ctr_upgrade)
 {
 	char *p;
 	void *data_ptr = NULL;
 	unsigned int data_len, len, i;
-	unsigned int cert_nv_ctr, plat_nv_ctr;
+	unsigned int plat_nv_ctr;
 	int rc = 0;
 
 	/* Get the counter value from current image. The AM expects the IPM
@@ -265,22 +271,20 @@
 	}
 
 	/* Convert to unsigned int. This code is for a little-endian CPU */
-	cert_nv_ctr = 0;
+	*cert_nv_ctr = 0;
 	for (i = 0; i < len; i++) {
-		cert_nv_ctr = (cert_nv_ctr << 8) | *p++;
+		*cert_nv_ctr = (*cert_nv_ctr << 8) | *p++;
 	}
 
 	/* Get the counter from the platform */
 	rc = plat_get_nv_ctr(param->plat_nv_ctr->cookie, &plat_nv_ctr);
 	return_if_error(rc);
 
-	if (cert_nv_ctr < plat_nv_ctr) {
+	if (*cert_nv_ctr < plat_nv_ctr) {
 		/* Invalid NV-counter */
 		return 1;
-	} else if (cert_nv_ctr > plat_nv_ctr) {
-		rc = plat_set_nv_ctr2(param->plat_nv_ctr->cookie,
-			img_desc, cert_nv_ctr);
-		return_if_error(rc);
+	} else if (*cert_nv_ctr > plat_nv_ctr) {
+		*need_nv_ctr_upgrade = true;
 	}
 
 	return 0;
@@ -351,6 +355,10 @@
 	void *param_ptr;
 	unsigned int param_len;
 	int rc, i;
+	unsigned int cert_nv_ctr = 0;
+	bool need_nv_ctr_upgrade = false;
+	bool sig_auth_done = false;
+	const auth_method_param_nv_ctr_t *nv_ctr_param = NULL;
 
 	/* Get the image descriptor from the chain of trust */
 	img_desc = FCONF_GET_PROPERTY(tbbr, cot, img_id);
@@ -376,10 +384,13 @@
 		case AUTH_METHOD_SIG:
 			rc = auth_signature(&auth_method->param.sig,
 					img_desc, img_ptr, img_len);
+			sig_auth_done = true;
 			break;
 		case AUTH_METHOD_NV_CTR:
-			rc = auth_nvctr(&auth_method->param.nv_ctr,
-					img_desc, img_ptr, img_len);
+			nv_ctr_param = &auth_method->param.nv_ctr;
+			rc = auth_nvctr(nv_ctr_param,
+					img_desc, img_ptr, img_len,
+					&cert_nv_ctr, &need_nv_ctr_upgrade);
 			break;
 		default:
 			/* Unknown authentication method */
@@ -389,6 +400,16 @@
 		return_if_error(rc);
 	}
 
+	/*
+	 * Do platform NV counter upgrade only if the certificate gets
+	 * authenticated, and platform NV-counter upgrade is needed.
+	 */
+	if (need_nv_ctr_upgrade && sig_auth_done) {
+		rc = plat_set_nv_ctr2(nv_ctr_param->plat_nv_ctr->cookie,
+				      img_desc, cert_nv_ctr);
+		return_if_error(rc);
+	}
+
 	/* Extract the parameters indicated in the image descriptor to
 	 * authenticate the children images. */
 	if (img_desc->authenticated_data != NULL) {
diff --git a/drivers/brcm/mdio/mdio.c b/drivers/brcm/mdio/mdio.c
new file mode 100644
index 0000000..1cf9d66
--- /dev/null
+++ b/drivers/brcm/mdio/mdio.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <string.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <mdio.h>
+
+static int mdio_op_status(uint32_t result)
+{
+	uint32_t timeout = 1000000U; /* loop for 1s */
+	uint32_t val;
+
+	do {
+		val = mmio_read_32(CMIC_MIIM_STAT);
+		if ((val & MDIO_STAT_DONE) == result) {
+			return 0;
+		}
+
+		udelay(1U);
+	} while (timeout-- != 0U);
+	return -1;
+}
+
+static int mdio_op(uint16_t busid, uint16_t phyid, uint32_t reg,
+	       uint16_t val, uint8_t op)
+{
+	uint32_t param;
+	int ret;
+
+	mmio_write_32(CMIC_MIIM_CTRL, 0U);
+	ret = mdio_op_status(0U);
+	if (ret != 0) {
+		goto err;
+	}
+
+	param = 0U;
+	param |= 1U << MDIO_PARAM_INTERNAL_SEL;
+	param |= (busid & MDIO_PARAM_BUSID_MASK) << MDIO_PARAM_BUSID;
+	param |= (phyid & MDIO_PARAM_PHYID_MASK) << MDIO_PARAM_PHYID;
+	param |= (val & MDIO_PARAM_DATA_MASK) << MDIO_PARAM_DATA;
+
+	mmio_write_32(CMIC_MIIM_PARAM, param);
+
+	mmio_write_32(CMIC_MIIM_ADDRESS, reg);
+
+	mmio_write_32(CMIC_MIIM_CTRL, op);
+
+	ret = mdio_op_status(1U);
+	if (ret != 0) {
+		goto err;
+	}
+
+	if (op == MDIO_CTRL_READ_OP) {
+		ret = mmio_read_32(CMIC_MIIM_READ_DATA) & MDIO_READ_DATA_MASK;
+	}
+err:
+	return ret;
+}
+
+int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val)
+{
+	int ret;
+
+	ret = mdio_op(busid, phyid, reg, val, MDIO_CTRL_WRITE_OP);
+	if (ret == -1) {
+		INFO("MDIO write fail\n");
+	}
+	return ret;
+}
+
+int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg)
+{
+	int ret;
+
+	ret = mdio_op(busid, phyid, reg, 0U, MDIO_CTRL_READ_OP);
+	if (ret == -1) {
+		INFO("MDIO read fail\n");
+	}
+	return ret;
+}
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index f6a40a5..7377e5e 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -14,6 +14,7 @@
 
 #include <mvebu.h>
 #include <mvebu_def.h>
+#include <plat_marvell.h>
 
 #include "phy-comphy-3700.h"
 #include "phy-comphy-common.h"
@@ -29,15 +30,6 @@
 #define USB3_GBE1_PHY		(MVEBU_REGS_BASE + 0x5C000)
 #define COMPHY_SD_ADDR		(MVEBU_REGS_BASE + 0x1F000)
 
-/*
- * Below address in used only for reading, therefore no problem with concurrent
- * Linux access.
- */
-#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
- #define MVEBU_XTAL_MODE_MASK		BIT(9)
- #define MVEBU_XTAL_MODE_OFFS		9
- #define MVEBU_XTAL_CLOCK_25MHZ		0x0
-
 struct sgmii_phy_init_data_fix {
 	uint16_t addr;
 	uint16_t value;
@@ -125,20 +117,6 @@
 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000	/*1F8 */
 };
 
-/* returns reference clock in MHz (25 or 40) */
-static uint32_t get_ref_clk(void)
-{
-	uint32_t val;
-
-	val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
-		MVEBU_XTAL_MODE_OFFS;
-
-	if (val == MVEBU_XTAL_CLOCK_25MHZ)
-		return 25;
-	else
-		return 40;
-}
-
 /* PHY selector configures with corresponding modes */
 static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
 						uint32_t comphy_mode)
@@ -525,7 +503,8 @@
 		data |= TXD_INVERT_BIT;
 	if (invert & COMPHY_POLARITY_RXD_INVERT)
 		data |= RXD_INVERT_BIT;
-	reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, 0);
+	mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
+	reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask);
 
 	/*
 	 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
@@ -563,7 +542,7 @@
 	 * refer to RX initialization part for details.
 	 */
 	reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
-		PHY_RX_INIT_BIT, 0x0);
+		PHY_RX_INIT_BIT, PHY_RX_INIT_BIT);
 
 	ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
 				   COMPHY_PHY_STATUS_OFFSET(comphy_index),
@@ -594,7 +573,7 @@
 	debug_enter();
 
 	data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT;
-	mask = 0;
+	mask = data;
 	offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
 	reg_set(offset, data, mask);
 
@@ -746,12 +725,15 @@
 	/*
 	 * 13. Check the Polarity invert bit
 	 */
-	if (invert & COMPHY_POLARITY_TXD_INVERT)
-		usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, TXD_INVERT_BIT,
-			     TXD_INVERT_BIT, mode);
-	if (invert & COMPHY_POLARITY_RXD_INVERT)
-		usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, RXD_INVERT_BIT,
-			     RXD_INVERT_BIT, mode);
+	data = 0U;
+	if (invert & COMPHY_POLARITY_TXD_INVERT) {
+		data |= TXD_INVERT_BIT;
+	}
+	if (invert & COMPHY_POLARITY_RXD_INVERT) {
+		data |= RXD_INVERT_BIT;
+	}
+	mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
+	usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask, mode);
 
 	/*
 	 * 14. Set max speed generation to USB3.0 5Gbps
@@ -802,21 +784,22 @@
 {
 	int ret;
 	uint32_t ref_clk;
+	uint32_t mask, data;
 	int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
 
 	debug_enter();
 
 	/* 1. Enable max PLL. */
 	reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR,
-		  USE_MAX_PLL_RATE_EN, 0x0);
+		  USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);
 
 	/* 2. Select 20 bit SERDES interface. */
 	reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
-		  CFG_SEL_20B, 0);
+		  CFG_SEL_20B, CFG_SEL_20B);
 
 	/* 3. Force to use reg setting for PCIe mode */
 	reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR,
-		  SEL_BITS_PCIE_FORCE, 0);
+		  SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
 
 	/* 4. Change RX wait */
 	reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR,
@@ -830,7 +813,7 @@
 
 	/* 6. Enable the output of 100M/125M/500M clock */
 	reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR,
-		  MISC_REG0_DEFAULT_VALUE | CLK500M_EN | CLK100M_125M_EN,
+		  MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
 		  REG_16_BIT_MASK);
 
 	/*
@@ -858,13 +841,15 @@
 		  SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK);
 
 	/* 10. Check the Polarity invert bit */
-	if (invert & COMPHY_POLARITY_TXD_INVERT)
-		reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR,
-			  TXD_INVERT_BIT, 0x0);
-
-	if (invert & COMPHY_POLARITY_RXD_INVERT)
-		reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR,
-			  RXD_INVERT_BIT, 0x0);
+	data = 0U;
+	if (invert & COMPHY_POLARITY_TXD_INVERT) {
+		data |= TXD_INVERT_BIT;
+	}
+	if (invert & COMPHY_POLARITY_RXD_INVERT) {
+		data |= RXD_INVERT_BIT;
+	}
+	mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
+	reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
 
 	/* 11. Release SW reset */
 	reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 1628e36..94056f1 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -104,6 +104,7 @@
 #define COMPHY_MISC_REG0_ADDR		0x4F
 #define MISC_REG0_ADDR(unit)		(COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit))
 #define CLK100M_125M_EN			BIT(4)
+#define TXDCLK_2X_SEL			BIT(6)
 #define CLK500M_EN			BIT(7)
 #define PHY_REF_CLK_SEL			BIT(10)
 #define MISC_REG0_DEFAULT_VALUE		0xA00D
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index d1c26f8..86f4c77 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -53,14 +53,19 @@
 #define SYS_CTRL_FROM_COMPHY_ADDR(x)	((x & ~0xffffff) + 0x440000)
 
 /* DFX register spaces */
-#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET	(0)
-#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK	(0x1 << \
-					SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET)
-#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET	(1)
-#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK	(0x1 << \
-					SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET)
-#define SAR_STATUS_0_REG			200
+#define SAR_RST_PCIE0_CLOCK_CONFIG_CP0_OFFSET	(30)
+#define SAR_RST_PCIE0_CLOCK_CONFIG_CP0_MASK	(0x1UL << \
+					SAR_RST_PCIE0_CLOCK_CONFIG_CP0_OFFSET)
+#define SAR_RST_PCIE1_CLOCK_CONFIG_CP0_OFFSET	(31)
+#define SAR_RST_PCIE1_CLOCK_CONFIG_CP0_MASK	(0x1UL << \
+					SAR_RST_PCIE1_CLOCK_CONFIG_CP0_OFFSET)
+#define SAR_STATUS_0_REG			0x40600
 #define DFX_FROM_COMPHY_ADDR(x)			((x & ~0xffffff) + DFX_BASE)
+/* Common Phy training  */
+#define COMPHY_TRX_TRAIN_COMPHY_OFFS		0x1000
+#define COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE	0x1
+#define COMPHY_TRX_RELATIVE_ADDR(comphy_index)	(comphy_train_base + \
+			(comphy_index) * COMPHY_TRX_TRAIN_COMPHY_OFFS)
 
 /* The same Units Soft Reset Config register are accessed in all PCIe ports
  * initialization, so a spin lock is defined in case when more than 1 CPUs
@@ -829,7 +834,8 @@
 
 static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
 					   uint8_t comphy_index,
-					   uint32_t comphy_mode)
+					   uint32_t comphy_mode,
+					   uint64_t comphy_train_base)
 {
 	uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
 	uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode);
@@ -837,7 +843,6 @@
 	uint8_t ap_nr, cp_nr;
 
 	debug_enter();
-
 	mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
 
 	if (rx_trainng_done[ap_nr][cp_nr][comphy_index]) {
@@ -1234,6 +1239,14 @@
 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
 
+	/* Force rx training on 10G port */
+	data = mmio_read_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index));
+	data |= COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE;
+	mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data);
+	mdelay(200);
+	data &= ~COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE;
+	mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data);
+
 	debug_exit();
 
 	return ret;
@@ -1305,11 +1318,11 @@
 	reg = mmio_read_32(DFX_FROM_COMPHY_ADDR(comphy_base) +
 			   SAR_STATUS_0_REG);
 	if (comphy_index == COMPHY_LANE4 || comphy_index == COMPHY_LANE5)
-		clk_dir = (reg & SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK) >>
-					  SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET;
+		clk_dir = (reg & SAR_RST_PCIE1_CLOCK_CONFIG_CP0_MASK) >>
+					  SAR_RST_PCIE1_CLOCK_CONFIG_CP0_OFFSET;
 	else
-		clk_dir = (reg & SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK) >>
-					  SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET;
+		clk_dir = (reg & SAR_RST_PCIE0_CLOCK_CONFIG_CP0_MASK) >>
+					  SAR_RST_PCIE0_CLOCK_CONFIG_CP0_OFFSET;
 
 	debug("On lane %d\n", comphy_index);
 	debug("PCIe clock direction = %x\n", clk_dir);
@@ -2284,7 +2297,6 @@
 					  uint32_t comphy_mode)
 {
 	uint32_t mask, data;
-	uint8_t ap_nr, cp_nr;
 	uintptr_t comphy_addr = comphy_addr =
 				COMPHY_ADDR(comphy_base, comphy_index);
 
@@ -2301,10 +2313,16 @@
 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
 	debug_exit();
 
-	/* Start AP Firmware */
-	mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
-	mg_start_ap_fw(cp_nr, comphy_index);
+#if MSS_SUPPORT
+	do {
+		uint8_t ap_nr, cp_nr;
 
+		/* start ap fw */
+		mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
+		mg_start_ap_fw(cp_nr, comphy_index);
+
+	} while (0);
+#endif
 	return 0;
 }
 
@@ -2343,8 +2361,10 @@
 	return 0;
 }
 
-int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
-				uint64_t comphy_mode)
+int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
+				uint8_t comphy_index,
+				uint64_t comphy_mode,
+				uint64_t comphy_train_base)
 {
 	int mode = COMPHY_GET_MODE(comphy_mode);
 	int err = 0;
@@ -2368,7 +2388,8 @@
 	case (COMPHY_SFI_MODE):
 		err = mvebu_cp110_comphy_xfi_power_on(comphy_base,
 						      comphy_index,
-						      comphy_mode);
+						      comphy_mode,
+						      comphy_train_base);
 		break;
 	case (COMPHY_PCIE_MODE):
 		err = mvebu_cp110_comphy_pcie_power_on(comphy_base,
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.h b/drivers/marvell/comphy/phy-comphy-cp110.h
index b4a2102..0be6c26 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.h
+++ b/drivers/marvell/comphy/phy-comphy-cp110.h
@@ -89,8 +89,9 @@
 				     uint8_t comphy_index);
 int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
 				 uint8_t comphy_index, uint64_t comphy_mode);
-int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
-				uint8_t comphy_index, uint64_t comphy_mode);
+int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
+				uint64_t comphy_mode,
+				uint64_t comphy_train_base);
 int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
 				       uint8_t comphy_index);
 int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,
diff --git a/drivers/marvell/ddr_phy_access.c b/drivers/marvell/ddr_phy_access.c
new file mode 100644
index 0000000..352d1ef
--- /dev/null
+++ b/drivers/marvell/ddr_phy_access.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include "ddr_phy_access.h"
+#include <lib/mmio.h>
+#include <drivers/marvell/ccu.h>
+#include <errno.h>
+
+#define DDR_PHY_END_ADDRESS	0x100000
+
+#ifdef DDR_PHY_DEBUG
+#define debug_printf(...) printf(__VA_ARGS__)
+#else
+#define debug_printf(...)
+#endif
+
+
+/*
+ * This routine writes 'data' to specified 'address' offset,
+ * with optional debug print support
+ */
+int snps_fw_write(uintptr_t offset, uint16_t data)
+{
+	debug_printf("In %s\n", __func__);
+
+	if (offset < DDR_PHY_END_ADDRESS) {
+		mmio_write_16(DDR_PHY_BASE_ADDR + (2 * offset), data);
+		return 0;
+	}
+	debug_printf("%s: illegal offset value: 0x%x\n", __func__, offset);
+	return -EINVAL;
+}
+
+int snps_fw_read(uintptr_t offset, uint16_t *read)
+{
+	debug_printf("In %s\n", __func__);
+
+	if (offset < DDR_PHY_END_ADDRESS) {
+		*read = mmio_read_16(DDR_PHY_BASE_ADDR + (2 * offset));
+		return 0;
+	}
+	debug_printf("%s: illegal offset value: 0x%x\n", __func__, offset);
+	return -EINVAL;
+}
+
+int mvebu_ddr_phy_write(uintptr_t offset, uint16_t data)
+{
+	return snps_fw_write(offset, data);
+}
+
+int mvebu_ddr_phy_read(uintptr_t offset, uint16_t *read)
+{
+	return snps_fw_read(offset, read);
+}
diff --git a/drivers/marvell/ddr_phy_access.h b/drivers/marvell/ddr_phy_access.h
new file mode 100644
index 0000000..5f9a668
--- /dev/null
+++ b/drivers/marvell/ddr_phy_access.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <plat_marvell.h>
+
+#define DEVICE_BASE		0xF0000000
+#define DDR_PHY_OFFSET		0x1000000
+#define DDR_PHY_BASE_ADDR	(DEVICE_BASE + DDR_PHY_OFFSET)
+
+int mvebu_ddr_phy_write(uintptr_t offset, uint16_t data);
+int mvebu_ddr_phy_read(uintptr_t offset, uint16_t *read);
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index 906df66..f12da0e 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -14,6 +14,7 @@
 #include <drivers/marvell/mochi/cp110_setup.h>
 #include <drivers/rambus/trng_ip_76.h>
 
+#include <efuse_def.h>
 #include <plat_marvell.h>
 
 /*
@@ -110,6 +111,8 @@
  * TRNG Configuration
  ******************************************************************************/
 #define MVEBU_TRNG_BASE					(0x760000)
+#define MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD		MVEBU_AP_LDX_220_189_EFUSE_OFFS
+#define MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET		13	/* LD0[202] */
 
 enum axi_attr {
 	AXI_ADUNIT_ATTR = 0,
@@ -389,6 +392,22 @@
 {
 	static bool done;
 	int ret;
+	uint32_t reg_val, efuse;
+
+	/* Set access to LD0 */
+	reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
+	reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK;
+	mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
+
+	/* Obtain the AP LD0 bit defining TRNG presence */
+	efuse = mmio_read_32(MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD);
+	efuse >>= MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET;
+	efuse &= 1;
+
+	if (efuse == 0) {
+		VERBOSE("TRNG is not present, skipping");
+		return;
+	}
 
 	if (!done) {
 		ret = eip76_rng_probe(base + MVEBU_TRNG_BASE);
diff --git a/drivers/marvell/secure_dfx_access/armada_thermal.c b/drivers/marvell/secure_dfx_access/armada_thermal.c
new file mode 100644
index 0000000..4f7191b
--- /dev/null
+++ b/drivers/marvell/secure_dfx_access/armada_thermal.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <errno.h>
+#include <lib/mmio.h>
+#include <mvebu.h>
+#include <stdbool.h>
+#include "dfx.h"
+
+/* #define DEBUG_DFX */
+#ifdef DEBUG_DFX
+#define debug(format...) NOTICE(format)
+#else
+#define debug(format, arg...)
+#endif
+
+#define TSEN_CTRL0			0xf06f8084
+ #define TSEN_CTRL0_START		BIT(0)
+ #define TSEN_CTRL0_RESET		BIT(1)
+ #define TSEN_CTRL0_ENABLE		BIT(2)
+ #define TSEN_CTRL0_AVG_BYPASS		BIT(6)
+ #define TSEN_CTRL0_CHAN_SHIFT		13
+ #define TSEN_CTRL0_CHAN_MASK		0xF
+ #define TSEN_CTRL0_OSR_SHIFT		24
+ #define TSEN_CTRL0_OSR_MAX		0x3
+ #define TSEN_CTRL0_MODE_SHIFT		30
+ #define TSEN_CTRL0_MODE_EXTERNAL	0x2U
+ #define TSEN_CTRL0_MODE_MASK		0x3U
+
+#define TSEN_CTRL1			0xf06f8088
+ #define TSEN_CTRL1_INT_EN		BIT(25)
+ #define TSEN_CTRL1_HYST_SHIFT		19
+ #define TSEN_CTRL1_HYST_MASK		(0x3 << TSEN_CTRL1_HYST_SHIFT)
+ #define TSEN_CTRL1_THRESH_SHIFT	3
+ #define TSEN_CTRL1_THRESH_MASK		(0x3ff << TSEN_CTRL1_THRESH_SHIFT)
+
+#define TSEN_STATUS			0xf06f808c
+ #define TSEN_STATUS_VALID_OFFSET	16
+ #define TSEN_STATUS_VALID_MASK		(0x1 << TSEN_STATUS_VALID_OFFSET)
+ #define TSEN_STATUS_TEMP_OUT_OFFSET	0
+ #define TSEN_STATUS_TEMP_OUT_MASK	(0x3FF << TSEN_STATUS_TEMP_OUT_OFFSET)
+
+#define DFX_SERVER_IRQ_SUM_MASK_REG	0xf06f8104
+ #define DFX_SERVER_IRQ_EN		BIT(1)
+
+#define DFX_IRQ_CAUSE_REG		0xf06f8108
+
+#define DFX_IRQ_MASK_REG		0xf06f810c
+ #define DFX_IRQ_TSEN_OVERHEAT_OFFSET	BIT(22)
+
+#define THERMAL_SEN_OUTPUT_MSB		512
+#define THERMAL_SEN_OUTPUT_COMP		1024
+
+#define COEF_M 423
+#define COEF_B -150000LL
+
+static void armada_ap806_thermal_read(u_register_t *temp)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(TSEN_STATUS);
+
+	reg = ((reg & TSEN_STATUS_TEMP_OUT_MASK) >>
+	      TSEN_STATUS_TEMP_OUT_OFFSET);
+
+	/*
+	 * TSEN output format is signed as a 2s complement number
+	 * ranging from-512 to +511. when MSB is set, need to
+	 * calculate the complement number
+	 */
+	if (reg >= THERMAL_SEN_OUTPUT_MSB)
+		reg -= THERMAL_SEN_OUTPUT_COMP;
+
+	*temp = ((COEF_M * ((signed int)reg)) - COEF_B);
+}
+
+static void armada_ap806_thermal_irq(void)
+{
+	/* Dummy read, register ROC */
+	mmio_read_32(DFX_IRQ_CAUSE_REG);
+}
+
+static void armada_ap806_thermal_overheat_irq_init(void)
+{
+	uint32_t reg;
+
+	/* Clear DFX temperature IRQ cause */
+	reg = mmio_read_32(DFX_IRQ_CAUSE_REG);
+
+	/* Enable DFX Temperature IRQ */
+	reg = mmio_read_32(DFX_IRQ_MASK_REG);
+	reg |= DFX_IRQ_TSEN_OVERHEAT_OFFSET;
+	mmio_write_32(DFX_IRQ_MASK_REG, reg);
+
+	/* Enable DFX server IRQ */
+	reg = mmio_read_32(DFX_SERVER_IRQ_SUM_MASK_REG);
+	reg |= DFX_SERVER_IRQ_EN;
+	mmio_write_32(DFX_SERVER_IRQ_SUM_MASK_REG, reg);
+
+	/* Enable overheat interrupt */
+	reg = mmio_read_32(TSEN_CTRL1);
+	reg |= TSEN_CTRL1_INT_EN;
+	mmio_write_32(TSEN_CTRL1, reg);
+}
+
+static unsigned int armada_mc_to_reg_temp(unsigned int temp_mc)
+{
+	unsigned int sample;
+
+	sample = (temp_mc + COEF_B) / COEF_M;
+
+	return sample & 0x3ff;
+}
+
+/*
+ * The documentation states:
+ * high/low watermark = threshold +/- 0.4761 * 2^(hysteresis + 2)
+ * which is the mathematical derivation for:
+ * 0x0 <=> 1.9°C, 0x1 <=> 3.8°C, 0x2 <=> 7.6°C, 0x3 <=> 15.2°C
+ */
+static unsigned int hyst_levels_mc[] = {1900, 3800, 7600, 15200};
+
+static unsigned int armada_mc_to_reg_hyst(int hyst_mc)
+{
+	int i;
+
+	/*
+	 * We will always take the smallest possible hysteresis to avoid risking
+	 * the hardware integrity by enlarging the threshold by +8°C in the
+	 * worst case.
+	 */
+	for (i = ARRAY_SIZE(hyst_levels_mc) - 1; i > 0; i--)
+		if (hyst_mc >= hyst_levels_mc[i])
+			break;
+
+	return i;
+}
+
+static void armada_ap806_thermal_threshold(int thresh_mc, int hyst_mc)
+{
+	uint32_t ctrl1;
+	unsigned int threshold = armada_mc_to_reg_temp(thresh_mc);
+	unsigned int hysteresis = armada_mc_to_reg_hyst(hyst_mc);
+
+	ctrl1 = mmio_read_32(TSEN_CTRL1);
+	/* Set Threshold */
+	if (thresh_mc >= 0) {
+		ctrl1 &= ~(TSEN_CTRL1_THRESH_MASK);
+		ctrl1 |= threshold << TSEN_CTRL1_THRESH_SHIFT;
+	}
+
+	/* Set Hysteresis */
+	if (hyst_mc >= 0) {
+		ctrl1 &= ~(TSEN_CTRL1_HYST_MASK);
+		ctrl1 |= hysteresis << TSEN_CTRL1_HYST_SHIFT;
+	}
+
+	mmio_write_32(TSEN_CTRL1, ctrl1);
+}
+
+static void armada_select_channel(int channel)
+{
+	uint32_t ctrl0;
+
+	/* Stop the measurements */
+	ctrl0 = mmio_read_32(TSEN_CTRL0);
+	ctrl0 &= ~TSEN_CTRL0_START;
+	mmio_write_32(TSEN_CTRL0, ctrl0);
+
+	/* Reset the mode, internal sensor will be automatically selected */
+	ctrl0 &= ~(TSEN_CTRL0_MODE_MASK << TSEN_CTRL0_MODE_SHIFT);
+
+	/* Other channels are external and should be selected accordingly */
+	if (channel) {
+		/* Change the mode to external */
+		ctrl0 |= TSEN_CTRL0_MODE_EXTERNAL <<
+			 TSEN_CTRL0_MODE_SHIFT;
+		/* Select the sensor */
+		ctrl0 &= ~(TSEN_CTRL0_CHAN_MASK << TSEN_CTRL0_CHAN_SHIFT);
+		ctrl0 |= (channel - 1) << TSEN_CTRL0_CHAN_SHIFT;
+	}
+
+	/* Actually set the mode/channel */
+	mmio_write_32(TSEN_CTRL0, ctrl0);
+
+	/* Re-start the measurements */
+	ctrl0 |= TSEN_CTRL0_START;
+	mmio_write_32(TSEN_CTRL0, ctrl0);
+}
+
+static void armada_ap806_thermal_init(void)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(TSEN_CTRL0);
+	reg &= ~TSEN_CTRL0_RESET;
+	reg |= TSEN_CTRL0_START | TSEN_CTRL0_ENABLE;
+
+	/* Sample every ~2ms */
+	reg |= TSEN_CTRL0_OSR_MAX << TSEN_CTRL0_OSR_SHIFT;
+
+	/* Enable average (2 samples by default) */
+	reg &= ~TSEN_CTRL0_AVG_BYPASS;
+
+	mmio_write_32(TSEN_CTRL0, reg);
+
+	debug("thermal: Initialization done\n");
+}
+
+static void armada_is_valid(u_register_t *read)
+{
+	*read = (mmio_read_32(TSEN_STATUS) & TSEN_STATUS_VALID_MASK);
+}
+
+int mvebu_dfx_thermal_handle(u_register_t func, u_register_t *read,
+			     u_register_t x2, u_register_t x3)
+{
+	debug_enter();
+
+	switch (func) {
+	case MV_SIP_DFX_THERMAL_INIT:
+		armada_ap806_thermal_init();
+		break;
+	case MV_SIP_DFX_THERMAL_READ:
+		armada_ap806_thermal_read(read);
+		break;
+	case MV_SIP_DFX_THERMAL_IRQ:
+		armada_ap806_thermal_irq();
+		break;
+	case MV_SIP_DFX_THERMAL_THRESH:
+		armada_ap806_thermal_threshold(x2, x3);
+		armada_ap806_thermal_overheat_irq_init();
+		break;
+	case MV_SIP_DFX_THERMAL_IS_VALID:
+		armada_is_valid(read);
+		break;
+	case MV_SIP_DFX_THERMAL_SEL_CHANNEL:
+		armada_select_channel(x2);
+		break;
+	default:
+		ERROR("unsupported dfx func\n");
+		return -EINVAL;
+	}
+
+	debug_exit();
+
+	return 0;
+}
diff --git a/drivers/marvell/secure_dfx_access/dfx.h b/drivers/marvell/secure_dfx_access/dfx.h
new file mode 100644
index 0000000..88c4de8
--- /dev/null
+++ b/drivers/marvell/secure_dfx_access/dfx.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* DFX sub-FID */
+#define MV_SIP_DFX_THERMAL_INIT		1
+#define MV_SIP_DFX_THERMAL_READ		2
+#define MV_SIP_DFX_THERMAL_IS_VALID	3
+#define MV_SIP_DFX_THERMAL_IRQ		4
+#define MV_SIP_DFX_THERMAL_THRESH	5
+#define MV_SIP_DFX_THERMAL_SEL_CHANNEL	6
+
+#define MV_SIP_DFX_SREAD		20
+#define MV_SIP_DFX_SWRITE		21
+
+int mvebu_dfx_thermal_handle(u_register_t func, u_register_t *read,
+			     u_register_t x2, u_register_t x3);
+int mvebu_dfx_misc_handle(u_register_t func, u_register_t *read,
+			  u_register_t addr, u_register_t val);
diff --git a/drivers/marvell/secure_dfx_access/misc_dfx.c b/drivers/marvell/secure_dfx_access/misc_dfx.c
new file mode 100644
index 0000000..189105f
--- /dev/null
+++ b/drivers/marvell/secure_dfx_access/misc_dfx.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include "dfx.h"
+#include <mvebu_def.h>
+#include <mvebu.h>
+#include <errno.h>
+
+/* #define DEBUG_DFX */
+#ifdef DEBUG_DFX
+#define debug(format...) NOTICE(format)
+#else
+#define debug(format, arg...)
+#endif
+
+#define SAR_BASE			(MVEBU_REGS_BASE + 0x6F8200)
+#define SAR_SIZE			0x4
+#define AP_DEV_ID_STATUS_REG		(MVEBU_REGS_BASE + 0x6F8240)
+#define JTAG_DEV_ID_STATUS_REG		(MVEBU_REGS_BASE + 0x6F8244)
+#define EFUSE_CTRL			(MVEBU_REGS_BASE + 0x6F8008)
+#define EFUSE_LD_BASE			(MVEBU_REGS_BASE + 0x6F8F00)
+#define EFUSE_LD_SIZE			0x1C
+#define EFUSE_HD_BASE			(MVEBU_REGS_BASE + 0x6F9000)
+#define EFUSE_HD_SIZE			0x3F8
+
+/* AP806 CPU DFS register mapping*/
+#define AP806_CA72MP2_0_PLL_CR_0_BASE		(MVEBU_REGS_BASE + 0x6F8278)
+#define AP806_CA72MP2_0_PLL_CR_1_BASE		(MVEBU_REGS_BASE + 0x6F8280)
+#define AP806_CA72MP2_0_PLL_CR_2_BASE		(MVEBU_REGS_BASE + 0x6F8284)
+#define AP806_CA72MP2_0_PLL_SR_BASE		(MVEBU_REGS_BASE + 0x6F8C94)
+
+/* AP807 CPU DFS register mapping */
+#define AP807_DEVICE_GENERAL_CR_10_BASE		(MVEBU_REGS_BASE + 0x6F8278)
+#define AP807_DEVICE_GENERAL_CR_11_BASE		(MVEBU_REGS_BASE + 0x6F827C)
+#define AP807_DEVICE_GENERAL_STATUS_6_BASE	(MVEBU_REGS_BASE + 0x6F8C98)
+
+#ifdef MVEBU_SOC_AP807
+ #define CLUSTER_OFFSET		0x8
+ #define CLK_DIVIDER_REG	AP807_DEVICE_GENERAL_CR_10_BASE
+ #define CLK_FORCE_REG		AP807_DEVICE_GENERAL_CR_11_BASE
+ #define CLK_RATIO_REG		AP807_DEVICE_GENERAL_CR_11_BASE
+ #define CLK_RATIO_STATE_REG	AP807_DEVICE_GENERAL_STATUS_6_BASE
+#else
+ #define CLUSTER_OFFSET		0x14
+ #define CLK_DIVIDER_REG		AP806_CA72MP2_0_PLL_CR_0_BASE
+ #define CLK_FORCE_REG		AP806_CA72MP2_0_PLL_CR_1_BASE
+ #define CLK_RATIO_REG		AP806_CA72MP2_0_PLL_CR_2_BASE
+ #define CLK_RATIO_STATE_REG	AP806_CA72MP2_0_PLL_SR_BASE
+#endif /* MVEBU_SOC_AP807 */
+
+static _Bool is_valid(u_register_t addr)
+{
+	switch (addr) {
+	case AP_DEV_ID_STATUS_REG:
+	case JTAG_DEV_ID_STATUS_REG:
+	case SAR_BASE ... (SAR_BASE + SAR_SIZE):
+	case EFUSE_LD_BASE ... (EFUSE_LD_BASE + EFUSE_LD_SIZE):
+	case EFUSE_HD_BASE ... (EFUSE_HD_BASE + EFUSE_HD_SIZE):
+	case EFUSE_CTRL:
+	/* cpu-clk related registers */
+	case CLK_DIVIDER_REG:
+	case CLK_DIVIDER_REG + CLUSTER_OFFSET:
+	case CLK_FORCE_REG:
+	case CLK_FORCE_REG + CLUSTER_OFFSET:
+#ifndef MVEBU_SOC_AP807
+	case CLK_RATIO_REG:
+	case CLK_RATIO_REG + CLUSTER_OFFSET:
+#endif
+	case CLK_RATIO_STATE_REG:
+	case CLK_RATIO_STATE_REG + CLUSTER_OFFSET:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static int armada_dfx_sread(u_register_t *read, u_register_t addr)
+{
+	if (!is_valid(addr))
+		return -EINVAL;
+
+	*read = mmio_read_32(addr);
+
+	return 0;
+}
+
+static int armada_dfx_swrite(u_register_t addr, u_register_t val)
+{
+	if (!is_valid(addr))
+		return -EINVAL;
+
+	mmio_write_32(addr, val);
+
+	return 0;
+}
+
+int mvebu_dfx_misc_handle(u_register_t func, u_register_t *read,
+			  u_register_t addr, u_register_t val)
+{
+	debug_enter();
+
+	debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val);
+
+	switch (func) {
+	case MV_SIP_DFX_SREAD:
+		return armada_dfx_sread(read, addr);
+	case MV_SIP_DFX_SWRITE:
+		return armada_dfx_swrite(addr, val);
+	default:
+		ERROR("unsupported dfx misc sub-func\n");
+		return -EINVAL;
+	}
+
+	debug_exit();
+
+	return 0;
+}
diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S
index b377321..218fd86 100644
--- a/drivers/marvell/uart/a3700_console.S
+++ b/drivers/marvell/uart/a3700_console.S
@@ -45,15 +45,13 @@
 	cbz	w2, init_fail
 
 	/* Program the baudrate */
-	/* Divisor =  Uart clock / (16 * baudrate) */
+	/* Divisor = Round(Uartclock / (16 * baudrate)) */
 	lsl	w2, w2, #4
+	add	w1, w1, w2, lsr #1
 	udiv	w2, w1, w2
-	and	w2, w2, #0x3ff
+	and	w2, w2, #0x3ff /* clear all other bits to use default clock */
 
-	ldr	w3, [x0, #UART_BAUD_REG]
-	bic	w3, w3, 0x3ff
-	orr	w3, w3, w2
-	str	w3, [x0, #UART_BAUD_REG]/* set baud rate divisor */
+	str	w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */
 
 	/* Set UART to default 16X scheme */
 	mov	w3, #0
diff --git a/drivers/measured_boot/event_log.c b/drivers/measured_boot/event_log.c
index 727bdf5..0157b03 100644
--- a/drivers/measured_boot/event_log.c
+++ b/drivers/measured_boot/event_log.c
@@ -58,78 +58,48 @@
 };
 
 static const event2_header_t locality_event_header = {
-		/*
-		 * All EV_NO_ACTION events SHALL set
-		 * TCG_PCR_EVENT2.pcrIndex = 0, unless otherwise specified
-		 */
-		.pcr_index = PCR_0,
-
-		/*
-		 * All EV_NO_ACTION events SHALL set
-		 * TCG_PCR_EVENT2.eventType = 03h
-		 */
-		.event_type = EV_NO_ACTION,
-
-		/*
-		 * All EV_NO_ACTION events SHALL set
-		 * TCG_PCR_EVENT2.digests to all
-		 * 0x00's for each allocated Hash algorithm
-		 */
-		.digests = {
-			.count = HASH_ALG_COUNT
-		}
-};
+	/*
+	 * All EV_NO_ACTION events SHALL set
+	 * TCG_PCR_EVENT2.pcrIndex = 0, unless otherwise specified
+	 */
+	.pcr_index = PCR_0,
 
-/* Platform's table with platform specific image IDs, names and PCRs */
-static const image_data_t plat_images_data[] = {
-	{ BL2_IMAGE_ID, BL2_STRING, PCR_0 },		/* Reserved for BL2 */
-	{ INVALID_ID, NULL, (unsigned int)(-1) }	/* Terminator */
-};
+	/*
+	 * All EV_NO_ACTION events SHALL set
+	 * TCG_PCR_EVENT2.eventType = 03h
+	 */
+	.event_type = EV_NO_ACTION,
 
-static const measured_boot_data_t plat_measured_boot_data = {
-	plat_images_data,
-	NULL,	/* platform_set_nt_fw_info */
-	NULL	/* platform_set_tos_fw_info */
+	/*
+	 * All EV_NO_ACTION events SHALL set TCG_PCR_EVENT2.digests to all
+	 * 0x00's for each allocated Hash algorithm
+	 */
+	.digests = {
+		.count = HASH_ALG_COUNT
+	}
 };
 
 /*
- * Function retuns pointer to platform's measured_boot_data_t structure
- *
- * Must be overridden in the platform code
- */
-#pragma weak plat_get_measured_boot_data
-
-const measured_boot_data_t *plat_get_measured_boot_data(void)
-{
-	return &plat_measured_boot_data;
-}
-
-/*
  * Add TCG_PCR_EVENT2 event
  *
  * @param[in] hash	Pointer to hash data of TCG_DIGEST_SIZE bytes
  * @param[in] image_ptr	Pointer to image_data_t structure
- * @return:
- *	0 = success
- *    < 0 = error code
+ *
+ * There must be room for storing this new event into the event log buffer.
  */
-static int add_event2(const uint8_t *hash, const image_data_t *image_ptr)
+static void add_event2(const uint8_t *hash, const image_data_t *image_ptr)
 {
 	void *ptr = log_ptr;
 	uint32_t name_len;
-	uint32_t size_of_event;
 
 	assert(image_ptr != NULL);
 	assert(image_ptr->name != NULL);
 
 	name_len = (uint32_t)strlen(image_ptr->name) + 1U;
-	size_of_event = name_len + (uint32_t)EVENT2_HDR_SIZE;
 
 	/* Check for space in Event Log buffer */
-	if (((uintptr_t)ptr + size_of_event) > EVENT_LOG_END) {
-		ERROR("%s(): Event Log is short of memory", __func__);
-		return -ENOMEM;
-	}
+	assert(((uintptr_t)ptr + (uint32_t)EVENT2_HDR_SIZE + name_len) <=
+	       EVENT_LOG_END);
 
 	/*
 	 * As per TCG specifications, firmware components that are measured
@@ -156,12 +126,6 @@
 	/* TCG_PCR_EVENT2.Digests[].Digest[] */
 	ptr = (uint8_t *)((uintptr_t)ptr + offsetof(tpmt_ha, digest));
 
-	/* Check for space in Event Log buffer */
-	if (((uintptr_t)ptr + TCG_DIGEST_SIZE) > EVENT_LOG_END) {
-		ERROR("%s(): Event Log is short of memory", __func__);
-		return -ENOMEM;
-	}
-
 	if (hash == NULL) {
 		/* Get BL2 hash from DTB */
 		bl2_plat_get_hash(ptr);
@@ -181,8 +145,6 @@
 	/* End of event data */
 	log_ptr = (uint8_t *)((uintptr_t)ptr +
 			offsetof(event2_data_t, event) + name_len);
-
-	return 0;
 }
 
 /*
@@ -194,7 +156,6 @@
 void event_log_init(void)
 {
 	const char locality_signature[] = TCG_STARTUP_LOCALITY_SIGNATURE;
-	const uint8_t *start_ptr;
 	void *ptr = event_log;
 
 	/* Get pointer to platform's measured_boot_data_t structure */
@@ -221,11 +182,6 @@
 	((id_event_struct_data_t *)ptr)->vendor_info_size = 0;
 	ptr = (uint8_t *)((uintptr_t)ptr +
 			offsetof(id_event_struct_data_t, vendor_info));
-	if ((uintptr_t)ptr != ((uintptr_t)event_log + ID_EVENT_SIZE)) {
-		panic();
-	}
-
-	start_ptr = (uint8_t *)ptr;
 
 	/*
 	 * The Startup Locality event should be placed in the log before
@@ -262,16 +218,11 @@
 	 */
 	((startup_locality_event_t *)ptr)->startup_locality = 0U;
 	ptr = (uint8_t *)((uintptr_t)ptr + sizeof(startup_locality_event_t));
-	if ((uintptr_t)ptr != ((uintptr_t)start_ptr + LOC_EVENT_SIZE)) {
-		panic();
-	}
 
 	log_ptr = (uint8_t *)ptr;
 
 	/* Add BL2 event */
-	if (add_event2(NULL, plat_data_ptr->images_data) != 0) {
-		panic();
-	}
+	add_event2(NULL, plat_data_ptr->images_data);
 }
 
 /*
@@ -292,14 +243,11 @@
 	unsigned char hash_data[MBEDTLS_MD_MAX_SIZE];
 	int rc;
 
-	/* Check if image_id is supported */
-	while (data_ptr->id != data_id) {
-		if ((data_ptr++)->id == INVALID_ID) {
-			ERROR("%s(): image_id %u not supported\n",
-				__func__, data_id);
-			return -EINVAL;
-		}
+	/* Get the metadata associated with this image. */
+	while ((data_ptr->id != INVALID_ID) && (data_ptr->id != data_id)) {
+		data_ptr++;
 	}
+	assert(data_ptr->id != INVALID_ID);
 
 	if (data_id == TOS_FW_CONFIG_ID) {
 		tos_fw_config_base = data_base;
@@ -316,7 +264,8 @@
 		return rc;
 	}
 
-	return add_event2(hash_data, data_ptr);
+	add_event2(hash_data, data_ptr);
+	return 0;
 }
 
 /*
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 3ea17fb..c327e71 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,7 +27,7 @@
 static struct mmc_csd_emmc mmc_csd;
 static unsigned char mmc_ext_csd[512] __aligned(16);
 static unsigned int mmc_flags;
-static struct mmc_device_info mmc_dev_info;
+static struct mmc_device_info *mmc_dev_info;
 static unsigned int rca;
 static unsigned int scr[2]__aligned(16) = { 0 };
 
@@ -105,6 +105,36 @@
 	return MMC_GET_STATE(resp_data[0]);
 }
 
+static int mmc_send_part_switch_cmd(unsigned int part_config)
+{
+	int ret;
+	unsigned int part_time = 0;
+
+	ret = mmc_send_cmd(MMC_CMD(6),
+			   EXTCSD_WRITE_BYTES |
+			   EXTCSD_CMD(CMD_EXTCSD_PARTITION_CONFIG) |
+			   EXTCSD_VALUE(part_config) |
+			   EXTCSD_CMD_SET_NORMAL,
+			   MMC_RESPONSE_R1B, NULL);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/* Partition switch timing is in 10ms units */
+	part_time = mmc_ext_csd[CMD_EXTCSD_PART_SWITCH_TIME] * 10;
+
+	mdelay(part_time);
+
+	do {
+		ret = mmc_device_state();
+		if (ret < 0) {
+			return ret;
+		}
+	} while (ret == MMC_STATE_PRG);
+
+	return 0;
+}
+
 static int mmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
 {
 	int ret;
@@ -195,7 +225,7 @@
 	int ret;
 	unsigned int width = bus_width;
 
-	if (mmc_dev_info.mmc_dev_type != MMC_IS_EMMC) {
+	if (mmc_dev_info->mmc_dev_type != MMC_IS_EMMC) {
 		if (width == MMC_BUS_WIDTH_8) {
 			WARN("Wrong bus config for SD-card, force to 4\n");
 			width = MMC_BUS_WIDTH_4;
@@ -226,9 +256,9 @@
 	int ret = 0;
 	struct mmc_csd_sd_v2 *csd_sd_v2;
 
-	switch (mmc_dev_info.mmc_dev_type) {
+	switch (mmc_dev_info->mmc_dev_type) {
 	case MMC_IS_EMMC:
-		mmc_dev_info.block_size = MMC_BLOCK_SIZE;
+		mmc_dev_info->block_size = MMC_BLOCK_SIZE;
 
 		ret = ops->prepare(0, (uintptr_t)&mmc_ext_csd,
 				   sizeof(mmc_ext_csd));
@@ -260,8 +290,8 @@
 			    (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 2] << 16) |
 			    (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 3] << 24);
 
-		mmc_dev_info.device_size = (unsigned long long)nb_blocks *
-			mmc_dev_info.block_size;
+		mmc_dev_info->device_size = (unsigned long long)nb_blocks *
+			mmc_dev_info->block_size;
 
 		break;
 
@@ -270,29 +300,29 @@
 		 * Use the same mmc_csd struct, as required fields here
 		 * (READ_BL_LEN, C_SIZE, CSIZE_MULT) are common with eMMC.
 		 */
-		mmc_dev_info.block_size = BIT_32(mmc_csd.read_bl_len);
+		mmc_dev_info->block_size = BIT_32(mmc_csd.read_bl_len);
 
 		c_size = ((unsigned long long)mmc_csd.c_size_high << 2U) |
 			 (unsigned long long)mmc_csd.c_size_low;
 		assert(c_size != 0xFFFU);
 
-		mmc_dev_info.device_size = (c_size + 1U) *
+		mmc_dev_info->device_size = (c_size + 1U) *
 					    BIT_64(mmc_csd.c_size_mult + 2U) *
-					    mmc_dev_info.block_size;
+					    mmc_dev_info->block_size;
 
 		break;
 
 	case MMC_IS_SD_HC:
 		assert(mmc_csd.csd_structure == 1U);
 
-		mmc_dev_info.block_size = MMC_BLOCK_SIZE;
+		mmc_dev_info->block_size = MMC_BLOCK_SIZE;
 
 		/* Need to use mmc_csd_sd_v2 struct */
 		csd_sd_v2 = (struct mmc_csd_sd_v2 *)&mmc_csd;
 		c_size = ((unsigned long long)csd_sd_v2->c_size_high << 16) |
 			 (unsigned long long)csd_sd_v2->c_size_low;
 
-		mmc_dev_info.device_size = (c_size + 1U) << MULT_BY_512K_SHIFT;
+		mmc_dev_info->device_size = (c_size + 1U) << MULT_BY_512K_SHIFT;
 
 		break;
 
@@ -310,19 +340,19 @@
 
 	assert(speed_idx > 0U);
 
-	if (mmc_dev_info.mmc_dev_type == MMC_IS_EMMC) {
-		mmc_dev_info.max_bus_freq = tran_speed_base[speed_idx];
+	if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
+		mmc_dev_info->max_bus_freq = tran_speed_base[speed_idx];
 	} else {
-		mmc_dev_info.max_bus_freq = sd_tran_speed_base[speed_idx];
+		mmc_dev_info->max_bus_freq = sd_tran_speed_base[speed_idx];
 	}
 
 	freq_unit = mmc_csd.tran_speed & CSD_TRAN_SPEED_UNIT_MASK;
 	while (freq_unit != 0U) {
-		mmc_dev_info.max_bus_freq *= 10U;
+		mmc_dev_info->max_bus_freq *= 10U;
 		--freq_unit;
 	}
 
-	mmc_dev_info.max_bus_freq *= 10000U;
+	mmc_dev_info->max_bus_freq *= 10000U;
 
 	return 0;
 }
@@ -343,7 +373,7 @@
 
 		/* ACMD41: SD_SEND_OP_COND */
 		ret = mmc_send_cmd(MMC_ACMD(41), OCR_HCS |
-			mmc_dev_info.ocr_voltage, MMC_RESPONSE_R3,
+			mmc_dev_info->ocr_voltage, MMC_RESPONSE_R3,
 			&resp_data[0]);
 		if (ret != 0) {
 			return ret;
@@ -353,9 +383,9 @@
 			mmc_ocr_value = resp_data[0];
 
 			if ((mmc_ocr_value & OCR_HCS) != 0U) {
-				mmc_dev_info.mmc_dev_type = MMC_IS_SD_HC;
+				mmc_dev_info->mmc_dev_type = MMC_IS_SD_HC;
 			} else {
-				mmc_dev_info.mmc_dev_type = MMC_IS_SD;
+				mmc_dev_info->mmc_dev_type = MMC_IS_SD;
 			}
 
 			return 0;
@@ -392,7 +422,7 @@
 	ret = mmc_reset_to_idle();
 	if (ret != 0) {
 		return ret;
-	};
+	}
 
 	for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
 		ret = mmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
@@ -427,7 +457,7 @@
 		return ret;
 	}
 
-	if (mmc_dev_info.mmc_dev_type == MMC_IS_EMMC) {
+	if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
 		ret = mmc_send_op_cond();
 	} else {
 		/* CMD8: Send Interface Condition Command */
@@ -449,7 +479,7 @@
 	}
 
 	/* CMD3: Set Relative Address */
-	if (mmc_dev_info.mmc_dev_type == MMC_IS_EMMC) {
+	if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
 		rca = MMC_FIX_RCA;
 		ret = mmc_send_cmd(MMC_CMD(3), rca << RCA_SHIFT_OFFSET,
 				   MMC_RESPONSE_R1, NULL);
@@ -530,7 +560,7 @@
 	}
 
 	if (((mmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) &&
-	    (mmc_dev_info.mmc_dev_type != MMC_IS_SD_HC)) {
+	    (mmc_dev_info->mmc_dev_type != MMC_IS_SD_HC)) {
 		cmd_arg = lba * MMC_BLOCK_SIZE;
 	} else {
 		cmd_arg = lba;
@@ -668,7 +698,7 @@
 {
 	mmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
 			PART_CFG_BOOT_PARTITION1_ENABLE |
-			PART_CFG_PARTITION1_ACCESS);
+			PART_CFG_BOOT_PARTITION1_ACCESS);
 }
 
 static inline void mmc_rpmb_disable(void)
@@ -710,6 +740,50 @@
 	return size_erased;
 }
 
+static int mmc_part_switch(unsigned int part_type)
+{
+	uint8_t part_config = mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG];
+
+	part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK;
+	part_config |= part_type;
+
+	return mmc_send_part_switch_cmd(part_config);
+}
+
+static unsigned char mmc_current_boot_part(void)
+{
+	return PART_CFG_CURRENT_BOOT_PARTITION(mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG]);
+}
+
+size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size)
+{
+	size_t size_read;
+	int ret;
+	unsigned char current_boot_part = mmc_current_boot_part();
+
+	if (current_boot_part != 1U &&
+	    current_boot_part != 2U) {
+		ERROR("Got unexpected value for active boot partition, %u\n", current_boot_part);
+		return 0;
+	}
+
+	ret = mmc_part_switch(current_boot_part);
+	if (ret < 0) {
+		ERROR("Failed to switch to boot partition, %d\n", ret);
+		return 0;
+	}
+
+	size_read = mmc_read_blocks(lba, buf, size);
+
+	ret = mmc_part_switch(0);
+	if (ret < 0) {
+		ERROR("Failed to switch back to user partition, %d\n", ret);
+		return 0;
+	}
+
+	return size_read;
+}
+
 int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
 	     unsigned int width, unsigned int flags,
 	     struct mmc_device_info *device_info)
@@ -731,7 +805,7 @@
 
 	ops = ops_ptr;
 	mmc_flags = flags;
-	memcpy(&mmc_dev_info, device_info, sizeof(struct mmc_device_info));
+	mmc_dev_info = device_info;
 
 	return mmc_enumerate(clk, width);
 }
diff --git a/drivers/mtd/nor/spi_nor.c b/drivers/mtd/nor/spi_nor.c
index 108f893..6b4643e 100644
--- a/drivers/mtd/nor/spi_nor.c
+++ b/drivers/mtd/nor/spi_nor.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -103,7 +103,7 @@
 			0 : 1;
 	}
 
-	return (((sr & SR_WIP) != 0U) ? 1 : 0);
+	return (((sr & SR_WIP) == 0U) ? 0 : 1);
 }
 
 static int spi_nor_wait_ready(void)
@@ -131,7 +131,7 @@
 		return ret;
 	}
 
-	if ((sr & SR_QUAD_EN_MX) == 0U) {
+	if ((sr & SR_QUAD_EN_MX) != 0U) {
 		return 0;
 	}
 
@@ -141,7 +141,7 @@
 	}
 
 	sr |= SR_QUAD_EN_MX;
-	ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1, SPI_MEM_DATA_OUT);
+	ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1U, SPI_MEM_DATA_OUT);
 	if (ret != 0) {
 		return ret;
 	}
@@ -168,7 +168,7 @@
 		return ret;
 	}
 
-	ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2, SPI_MEM_DATA_OUT);
+	ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2U, SPI_MEM_DATA_OUT);
 	if (ret != 0) {
 		return -EINVAL;
 	}
@@ -230,7 +230,7 @@
 	}
 
 	return spi_nor_reg(nor_dev.bank_write_cmd, &nor_dev.selected_bank,
-			   1, SPI_MEM_DATA_OUT);
+			   1U, SPI_MEM_DATA_OUT);
 }
 
 static int spi_nor_write_bar(uint32_t offset)
@@ -248,7 +248,7 @@
 	}
 
 	ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank,
-			  1, SPI_MEM_DATA_OUT);
+			  1U, SPI_MEM_DATA_OUT);
 	if (ret != 0) {
 		return ret;
 	}
@@ -260,11 +260,11 @@
 
 static int spi_nor_read_bar(void)
 {
-	uint8_t selected_bank = 0;
+	uint8_t selected_bank = 0U;
 	int ret;
 
 	ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank,
-			  1, SPI_MEM_DATA_IN);
+			  1U, SPI_MEM_DATA_IN);
 	if (ret != 0) {
 		return ret;
 	}
@@ -280,7 +280,7 @@
 	size_t remain_len;
 	int ret;
 
-	*length_read = 0;
+	*length_read = 0U;
 	nor_dev.read_op.addr.val = offset;
 	nor_dev.read_op.data.buf = (void *)buffer;
 
@@ -324,7 +324,7 @@
 
 int spi_nor_init(unsigned long long *size, unsigned int *erase_size)
 {
-	int ret = 0;
+	int ret;
 	uint8_t id;
 
 	/* Default read command used */
@@ -339,7 +339,7 @@
 		return -EINVAL;
 	}
 
-	assert(nor_dev.size != 0);
+	assert(nor_dev.size != 0U);
 
 	if (nor_dev.size > BANK_SIZE) {
 		nor_dev.flags |= SPI_NOR_USE_BANK;
diff --git a/drivers/renesas/rcar/ddr/boot_init_dram.h b/drivers/renesas/common/ddr/boot_init_dram.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/boot_init_dram.h
rename to drivers/renesas/common/ddr/boot_init_dram.h
diff --git a/drivers/renesas/common/ddr/ddr.mk b/drivers/renesas/common/ddr/ddr.mk
new file mode 100644
index 0000000..9483686
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq ($(RCAR_LSI),$(filter $(RCAR_LSI),${RCAR_E3} ${RZ_G2E}))
+    include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+    BL2_SOURCES += drivers/renesas/common/ddr/dram_sub_func.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+    include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+else ifeq (${RCAR_LSI},${RCAR_V3M})
+    include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+else
+    include drivers/renesas/common/ddr/ddr_b/ddr_b.mk
+    BL2_SOURCES += drivers/renesas/common/ddr/dram_sub_func.c
+endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_a/boot_init_dram_regdef.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
rename to drivers/renesas/common/ddr/ddr_a/boot_init_dram_regdef.h
diff --git a/drivers/renesas/common/ddr/ddr_a/ddr_a.mk b/drivers/renesas/common/ddr/ddr_a/ddr_a.mk
new file mode 100644
index 0000000..cd6433d
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_a/ddr_a.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq ($(RCAR_LSI),$(filter $(RCAR_LSI),${RCAR_E3} ${RZ_G2E}))
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
+else
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
+endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
similarity index 99%
rename from drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
rename to drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
index ac83c9a..aa3bc24 100644
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -36,6 +36,10 @@
 #define RCAR_E3		3	/* NON */
 #define RCAR_H3N	4
 
+#define RZ_G2M		100U
+#define RZ_G2H		101U
+#define RZ_G2N		102U
+
 #define RCAR_CUT_10	0
 #define RCAR_CUT_11	1
 #define RCAR_CUT_20	10
@@ -51,11 +55,11 @@
 #else
 #if (RCAR_LSI == RCAR_H3)
 static const uint32_t prr_product = PRR_PRODUCT_H3;
-#elif(RCAR_LSI == RCAR_M3)
+#elif(RCAR_LSI == RCAR_M3 || RCAR_LSI == RZ_G2M)
 static const uint32_t prr_product = PRR_PRODUCT_M3;
-#elif(RCAR_LSI == RCAR_M3N)
+#elif(RCAR_LSI == RCAR_M3N || RCAR_LSI == RZ_G2N)
 static const uint32_t prr_product = PRR_PRODUCT_M3N;
-#elif(RCAR_LSI == RCAR_H3N)
+#elif(RCAR_LSI == RCAR_H3N || RCAR_LSI == RZ_G2H)
 static const uint32_t prr_product = PRR_PRODUCT_H3;
 #endif /* RCAR_LSI */
 
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
similarity index 86%
rename from drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
rename to drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
index de126de..45b6b08 100644
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
@@ -1,11 +1,19 @@
 /*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#ifndef RZG_SOC
+#define RZG_SOC		0
+#endif
+
+#if (RZG_SOC == 1)
+#define BOARDNUM 4
+#else
 #define BOARDNUM 22
+#endif /* RZG_SOC == 1 */
 #define BOARD_JUDGE_AUTO
 
 #ifdef BOARD_JUDGE_AUTO
@@ -66,6 +74,225 @@
 	0x000F,\
 	0x010F}
 
+#if (RZG_SOC == 1)
+static const struct _boardcnf boardcnfs[BOARDNUM] = {
+	{
+/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
+	 .phyvalid = 0x03U,
+	 .dbi_en = 0x01U,
+	 .cacs_dly = 0x02c0U,
+	 .cacs_dly_adj = 0x0U,
+	 .dqdm_dly_w = 0x0300U,
+	 .dqdm_dly_r = 0x00a0U,
+	 .ch = {
+		{
+		 { 0x04U, 0xffU },
+		 0x00345201UL,
+		 0x3201U,
+		 { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+		 { 0x08U, 0x08U, 0x08U, 0x08U },
+		 WDQLVL_PAT,
+		 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 }
+		},
+		{
+		 { 0x04U, 0xffU },
+		 0x00302154UL,
+		 0x2310U,
+		 { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+		 { 0x08U, 0x08U, 0x08U, 0x08U },
+		 WDQLVL_PAT,
+		 { 0, 0, 0, 0, 0, 0, 0, 0,  0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 }
+		}
+		}
+	},
+/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
+	{
+	 0x03U,
+	 0x01U,
+	 0x02c0U,
+	 0x0U,
+	 0x0300U,
+	 0x00a0U,
+	{
+		{
+		 { 0x02U, 0x02U },
+		 0x00345201UL,
+		 0x3201U,
+		 { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+		 { 0x08U, 0x08U, 0x08U, 0x08U },
+		 WDQLVL_PAT,
+		 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 }
+		},
+		{
+		 { 0x02U, 0x02U },
+		 0x00302154UL,
+		 0x2310,
+		 { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+		 { 0x08U, 0x08U, 0x08U, 0x08U },
+		 WDQLVL_PAT,
+		 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+		 { 0, 0, 0, 0 },
+		 { 0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0,
+		   0, 0, 0, 0, 0, 0, 0, 0 },
+		{ 0, 0, 0, 0 },
+		{ 0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0 }
+		}
+	}
+	},
+/* boardcnf[2] HopeRun HiHope RZ/G2H board 16Gbit/1rank/2ch */
+	{
+		0x05U,
+		0x01U,
+		0x0300U,
+		0,
+		0x0300U,
+		0x00a0U,
+		{
+			{
+				{ 0x04U, 0xffU },
+				0x00345201UL,
+				0x3201U,
+				{ 0x01672543U, 0x45367012U, 0x45632107U, 0x60715234U },
+				{ 0x08U, 0x08U, 0x08U, 0x08U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			},
+			{
+				{ 0x04U, 0xffU },
+				0x00302154UL,
+				0x2310U,
+				{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+				{ 0x08U, 0x08U, 0x08U, 0x08U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			},
+			{
+				{ 0x04U, 0xffU },
+				0x00302154UL,
+				0x2310U,
+				{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+				{ 0x08U, 0x08U, 0x08U, 0x08U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			},
+			{
+				{ 0xffU, 0xffU },
+				0UL,
+				0U,
+				{ 0U, 0U, 0U, 0U },
+				{ 0U, 0U, 0U, 0U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			}
+		}
+	},
+/* boardcnf[3] HopeRun HiHope RZ/G2N board 16Gbit/2rank/1ch */
+	{
+		0x01U,
+		0x01U,
+		0x0300U,
+		0,
+		0x0300U,
+		0x00a0U,
+		{
+			{
+				{ 0x04U, 0x04U },
+				0x00345201UL,
+				0x3201U,
+				{ 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+				{ 0x08U, 0x08U, 0x08U, 0x08U },
+				WDQLVL_PAT,
+				{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 },
+				{ 0, 0, 0, 0 },
+				{ 0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0,
+				  0, 0, 0, 0, 0, 0, 0, 0 }
+			}
+		}
+	},
+};
+#else
 static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	{
 /* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */
@@ -1535,6 +1762,7 @@
 	}
 	}
 };
+#endif /* RZG_SOC == 1 */
 
 void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
 {
@@ -1636,7 +1864,7 @@
 #define GPIO_INDT5	0xE605500CU
 #define GPIO_GPSR6	0xE6060118U
 
-#if (RCAR_GEN3_ULCB == 0)
+#if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0)
 static void pfc_write_and_poll(uint32_t a, uint32_t v)
 {
 	mmio_write_32(PFC_PMMR, ~v);
@@ -1652,7 +1880,7 @@
 #define RCAR_GEN3_ULCB		0
 #endif
 
-#if (RCAR_GEN3_ULCB == 0)	/* non Starter Kit */
+#if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0)	/* non Starter Kit */
 
 static uint32_t opencheck_SSI_WS6(void)
 {
@@ -1709,9 +1937,43 @@
 
 #endif
 
+#if (RZG_SOC == 1)
+#define LPDDR4_2RANK   (0x01U << 25U)
+
+static uint32_t rzg2_board_judge(void)
+{
+	uint32_t brd;
+
+	switch (prr_product) {
+	case PRR_PRODUCT_M3:
+		brd = 1U;
+		if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
+			if ((mmio_read_32(GPIO_INDT5) & LPDDR4_2RANK) == 0U) {
+				brd = 0U;
+			}
+		}
+		break;
+	case PRR_PRODUCT_H3:
+		brd = 2U;
+		break;
+	case PRR_PRODUCT_M3N:
+		brd = 3U;
+		break;
+	default:
+		brd = 99U;
+	}
+
+	return brd;
+}
+#endif /* RZG_SOC == 1 */
+
 static uint32_t _board_judge(void)
 {
 	uint32_t brd;
+
+#if (RZG_SOC == 1)
+	brd = rzg2_board_judge();
+#else
 #if (RCAR_GEN3_ULCB == 1)
 	/* Starter Kit */
 	if (prr_product == PRR_PRODUCT_H3) {
@@ -1798,6 +2060,7 @@
 		}
 	}
 #endif
+#endif /* RZG_SOC == 1 */
 
 	return brd;
 }
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
rename to drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
diff --git a/drivers/renesas/common/ddr/ddr_b/ddr_b.mk b/drivers/renesas/common/ddr/ddr_b/ddr_b.mk
new file mode 100644
index 0000000..0334780
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_b/ddr_b.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/common/ddr/ddr_b/ddr_regdef.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h
rename to drivers/renesas/common/ddr/ddr_b/ddr_regdef.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h
diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.c b/drivers/renesas/common/ddr/dram_sub_func.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/dram_sub_func.c
rename to drivers/renesas/common/ddr/dram_sub_func.c
diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.h b/drivers/renesas/common/ddr/dram_sub_func.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/dram_sub_func.h
rename to drivers/renesas/common/ddr/dram_sub_func.h
diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h
index 392abb8..7fae5e4 100644
--- a/drivers/renesas/common/emmc/emmc_registers.h
+++ b/drivers/renesas/common/emmc/emmc_registers.h
@@ -11,11 +11,11 @@
 #define MMC_CH0		(0U)	/* SDHI2/MMC0 */
 #define MMC_CH1		(1U)	/* SDHI3/MMC1 */
 
-#if (RCAR_LSI == RCAR_E3)  || (RCAR_LSI == RZ_G2M)
-#define USE_MMC_CH	(MMC_CH1)	/* R-Car E3 or RZ/G2M */
-#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
+#if (RCAR_LSI == RCAR_E3)  || (RCAR_LSI == RZ_G2M) || (RCAR_LSI == RZ_G2H) || (RCAR_LSI == RZ_G2N)
+#define USE_MMC_CH	(MMC_CH1)	/* R-Car E3 or RZ/G2{H,M,N} */
+#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
 #define USE_MMC_CH	(MMC_CH0)	/* R-Car H3/M3/M3N */
-#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
+#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
 
 #define BIT0	(0x00000001U)
 #define BIT1	(0x00000002U)
diff --git a/drivers/renesas/common/watchdog/swdt.c b/drivers/renesas/common/watchdog/swdt.c
index 05987ab..1a351ca 100644
--- a/drivers/renesas/common/watchdog/swdt.c
+++ b/drivers/renesas/common/watchdog/swdt.c
@@ -78,7 +78,7 @@
 void rcar_swdt_init(void)
 {
 	uint32_t rmsk, sr;
-#if (RCAR_LSI != RCAR_E3)
+#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RZ_G2E)
 	uint32_t reg, val, product_cut, chk_data;
 
 	reg = mmio_read_32(RCAR_PRR);
@@ -94,7 +94,7 @@
 	mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE |
 		      WTCSRA_WOVFE | WTCSRA_CKS_DIV16);
 
-#if (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 	mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
 #else
 	val = WTCNT_UPPER_BYTE;
diff --git a/drivers/renesas/rcar/ddr/ddr.mk b/drivers/renesas/rcar/ddr/ddr.mk
deleted file mode 100644
index c26993d..0000000
--- a/drivers/renesas/rcar/ddr/ddr.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
-    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
-    BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
-    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else ifeq (${RCAR_LSI},${RCAR_V3M})
-    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else
-    include drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
-    BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
-endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
deleted file mode 100644
index 7882558..0000000
--- a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
-else
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
-endif
diff --git a/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
deleted file mode 100644
index 2bcc292..0000000
--- a/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rzg/board/board.c b/drivers/renesas/rzg/board/board.c
index cfbb047..7636372 100644
--- a/drivers/renesas/rzg/board/board.c
+++ b/drivers/renesas/rzg/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,15 @@
 #include "rcar_def.h"
 
 #ifndef BOARD_DEFAULT
+#if (RCAR_LSI == RZ_G2H)
+#define BOARD_DEFAULT		(BOARD_HIHOPE_RZ_G2H << BOARD_CODE_SHIFT)
+#elif (RCAR_LSI == RZ_G2N)
+#define BOARD_DEFAULT		(BOARD_HIHOPE_RZ_G2N << BOARD_CODE_SHIFT)
+#elif (RCAR_LSI == RZ_G2E)
+#define BOARD_DEFAULT		(BOARD_EK874_RZ_G2E << BOARD_CODE_SHIFT)
+#else
 #define BOARD_DEFAULT		(BOARD_HIHOPE_RZ_G2M << BOARD_CODE_SHIFT)
+#endif /* RCAR_LSI == RZ_G2H */
 #endif /* BOARD_DEFAULT */
 
 #define BOARD_CODE_MASK		(0xF8U)
@@ -27,9 +35,15 @@
 #define GP5_25_BIT	(0x01U << 25)
 
 #define HM_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define HH_ID	HM_ID
+#define HN_ID	{ 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define EK_ID	HM_ID
 
 const char *g_board_tbl[] = {
 	[BOARD_HIHOPE_RZ_G2M] = "HiHope RZ/G2M",
+	[BOARD_HIHOPE_RZ_G2H] = "HiHope RZ/G2H",
+	[BOARD_HIHOPE_RZ_G2N] = "HiHope RZ/G2N",
+	[BOARD_EK874_RZ_G2E] = "EK874 RZ/G2E",
 	[BOARD_UNKNOWN] = "unknown"
 };
 
@@ -38,8 +52,14 @@
 	static uint8_t board_id = BOARD_ID_UNKNOWN;
 	const uint8_t board_tbl[][8] = {
 		[BOARD_HIHOPE_RZ_G2M] = HM_ID,
+		[BOARD_HIHOPE_RZ_G2H] = HH_ID,
+		[BOARD_HIHOPE_RZ_G2N] = HN_ID,
+		[BOARD_EK874_RZ_G2E] = EK_ID,
 	};
-	uint32_t reg, boardInfo;
+	uint32_t reg;
+#if (RCAR_LSI != RZ_G2E)
+	uint32_t boardInfo;
+#endif /* RCAR_LSI == RZ_G2E */
 
 	if (board_id == BOARD_ID_UNKNOWN) {
 		board_id = BOARD_DEFAULT;
@@ -50,15 +70,28 @@
 	if (*type >= ARRAY_SIZE(board_tbl)) {
 		/* no revision information, set Rev0.0. */
 		*rev = 0;
+		return;
+	}
+
+	reg = mmio_read_32(RCAR_PRR);
+#if (RCAR_LSI == RZ_G2E)
+	if (reg & RCAR_MINOR_MASK) {
+		*rev = 0x30U;
+	} else {
+		*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
+	}
+#else
+	if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
+		*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
 	} else {
-		reg = mmio_read_32(RCAR_PRR);
-		if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
+		reg = mmio_read_32(GPIO_INDT5);
+		if (reg & GP5_25_BIT) {
 			*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
 		} else {
-			boardInfo = mmio_read_32(GPIO_INDT5) &
-				    (GP5_19_BIT | GP5_21_BIT);
+			boardInfo = reg & (GP5_19_BIT | GP5_21_BIT);
 			*rev = (((boardInfo & GP5_19_BIT) >> 14) |
 				((boardInfo & GP5_21_BIT) >> 17)) + 0x30U;
 		}
 	}
+#endif /* RCAR_LSI == RZ_G2E */
 }
diff --git a/drivers/renesas/rzg/board/board.h b/drivers/renesas/rzg/board/board.h
index c0c3d0c..1a76849 100644
--- a/drivers/renesas/rzg/board/board.h
+++ b/drivers/renesas/rzg/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,9 @@
 
 enum rzg2_board_id {
 	BOARD_HIHOPE_RZ_G2M = 0,
+	BOARD_HIHOPE_RZ_G2H,
+	BOARD_HIHOPE_RZ_G2N,
+	BOARD_EK874_RZ_G2E,
 	BOARD_UNKNOWN
 };
 
diff --git a/drivers/renesas/rzg/ddr/boot_init_dram.h b/drivers/renesas/rzg/ddr/boot_init_dram.h
deleted file mode 100644
index 294582f..0000000
--- a/drivers/renesas/rzg/ddr/boot_init_dram.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_H
-#define BOOT_INIT_DRAM_H
-
-extern int32_t rzg_dram_init(void);
-
-#define INITDRAM_OK		0
-#define INITDRAM_NG		0xffffffff
-#define INITDRAM_ERR_I		0xffffffff
-#define INITDRAM_ERR_O		0xfffffffe
-#define INITDRAM_ERR_T		0xfffffff0
-
-#endif /* BOOT_INIT_DRAM_H */
diff --git a/drivers/renesas/rzg/ddr/ddr.mk b/drivers/renesas/rzg/ddr/ddr.mk
deleted file mode 100644
index 7558216..0000000
--- a/drivers/renesas/rzg/ddr/ddr.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
deleted file mode 100644
index 45259e3..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
+++ /dev/null
@@ -1,3700 +0,0 @@
-/*
- * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "boot_init_dram.h"
-#include "boot_init_dram_regdef.h"
-#include "ddr_regdef.h"
-#include "dram_sub_func.h"
-#include "init_dram_tbl_g2m.h"
-#include "micro_delay.h"
-#include "rcar_def.h"
-
-/* load board configuration */
-#include "boot_init_dram_config.c"
-
-#define DDR_BACKUPMODE
-#define FATAL_MSG(x) NOTICE(x)
-
-/* variables */
-#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#ifndef RCAR_AUTO
-#define RCAR_AUTO	99U
-#define RZ_G2M		100U
-
-#define RCAR_CUT_10	0U
-#define RCAR_CUT_11	1U
-#define RCAR_CUT_20	10U
-#define RCAR_CUT_30	20U
-#endif /* RCAR_AUTO */
-#ifndef RCAR_LSI
-#define RCAR_LSI	RCAR_AUTO
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO)
-static uint32_t prr_product;
-static uint32_t prr_cut;
-#else /* RCAR_LSI == RCAR_AUTO */
-#if (RCAR_LSI == RZ_G2M)
-static const uint32_t prr_product = PRR_PRODUCT_M3;
-#endif /* RCAR_LSI == RZ_G2M */
-
-#ifndef RCAR_LSI_CUT
-static uint32_t prr_cut;
-#else /* RCAR_LSI_CUT */
-#if (RCAR_LSI_CUT == RCAR_CUT_10)
-static const uint32_t prr_cut = PRR_PRODUCT_10;
-#elif(RCAR_LSI_CUT == RCAR_CUT_11)
-static const uint32_t prr_cut = PRR_PRODUCT_11;
-#elif(RCAR_LSI_CUT == RCAR_CUT_20)
-static const uint32_t prr_cut = PRR_PRODUCT_20;
-#elif(RCAR_LSI_CUT == RCAR_CUT_30)
-static const uint32_t prr_cut = PRR_PRODUCT_30;
-#endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_LSI == RCAR_AUTO */
-#else /* RCAR_DDR_FIXED_LSI_TYPE */
-static uint32_t prr_product;
-static uint32_t prr_cut;
-#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-
-static const uint32_t *p_ddr_regdef_tbl;
-static uint32_t brd_clk;
-static uint32_t brd_clkdiv;
-static uint32_t brd_clkdiva;
-static uint32_t ddr_mbps;
-static uint32_t ddr_mbpsdiv;
-static uint32_t ddr_tccd;
-static uint32_t ddr_phycaslice;
-static const struct _boardcnf *board_cnf;
-static uint32_t ddr_phyvalid;
-static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
-static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
-static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2U][9U];
-static uint32_t max_density;
-static uint32_t ddr0800_mul;
-static uint32_t ddr_mul;
-static uint32_t DDR_PHY_SLICE_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_G_REGSET_OFS;
-static uint32_t DDR_PI_REGSET_OFS;
-static uint32_t DDR_PHY_SLICE_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_V_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_I_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_G_REGSET_SIZE;
-static uint32_t DDR_PI_REGSET_SIZE;
-static uint32_t DDR_PHY_SLICE_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_V_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_I_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_G_REGSET_NUM;
-static uint32_t DDR_PI_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_I_NUM;
-#define DDR_PHY_REGSET_MAX 128
-#define DDR_PI_REGSET_MAX 320
-static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
-static uint32_t pll3_mode;
-static uint32_t loop_max;
-#ifdef DDR_BACKUPMODE
-uint32_t ddr_backup = DRAM_BOOT_STATUS_COLD;
-/* #define DDR_BACKUPMODE_HALF  */  /* for Half channel(ch0,1 only) */
-#endif
-
-#ifdef DDR_QOS_INIT_SETTING	/*  only for non qos_init */
-#define OPERATING_FREQ			(400U)	/* Mhz */
-#define BASE_SUB_SLOT_NUM		(0x6U)
-#define SUB_SLOT_CYCLE			(0x7EU)	/* 126 */
-#define QOSWT_WTSET0_CYCLE		\
-	((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
-	OPERATING_FREQ)	/* unit:ns */
-
-uint32_t get_refperiod(void)
-{
-	return QOSWT_WTSET0_CYCLE;
-}
-#else /*  DDR_QOS_INIT_SETTING */
-extern uint32_t get_refperiod(void);
-#endif /* DDR_QOS_INIT_SETTING */
-
-#define _reg_PHY_RX_CAL_X_NUM 11U
-static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = {
-	_reg_PHY_RX_CAL_DQ0,
-	_reg_PHY_RX_CAL_DQ1,
-	_reg_PHY_RX_CAL_DQ2,
-	_reg_PHY_RX_CAL_DQ3,
-	_reg_PHY_RX_CAL_DQ4,
-	_reg_PHY_RX_CAL_DQ5,
-	_reg_PHY_RX_CAL_DQ6,
-	_reg_PHY_RX_CAL_DQ7,
-	_reg_PHY_RX_CAL_DM,
-	_reg_PHY_RX_CAL_DQS,
-	_reg_PHY_RX_CAL_FDBK
-};
-
-#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10U
-static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY
-	[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
-	_reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ3_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ4_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ5_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ6_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQ7_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDM_SLAVE_DELAY,
-	_reg_PHY_CLK_WRDQS_SLAVE_DELAY
-};
-
-#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9U
-static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
-	[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
-	_reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY
-};
-
-#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9U
-static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
-	[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
-	_reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY,
-	_reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY
-};
-
-#define _reg_PHY_PAD_TERM_X_NUM 8U
-static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = {
-	_reg_PHY_PAD_FDBK_TERM,
-	_reg_PHY_PAD_DATA_TERM,
-	_reg_PHY_PAD_DQS_TERM,
-	_reg_PHY_PAD_ADDR_TERM,
-	_reg_PHY_PAD_CLK_TERM,
-	_reg_PHY_PAD_CKE_TERM,
-	_reg_PHY_PAD_RST_TERM,
-	_reg_PHY_PAD_CS_TERM
-};
-
-#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10U
-static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X
-	[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
-	_reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR3_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR4_CLK_WR_SLAVE_DELAY,
-	_reg_PHY_ADR5_CLK_WR_SLAVE_DELAY,
-
-	_reg_PHY_GRP_SLAVE_DELAY_0,
-	_reg_PHY_GRP_SLAVE_DELAY_1,
-	_reg_PHY_GRP_SLAVE_DELAY_2,
-	_reg_PHY_GRP_SLAVE_DELAY_3
-};
-
-/* Prototypes */
-static inline uint32_t vch_nxt(uint32_t pos);
-static void cpg_write_32(uint32_t a, uint32_t v);
-static void pll3_control(uint32_t high);
-static inline void dsb_sev(void);
-static void wait_dbcmd(void);
-static void send_dbcmd(uint32_t cmd);
-static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd);
-static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata);
-static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata);
-static inline uint32_t ddr_regdef(uint32_t _regdef);
-static inline uint32_t ddr_regdef_adr(uint32_t _regdef);
-static inline uint32_t ddr_regdef_lsb(uint32_t _regdef);
-static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
-			 uint32_t val);
-static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
-static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
-static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
-static void ddr_setval_ach(uint32_t regdef, uint32_t val);
-static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
-static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
-static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
-static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
-static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
-static uint32_t ddrphy_regif_chk(void);
-static inline void ddrphy_regif_idle(void);
-static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
-			 uint16_t cyc);
-static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
-			 uint16_t *_js2);
-static int16_t _f_scale_adj(int16_t ps);
-static void ddrtbl_load(void);
-static void ddr_config_sub(void);
-static void ddr_config(void);
-static void dbsc_regset(void);
-static void dbsc_regset_post(void);
-static uint32_t dfi_init_start(void);
-static void change_lpddr4_en(uint32_t mode);
-static uint32_t set_term_code(void);
-static void ddr_register_set(void);
-static inline uint32_t wait_freqchgreq(uint32_t assert);
-static inline void set_freqchgack(uint32_t assert);
-static inline void set_dfifrequency(uint32_t freq);
-static uint32_t pll3_freq(uint32_t on);
-static void update_dly(void);
-static uint32_t pi_training_go(void);
-static uint32_t init_ddr(void);
-static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
-static uint32_t wdqdm_man1(void);
-static uint32_t wdqdm_man(void);
-static uint32_t rdqdm_man1(void);
-static uint32_t rdqdm_man(void);
-
-static int32_t _find_change(uint64_t val, uint32_t dir);
-static uint32_t _rx_offset_cal_updn(uint32_t code);
-static uint32_t rx_offset_cal(void);
-static uint32_t rx_offset_cal_hw(void);
-static void adjust_wpath_latency(void);
-
-struct ddrt_data {
-	int32_t init_temp;	/* Initial Temperature (do) */
-	uint32_t init_cal[4U];	/* Initial io-code (4 is for G2H) */
-	uint32_t tcomp_cal[4U];	/* Temp. compensated io-code (4 is for G2H) */
-};
-
-static struct ddrt_data tcal;
-
-static void pvtcode_update(void);
-static void pvtcode_update2(void);
-static void ddr_padcal_tcompensate_getinit(uint32_t override);
-
-#ifndef DDR_FAST_INIT
-static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U];
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
-
-static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
-#endif/* DDR_FAST_INIT */
-
-/* macro for channel selection loop */
-static inline uint32_t vch_nxt(uint32_t pos)
-{
-	uint32_t posn;
-
-	for (posn = pos; posn < DRAM_CH_CNT; posn++) {
-		if ((ddr_phyvalid & (1U << posn)) != 0U) {
-			break;
-		}
-	}
-	return posn;
-}
-
-#define foreach_vch(ch) \
-for (ch = vch_nxt(0U); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1U))
-
-#define foreach_ech(ch) \
-for (ch = 0U; ch < DRAM_CH_CNT; ch++)
-
-/* Printing functions */
-#define MSG_LF(...)
-
-/* clock settings, reset control */
-static void cpg_write_32(uint32_t a, uint32_t v)
-{
-	mmio_write_32(CPG_CPGWPR, ~v);
-	mmio_write_32(a, v);
-}
-
-static void wait_for_pll3_status_bit_turned_on(void)
-{
-	uint32_t data_l;
-
-	do {
-		data_l = mmio_read_32(CPG_PLLECR);
-	} while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
-	dsb_sev();
-}
-
-static void pll3_control(uint32_t high)
-{
-	uint32_t data_l, data_div, data_mul, tmp_div;
-
-	if (high != 0U) {
-		tmp_div = 3999U * brd_clkdiv * (brd_clkdiva + 1U) /
-			(brd_clk * ddr_mul) / 2U;
-		data_mul = ((ddr_mul * tmp_div) - 1U) << 24U;
-		pll3_mode = 1U;
-		loop_max = 2U;
-	} else {
-		tmp_div = 3999U * brd_clkdiv * (brd_clkdiva + 1U) /
-			(brd_clk * ddr0800_mul) / 2U;
-		data_mul = ((ddr0800_mul * tmp_div) - 1U) << 24U;
-		pll3_mode = 0U;
-		loop_max = 8U;
-	}
-
-	switch (tmp_div) {
-	case 1:
-		data_div = 0U;
-		break;
-	case 2:
-	case 3:
-	case 4:
-		data_div = tmp_div;
-		break;
-	default:
-		data_div = 6U;
-		data_mul = (data_mul * tmp_div) / 3U;
-		break;
-	}
-	data_mul = data_mul | (brd_clkdiva << 7);
-
-	/* PLL3 disable */
-	data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
-	cpg_write_32(CPG_PLLECR, data_l);
-	dsb_sev();
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		/* PLL3 DIV resetting(Lowest value:3) */
-		data_l = 0x00030003U | (0xFF80FF80U & mmio_read_32(CPG_FRQCRD));
-		cpg_write_32(CPG_FRQCRD, data_l);
-		dsb_sev();
-
-		/* zb3 clk stop */
-		data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
-		cpg_write_32(CPG_ZB3CKCR, data_l);
-		dsb_sev();
-
-		/* PLL3 enable */
-		data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
-		cpg_write_32(CPG_PLLECR, data_l);
-		dsb_sev();
-
-		wait_for_pll3_status_bit_turned_on();
-
-		/* PLL3 DIV resetting (Highest value:0) */
-		data_l = (0xFF80FF80U & mmio_read_32(CPG_FRQCRD));
-		cpg_write_32(CPG_FRQCRD, data_l);
-		dsb_sev();
-
-		/* DIV SET KICK */
-		data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-		cpg_write_32(CPG_FRQCRB, data_l);
-		dsb_sev();
-
-		/* PLL3 multiplier set */
-		cpg_write_32(CPG_PLL3CR, data_mul);
-		dsb_sev();
-
-		wait_for_pll3_status_bit_turned_on();
-
-		/* PLL3 DIV resetting(Target value) */
-		data_l = (data_div << 16U) | data_div |
-			 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80U);
-		cpg_write_32(CPG_FRQCRD, data_l);
-		dsb_sev();
-
-		/* DIV SET KICK */
-		data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-		cpg_write_32(CPG_FRQCRB, data_l);
-		dsb_sev();
-
-		wait_for_pll3_status_bit_turned_on();
-
-		/* zb3 clk start */
-		data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
-		cpg_write_32(CPG_ZB3CKCR, data_l);
-		dsb_sev();
-	}
-}
-
-/* barrier */
-static inline void dsb_sev(void)
-{
-	__asm__ __volatile__("dsb sy");
-}
-
-/* DDR memory register access */
-static void wait_dbcmd(void)
-{
-	uint32_t data_l;
-	/* dummy read */
-	data_l = mmio_read_32(DBSC_DBCMD);
-	dsb_sev();
-	while (true) {
-		/* wait DBCMD 1=busy, 0=ready */
-		data_l = mmio_read_32(DBSC_DBWAIT);
-		dsb_sev();
-		if ((data_l & 0x00000001U) == 0x00U) {
-			break;
-		}
-	}
-}
-
-static void send_dbcmd(uint32_t cmd)
-{
-	/* dummy read */
-	wait_dbcmd();
-	mmio_write_32(DBSC_DBCMD, cmd);
-	dsb_sev();
-}
-
-static void dbwait_loop(uint32_t wait_loop)
-{
-	uint32_t i;
-
-	for (i = 0U; i < wait_loop; i++) {
-		wait_dbcmd();
-	}
-}
-
-/* DDRPHY register access (raw) */
-static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
-{
-	uint32_t val;
-	uint32_t loop;
-
-	val = 0U;
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
-	dsb_sev();
-
-	while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
-		dsb_sev();
-	}
-	dsb_sev();
-
-	for (loop = 0U; loop < loop_max; loop++) {
-		val = mmio_read_32(DBSC_DBPDRGD(phyno));
-		dsb_sev();
-	}
-
-	return val;
-}
-
-static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
-{
-	uint32_t loop;
-
-	mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
-	dsb_sev();
-	for (loop = 0U; loop < loop_max; loop++) {
-		mmio_read_32(DBSC_DBPDRGA(phyno));
-		dsb_sev();
-	}
-	mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
-	dsb_sev();
-
-	for (loop = 0U; loop < loop_max; loop++) {
-		mmio_read_32(DBSC_DBPDRGD(phyno));
-		dsb_sev();
-	}
-}
-
-static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
-{
-	uint32_t ch;
-	uint32_t loop;
-
-	foreach_vch(ch) {
-		mmio_write_32(DBSC_DBPDRGA(ch), regadd);
-		dsb_sev();
-	}
-
-	foreach_vch(ch) {
-		mmio_write_32(DBSC_DBPDRGD(ch), regdata);
-		dsb_sev();
-	}
-
-	for (loop = 0U; loop < loop_max; loop++) {
-		mmio_read_32(DBSC_DBPDRGD(0));
-		dsb_sev();
-	}
-}
-
-static inline void ddrphy_regif_idle(void)
-{
-	reg_ddrphy_read(0U, ddr_regdef_adr(_reg_PI_INT_STATUS));
-	dsb_sev();
-}
-
-/* DDRPHY register access (field modify) */
-static inline uint32_t ddr_regdef(uint32_t _regdef)
-{
-	return p_ddr_regdef_tbl[_regdef];
-}
-
-static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
-{
-	return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
-}
-
-static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
-{
-	return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
-}
-
-static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
-			 uint32_t val)
-{
-	uint32_t adr;
-	uint32_t lsb;
-	uint32_t len;
-	uint32_t msk;
-	uint32_t tmp;
-	uint32_t regdef;
-
-	regdef = ddr_regdef(_regdef);
-	adr = DDR_REGDEF_ADR(regdef) + 0x80U * slice;
-	len = DDR_REGDEF_LEN(regdef);
-	lsb = DDR_REGDEF_LSB(regdef);
-	if (len == 0x20U) {
-		msk = 0xffffffffU;
-	} else {
-		msk = ((1U << len) - 1U) << lsb;
-	}
-
-	tmp = reg_ddrphy_read(ch, adr);
-	tmp = (tmp & (~msk)) | ((val << lsb) & msk);
-	reg_ddrphy_write(ch, adr, tmp);
-}
-
-static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
-{
-	uint32_t adr;
-	uint32_t lsb;
-	uint32_t len;
-	uint32_t msk;
-	uint32_t tmp;
-	uint32_t regdef;
-
-	regdef = ddr_regdef(_regdef);
-	adr = DDR_REGDEF_ADR(regdef) + 0x80U * slice;
-	len = DDR_REGDEF_LEN(regdef);
-	lsb = DDR_REGDEF_LSB(regdef);
-	if (len == 0x20U) {
-		msk = 0xffffffffU;
-	} else {
-		msk = ((1U << len) - 1U);
-	}
-
-	tmp = reg_ddrphy_read(ch, adr);
-	tmp = (tmp >> lsb) & msk;
-
-	return tmp;
-}
-
-static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
-{
-	ddr_setval_s(ch, 0U, regdef, val);
-}
-
-static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
-{
-	uint32_t ch;
-
-	foreach_vch(ch) {
-	    ddr_setval_s(ch, slice, regdef, val);
-	}
-}
-
-static void ddr_setval_ach(uint32_t regdef, uint32_t val)
-{
-	ddr_setval_ach_s(0U, regdef, val);
-}
-
-static void ddr_setval_ach_as(uint32_t regdef, uint32_t val)
-{
-	uint32_t slice;
-
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		ddr_setval_ach_s(slice, regdef, val);
-	}
-}
-
-static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
-{
-	return ddr_getval_s(ch, 0U, regdef);
-}
-
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
-{
-	uint32_t ch;
-
-	foreach_vch(ch) {
-	    p[ch] = ddr_getval_s(ch, 0U, regdef);
-	}
-	return p[0U];
-}
-
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
-{
-	uint32_t ch, slice;
-	uint32_t *pp;
-
-	pp = p;
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			*pp++ = ddr_getval_s(ch, slice, regdef);
-		}
-	}
-	return p[0U];
-}
-
-/* handling functions for setting ddrphy value table */
-static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
-{
-	uint32_t i;
-
-	for (i = 0U; i < size; i++) {
-		to[i] = from[i];
-	}
-}
-
-static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
-{
-	uint32_t adr;
-	uint32_t lsb;
-	uint32_t len;
-	uint32_t msk;
-	uint32_t tmp;
-	uint32_t adrmsk;
-	uint32_t regdef;
-
-	regdef = ddr_regdef(_regdef);
-	adr = DDR_REGDEF_ADR(regdef);
-	len = DDR_REGDEF_LEN(regdef);
-	lsb = DDR_REGDEF_LSB(regdef);
-	if (len == 0x20U) {
-		msk = 0xffffffffU;
-	} else {
-		msk = ((1U << len) - 1U) << lsb;
-	}
-
-	if (adr < 0x400U) {
-		adrmsk = 0xffU;
-	} else {
-		adrmsk = 0x7fU;
-	}
-
-	tmp = tbl[adr & adrmsk];
-	tmp = (tmp & (~msk)) | ((val << lsb) & msk);
-	tbl[adr & adrmsk] = tmp;
-}
-
-static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
-{
-	uint32_t adr;
-	uint32_t lsb;
-	uint32_t len;
-	uint32_t msk;
-	uint32_t tmp;
-	uint32_t adrmsk;
-	uint32_t regdef;
-
-	regdef = ddr_regdef(_regdef);
-	adr = DDR_REGDEF_ADR(regdef);
-	len = DDR_REGDEF_LEN(regdef);
-	lsb = DDR_REGDEF_LSB(regdef);
-	if (len == 0x20U) {
-		msk = 0xffffffffU;
-	} else {
-		msk = ((1U << len) - 1U);
-	}
-
-	if (adr < 0x400U) {
-		adrmsk = 0xffU;
-	} else {
-		adrmsk = 0x7fU;
-	}
-
-	tmp = tbl[adr & adrmsk];
-	tmp = (tmp >> lsb) & msk;
-
-	return tmp;
-}
-
-/* DDRPHY register access handling */
-static uint32_t ddrphy_regif_chk(void)
-{
-	uint32_t tmp_ach[DRAM_CH_CNT];
-	uint32_t ch;
-	uint32_t err;
-	uint32_t PI_VERSION_CODE;
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		PI_VERSION_CODE = 0x2041U; /* G2M */
-	}
-
-	ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
-	err = 0U;
-	foreach_vch(ch) {
-		if (tmp_ach[ch] != PI_VERSION_CODE) {
-			err = 1U;
-		}
-	}
-	return err;
-}
-
-/* functions and parameters for timing setting */
-struct _jedec_spec1 {
-	uint16_t fx3;
-	uint8_t rlwodbi;
-	uint8_t rlwdbi;
-	uint8_t WL;
-	uint8_t nwr;
-	uint8_t nrtp;
-	uint8_t odtlon;
-	uint8_t MR1;
-	uint8_t MR2;
-};
-
-#define JS1_USABLEC_SPEC_LO 2U
-#define JS1_USABLEC_SPEC_HI 5U
-#define JS1_FREQ_TBL_NUM 8
-#define JS1_MR1(f) (0x04U | ((f) << 4U))
-#define JS1_MR2(f) (0x00U | ((f) << 3U) | (f))
-static const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
-	/* 533.333Mbps */
-	{  800U,  6U,  6U,  4U,  6U,  8U, 0U, JS1_MR1(0U), JS1_MR2(0U) | 0x40U },
-	/* 1066.666Mbps */
-	{ 1600U, 10U, 12U,  8U, 10U,  8U, 0U, JS1_MR1(1U), JS1_MR2(1U) | 0x40U },
-	/* 1600.000Mbps */
-	{ 2400U, 14U, 16U, 12U, 16U,  8U, 6U, JS1_MR1(2U), JS1_MR2(2U) | 0x40U },
-	/* 2133.333Mbps */
-	{ 3200U, 20U, 22U, 10U, 20U,  8U, 4U, JS1_MR1(3U), JS1_MR2(3U) },
-	/* 2666.666Mbps */
-	{ 4000U, 24U, 28U, 12U, 24U, 10U, 4U, JS1_MR1(4U), JS1_MR2(4U) },
-	/* 3200.000Mbps */
-	{ 4800U, 28U, 32U, 14U, 30U, 12U, 6U, JS1_MR1(5U), JS1_MR2(5U) },
-	/* 3733.333Mbps */
-	{ 5600U, 32U, 36U, 16U, 34U, 14U, 6U, JS1_MR1(6U), JS1_MR2(6U) },
-	/* 4266.666Mbps */
-	{ 6400U, 36U, 40U, 18U, 40U, 16U, 8U, JS1_MR1(7U), JS1_MR2(7U) }
-};
-
-struct _jedec_spec2 {
-	uint16_t ps;
-	uint16_t cyc;
-};
-
-#define js2_tsr 0
-#define js2_txp 1
-#define js2_trtp 2
-#define js2_trcd 3
-#define js2_trppb 4
-#define js2_trpab 5
-#define js2_tras 6
-#define js2_twr 7
-#define js2_twtr 8
-#define js2_trrd 9
-#define js2_tppd 10
-#define js2_tfaw 11
-#define js2_tdqsck 12
-#define js2_tckehcmd 13
-#define js2_tckelcmd 14
-#define js2_tckelpd 15
-#define js2_tmrr 16
-#define js2_tmrw 17
-#define js2_tmrd 18
-#define js2_tzqcalns 19
-#define js2_tzqlat 20
-#define js2_tiedly 21
-#define js2_tODTon_min 22
-#define JS2_TBLCNT 23
-
-#define js2_trcpb (JS2_TBLCNT)
-#define js2_trcab (JS2_TBLCNT + 1)
-#define js2_trfcab (JS2_TBLCNT + 2)
-#define JS2_CNT (JS2_TBLCNT + 3)
-
-#ifndef JS2_DERATE
-#define JS2_DERATE 0
-#endif
-static const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
-	{
-/* tSR */	{ 15000, 3 },
-/* tXP */	{ 7500, 3 },
-/* tRTP */	{ 7500, 8 },
-/* tRCD */	{ 18000, 4 },
-/* tRPpb */	{ 18000, 3 },
-/* tRPab */	{ 21000, 3 },
-/* tRAS  */	{ 42000, 3 },
-/* tWR   */	{ 18000, 4 },
-/* tWTR  */	{ 10000, 8 },
-/* tRRD  */	{ 10000, 4 },
-/* tPPD  */	{ 0, 0 },
-/* tFAW  */	{ 40000, 0 },
-/* tDQSCK */	{ 3500, 0 },
-/* tCKEHCMD */	{ 7500, 3 },
-/* tCKELCMD */	{ 7500, 3 },
-/* tCKELPD */	{ 7500, 3 },
-/* tMRR */	{ 0, 8 },
-/* tMRW */	{ 10000, 10 },
-/* tMRD */	{ 14000, 10 },
-/* tZQCALns */	{ 1000 * 10, 0 },
-/* tZQLAT */	{ 30000, 10 },
-/* tIEdly */	{ 12500, 0 },
-/* tODTon_min */{ 1500, 0 }
-	 }, {
-/* tSR */	{ 15000, 3 },
-/* tXP */	{ 7500, 3 },
-/* tRTP */	{ 7500, 8 },
-/* tRCD */	{ 19875, 4 },
-/* tRPpb */	{ 19875, 3 },
-/* tRPab */	{ 22875, 3 },
-/* tRAS */	{ 43875, 3 },
-/* tWR */	{ 18000, 4 },
-/* tWTR */	{ 10000, 8 },
-/* tRRD */	{ 11875, 4 },
-/* tPPD */	{ 0, 0 },
-/* tFAW */	{ 40000, 0 },
-/* tDQSCK */	{ 3600, 0 },
-/* tCKEHCMD */	{ 7500, 3 },
-/* tCKELCMD */	{ 7500, 3 },
-/* tCKELPD */	{ 7500, 3 },
-/* tMRR */	{ 0, 8 },
-/* tMRW */	{ 10000, 10 },
-/* tMRD */	{ 14000, 10 },
-/* tZQCALns */	{ 1000 * 10, 0 },
-/* tZQLAT */	{ 30000, 10 },
-/* tIEdly */	{ 12500, 0 },
-/* tODTon_min */{ 1500, 0 }
-	}
-};
-
-static const uint16_t jedec_spec2_trfc_ab[7] = {
-	/* 4Gb, 6Gb,  8Gb,  12Gb, 16Gb, 24Gb(non), 32Gb(non) */
-	 130U, 180U, 180U, 280U, 280U, 560U, 560U
-};
-
-static uint32_t js1_ind;
-static uint16_t js2[JS2_CNT];
-static uint8_t RL;
-static uint8_t WL;
-
-static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
-			 uint16_t cyc)
-{
-	uint16_t ret = cyc;
-	uint32_t tmp;
-	uint32_t div;
-
-	tmp = (((uint32_t)(ps) + 9U) / 10U) * _ddr_mbps;
-	div = tmp / (200000U * _ddr_mbpsdiv);
-	if (tmp != (div * 200000U * _ddr_mbpsdiv)) {
-		div = div + 1U;
-	}
-
-	if (div > cyc) {
-		ret = (uint16_t)div;
-	}
-
-	return ret;
-}
-
-static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
-			 uint16_t *_js2)
-{
-	int i;
-
-	for (i = 0; i < JS2_TBLCNT; i++) {
-		_js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv,
-				   jedec_spec2[JS2_DERATE][i].ps,
-				   jedec_spec2[JS2_DERATE][i].cyc);
-	}
-
-	_js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb];
-	_js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab];
-}
-
-/* scaler for DELAY value */
-static int16_t _f_scale_adj(int16_t ps)
-{
-	int32_t tmp;
-	/*
-	 * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
-	 *     = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
-	 *     = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
-	 */
-	tmp = (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
-		(int32_t)ddr_mbpsdiv;
-	tmp = (int32_t)tmp / (int32_t)15625;
-
-	return (int16_t)tmp;
-}
-
-static const uint32_t reg_pi_mr1_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR1_DATA_F0_0,
-	 _reg_PI_MR1_DATA_F0_1,
-	 _reg_PI_MR1_DATA_F0_2,
-	 _reg_PI_MR1_DATA_F0_3},
-	{
-	 _reg_PI_MR1_DATA_F1_0,
-	 _reg_PI_MR1_DATA_F1_1,
-	 _reg_PI_MR1_DATA_F1_2,
-	 _reg_PI_MR1_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr2_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR2_DATA_F0_0,
-	 _reg_PI_MR2_DATA_F0_1,
-	 _reg_PI_MR2_DATA_F0_2,
-	 _reg_PI_MR2_DATA_F0_3},
-	{
-	 _reg_PI_MR2_DATA_F1_0,
-	 _reg_PI_MR2_DATA_F1_1,
-	 _reg_PI_MR2_DATA_F1_2,
-	 _reg_PI_MR2_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr3_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR3_DATA_F0_0,
-	 _reg_PI_MR3_DATA_F0_1,
-	 _reg_PI_MR3_DATA_F0_2,
-	 _reg_PI_MR3_DATA_F0_3},
-	{
-	 _reg_PI_MR3_DATA_F1_0,
-	 _reg_PI_MR3_DATA_F1_1,
-	 _reg_PI_MR3_DATA_F1_2,
-	 _reg_PI_MR3_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr11_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR11_DATA_F0_0,
-	 _reg_PI_MR11_DATA_F0_1,
-	 _reg_PI_MR11_DATA_F0_2,
-	 _reg_PI_MR11_DATA_F0_3},
-	{
-	 _reg_PI_MR11_DATA_F1_0,
-	 _reg_PI_MR11_DATA_F1_1,
-	 _reg_PI_MR11_DATA_F1_2,
-	 _reg_PI_MR11_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr12_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR12_DATA_F0_0,
-	 _reg_PI_MR12_DATA_F0_1,
-	 _reg_PI_MR12_DATA_F0_2,
-	 _reg_PI_MR12_DATA_F0_3},
-	{
-	 _reg_PI_MR12_DATA_F1_0,
-	 _reg_PI_MR12_DATA_F1_1,
-	 _reg_PI_MR12_DATA_F1_2,
-	 _reg_PI_MR12_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr14_data_fx_csx[2U][CSAB_CNT] = {
-	{
-	 _reg_PI_MR14_DATA_F0_0,
-	 _reg_PI_MR14_DATA_F0_1,
-	 _reg_PI_MR14_DATA_F0_2,
-	 _reg_PI_MR14_DATA_F0_3},
-	{
-	 _reg_PI_MR14_DATA_F1_0,
-	 _reg_PI_MR14_DATA_F1_1,
-	 _reg_PI_MR14_DATA_F1_2,
-	 _reg_PI_MR14_DATA_F1_3}
-};
-
-/*
- * regif pll w/a   ( REGIF G2M WA )
- */
-static void regif_pll_wa(void)
-{
-	uint32_t ch;
-	uint32_t reg_ofs;
-
-	/*  PLL setting for PHY : G2M */
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
-			   (0x5064U <<
-			    ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
-
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
-			   (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-			     _reg_PHY_PLL_CTRL_TOP) << 16) |
-			   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					 _reg_PHY_PLL_CTRL));
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA),
-			   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					 _reg_PHY_PLL_CTRL_CA));
-
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
-			   (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-			     _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) |
-			   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					 _reg_PHY_LP4_BOOT_PLL_CTRL));
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
-			   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					 _reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
-
-	reg_ofs = ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS;
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
-			   _cnf_DDR_PHY_ADR_G_REGSET[reg_ofs]);
-
-	/* protect register interface */
-	ddrphy_regif_idle();
-	pll3_control(0U);
-
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
-			   (0x01U << ddr_regdef_lsb(_reg_PHY_DLL_RST_EN)));
-	ddrphy_regif_idle();
-
-	/*
-	 * init start
-	 * dbdficnt0:
-	 * dfi_dram_clk_disable=1
-	 * dfi_frequency = 0
-	 * freq_ratio = 01 (2:1)
-	 * init_start =0
-	 */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10U);
-	}
-	dsb_sev();
-
-	/*
-	 * dbdficnt0:
-	 * dfi_dram_clk_disable=1
-	 * dfi_frequency = 0
-	 * freq_ratio = 01 (2:1)
-	 * init_start =1
-	 */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11U);
-	}
-	dsb_sev();
-
-	foreach_ech(ch) {
-		if ((board_cnf->phyvalid & BIT(ch)) != 0U) {
-			while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1fU) != 0x1fU) {
-			}
-		}
-	}
-	dsb_sev();
-}
-
-/* load table data into DDR registers */
-static void ddrtbl_load(void)
-{
-	uint32_t i;
-	uint32_t slice;
-	uint32_t csab;
-	uint32_t adr;
-	uint32_t data_l;
-	uint32_t tmp[3];
-	uint16_t dataS;
-
-	/*
-	 * TIMING REGISTERS
-	 * search jedec_spec1 index
-	 */
-	for (i = JS1_USABLEC_SPEC_LO; i < (uint32_t)JS1_FREQ_TBL_NUM - 1U; i++) {
-		if ((js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) != 0U) {
-			break;
-		}
-	}
-	if (i > JS1_USABLEC_SPEC_HI) {
-		js1_ind = JS1_USABLEC_SPEC_HI;
-	} else {
-		js1_ind = i;
-	}
-
-	if (board_cnf->dbi_en != 0U) {
-		RL = js1[js1_ind].rlwdbi;
-	} else {
-		RL = js1[js1_ind].rlwodbi;
-	}
-
-	WL = js1[js1_ind].WL;
-
-	/* calculate jedec_spec2 */
-	_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
-
-	/* PREPARE TBL */
-	if (prr_product == PRR_PRODUCT_M3) {
-		/*  G2M */
-		_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
-			 DDR_PHY_SLICE_REGSET_G2M, DDR_PHY_SLICE_REGSET_NUM_G2M);
-		_tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
-			 DDR_PHY_ADR_V_REGSET_G2M, DDR_PHY_ADR_V_REGSET_NUM_G2M);
-		_tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
-			 DDR_PHY_ADR_I_REGSET_G2M, DDR_PHY_ADR_I_REGSET_NUM_G2M);
-		_tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
-			 DDR_PHY_ADR_G_REGSET_G2M, DDR_PHY_ADR_G_REGSET_NUM_G2M);
-		_tblcopy(_cnf_DDR_PI_REGSET,
-			 DDR_PI_REGSET_G2M, DDR_PI_REGSET_NUM_G2M);
-
-		DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_G2M;
-		DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_G2M;
-		DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_G2M;
-		DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_G2M;
-		DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_G2M;
-		DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_G2M;
-		DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_G2M;
-		DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_G2M;
-		DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_G2M;
-		DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_G2M;
-		DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_G2M;
-		DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_G2M;
-		DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_G2M;
-		DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_G2M;
-		DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_G2M;
-
-		DDR_PHY_ADR_I_NUM = 2U;
-	}
-
-	/* on fly gate adjust */
-	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
-			      _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
-	}
-
-	/* Adjust PI parameters */
-#ifdef _def_LPDDR4_ODT
-	for (i = 0U; i < 2U; i++) {
-		for (csab = 0U; csab < CSAB_CNT; csab++) {
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr11_data_fx_csx[i][csab],
-				      _def_LPDDR4_ODT);
-		}
-	}
-#endif /* _def_LPDDR4_ODT */
-
-#ifdef _def_LPDDR4_VREFCA
-	for (i = 0U; i < 2U; i++) {
-		for (csab = 0U; csab < CSAB_CNT; csab++) {
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr12_data_fx_csx[i][csab],
-				      _def_LPDDR4_VREFCA);
-		}
-	}
-#endif /* _def_LPDDR4_VREFCA */
-
-	if ((js2[js2_tiedly]) >= 0x0eU) {
-		dataS = 0x0eU;
-	} else {
-		dataS = js2[js2_tiedly];
-	}
-
-	ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
-	ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
-		      (dataS - 2U));
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
-
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD) != 0U) {
-		data_l = WL - 1U;
-	} else {
-		data_l = WL;
-	}
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2U);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
-
-	if (board_cnf->dbi_en != 0U) {
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
-			      0x01U);
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
-			      _reg_PHY_WDQLVL_DATADM_MASK, 0x000U);
-	} else {
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
-			      0x00U);
-		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
-			      _reg_PHY_WDQLVL_DATADM_MASK, 0x100U);
-	}
-
-	tmp[0] = js1[js1_ind].MR1;
-	tmp[1] = js1[js1_ind].MR2;
-	data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
-	if (board_cnf->dbi_en != 0U) {
-		tmp[2] = data_l | 0xc0U;
-	} else {
-		tmp[2] = data_l & (~0xc0U);
-	}
-
-	for (i = 0U; i < 2U; i++) {
-		for (csab = 0U; csab < CSAB_CNT; csab++) {
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
-			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
-		}
-	}
-
-	/* DDRPHY INT START */
-	regif_pll_wa();
-	dbwait_loop(5U);
-
-	/* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
-	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U);
-
-	/* SET DATA SLICE TABLE */
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		adr =
-		    DDR_PHY_SLICE_REGSET_OFS +
-		    DDR_PHY_SLICE_REGSET_SIZE * slice;
-		for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) {
-			reg_ddrphy_write_a(adr + i,
-					   _cnf_DDR_PHY_SLICE_REGSET[i]);
-		}
-	}
-
-	/* SET ADR SLICE TABLE */
-	adr = DDR_PHY_ADR_V_REGSET_OFS;
-	for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
-		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
-	}
-
-	if ((prr_product == PRR_PRODUCT_M3) &&
-	    ((0x00ffffffU & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40U))
-	    != 0x00U)) {
-		adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
-		for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
-			reg_ddrphy_write_a(adr + i,
-					   _cnf_DDR_PHY_ADR_V_REGSET[i]);
-		}
-		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
-			      _reg_PHY_ADR_DISABLE, 0x02);
-		DDR_PHY_ADR_I_NUM -= 1U;
-		ddr_phycaslice = 1U;
-
-#ifndef _def_LPDDR4_ODT
-		for (i = 0U; i < 2U; i++) {
-			for (csab = 0U; csab < CSAB_CNT; csab++) {
-				ddrtbl_setval(_cnf_DDR_PI_REGSET,
-					      reg_pi_mr11_data_fx_csx[i][csab],
-					      0x66);
-			}
-		}
-#endif/* _def_LPDDR4_ODT */
-	} else {
-		ddr_phycaslice = 0U;
-	}
-
-	if (DDR_PHY_ADR_I_NUM > 0U) {
-		for (slice = 0U; slice < DDR_PHY_ADR_I_NUM; slice++) {
-			adr =
-			    DDR_PHY_ADR_I_REGSET_OFS +
-			    DDR_PHY_ADR_I_REGSET_SIZE * slice;
-			for (i = 0U; i < DDR_PHY_ADR_I_REGSET_NUM; i++) {
-				reg_ddrphy_write_a(adr + i,
-						   _cnf_DDR_PHY_ADR_I_REGSET
-						   [i]);
-			}
-		}
-	}
-
-	/* SET ADRCTRL SLICE TABLE */
-	adr = DDR_PHY_ADR_G_REGSET_OFS;
-	for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
-		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
-	}
-
-	/* SET PI REGISTERS */
-	adr = DDR_PI_REGSET_OFS;
-	for (i = 0U; i < DDR_PI_REGSET_NUM; i++) {
-		reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
-	}
-}
-
-/* CONFIGURE DDR REGISTERS */
-static void ddr_config_sub(void)
-{
-	const uint32_t _par_CALVL_DEVICE_MAP = 1U;
-	uint8_t high_byte[SLICE_CNT];
-	uint32_t ch, slice;
-	uint32_t data_l;
-	uint32_t tmp;
-	uint32_t i;
-
-	foreach_vch(ch) {
-		/* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			high_byte[slice] =
-			    (board_cnf->ch[ch].dqs_swap >> (4U * slice)) % 2U;
-			ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
-				     board_cnf->ch[ch].dq_swap[slice]);
-			ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
-				     board_cnf->ch[ch].dm_swap[slice]);
-			if (high_byte[slice] != 0U) {
-				/* HIGHER 16 BYTE */
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_CALVL_VREF_DRIVING_SLICE,
-					     0x00);
-			} else {
-				/* LOWER 16 BYTE */
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_CALVL_VREF_DRIVING_SLICE,
-					     0x01);
-			}
-		}
-
-		/* BOARD SETTINGS (CA,ADDR_SEL) */
-		data_l = (0x00ffffffU & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
-			0x00888888U;
-
-		/* --- ADR_CALVL_SWIZZLE --- */
-		if (prr_product == PRR_PRODUCT_M3) {
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
-				   0x00000000);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
-				   0x00000000);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
-				   _par_CALVL_DEVICE_MAP);
-		} else {
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
-			ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
-				   _par_CALVL_DEVICE_MAP);
-		}
-
-		/* --- ADR_ADDR_SEL --- */
-		data_l = 0U;
-		tmp = board_cnf->ch[ch].ca_swap;
-		for (i = 0U; i < 6U; i++) {
-			data_l |= ((tmp & 0x0fU) << (i * 5U));
-			tmp = tmp >> 4;
-		}
-		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
-		if (ddr_phycaslice == 1U) {
-			/* ----------- adr slice2 swap ----------- */
-			tmp  = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
-			data_l = (tmp & 0x00ffffffU) | 0x00888888U;
-
-			/* --- ADR_CALVL_SWIZZLE --- */
-			if (prr_product == PRR_PRODUCT_M3) {
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE0_0,
-					     data_l);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE1_0,
-					     0x00000000);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE0_1,
-					     data_l);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE1_1,
-					     0x00000000);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_DEVICE_MAP,
-					     _par_CALVL_DEVICE_MAP);
-			} else {
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE0,
-					     data_l);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_ADR_CALVL_SWIZZLE1,
-					     0x00000000);
-				ddr_setval_s(ch, 2,
-					     _reg_PHY_CALVL_DEVICE_MAP,
-					     _par_CALVL_DEVICE_MAP);
-			}
-
-			/* --- ADR_ADDR_SEL --- */
-			data_l = 0U;
-			for (i = 0U; i < 6U; i++) {
-				data_l |= ((tmp & 0x0fU) << (i * 5U));
-				tmp = tmp >> 4U;
-			}
-
-			ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
-		}
-
-		/* BOARD SETTINGS (BYTE_ORDER_SEL) */
-		if (prr_product == PRR_PRODUCT_M3) {
-			/* --- DATA_BYTE_SWAP --- */
-			data_l = 0U;
-			tmp = board_cnf->ch[ch].dqs_swap;
-			for (i = 0U; i < 4U; i++) {
-				data_l |= ((tmp & 0x03U) << (i * 2U));
-				tmp = tmp >> 4U;
-			}
-		} else {
-			/* --- DATA_BYTE_SWAP --- */
-			data_l = board_cnf->ch[ch].dqs_swap;
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
-				   (data_l) & 0x0fU);
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
-				   (data_l >> 4U * 1U) & 0x0fU);
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
-				   (data_l >> 4U * 2U) & 0x0fU);
-			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
-				   (data_l >> 4U * 3U) & 0x0fU);
-
-			ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00U);
-		}
-		ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
-	}
-}
-
-static void ddr_config(void)
-{
-	uint32_t num_cacs_dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM;
-	uint32_t reg_ofs, dly;
-	uint32_t ch, slice;
-	uint32_t data_l;
-	uint32_t tmp;
-	uint32_t i;
-	int8_t _adj;
-	int16_t adj;
-	uint32_t dq;
-	union {
-		uint32_t ui32[4];
-		uint8_t ui8[16];
-	} patt;
-	uint16_t patm;
-
-	/* configure ddrphy registers */
-	ddr_config_sub();
-
-	/* WDQ_USER_PATT */
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			patm = 0U;
-			for (i = 0U; i < 16U; i++) {
-				tmp = board_cnf->ch[ch].wdqlvl_patt[i];
-				patt.ui8[i] = tmp & 0xffU;
-				if ((tmp & 0x100U) != 0U) {
-					patm |= (1U << (uint16_t)i);
-				}
-			}
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
-				     patt.ui32[0]);
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
-				     patt.ui32[1]);
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
-				     patt.ui32[2]);
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
-				     patt.ui32[3]);
-			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
-		}
-	}
-
-	/* CACS DLY */
-	data_l = board_cnf->cacs_dly + (uint32_t)_f_scale_adj(board_cnf->cacs_dly_adj);
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
-	foreach_vch(ch) {
-		for (i = 0U; i < num_cacs_dly - 4U; i++) {
-			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
-			dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
-			ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, dly,
-				      data_l + (uint32_t)adj);
-			reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_V_REGSET_OFS;
-			reg_ddrphy_write(ch, ddr_regdef_adr(dly),
-					_cnf_DDR_PHY_ADR_V_REGSET[reg_ofs]);
-		}
-
-		for (i = num_cacs_dly - 4U; i < num_cacs_dly; i++) {
-			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
-			dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
-			ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, dly,
-				      data_l + (uint32_t)adj);
-			reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_G_REGSET_OFS;
-			reg_ddrphy_write(ch, ddr_regdef_adr(dly),
-					_cnf_DDR_PHY_ADR_G_REGSET[reg_ofs]);
-		}
-
-		if (ddr_phycaslice == 1U) {
-			for (i = 0U; i < 6U; i++) {
-				adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + num_cacs_dly]);
-				dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
-				ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, dly,
-					      data_l + (uint32_t)adj);
-				reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_V_REGSET_OFS;
-				reg_ddrphy_write(ch, ddr_regdef_adr(dly) + 0x0100U,
-						 _cnf_DDR_PHY_ADR_V_REGSET[reg_ofs]);
-			}
-		}
-	}
-
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
-
-	/* WDQDM DLY */
-	data_l = board_cnf->dqdm_dly_w;
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			for (i = 0U; i <= 8U; i++) {
-				dq = slice * 8U + (uint32_t)i;
-				if (i == 8U) {
-					_adj = board_cnf->ch[ch].dm_adj_w[slice];
-				} else {
-					_adj = board_cnf->ch[ch].dq_adj_w[dq];
-				}
-				adj = _f_scale_adj(_adj);
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
-					     data_l + (uint32_t)adj);
-			}
-		}
-	}
-
-	/* RDQDM DLY */
-	data_l = board_cnf->dqdm_dly_r;
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			for (i = 0U; i <= 8U; i++) {
-				dq = slice * 8U + (uint32_t)i;
-				if (i == 8U) {
-					_adj = board_cnf->ch[ch].dm_adj_r[slice];
-				} else {
-					_adj = board_cnf->ch[ch].dq_adj_r[dq];
-				}
-				adj = _f_scale_adj(_adj);
-				dly = _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i];
-				ddr_setval_s(ch, slice, dly, data_l + (uint32_t)adj);
-				dly = _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i];
-				ddr_setval_s(ch, slice, dly, data_l + (uint32_t)adj);
-			}
-		}
-	}
-}
-
-/* DBSC register setting functions */
-static void dbsc_regset_pre(void)
-{
-	uint32_t ch, csab;
-	uint32_t data_l;
-
-	/* PRIMARY SETTINGS */
-	/* LPDDR4, BL=16, DFI interface */
-	mmio_write_32(DBSC_DBKIND, 0x0000000aU);
-	mmio_write_32(DBSC_DBBL, 0x00000002U);
-	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001U);
-
-	/* FREQRATIO=2 */
-	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002U);
-
-	/*
-	 * DRAM SIZE REGISTER:
-	 * set all ranks as density=0(4Gb) for PHY initialization
-	 */
-	foreach_vch(ch) {
-		for (csab = 0U; csab < 4U; csab++) {
-			mmio_write_32(DBSC_DBMEMCONF(ch, csab),
-				      DBMEMCONF_REGD(0U));
-		}
-	}
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		data_l = 0xe4e4e4e4U;
-		foreach_ech(ch) {
-			if ((ddr_phyvalid & (1U << ch)) != 0U) {
-				data_l = (data_l & (~(0x000000FFU << (ch * 8U))))
-					| (((board_cnf->ch[ch].dqs_swap & 0x0003U)
-					| ((board_cnf->ch[ch].dqs_swap & 0x0030U) >> 2U)
-					| ((board_cnf->ch[ch].dqs_swap & 0x0300U) >> 4U)
-					| ((board_cnf->ch[ch].dqs_swap & 0x3000U) >> 6U))
-					   << (ch * 8U));
-			}
-		}
-		mmio_write_32(DBSC_DBBSWAP, data_l);
-	}
-}
-
-static void dbsc_regset(void)
-{
-	int32_t i;
-	uint32_t ch;
-	uint32_t data_l;
-	uint32_t data_l2;
-	uint32_t wdql;
-	uint32_t dqenltncy;
-	uint32_t dql;
-	uint32_t dqienltncy;
-	uint32_t wrcslat;
-	uint32_t wrcsgap;
-	uint32_t rdcslat;
-	uint32_t rdcsgap;
-	uint32_t scfctst0_act_act;
-	uint32_t scfctst0_rda_act;
-	uint32_t scfctst0_wra_act;
-	uint32_t scfctst0_pre_act;
-	uint32_t scfctst1_rd_wr;
-	uint32_t scfctst1_wr_rd;
-	uint32_t scfctst1_act_rd_wr;
-	uint32_t scfctst1_asyncofs;
-	uint32_t dbschhrw1_sctrfcab;
-
-	/* RFC */
-	js2[js2_trfcab] =
-	    _f_scale(ddr_mbps, ddr_mbpsdiv,
-		     jedec_spec2_trfc_ab[max_density] * 1000U, 0U);
-	/* DBTR0.CL  : RL */
-	mmio_write_32(DBSC_DBTR(0), RL);
-
-	/* DBTR1.CWL : WL */
-	mmio_write_32(DBSC_DBTR(1), WL);
-
-	/* DBTR2.AL  : 0 */
-	mmio_write_32(DBSC_DBTR(2), 0U);
-
-	/* DBTR3.TRCD: tRCD */
-	mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
-
-	/* DBTR4.TRPA,TRP: tRPab,tRPpb */
-	mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
-
-	/* DBTR5.TRC : use tRCpb */
-	mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
-
-	/* DBTR6.TRAS : tRAS */
-	mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
-
-	/* DBTR7.TRRD : tRRD */
-	mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
-
-	/* DBTR8.TFAW : tFAW */
-	mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
-
-	/* DBTR9.TRDPR : tRTP */
-	mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
-
-	/* DBTR10.TWR : nWR */
-	mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
-
-	/*
-	 * DBTR11.TRDWR : RL +  BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
-	 * odtlon + tDQSCK - tODTon,min +
-	 * PCB delay (out+in) + tPHY_ODToff
-	 */
-	mmio_write_32(DBSC_DBTR(11),
-		      RL + (16U / 2U) + 1U + 2U - js1[js1_ind].odtlon +
-		      js2[js2_tdqsck] - js2[js2_tODTon_min] +
-		      _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
-
-	/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
-	data_l = WL + 1U + (16U / 2U) + js2[js2_twtr];
-	mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
-
-	/* DBTR13.TRFCAB : tRFCab */
-	mmio_write_32(DBSC_DBTR(13), js2[js2_trfcab]);
-
-	/* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
-	mmio_write_32(DBSC_DBTR(14),
-		      (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
-
-	/* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
-	mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
-
-	/* DBTR16 */
-	/* WDQL : tphy_wrlat + tphy_wrdata */
-	wdql = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1);
-	/* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0
-	 *             tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0
-	 */
-	dqenltncy = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1);
-	/* DQL : tphy_rdlat + trdata_en */
-	/* it is not important for dbsc */
-	dql = RL + 16U;
-	/* DQIENLTNCY : trdata_en */
-	dqienltncy = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1U;
-	mmio_write_32(DBSC_DBTR(16),
-		      (dqienltncy << 24) | (dql << 16) | (dqenltncy << 8) | wdql);
-
-	/* DBTR24 */
-	/* WRCSLAT = WRLAT -5 */
-	wrcslat = wdql - 5U;
-	/* WRCSGAP = 5 */
-	wrcsgap = 5U;
-	/* RDCSLAT = RDLAT_ADJ +2 */
-	rdcslat = dqienltncy;
-	if (prr_product != PRR_PRODUCT_M3) {
-		rdcslat += 2U;
-	}
-	/* RDCSGAP = 6 */
-	rdcsgap = 6U;
-	if (prr_product == PRR_PRODUCT_M3) {
-		rdcsgap = 4U;
-	}
-	mmio_write_32(DBSC_DBTR(24),
-		      (rdcsgap << 24) | (rdcslat << 16) | (wrcsgap << 8) | wrcslat);
-
-	/* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
-	mmio_write_32(DBSC_DBTR(17),
-		      (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
-
-	/* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
-	mmio_write_32(DBSC_DBTR(18), 0);
-
-	/* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */
-	mmio_write_32(DBSC_DBTR(19), 0);
-
-	/* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
-	data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
-	mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
-
-	/* DBTR21.TCCD */
-	/* DBTR23.TCCD */
-	if (ddr_tccd == 8U) {
-		data_l = 8U;
-		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
-		mmio_write_32(DBSC_DBTR(23), 0x00000002);
-	} else if (ddr_tccd <= 11U) {
-		data_l = 11U;
-		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
-		mmio_write_32(DBSC_DBTR(23), 0x00000000);
-	} else {
-		data_l = ddr_tccd;
-		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
-		mmio_write_32(DBSC_DBTR(23), 0x00000000);
-	}
-
-	/* DBTR22.ZQLAT : */
-	data_l = js2[js2_tzqcalns] * 100U;	/*  1000 * 1000 ps */
-	data_l = (data_l << 16U) | (js2[js2_tzqlat] + 24U + 20U);
-	mmio_write_32(DBSC_DBTR(22), data_l);
-
-	/* DBTR25 : do not use in LPDDR4 */
-	mmio_write_32(DBSC_DBTR(25), 0U);
-
-	/*
-	 * DBRNK :
-	 * DBSC_DBRNK2 rkrr
-	 * DBSC_DBRNK3 rkrw
-	 * DBSC_DBRNK4 rkwr
-	 * DBSC_DBRNK5 rkww
-	 */
-#define _par_DBRNK_VAL	(0x7007U)
-
-	for (i = 0; i < 4; i++) {
-		data_l = (_par_DBRNK_VAL >> ((uint32_t)i * 4U)) & 0x0fU;
-		data_l2 = 0U;
-		foreach_vch(ch) {
-			data_l2 = data_l2 | (data_l << (4U * ch));
-		}
-		mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
-	}
-	mmio_write_32(DBSC_DBADJ0, 0x00000000U);
-
-	/* timing registers for scheduler */
-	/* SCFCTST0 */
-	/* SCFCTST0 ACT-ACT */
-	scfctst0_act_act = js2[js2_trcpb] * 800UL * ddr_mbpsdiv / ddr_mbps;
-	/* SCFCTST0 RDA-ACT */
-	scfctst0_rda_act = ((16U / 2U) + js2[js2_trtp] - 8U +
-		  js2[js2_trppb]) * 800UL * ddr_mbpsdiv / ddr_mbps;
-	/* SCFCTST0 WRA-ACT */
-	scfctst0_wra_act = (WL + 1U + (16U / 2U) +
-		  js1[js1_ind].nwr) * 800UL * ddr_mbpsdiv / ddr_mbps;
-	/* SCFCTST0 PRE-ACT */
-	scfctst0_pre_act = js2[js2_trppb];
-	mmio_write_32(DBSC_SCFCTST0,
-		      (scfctst0_act_act << 24) | (scfctst0_rda_act << 16) |
-		      (scfctst0_wra_act << 8) | scfctst0_pre_act);
-
-	/* SCFCTST1 */
-	/* SCFCTST1 RD-WR */
-	scfctst1_rd_wr = (mmio_read_32(DBSC_DBTR(11)) & 0xffU) * 800UL * ddr_mbpsdiv /
-		ddr_mbps;
-	/* SCFCTST1 WR-RD */
-	scfctst1_wr_rd = (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800UL * ddr_mbpsdiv /
-		ddr_mbps;
-	/* SCFCTST1 ACT-RD/WR */
-	scfctst1_act_rd_wr = js2[js2_trcd] * 800UL * ddr_mbpsdiv / ddr_mbps;
-	/* SCFCTST1 ASYNCOFS */
-	scfctst1_asyncofs = 12U;
-	mmio_write_32(DBSC_SCFCTST1,
-		      (scfctst1_rd_wr << 24) | (scfctst1_wr_rd << 16) |
-		      (scfctst1_act_rd_wr << 8) | scfctst1_asyncofs);
-
-	/* DBSCHRW1 */
-	/* DBSCHRW1 SCTRFCAB */
-	dbschhrw1_sctrfcab = js2[js2_trfcab] * 800UL * ddr_mbpsdiv / ddr_mbps;
-	data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000U) >> 16) +
-		  (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) +
-		  (0x28U * 2U)) * 400U * 2U * ddr_mbpsdiv / ddr_mbps + 7U;
-	if (dbschhrw1_sctrfcab < data_l) {
-		dbschhrw1_sctrfcab = data_l;
-	}
-
-	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
-		mmio_write_32(DBSC_DBSCHRW1, dbschhrw1_sctrfcab +
-			      ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) *
-			       400U * 2U * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps - 3U);
-	} else {
-		mmio_write_32(DBSC_DBSCHRW1, dbschhrw1_sctrfcab +
-			      ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) *
-			       400U * 2U * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps);
-	}
-
-	/* QOS and CAM */
-#ifdef DDR_QOS_INIT_SETTING	/*  only for non qos_init */
-	/* wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
-	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218U);
-	/* 0(fillunit),8(dirtymax),4(dirtymin) */
-	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);
-	/* stop_tolerance */
-	mmio_write_32(DBSC_DBSCHRW0, 0x22421111U);
-	/* rd-wr/wr-rd toggle priority */
-	mmio_write_32(DBSC_SCFCTST2, 0x012F1123U);
-	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001U);
-	mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037U);
-
-	/* QoS Settings */
-	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
-	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
-	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U);
-	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U);
-	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U);
-	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
-	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U);
-	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U);
-	mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U);
-	mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
-	mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
-	mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U);
-	mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U);
-	mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U);
-	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U);
-	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
-	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
-	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
-	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
-	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U);
-	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U);
-	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U);
-	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U);
-	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U);
-
-	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* DDR_QOS_INIT_SETTING */
-
-	/* resrdis */
-	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001U);
-}
-
-static void dbsc_regset_post(void)
-{
-	uint32_t slice, rdlat_max, rdlat_min;
-	uint32_t ch, cs;
-	uint32_t data_l;
-	uint32_t srx;
-
-	rdlat_max = 0U;
-	rdlat_min = 0xffffU;
-	foreach_vch(ch) {
-		for (cs = 0U; cs < CS_CNT; cs++) {
-			if ((ch_have_this_cs[cs] & (1U << ch)) != 0U) {
-				for (slice = 0U; slice < SLICE_CNT; slice++) {
-					ddr_setval_s(ch, slice,
-						     _reg_PHY_PER_CS_TRAINING_INDEX,
-						     cs);
-					data_l = ddr_getval_s(ch, slice,
-							      _reg_PHY_RDDQS_LATENCY_ADJUST);
-					if (data_l > rdlat_max) {
-						rdlat_max = data_l;
-					}
-					if (data_l < rdlat_min) {
-						rdlat_min = data_l;
-					}
-				}
-			}
-		}
-	}
-
-	mmio_write_32(DBSC_DBTR(24),
-		      ((rdlat_max + 2U) << 24) +
-		      ((rdlat_max + 2U) << 16) +
-		      mmio_read_32(DBSC_DBTR(24)));
-
-	/* set ddr density information */
-	foreach_ech(ch) {
-		for (cs = 0U; cs < CS_CNT; cs++) {
-			if (ddr_density[ch][cs] == 0xffU) {
-				mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U);
-			} else {
-				mmio_write_32(DBSC_DBMEMCONF(ch, cs),
-					      DBMEMCONF_REGD(ddr_density[ch]
-							     [cs]));
-			}
-		}
-		mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000U);
-		mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000U);
-	}
-
-	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010U);
-
-	/* set DBI */
-	if (board_cnf->dbi_en != 0U) {
-		mmio_write_32(DBSC_DBDBICNT, 0x00000003U);
-	}
-
-	/* set REFCYCLE */
-	data_l = (get_refperiod()) * ddr_mbps / 2000U / ddr_mbpsdiv;
-	mmio_write_32(DBSC_DBRFCNF1, 0x00080000U | (data_l & 0x0000ffffU));
-	mmio_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS);
-
-#if RCAR_REWT_TRAINING != 0
-	/* Periodic-WriteDQ Training seeting */
-	if ((prr_product == PRR_PRODUCT_M3) &&
-	    (prr_cut == PRR_PRODUCT_10)) {
-		/* G2M Ver.1.0 not support */
-	} else {
-		/* G2M Ver.1.1 or later */
-		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U);
-
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04U);
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0FU);
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50U);
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300U);
-
-		ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP,
-			       ddrtbl_getval(_cnf_DDR_PI_REGSET,
-					     _reg_PI_WDQLVL_CS_MAP));
-		ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1fU);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00U);
-		ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01U);
-		ddr_setval_ach(_reg_PI_TREF_F0, 0x0000U);
-		ddr_setval_ach(_reg_PI_TREF_F1, 0x0000U);
-		ddr_setval_ach(_reg_PI_TREF_F2, 0x0000U);
-
-		if (prr_product == PRR_PRODUCT_M3) {
-			ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02U);
-		} else {
-			ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02U);
-		}
-		ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01U);
-
-		/* DFI_PHYMSTR_ACK , WTmode setting */
-		/* DFI_PHYMSTR_ACK: WTmode =b'01 */
-		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U);
-	}
-#endif /* RCAR_REWT_TRAINING */
-	/* periodic dram zqcal enable */
-	mmio_write_32(DBSC_DBCALCNF, 0x01000010U);
-
-	/* periodic phy ctrl update enable */
-	if ((prr_product == PRR_PRODUCT_M3) &&
-	    (prr_cut < PRR_PRODUCT_30)) {
-		/* non : G2M Ver.1.x not support */
-	} else {
-		mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001U);
-	}
-
-#ifdef DDR_BACKUPMODE
-	/* SRX */
-	srx = 0x0A840001U; /* for All channels */
-	if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
-#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
-		NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
-		srx = 0x0A040001U;
-#endif /* DDR_BACKUPMODE_HALF */
-		send_dbcmd(srx);
-	}
-#endif /* DDR_BACKUPMODE */
-
-	/* set Auto Refresh */
-	mmio_write_32(DBSC_DBRFEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != 0
-	/* Periodic WriteDQ Traning */
-	if ((prr_product == PRR_PRODUCT_M3) &&
-	    (prr_cut == PRR_PRODUCT_10)) {
-		/* non : G2M Ver.1.0 not support */
-	} else {
-		/* G2M Ver.1.1 or later */
-		ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100U);
-	}
-#endif /* RCAR_REWT_TRAINING */
-
-	/* dram access enable */
-	mmio_write_32(DBSC_DBACEN, 0x00000001U);
-
-	MSG_LF(__func__ "(done)");
-}
-
-/* DFI_INIT_START */
-static uint32_t dfi_init_start(void)
-{
-	uint32_t ch;
-	uint32_t phytrainingok;
-	uint32_t retry;
-	uint32_t data_l;
-	uint32_t ret = 0U;
-	const uint32_t RETRY_MAX = 0x10000U;
-
-	ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02U);
-	dsb_sev();
-	ddrphy_regif_idle();
-
-	/* dll_rst negate */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01U);
-	}
-	dsb_sev();
-
-	/* wait init_complete */
-	phytrainingok = 0U;
-	retry = 0U;
-	while (retry++ < RETRY_MAX) {
-		foreach_vch(ch) {
-			data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
-			if (data_l & 0x00000001U)  {
-				phytrainingok |= (1U << ch);
-			}
-		}
-		dsb_sev();
-		if (phytrainingok == ddr_phyvalid)  {
-			break;
-		}
-		if (retry % 256U == 0U) {
-			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01U);
-		}
-	}
-
-	/* all ch ok? */
-	if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) {
-		ret = 0xffU;
-		goto done;
-	}
-
-	/*
-	 * dbdficnt0:
-	 * dfi_dram_clk_disable=0
-	 * dfi_frequency = 0
-	 * freq_ratio = 01 (2:1)
-	 * init_start =0
-	 */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010U);
-	}
-	dsb_sev();
-done:
-	return ret;
-}
-
-/* drivability setting : CMOS MODE ON/OFF */
-static void change_lpddr4_en(uint32_t mode)
-{
-	uint32_t ch;
-	uint32_t i;
-	uint32_t data_l;
-	const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
-		_reg_PHY_PAD_ADDR_DRIVE,
-		_reg_PHY_PAD_CLK_DRIVE,
-		_reg_PHY_PAD_CS_DRIVE
-	};
-
-	foreach_vch(ch) {
-		for (i = 0U; i < 3U; i++) {
-			data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
-			if (mode != 0U) {
-				data_l |= (1U << 14);
-			} else {
-				data_l &= ~(1U << 14);
-			}
-			ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
-		}
-	}
-}
-
-/* drivability setting */
-static uint32_t set_term_code(void)
-{
-	uint32_t i;
-	uint32_t ch, index;
-	uint32_t data_l;
-	uint32_t chip_id[2];
-	uint32_t term_code;
-	uint32_t override;
-
-	term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-				  _reg_PHY_PAD_DATA_TERM);
-	override = 0U;
-	for (i = 0U; i < 2U; i++) {
-		chip_id[i] = mmio_read_32(LIFEC_CHIPID(i));
-	}
-
-	index = 0U;
-	while (true) {
-		if (termcode_by_sample[index][0] == 0xffffffff) {
-			break;
-		}
-		if ((termcode_by_sample[index][0] == chip_id[0]) &&
-		    (termcode_by_sample[index][1] == chip_id[1])) {
-			term_code = termcode_by_sample[index][2];
-			override = 1;
-			break;
-		}
-		index++;
-	}
-
-	if (override != 0U) {
-		for (index = 0U; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
-			data_l =
-			    ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					  _reg_PHY_PAD_TERM_X[index]);
-			data_l = (data_l & 0xfffe0000U) | term_code;
-			ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
-		}
-	} else if ((prr_product == PRR_PRODUCT_M3) &&
-		   (prr_cut == PRR_PRODUCT_10)) {
-		/*  non */
-	} else {
-		ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
-			       (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-					      _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000U));
-		ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01U);
-		ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01U);
-		foreach_vch(ch) {
-			do {
-				data_l =
-				    ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
-			} while (!(data_l & 0x00800000U));
-		}
-
-		/* G2M Ver.1.1 or later */
-		foreach_vch(ch) {
-			for (index = 0U; index < _reg_PHY_PAD_TERM_X_NUM;
-			     index++) {
-				data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[index]);
-				ddr_setval(ch, _reg_PHY_PAD_TERM_X[index],
-					   (data_l & 0xFFFE0FFFU) | 0x00015000U);
-			}
-		}
-	}
-
-	ddr_padcal_tcompensate_getinit(override);
-
-	return 0U;
-}
-
-/* DDR mode register setting */
-static void ddr_register_set(void)
-{
-	int32_t fspwp;
-	uint32_t tmp;
-
-	for (fspwp = 1; fspwp >= 0; fspwp--) {
-		/*MR13, fspwp */
-		send_dbcmd(0x0e840d08U | ((2U - fspwp) << 6));
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr1_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840100U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr2_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840200U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr3_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840300U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr11_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840b00U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr12_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840c00U | tmp);
-
-		tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				    reg_pi_mr14_data_fx_csx[fspwp][0]);
-		send_dbcmd(0x0e840e00U | tmp);
-		/* MR22 */
-		send_dbcmd(0x0e841616U);
-
-		/* ZQCAL start */
-		send_dbcmd(0x0d84004FU);
-
-		/* ZQLAT */
-		send_dbcmd(0x0d840051U);
-	}
-
-	/* MR13, fspwp */
-	send_dbcmd(0x0e840d08U);
-}
-
-/* Training handshake functions */
-static inline uint32_t wait_freqchgreq(uint32_t assert)
-{
-	uint32_t data_l;
-	uint32_t count;
-	uint32_t ch;
-
-	count = 100000U;
-
-	if (assert != 0U) {
-		do {
-			data_l = 1U;
-			foreach_vch(ch) {
-				data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
-			}
-			count = count - 1U;
-		} while (((data_l & 0x01U) != 0x01U) && (count != 0U));
-	} else {
-		do {
-			data_l = 0U;
-			foreach_vch(ch) {
-				data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
-			}
-			count = count - 1U;
-		} while (((data_l & 0x01U) != 0x00U) && (count != 0U));
-	}
-
-	return (count == 0U);
-}
-
-static inline void set_freqchgack(uint32_t assert)
-{
-	uint32_t ch;
-	uint32_t data_l;
-
-	if (assert != 0U) {
-		data_l = 0x0CF20000U;
-	} else {
-		data_l = 0x00000000U;
-	}
-
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
-	}
-}
-
-static inline void set_dfifrequency(uint32_t freq)
-{
-	uint32_t ch;
-
-	foreach_vch(ch) {
-		mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, freq << 24);
-	}
-	dsb_sev();
-}
-
-static uint32_t pll3_freq(uint32_t on)
-{
-	uint32_t timeout;
-
-	timeout = wait_freqchgreq(1U);
-
-	if (timeout != 0U) {
-		return 1U;
-	}
-
-	pll3_control(on);
-	set_dfifrequency(on);
-
-	set_freqchgack(1U);
-	timeout = wait_freqchgreq(0U);
-	set_freqchgack(0U);
-
-	if (timeout != 0U) {
-		FATAL_MSG("BL2: Time out[2]\n");
-		return 1U;
-	}
-
-	return 0U;
-}
-
-/* update dly */
-static void update_dly(void)
-{
-	ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01U);
-	ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01U);
-}
-
-/* training by pi */
-static uint32_t pi_training_go(void)
-{
-	uint32_t flag;
-	uint32_t data_l;
-	uint32_t retry;
-	const uint32_t RETRY_MAX = 4096U * 16U;
-	uint32_t ch;
-	uint32_t mst_ch;
-	uint32_t cur_frq;
-	uint32_t complete;
-	uint32_t frqchg_req;
-
-	/* pi_start */
-	ddr_setval_ach(_reg_PI_START, 0x01U);
-	foreach_vch(ch) {
-	    ddr_getval(ch, _reg_PI_INT_STATUS);
-	}
-
-	/* set dfi_phymstr_ack = 1 */
-	mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U);
-	dsb_sev();
-
-	/* wait pi_int_status[0] */
-	mst_ch = 0U;
-	flag = 0U;
-	complete = 0U;
-	cur_frq = 0U;
-	for (retry = 0U; retry < RETRY_MAX; retry++) {
-		frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
-
-		if (frqchg_req != 0U) {
-			if (cur_frq != 0U) {
-				/* Low frequency */
-				flag = pll3_freq(0U);
-				cur_frq = 0U;
-			} else {
-				/* High frequency */
-				flag = pll3_freq(1U);
-				cur_frq = 1U;
-			}
-			if (flag != 0U) {
-				break;
-			}
-		} else {
-			if (cur_frq != 0U) {
-				foreach_vch(ch) {
-					if ((complete & (1U << ch)) != 0U) {
-						continue;
-					}
-					data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
-					if ((data_l & 0x01U) != 0U) {
-						complete |= (1U << ch);
-					}
-				}
-				if (complete == ddr_phyvalid) {
-					break;
-				}
-			}
-		}
-	}
-	foreach_vch(ch) {
-		/* dummy read */
-		data_l = ddr_getval_s(ch, 0U, _reg_PHY_CAL_RESULT2_OBS_0);
-		data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
-		ddr_setval(ch, _reg_PI_INT_ACK, data_l);
-	}
-	if (ddrphy_regif_chk() != 0U) {
-		complete = 0xfdU;
-	}
-	return complete;
-}
-
-/* Initialize DDR */
-static uint32_t init_ddr(void)
-{
-	uint32_t i;
-	uint32_t data_l;
-	uint32_t phytrainingok;
-	uint32_t ch, slice;
-	uint32_t index;
-	uint32_t err;
-	int16_t adj;
-
-	MSG_LF(__func__ ":0\n");
-
-	/* unlock phy */
-	/* Unlock DDRPHY register(AGAIN) */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU);
-	}
-	dsb_sev();
-
-	reg_ddrphy_write_a(0x00001010U, 0x00000001U);
-	/* DBSC register pre-setting */
-	dbsc_regset_pre();
-
-	/* load ddrphy registers */
-	ddrtbl_load();
-
-	/* configure ddrphy registers */
-	ddr_config();
-
-	/* dfi_reset assert */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDCNT0(ch), 0x01U);
-	}
-	dsb_sev();
-
-	/* dbsc register set */
-	dbsc_regset();
-	MSG_LF(__func__ ":1\n");
-
-	/* dfi_reset negate */
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDCNT0(ch), 0x00U);
-	}
-	dsb_sev();
-
-	/* dfi_init_start (start ddrphy) */
-	err = dfi_init_start();
-	if (err != 0U) {
-		return INITDRAM_ERR_I;
-	}
-	MSG_LF(__func__ ":2\n");
-
-	/* ddr backupmode end */
-#ifdef DDR_BACKUPMODE
-	if (ddr_backup != 0U) {
-		NOTICE("BL2: [WARM_BOOT]\n");
-	} else {
-		NOTICE("BL2: [COLD_BOOT]\n");
-	}
-#endif
-	MSG_LF(__func__ ":3\n");
-
-	/* override term code after dfi_init_complete */
-	err = set_term_code();
-	if (err != 0U) {
-		return INITDRAM_ERR_I;
-	}
-	MSG_LF(__func__ ":4\n");
-
-	/* rx offset calibration */
-	if (prr_cut > PRR_PRODUCT_11) {
-		err = rx_offset_cal_hw();
-	} else {
-		err = rx_offset_cal();
-	}
-	if (err != 0U) {
-		return INITDRAM_ERR_O;
-	}
-	MSG_LF(__func__ ":5\n");
-
-	/* Dummy PDE */
-	send_dbcmd(0x08840000U);
-
-	/* PDX */
-	send_dbcmd(0x08840001U);
-
-	/* check register i/f is alive */
-	err = ddrphy_regif_chk();
-	if (err != 0U) {
-		return INITDRAM_ERR_O;
-	}
-	MSG_LF(__func__ ":6\n");
-
-	/* phy initialize end */
-
-	/* setup DDR mode registers */
-	/* CMOS MODE */
-	change_lpddr4_en(0);
-
-	/* MRS */
-	ddr_register_set();
-
-	/* Thermal sensor setting */
-	/* THCTR Bit6: PONM=0 , Bit0: THSST=1  */
-	data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBFU) | 0x00000001U;
-	mmio_write_32(THS1_THCTR, data_l);
-
-	/* LPDDR4 MODE */
-	change_lpddr4_en(1);
-
-	MSG_LF(__func__ ":7\n");
-
-	/* mask CS_MAP if RANKx is not found */
-	foreach_vch(ch) {
-		data_l = ddr_getval(ch, _reg_PI_CS_MAP);
-		if ((ch_have_this_cs[1] & (1U << ch)) == 0U) {
-			data_l = data_l & 0x05U;
-		}
-		ddr_setval(ch, _reg_PI_CS_MAP, data_l);
-	}
-
-	/* exec pi_training */
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
-	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U);
-
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			ddr_setval_s(ch, slice,
-				     _reg_PHY_PER_CS_TRAINING_EN,
-				     ((ch_have_this_cs[1]) >> ch) & 0x01U);
-		}
-	}
-
-	phytrainingok = pi_training_go();
-
-	if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
-		return INITDRAM_ERR_T | phytrainingok;
-	}
-
-	MSG_LF(__func__ ":8\n");
-
-	/* CACS DLY ADJUST */
-	data_l = board_cnf->cacs_dly + (uint32_t)_f_scale_adj(board_cnf->cacs_dly_adj);
-	foreach_vch(ch) {
-		for (i = 0U; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
-			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
-			ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-				   data_l + (uint32_t)adj);
-		}
-
-		if (ddr_phycaslice == 1U) {
-			for (i = 0U; i < 6U; i++) {
-				index = i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM;
-				adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[index]);
-				ddr_setval_s(ch, 2U,
-					     _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-					     data_l + (uint32_t)adj);
-			}
-		}
-	}
-
-	update_dly();
-	MSG_LF(__func__ ":9\n");
-
-	/* Adjust write path latency */
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD) != 0U) {
-		adjust_wpath_latency();
-	}
-
-	/* RDQLVL Training */
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0U) {
-		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01U);
-	}
-
-	err = rdqdm_man();
-
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0U) {
-		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00U);
-	}
-
-	if (err != 0U) {
-		return INITDRAM_ERR_T;
-	}
-	update_dly();
-	MSG_LF(__func__ ":10\n");
-
-	/* WDQLVL Training */
-	err = wdqdm_man();
-	if (err != 0U) {
-		return INITDRAM_ERR_T;
-	}
-	update_dly();
-	MSG_LF(__func__ ":11\n");
-
-	dbsc_regset_post();
-	MSG_LF(__func__ ":12\n");
-
-	return phytrainingok;
-}
-
-/* SW LEVELING COMMON */
-static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
-{
-	const uint32_t RETRY_MAX = 0x1000U;
-	uint32_t ch, data_l;
-	uint32_t waiting;
-	uint32_t retry;
-	uint32_t err = 0U;
-
-	/* set EXIT -> OP_DONE is cleared */
-	ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
-
-	/* kick */
-	foreach_vch(ch) {
-		if ((ch_have_this_cs[ddr_csn % 2U] & (1U << ch)) != 0U) {
-			ddr_setval(ch, reg_cs, ddr_csn);
-			ddr_setval(ch, reg_kick, 0x01U);
-		}
-	}
-	foreach_vch(ch) {
-		/*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */
-		ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
-	}
-	waiting = ch_have_this_cs[ddr_csn % 2U];
-	dsb_sev();
-	retry = RETRY_MAX;
-	do {
-		foreach_vch(ch) {
-			if ((waiting & (1U << ch)) == 0U) {
-				continue;
-			}
-			data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
-			if ((data_l & 0x01U) != 0U) {
-				waiting &= ~(1U << ch);
-			}
-		}
-		retry--;
-	} while ((waiting != 0U) && (retry > 0U));
-	if (retry == 0U) {
-		err = 1U;
-	}
-
-	dsb_sev();
-	/* set EXIT -> OP_DONE is cleared */
-	ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01U);
-	dsb_sev();
-
-	return err;
-}
-
-/* WDQ TRAINING */
-#ifndef DDR_FAST_INIT
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
-{
-	uint32_t cs, slice;
-	uint32_t data_l;
-	int32_t i, k;
-
-	/* clr of training results buffer */
-	cs = ddr_csn % 2U;
-	data_l = board_cnf->dqdm_dly_w;
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
-			continue;
-		}
-
-		for (i = 0; i <= 8; i++) {
-			if ((ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) != 0U) {
-				wdqdm_dly[ch][cs][slice][i] =
-				    wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
-			} else {
-				wdqdm_dly[ch][cs][slice][i] = data_l;
-			}
-			wdqdm_le[ch][cs][slice][i] = 0U;
-			wdqdm_te[ch][cs][slice][i] = 0U;
-		}
-		wdqdm_st[ch][cs][slice] = 0U;
-		wdqdm_win[ch][cs][slice] = 0U;
-	}
-}
-
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
-{
-	const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0U;
-	uint32_t cs, slice;
-	uint32_t data_l;
-	int32_t min_win;
-	int32_t i, k;
-	uint32_t err;
-	int32_t win;
-	int8_t _adj;
-	int16_t adj;
-	uint32_t dq;
-
-	/* analysis of training results */
-	err = 0U;
-	for (slice = 0U; slice < SLICE_CNT; slice += 1U) {
-		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
-			continue;
-		}
-
-		cs = ddr_csn % 2U;
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
-		for (i = 0; i < 9; i++) {
-			dq = slice * 8U + i;
-			if (i == 8) {
-				_adj = board_cnf->ch[ch].dm_adj_w[slice];
-			} else {
-				_adj = board_cnf->ch[ch].dq_adj_w[dq];
-			}
-			adj = _f_scale_adj(_adj);
-
-			data_l =
-			    ddr_getval_s(ch, slice,
-					 _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
-			ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
-				     data_l);
-			wdqdm_dly[ch][cs][slice][i] = data_l;
-		}
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
-		data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
-		wdqdm_st[ch][cs][slice] = data_l;
-		min_win = INT_LEAST32_MAX;
-		for (i = 0; i <= 8; i++) {
-			ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
-				     i);
-
-			data_l =
-			    ddr_getval_s(ch, slice,
-					 _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
-			wdqdm_te[ch][cs][slice][i] = data_l;
-			data_l =
-			    ddr_getval_s(ch, slice,
-					 _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
-			wdqdm_le[ch][cs][slice][i] = data_l;
-			win = (int32_t)wdqdm_te[ch][cs][slice][i] -
-			      wdqdm_le[ch][cs][slice][i];
-			if (min_win > win) {
-				min_win = win;
-			}
-			if (data_l >= _par_WDQLVL_RETRY_THRES) {
-				err = 2;
-			}
-		}
-		wdqdm_win[ch][cs][slice] = min_win;
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
-			     ((ch_have_this_cs[1]) >> ch) & 0x01);
-	}
-	return err;
-}
-#endif/* DDR_FAST_INIT */
-
-static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
-{
-	uint32_t tgt_cs, src_cs;
-	uint32_t ch, slice;
-	uint32_t tmp_r;
-	uint32_t i;
-
-	/* copy of training results */
-	foreach_vch(ch) {
-		for (tgt_cs = 0U; tgt_cs < CS_CNT; tgt_cs++) {
-			for (slice = 0U; slice < SLICE_CNT; slice++) {
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_PER_CS_TRAINING_INDEX,
-					     tgt_cs);
-				src_cs = ddr_csn % 2U;
-				if ((ch_have_this_cs[1] & (1U << ch)) == 0U) {
-					src_cs = 0U;
-				}
-				for (i = 0U; i <= 4U; i += 4U) {
-					if (restore != 0U) {
-						tmp_r = rdqdm_dly[ch][tgt_cs][slice][i];
-					} else {
-						tmp_r = rdqdm_dly[ch][src_cs][slice][i];
-					}
-
-					ddr_setval_s(ch, slice,
-						     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
-						     tmp_r);
-				}
-			}
-		}
-	}
-}
-
-static uint32_t wdqdm_man1(void)
-{
-	uint32_t mr14_csab0_bak[DRAM_CH_CNT];
-	uint32_t ch, cs, ddr_csn;
-	uint32_t data_l;
-	uint32_t err = 0U;
-#ifndef DDR_FAST_INIT
-	uint32_t err_flg = 0U;
-#endif/* DDR_FAST_INIT */
-
-	/* CLEAR PREV RESULT */
-	for (cs = 0U; cs < CS_CNT; cs++) {
-		ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
-		ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01U);
-	}
-	ddrphy_regif_idle();
-
-	for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
-		if (((prr_product == PRR_PRODUCT_M3) &&
-		     (prr_cut == PRR_PRODUCT_10))) {
-			wdqdm_cp(ddr_csn, 0U);
-		}
-
-		foreach_vch(ch) {
-			data_l = ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][ddr_csn]);
-			ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
-		}
-
-		/* KICK WDQLVL */
-		err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ);
-		if (err != 0U) {
-			goto err_exit;
-		}
-
-		if (ddr_csn == 0U) {
-			foreach_vch(ch) {
-				mr14_csab0_bak[ch] = ddr_getval(ch,
-								reg_pi_mr14_data_fx_csx[1][0]);
-			}
-		} else {
-			foreach_vch(ch) {
-				ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
-					   mr14_csab0_bak[ch]);
-			}
-		}
-#ifndef DDR_FAST_INIT
-		foreach_vch(ch) {
-			if ((ch_have_this_cs[ddr_csn % 2U] & (1U << ch)) == 0U) {
-				wdqdm_clr1(ch, ddr_csn);
-				continue;
-			}
-			err = wdqdm_ana1(ch, ddr_csn);
-			if (err != 0U) {
-				err_flg |= (1U << (ddr_csn * 4U + ch));
-			}
-			ddrphy_regif_idle();
-		}
-#endif/* DDR_FAST_INIT */
-	}
-err_exit:
-#ifndef DDR_FAST_INIT
-	err |= err_flg;
-#endif/* DDR_FAST_INIT */
-
-	return err;
-}
-
-static uint32_t wdqdm_man(void)
-{
-	uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
-	const uint32_t retry_max = 0x10U;
-	uint32_t err, retry_cnt;
-
-	datal = RL + js2[js2_tdqsck] + (16U / 2U) + 1U - WL + 2U + 2U + 19U;
-	if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal) {
-		datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
-	}
-	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
-
-	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
-		       (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
-
-	ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
-	ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
-
-	retry_cnt = 0U;
-	err = 0U;
-	do {
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C);
-		dsb_sev();
-		err = wdqdm_man1();
-		foreach_vch(ch) {
-			for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
-				mr14_bkup[ch][ddr_csn] =
-				    ddr_getval(ch, reg_pi_mr14_data_fx_csx
-					       [1][ddr_csn]);
-				dsb_sev();
-			}
-		}
-
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04);
-
-		pvtcode_update();
-		err = wdqdm_man1();
-		foreach_vch(ch) {
-			for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
-				mr14_bkup[ch][ddr_csn] =
-				    (mr14_bkup[ch][ddr_csn] +
-				     ddr_getval(ch, reg_pi_mr14_data_fx_csx
-						[1][ddr_csn])) / 2U;
-				ddr_setval(ch,
-					   reg_pi_mr14_data_fx_csx[1]
-					   [ddr_csn],
-					   mr14_bkup[ch][ddr_csn]);
-			}
-		}
-
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x0U);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0U);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 0x0U);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 0x0U);
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 0x0U);
-
-		pvtcode_update2();
-		err = wdqdm_man1();
-		ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x0U);
-
-	} while ((err != 0U) && (++retry_cnt < retry_max));
-
-	if (prr_product == PRR_PRODUCT_M3 && prr_cut <= PRR_PRODUCT_10) {
-		wdqdm_cp(0U, 1U);
-	}
-
-	return (retry_cnt >= retry_max);
-}
-
-/* RDQ TRAINING */
-#ifndef DDR_FAST_INIT
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
-{
-	uint32_t cs, slice;
-	uint32_t data_l;
-	int32_t i, k;
-
-	/* clr of training results buffer */
-	cs = ddr_csn % 2U;
-	data_l = board_cnf->dqdm_dly_r;
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
-			continue;
-		}
-
-		for (i = 0; i <= 8; i++) {
-			if ((ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) != 0U) {
-				rdqdm_dly[ch][cs][slice][i] =
-				    rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
-				rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
-				    rdqdm_dly[ch][CS_CNT - 1 - cs][slice + SLICE_CNT][i];
-			} else {
-				rdqdm_dly[ch][cs][slice][i] = data_l;
-				rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
-			}
-			rdqdm_le[ch][cs][slice][i] = 0U;
-			rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0U;
-			rdqdm_te[ch][cs][slice][i] = 0U;
-			rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0U;
-			rdqdm_nw[ch][cs][slice][i] = 0U;
-			rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0U;
-		}
-		rdqdm_st[ch][cs][slice] = 0U;
-		rdqdm_win[ch][cs][slice] = 0U;
-	}
-}
-
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
-{
-	uint32_t rdq_status_obs_select;
-	uint32_t cs, slice;
-	uint32_t data_l;
-	uint32_t err;
-	uint32_t dq;
-	int32_t min_win;
-	int8_t _adj;
-	int16_t adj;
-	int32_t min_win;
-	int32_t win;
-	int32_t i, k;
-
-	/* analysis of training results */
-	err = 0U;
-	for (slice = 0U; slice < SLICE_CNT; slice++) {
-		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
-		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
-			continue;
-		}
-
-		cs = ddr_csn % 2U;
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
-		ddrphy_regif_idle();
-
-		ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
-		ddrphy_regif_idle();
-
-		for (i = 0; i <= 8; i++) {
-			dq = slice * 8 + i;
-			if (i == 8) {
-				_adj = board_cnf->ch[ch].dm_adj_r[slice];
-			} else {
-				_adj = board_cnf->ch[ch].dq_adj_r[dq];
-			}
-
-			adj = _f_scale_adj(_adj);
-
-			data_l = ddr_getval_s(ch, slice,
-					      _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
-			ddr_setval_s(ch, slice,
-				     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
-				     data_l);
-			rdqdm_dly[ch][cs][slice][i] = data_l;
-
-			data_l = ddr_getval_s(ch, slice,
-					      _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
-			ddr_setval_s(ch, slice,
-				     _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
-				     data_l);
-			rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
-		}
-		min_win = INT_LEAST32_MAX;
-		for (i = 0; i <= 8; i++) {
-			data_l =
-			    ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
-			rdqdm_st[ch][cs][slice] = data_l;
-			rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
-			/* k : rise/fall */
-			for (k = 0; k < 2; k++) {
-				if (i == 8) {
-					rdq_status_obs_select = 16 + 8 * k;
-				} else {
-					rdq_status_obs_select = i + k * 8;
-				}
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
-					     rdq_status_obs_select);
-
-				data_l =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
-				rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
-				data_l =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
-				rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
-				data_l =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
-				rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
-				win =
-				    (int32_t)rdqdm_te[ch][cs][slice +
-							      SLICE_CNT *
-							      k][i] -
-				    rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
-				if (i != 8) {
-					if (min_win > win) {
-						min_win = win;
-					}
-				}
-			}
-		}
-		rdqdm_win[ch][cs][slice] = min_win;
-		if (min_win <= 0) {
-			err = 2;
-		}
-	}
-	return err;
-}
-#else /* DDR_FAST_INIT */
-static void rdqdm_man1_set(uint32_t ddr_csn, uint32_t ch, uint32_t slice)
-{
-	uint32_t i, adj, data_l;
-
-	for (i = 0U; i <= 8U; i++) {
-		if (i == 8U) {
-			adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
-		} else {
-			adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8U + i]);
-		}
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
-		data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
-		ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
-		rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
-		rdqdm_dly[ch][ddr_csn | 1U][slice][i] = data_l;
-
-		data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
-		ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
-		rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
-		rdqdm_dly[ch][ddr_csn | 1U][slice + SLICE_CNT][i] = data_l;
-	}
-}
-#endif /* DDR_FAST_INIT */
-
-static uint32_t rdqdm_man1(void)
-{
-	uint32_t ch;
-	uint32_t ddr_csn;
-	uint32_t val;
-#ifdef DDR_FAST_INIT
-	uint32_t slice;
-#endif/* DDR_FAST_INIT */
-	uint32_t err;
-
-	/* manual execution of training */
-	err = 0U;
-
-	for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
-		/* KICK RDQLVL */
-		err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
-		if (err != 0U) {
-			goto err_exit;
-		}
-#ifndef DDR_FAST_INIT
-		foreach_vch(ch) {
-			if ((ch_have_this_cs[ddr_csn % 2] & (1U << ch)) == 0U) {
-				rdqdm_clr1(ch, ddr_csn);
-				ddrphy_regif_idle();
-				continue;
-			}
-			err = rdqdm_ana1(ch, ddr_csn);
-			ddrphy_regif_idle();
-			if (err != 0U)  {
-				goto err_exit;
-			}
-		}
-#else/* DDR_FAST_INIT */
-		foreach_vch(ch) {
-			if ((ch_have_this_cs[ddr_csn] & (1U << ch)) != 0U) {
-				for (slice = 0U; slice < SLICE_CNT; slice++) {
-					val = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
-					if (val != 0x0D00FFFFU) {
-						err = (1U << ch) | (0x10U << slice);
-						goto err_exit;
-					}
-				}
-			}
-			if ((prr_product == PRR_PRODUCT_M3) &&
-			    (prr_cut <= PRR_PRODUCT_10)) {
-				for (slice = 0U; slice < SLICE_CNT; slice++) {
-					rdqdm_man1_set(ddr_csn, ch, slice);
-				}
-			}
-		}
-		ddrphy_regif_idle();
-
-#endif/* DDR_FAST_INIT */
-	}
-
-err_exit:
-	return err;
-}
-
-static uint32_t rdqdm_man(void)
-{
-	uint32_t err, retry_cnt;
-	const uint32_t retry_max = 0x01U;
-
-	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
-			  0x00000004U | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						     _reg_PHY_DQ_TSEL_ENABLE));
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
-			  0x00000004U | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						     _reg_PHY_DQS_TSEL_ENABLE));
-	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
-			  0xFF0FFFFFU & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						     _reg_PHY_DQ_TSEL_SELECT));
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
-			  0xFF0FFFFFU & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-						     _reg_PHY_DQS_TSEL_SELECT));
-
-	retry_cnt = 0U;
-	do {
-		err = rdqdm_man1();
-		ddrphy_regif_idle();
-	} while ((err != 0U) && (++retry_cnt < retry_max));
-	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_DQ_TSEL_ENABLE));
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_DQS_TSEL_ENABLE));
-	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_DQ_TSEL_SELECT));
-	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
-			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
-					_reg_PHY_DQS_TSEL_SELECT));
-
-	return (retry_cnt >= retry_max);
-}
-
-/* rx offset calibration */
-static int32_t _find_change(uint64_t val, uint32_t dir)
-{
-	int32_t i;
-	uint32_t startval;
-	uint32_t curval;
-	const int32_t VAL_END = 0x3fU;
-
-	if (dir == 0U) {
-		startval = (val & 0x01U);
-		for (i = 1; i <= VAL_END; i++) {
-			curval = (val >> i) & 0x01U;
-			if (curval != startval) {
-				return i;
-			}
-		}
-		return VAL_END;
-	}
-
-	startval = (val >> dir) & 0x01U;
-	for (i = (int32_t)dir - 1; i >= 0; i--) {
-		curval = (val >> i) & 0x01U;
-		if (curval != startval) {
-			return i;
-		}
-	}
-
-	return 0;
-}
-
-static uint32_t _rx_offset_cal_updn(uint32_t code)
-{
-	const uint32_t CODE_MAX = 0x40U;
-	uint32_t tmp;
-
-	if (code == 0U) {
-		tmp = (1U << 6) | (CODE_MAX - 1U);
-	} else {
-		tmp = (code << 6) | (CODE_MAX - code);
-	}
-
-	return tmp;
-}
-
-static uint32_t rx_offset_cal(void)
-{
-	uint32_t index;
-	uint32_t code;
-	const uint32_t CODE_MAX = 0x40U;
-	const uint32_t CODE_STEP = 2U;
-	uint32_t ch, slice;
-	uint32_t tmp;
-	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
-	uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
-	uint64_t tmpval;
-	int32_t lsb, msb;
-
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM; index++) {
-				val[ch][slice][index] = 0U;
-			}
-		}
-	}
-
-	for (code = 0U; code < CODE_MAX / CODE_STEP; code++) {
-		tmp = _rx_offset_cal_updn(code * CODE_STEP);
-		for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM; index++) {
-			ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
-		}
-		dsb_sev();
-		ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
-
-		foreach_vch(ch) {
-			for (slice = 0U; slice < SLICE_CNT; slice++) {
-				tmp = tmp_ach_as[ch][slice];
-				for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM;
-				     index++) {
-					if ((tmp & (1U << index)) != 0U) {
-						val[ch][slice][index] |=
-						    (1ULL << code);
-					} else {
-						val[ch][slice][index] &=
-						    ~(1ULL << code);
-					}
-				}
-			}
-		}
-	}
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice++) {
-			for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM;
-			     index++) {
-				tmpval = val[ch][slice][index];
-				lsb = _find_change(tmpval, 0U);
-				msb = _find_change(tmpval,
-						   (CODE_MAX / CODE_STEP) - 1U);
-				tmp = (lsb + msb) >> 1U;
-
-				tmp = _rx_offset_cal_updn(tmp * CODE_STEP);
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_RX_CAL_X[index], tmp);
-			}
-		}
-	}
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
-
-	return 0U;
-}
-
-static uint32_t rx_offset_cal_hw(void)
-{
-	uint32_t ch, slice;
-	uint32_t retry;
-	uint32_t complete;
-	uint32_t tmp;
-	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
-
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
-	ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
-
-	retry = 0U;
-	while (retry < 4096U) {
-		if ((retry & 0xffU) == 0U) {
-			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
-		}
-		foreach_vch(ch)  {
-			for (slice = 0U; slice < SLICE_CNT; slice++) {
-				tmp_ach_as[ch][slice] =
-					ddr_getval_s(ch, slice,
-						     _reg_PHY_RX_CAL_X[9]);
-			}
-		}
-
-		complete = 1U;
-		foreach_vch(ch) {
-			for (slice = 0U; slice < SLICE_CNT; slice++) {
-				tmp = tmp_ach_as[ch][slice];
-				tmp = (tmp & 0x3fU) + ((tmp >> 6) & 0x3fU);
-				if (tmp != 0x40U) {
-					complete = 0U;
-				}
-			}
-		}
-		if (complete != 0U) {
-			break;
-		}
-
-		retry++;
-	}
-
-	return (complete == 0U);
-}
-
-/* adjust wpath latency */
-static void adjust_wpath_latency(void)
-{
-	uint32_t ch, cs, slice;
-	uint32_t dly;
-	uint32_t wpath_add;
-	const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180U;
-
-	foreach_vch(ch) {
-		for (slice = 0U; slice < SLICE_CNT; slice += 1U) {
-			for (cs = 0U; cs < CS_CNT; cs++) {
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_PER_CS_TRAINING_INDEX,
-					     cs);
-				ddr_getval_s(ch, slice,
-					     _reg_PHY_PER_CS_TRAINING_INDEX);
-				dly =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_CLK_WRDQS_SLAVE_DELAY);
-				if (dly <= _par_EARLY_THRESHOLD_VAL) {
-					continue;
-				}
-
-				wpath_add =
-				    ddr_getval_s(ch, slice,
-						 _reg_PHY_WRITE_PATH_LAT_ADD);
-				ddr_setval_s(ch, slice,
-					     _reg_PHY_WRITE_PATH_LAT_ADD,
-					     wpath_add - 1U);
-			}
-		}
-	}
-}
-
-/* DDR Initialize entry */
-int32_t rzg_dram_init(void)
-{
-	uint32_t ch, cs;
-	uint32_t data_l;
-	uint32_t bus_mbps, bus_mbpsdiv;
-	uint32_t tmp_tccd;
-	uint32_t failcount;
-	uint32_t cnf_boardtype;
-	int32_t ret = INITDRAM_NG;
-
-	/* Thermal sensor setting */
-	data_l = mmio_read_32(CPG_MSTPSR5);
-	if ((data_l & BIT(22)) != 0U) {	/*  case THS/TSC Standby */
-		data_l &= ~BIT(22);
-		cpg_write_32(CPG_SMSTPCR5, data_l);
-		while ((mmio_read_32(CPG_MSTPSR5) & BIT(22)) != 0U) {
-			/*  wait bit=0 */
-		}
-	}
-
-	/* THCTR Bit6: PONM=0 , Bit0: THSST=0   */
-	data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
-	mmio_write_32(THS1_THCTR, data_l);
-
-	/* Judge product and cut */
-#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#if (RCAR_LSI == RCAR_AUTO)
-	prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#else /* RCAR_LSI */
-#ifndef RCAR_LSI_CUT
-	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_LSI */
-#else /* RCAR_DDR_FIXED_LSI_TYPE */
-	prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		p_ddr_regdef_tbl =
-			(const uint32_t *)&DDR_REGDEF_TBL[1][0];
-	} else {
-		FATAL_MSG("BL2: DDR:Unknown Product\n");
-		goto done;
-	}
-
-	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
-		/* non : G2M Ver.1.x not support */
-	} else {
-		mmio_write_32(DBSC_DBSYSCNT0, 0x00001234U);
-	}
-
-	/* Judge board type */
-	cnf_boardtype = boardcnf_get_brd_type(prr_product);
-	if (cnf_boardtype >= (uint32_t)BOARDNUM) {
-		FATAL_MSG("BL2: DDR:Unknown Board\n");
-		goto done;
-	}
-	board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
-
-/* RCAR_DRAM_SPLIT_2CH           (2U) */
-#if RCAR_DRAM_SPLIT == 2
-	ddr_phyvalid = board_cnf->phyvalid;
-#else /* RCAR_DRAM_SPLIT_2CH */
-	ddr_phyvalid = board_cnf->phyvalid;
-#endif /* RCAR_DRAM_SPLIT_2CH */
-
-	max_density = 0U;
-
-	for (cs = 0U; cs < CS_CNT; cs++) {
-		ch_have_this_cs[cs] = 0U;
-	}
-
-	foreach_ech(ch) {
-		for (cs = 0U; cs < CS_CNT; cs++) {
-			ddr_density[ch][cs] = 0xffU;
-		}
-	}
-
-	foreach_vch(ch) {
-		for (cs = 0U; cs < CS_CNT; cs++) {
-			data_l = board_cnf->ch[ch].ddr_density[cs];
-			ddr_density[ch][cs] = data_l;
-
-			if (data_l == 0xffU) {
-				continue;
-			}
-			if (data_l > max_density) {
-				max_density = data_l;
-			}
-			ch_have_this_cs[cs] |= (1U << ch);
-		}
-	}
-
-	/* Judge board clock frequency (in MHz) */
-	boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
-	if ((brd_clk / brd_clkdiv) > 25U) {
-		brd_clkdiva = 1U;
-	} else {
-		brd_clkdiva = 0U;
-	}
-
-	/* Judge ddr operating frequency clock(in Mbps) */
-	boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
-
-	ddr0800_mul = CLK_DIV(800U, 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U));
-
-	ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk,
-			  brd_clkdiv * (brd_clkdiva + 1U));
-
-	/* Adjust tccd */
-	data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
-	bus_mbps = 0U;
-	bus_mbpsdiv = 0U;
-	switch (data_l) {
-	case 0:
-		bus_mbps = brd_clk * 0x60U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 1U;
-		break;
-	case 1:
-		bus_mbps = brd_clk * 0x50U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 1U;
-		break;
-	case 2:
-		bus_mbps = brd_clk * 0x40U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 1U;
-		break;
-	case 3:
-		bus_mbps = brd_clk * 0x60U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 2U;
-		break;
-	default:
-		bus_mbps = brd_clk * 0x60U * 2U;
-		bus_mbpsdiv = brd_clkdiv * 2U;
-		WARN("BL2: DDR using default values for adjusting tccd");
-		break;
-	}
-	tmp_tccd = CLK_DIV(ddr_mbps * 8U, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv);
-	if (8U * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) {
-		tmp_tccd = tmp_tccd + 1U;
-	}
-
-	if (tmp_tccd < 8U) {
-		ddr_tccd = 8U;
-	} else {
-		ddr_tccd = tmp_tccd;
-	}
-
-	NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
-
-	MSG_LF("Start\n");
-
-	/* PLL Setting */
-	pll3_control(1U);
-
-	/* initialize DDR */
-	data_l = init_ddr();
-	if (data_l == ddr_phyvalid) {
-		failcount = 0U;
-	} else {
-		failcount = 1U;
-	}
-
-	foreach_vch(ch) {
-	    mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U);
-	}
-	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
-		/* non : G2M Ver.1.x not support */
-	} else {
-		mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-	}
-
-	if (failcount == 0U) {
-		ret = INITDRAM_OK;
-	}
-
-done:
-	return ret;
-}
-
-static void pvtcode_update(void)
-{
-	uint32_t ch;
-	uint32_t data_l;
-	uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
-	int32_t pvtp_tmp, pvtn_tmp;
-
-	foreach_vch(ch) {
-		pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0U) >> 6;
-		pvtp_init = (tcal.tcomp_cal[ch] & 0x03FU) >> 0;
-
-		if (8912U * pvtp_init > 44230U) {
-			pvtp_tmp = (5000U + 8912U * pvtp_init - 44230U) / 10000U;
-		} else {
-			pvtp_tmp =
-			    -((-(5000 + 8912 * pvtp_init - 44230)) / 10000);
-		}
-		pvtn_tmp = (5000U + 5776U * (uint32_t)pvtn_init + 30280U) / 10000U;
-
-		pvtn[ch] = (uint32_t)pvtn_tmp + pvtn_init;
-		pvtp[ch] = (uint32_t)pvtp_tmp + pvtp_init;
-
-		if (pvtn[ch] > 63U) {
-			pvtn[ch] = 63U;
-			pvtp[ch] =
-			    (pvtp_tmp) * (63 - 6 * pvtn_tmp -
-					  pvtn_init) / (pvtn_tmp) +
-			    6 * pvtp_tmp + pvtp_init;
-		}
-
-		data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000U;
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-				 data_l | 0x00020000U);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-				 data_l);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-				 data_l);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-				 data_l);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-				 data_l);
-	}
-}
-
-static void pvtcode_update2(void)
-{
-	uint32_t ch;
-
-	foreach_vch(ch) {
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-				 tcal.init_cal[ch] | 0x00020000U);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-				 tcal.init_cal[ch]);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-				 tcal.init_cal[ch]);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-				 tcal.init_cal[ch]);
-		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-				 tcal.init_cal[ch]);
-	}
-}
-
-static void ddr_padcal_tcompensate_getinit(uint32_t override)
-{
-	uint32_t ch;
-	uint32_t data_l;
-	uint32_t pvtp, pvtn;
-
-	tcal.init_temp = 0;
-	for (ch = 0U; ch < 4U; ch++) {
-		tcal.init_cal[ch] = 0U;
-		tcal.tcomp_cal[ch] = 0U;
-	}
-
-	foreach_vch(ch) {
-		tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
-		tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
-	}
-
-	if (override == 0U) {
-		data_l = mmio_read_32(THS1_TEMP);
-		if (data_l < 2800U) {
-			tcal.init_temp =
-			    (143 * (int32_t)data_l - 359000) / 1000;
-		} else {
-			tcal.init_temp =
-			    (121 * (int32_t)data_l - 296300) / 1000;
-		}
-
-		foreach_vch(ch) {
-			pvtp = (tcal.init_cal[ch] >> 0) & 0x000003FU;
-			pvtn = (tcal.init_cal[ch] >> 6) & 0x000003FU;
-			if ((int32_t)pvtp >
-			    ((tcal.init_temp * 29 - 3625) / 1000)) {
-				pvtp = (int32_t)pvtp +
-				    ((3625 - tcal.init_temp * 29) / 1000);
-			} else {
-				pvtp = 0U;
-			}
-
-			if ((int32_t)pvtn >
-			    ((tcal.init_temp * 54 - 6750) / 1000)) {
-				pvtn = (int32_t)pvtn +
-				    ((6750 - tcal.init_temp * 54) / 1000);
-			} else {
-				pvtn = 0U;
-			}
-
-			tcal.init_cal[ch] = 0x00015000U | (pvtn << 6) | pvtp;
-		}
-		tcal.init_temp = 125;
-	}
-}
-
-#ifndef DDR_QOS_INIT_SETTING
-/* For QoS init */
-uint8_t rzg_get_boardcnf_phyvalid(void)
-{
-	return ddr_phyvalid;
-}
-#endif /* DDR_QOS_INIT_SETTING */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
deleted file mode 100644
index 345ef24..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define BOARDNUM 2
-#define BOARD_JUDGE_AUTO
-
-#ifdef BOARD_JUDGE_AUTO
-static uint32_t _board_judge(uint32_t prr_product);
-
-static uint32_t boardcnf_get_brd_type(uint32_t prr_product)
-{
-	return _board_judge(prr_product);
-}
-#else /* BOARD_JUDGE_AUTO */
-static uint32_t boardcnf_get_brd_type(void)
-{
-	return 1U;
-}
-#endif /* BOARD_JUDGE_AUTO */
-
-#define DDR_FAST_INIT
-
-struct _boardcnf_ch {
-	uint8_t ddr_density[CS_CNT];
-	uint64_t ca_swap;
-	uint16_t dqs_swap;
-	uint32_t dq_swap[SLICE_CNT];
-	uint8_t dm_swap[SLICE_CNT];
-	uint16_t wdqlvl_patt[16];
-	int8_t cacs_adj[16];
-	int8_t dm_adj_w[SLICE_CNT];
-	int8_t dq_adj_w[SLICE_CNT * 8U];
-	int8_t dm_adj_r[SLICE_CNT];
-	int8_t dq_adj_r[SLICE_CNT * 8U];
-};
-
-struct _boardcnf {
-	uint8_t phyvalid;
-	uint8_t dbi_en;
-	uint16_t cacs_dly;
-	int16_t cacs_dly_adj;
-	uint16_t dqdm_dly_w;
-	uint16_t dqdm_dly_r;
-	struct _boardcnf_ch ch[DRAM_CH_CNT];
-};
-
-#define WDQLVL_PAT {\
-	0x00AA,\
-	0x0055,\
-	0x00AA,\
-	0x0155,\
-	0x01CC,\
-	0x0133,\
-	0x00CC,\
-	0x0033,\
-	0x00F0,\
-	0x010F,\
-	0x01F0,\
-	0x010F,\
-	0x00F0,\
-	0x00F0,\
-	0x000F,\
-	0x010F}
-
-static const struct _boardcnf boardcnfs[BOARDNUM] = {
-	{
-/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
-	 .phyvalid = 0x03,
-	 .dbi_en = 0x01,
-	 .cacs_dly = 0x02c0,
-	 .cacs_dly_adj = 0,
-	 .dqdm_dly_w = 0x0300,
-	 .dqdm_dly_r = 0x00a0,
-	 .ch = {
-		{
-		 {0x04, 0xff},
-		 0x00345201U,
-		 0x3201,
-		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
-		 {0x08, 0x08, 0x08, 0x08},
-		 WDQLVL_PAT,
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0}
-		},
-
-		{
-		 {0x04, 0xff},
-		 0x00302154U,
-		 0x2310,
-		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
-		 {0x08, 0x08, 0x08, 0x08},
-		 WDQLVL_PAT,
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0}
-		}
-		}
-	},
-/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
-	{
-	 0x03,
-	 0x01,
-	 0x02c0,
-	 0,
-	 0x0300,
-	 0x00a0,
-	{
-		{
-		 {0x02, 0x02},
-		 0x00345201U,
-		 0x3201,
-		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
-		 {0x08, 0x08, 0x08, 0x08},
-		 WDQLVL_PAT,
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0}
-		},
-		{
-		 {0x02, 0x02},
-		 0x00302154U,
-		 0x2310,
-		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
-		 {0x08, 0x08, 0x08, 0x08},
-		 WDQLVL_PAT,
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0},
-		 {0, 0, 0, 0},
-		 {0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0,
-		  0, 0, 0, 0, 0, 0, 0, 0},
-		{0, 0, 0, 0},
-		{0, 0, 0, 0, 0, 0, 0, 0,
-		 0, 0, 0, 0, 0, 0, 0, 0,
-		 0, 0, 0, 0, 0, 0, 0, 0,
-		 0, 0, 0, 0, 0, 0, 0, 0}
-		}
-	}
-	}
-};
-
-void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
-{
-	uint32_t md;
-
-	md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3U;
-	switch (md) {
-	case 0x0U:
-		*clk = 50U;
-		*div = 3U;
-		break;
-	case 0x1U:
-		*clk = 60U;
-		*div = 3U;
-		break;
-	case 0x2U:
-		*clk = 75U;
-		*div = 3U;
-		break;
-	case 0x3U:
-		*clk = 100U;
-		*div = 3U;
-		break;
-	default:
-		break;
-	}
-	(void)brd;
-}
-
-void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
-{
-	uint32_t md;
-
-	md = (mmio_read_32(RST_MODEMR) >> 17U) & 0x5U;
-	md = (md | (md >> 1U)) & 0x3U;
-	switch (md) {
-	case 0x0U:
-		*mbps = 3200U;
-		*div = 1U;
-		break;
-	case 0x1U:
-		*mbps = 2800U;
-		*div = 1U;
-		break;
-	case 0x2U:
-		*mbps = 2400U;
-		*div = 1U;
-		break;
-	case 0x3U:
-		*mbps = 1600U;
-		*div = 1U;
-		break;
-	default:
-		break;
-	}
-	(void)brd;
-}
-
-#define _def_REFPERIOD  1890
-
-#define M3_SAMPLE_TT_A84        0xB866CC10U, 0x3B250421U
-#define M3_SAMPLE_TT_A85        0xB866CC10U, 0x3AA50421U
-#define M3_SAMPLE_TT_A86        0xB866CC10U, 0x3AA48421U
-#define M3_SAMPLE_FF_B45        0xB866CC10U, 0x3AB00C21U
-#define M3_SAMPLE_FF_B49        0xB866CC10U, 0x39B10C21U
-#define M3_SAMPLE_FF_B56        0xB866CC10U, 0x3AAF8C21U
-#define M3_SAMPLE_SS_E24        0xB866CC10U, 0x3BA39421U
-#define M3_SAMPLE_SS_E28        0xB866CC10U, 0x3C231421U
-#define M3_SAMPLE_SS_E32        0xB866CC10U, 0x3C241421U
-
-static const uint32_t termcode_by_sample[20][3] = {
-	{ M3_SAMPLE_TT_A84, 0x000158D5U },
-	{ M3_SAMPLE_TT_A85, 0x00015955U },
-	{ M3_SAMPLE_TT_A86, 0x00015955U },
-	{ M3_SAMPLE_FF_B45, 0x00015690U },
-	{ M3_SAMPLE_FF_B49, 0x00015753U },
-	{ M3_SAMPLE_FF_B56, 0x00015793U },
-	{ M3_SAMPLE_SS_E24, 0x00015996U },
-	{ M3_SAMPLE_SS_E28, 0x000159D7U },
-	{ M3_SAMPLE_SS_E32, 0x00015997U },
-	{ 0xFFFFFFFFU, 0xFFFFFFFFU, 0x0001554FU}
-};
-
-#ifdef BOARD_JUDGE_AUTO
-/* Board detect function */
-#define GPIO_INDT5	0xE605500CU
-#define LPDDR4_2RANK	(0x01U << 25U)
-
-static uint32_t _board_judge(uint32_t prr_product)
-{
-	uint32_t boardInfo;
-	uint32_t boardid = 1U;
-
-	if (prr_product == PRR_PRODUCT_M3) {
-		if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
-			boardInfo = mmio_read_32(GPIO_INDT5);
-			if ((boardInfo & LPDDR4_2RANK) == 0U) {
-				boardid = 0U;
-			}
-		}
-	}
-
-	return boardid;
-}
-#endif /* BOARD_JUDGE_AUTO */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
deleted file mode 100644
index 9f1c936..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_BOOT_INIT_DRAM_REGDEF_H
-#define RZG_BOOT_INIT_DRAM_REGDEF_H
-
-#define RCAR_DDR_VERSION	"rev.0.40"
-#define DRAM_CH_CNT		0x04U
-#define SLICE_CNT		0x04U
-#define CS_CNT			0x02U
-
-/* order : CS0A, CS0B, CS1A, CS1B */
-#define CSAB_CNT		(CS_CNT * 2U)
-
-/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
-#define CHAB_CNT		(DRAM_CH_CNT * 2)
-
-/* pll setting */
-#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
-#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
-
-/* for ddr density setting */
-#define DBMEMCONF_REG(d3, row, bank, col, dw)	\
-	(((d3) << 30U) | ((row) << 24U) | ((bank) << 16U) | ((col) << 8U) | (dw))
-
-#define DBMEMCONF_REGD(density)		\
-	(DBMEMCONF_REG((density) % 2U, ((density) + 1U) / \
-	2U + (29U - 3U - 10U - 2U), 3U, 10U, 2U))
-
-#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
-
-/* refresh mode */
-#define DBSC_REFINTS		(0x0U)
-
-/* system registers */
-#define CPG_FRQCRB		(CPG_BASE + 0x0004U)
-
-#define CPG_PLLECR		(CPG_BASE + 0x00D0U)
-#define CPG_MSTPSR5		(CPG_BASE + 0x003CU)
-#define CPG_SRCR4		(CPG_BASE + 0x00BCU)
-#define CPG_PLL3CR		(CPG_BASE + 0x00DCU)
-#define CPG_ZB3CKCR		(CPG_BASE + 0x0380U)
-#define CPG_FRQCRD		(CPG_BASE + 0x00E4U)
-#define CPG_SMSTPCR5		(CPG_BASE + 0x0144U)
-#define CPG_CPGWPR		(CPG_BASE + 0x0900U)
-#define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
-
-#define CPG_FRQCRB_KICK_BIT	BIT(31)
-#define CPG_PLLECR_PLL3E_BIT	BIT(3)
-#define CPG_PLLECR_PLL3ST_BIT	BIT(11)
-#define CPG_ZB3CKCR_ZB3ST_BIT	BIT(11)
-
-#define RST_BASE		(0xE6160000U)
-#define RST_MODEMR		(RST_BASE + 0x0060U)
-
-#define LIFEC_CHIPID(x)		(0xE6110040U + 0x04U * (x))
-
-/* DBSC registers */
-#include "ddr_regs.h"
-
-#define DBSC_DBMONCONF4		0xE6793010U
-
-#define DBSC_PLL_LOCK(ch)	(0xE6794054U + 0x100U * (ch))
-#define DBSC_PLL_LOCK_0		0xE6794054U
-#define DBSC_PLL_LOCK_1		0xE6794154U
-#define DBSC_PLL_LOCK_2		0xE6794254U
-#define DBSC_PLL_LOCK_3		0xE6794354U
-
-/* STAT registers */
-#define MSTAT_SL_INIT		0xE67E8000U
-#define MSTAT_REF_ARS		0xE67E8004U
-#define MSTATQ_STATQC		0xE67E8008U
-#define MSTATQ_WTENABLE		0xE67E8030U
-#define MSTATQ_WTREFRESH	0xE67E8034U
-#define MSTATQ_WTSETTING0	0xE67E8038U
-#define MSTATQ_WTSETTING1	0xE67E803CU
-
-#define QOS_BASE1		(0xE67F0000U)
-#define QOSCTRL_RAS		(QOS_BASE1 + 0x0000U)
-#define QOSCTRL_FIXTH		(QOS_BASE1 + 0x0004U)
-#define QOSCTRL_RAEN		(QOS_BASE1 + 0x0018U)
-#define QOSCTRL_REGGD		(QOS_BASE1 + 0x0020U)
-#define QOSCTRL_DANN		(QOS_BASE1 + 0x0030U)
-#define QOSCTRL_DANT		(QOS_BASE1 + 0x0038U)
-#define QOSCTRL_EC		(QOS_BASE1 + 0x003CU)
-#define QOSCTRL_EMS		(QOS_BASE1 + 0x0040U)
-#define QOSCTRL_INSFC		(QOS_BASE1 + 0x0050U)
-#define QOSCTRL_BERR		(QOS_BASE1 + 0x0054U)
-#define QOSCTRL_RACNT0		(QOS_BASE1 + 0x0080U)
-#define QOSCTRL_STATGEN0	(QOS_BASE1 + 0x0088U)
-
-/* other module */
-#define THS1_THCTR		0xE6198020U
-#define THS1_TEMP		0xE6198028U
-
-#endif /* RZG_BOOT_INIT_DRAM_REGDEF_H */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
deleted file mode 100644
index c137f26..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-BL2_SOURCES += drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
deleted file mode 100644
index 1da455f..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
+++ /dev/null
@@ -1,5891 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_DDR_REGDEF_H
-#define RZG_DDR_REGDEF_H
-
-#define _reg_PHY_DQ_DM_SWIZZLE0                            0x00000000U
-#define _reg_PHY_DQ_DM_SWIZZLE1                            0x00000001U
-#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY                 0x00000002U
-#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY             0x00000003U
-#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE                   0x00000004U
-#define _reg_PHY_CLK_BYPASS_OVERRIDE                       0x00000005U
-#define _reg_PHY_SW_WRDQ0_SHIFT                            0x00000006U
-#define _reg_PHY_SW_WRDQ1_SHIFT                            0x00000007U
-#define _reg_PHY_SW_WRDQ2_SHIFT                            0x00000008U
-#define _reg_PHY_SW_WRDQ3_SHIFT                            0x00000009U
-#define _reg_PHY_SW_WRDQ4_SHIFT                            0x0000000aU
-#define _reg_PHY_SW_WRDQ5_SHIFT                            0x0000000bU
-#define _reg_PHY_SW_WRDQ6_SHIFT                            0x0000000cU
-#define _reg_PHY_SW_WRDQ7_SHIFT                            0x0000000dU
-#define _reg_PHY_SW_WRDM_SHIFT                             0x0000000eU
-#define _reg_PHY_SW_WRDQS_SHIFT                            0x0000000fU
-#define _reg_PHY_DQ_TSEL_ENABLE                            0x00000010U
-#define _reg_PHY_DQ_TSEL_SELECT                            0x00000011U
-#define _reg_PHY_DQS_TSEL_ENABLE                           0x00000012U
-#define _reg_PHY_DQS_TSEL_SELECT                           0x00000013U
-#define _reg_PHY_TWO_CYC_PREAMBLE                          0x00000014U
-#define _reg_PHY_DBI_MODE                                  0x00000015U
-#define _reg_PHY_PER_RANK_CS_MAP                           0x00000016U
-#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN              0x00000017U
-#define _reg_PHY_PER_CS_TRAINING_INDEX                     0x00000018U
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY                 0x00000019U
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY                    0x0000001aU
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY               0x0000001bU
-#define _reg_PHY_LP4_BOOT_RPTR_UPDATE                      0x0000001cU
-#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY           0x0000001dU
-#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST             0x0000001eU
-#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE              0x0000001fU
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY                 0x00000020U
-#define _reg_PHY_LPBK_CONTROL                              0x00000021U
-#define _reg_PHY_LPBK_DFX_TIMEOUT_EN                       0x00000022U
-#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL                0x00000023U
-#define _reg_PHY_AUTO_TIMING_MARGIN_OBS                    0x00000024U
-#define _reg_PHY_SLICE_PWR_RDC_DISABLE                     0x00000025U
-#define _reg_PHY_PRBS_PATTERN_START                        0x00000026U
-#define _reg_PHY_PRBS_PATTERN_MASK                         0x00000027U
-#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY               0x00000028U
-#define _reg_PHY_GATE_ERROR_DELAY_SELECT                   0x00000029U
-#define _reg_SC_PHY_SNAP_OBS_REGS                          0x0000002aU
-#define _reg_PHY_LPDDR                                     0x0000002bU
-#define _reg_PHY_LPDDR_TYPE                                0x0000002cU
-#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY                    0x0000002dU
-#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY                    0x0000002eU
-#define _reg_ON_FLY_GATE_ADJUST_EN                         0x0000002fU
-#define _reg_PHY_GATE_TRACKING_OBS                         0x00000030U
-#define _reg_PHY_DFI40_POLARITY                            0x00000031U
-#define _reg_PHY_LP4_PST_AMBLE                             0x00000032U
-#define _reg_PHY_RDLVL_PATT8                               0x00000033U
-#define _reg_PHY_RDLVL_PATT9                               0x00000034U
-#define _reg_PHY_RDLVL_PATT10                              0x00000035U
-#define _reg_PHY_RDLVL_PATT11                              0x00000036U
-#define _reg_PHY_LP4_RDLVL_PATT8                           0x00000037U
-#define _reg_PHY_LP4_RDLVL_PATT9                           0x00000038U
-#define _reg_PHY_LP4_RDLVL_PATT10                          0x00000039U
-#define _reg_PHY_LP4_RDLVL_PATT11                          0x0000003aU
-#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE                     0x0000003bU
-#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE                   0x0000003cU
-#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT                0x0000003dU
-#define _reg_PHY_RDDQ_ENC_OBS_SELECT                       0x0000003eU
-#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT                   0x0000003fU
-#define _reg_PHY_WR_ENC_OBS_SELECT                         0x00000040U
-#define _reg_PHY_WR_SHIFT_OBS_SELECT                       0x00000041U
-#define _reg_PHY_FIFO_PTR_OBS_SELECT                       0x00000042U
-#define _reg_PHY_LVL_DEBUG_MODE                            0x00000043U
-#define _reg_SC_PHY_LVL_DEBUG_CONT                         0x00000044U
-#define _reg_PHY_WRLVL_CAPTURE_CNT                         0x00000045U
-#define _reg_PHY_WRLVL_UPDT_WAIT_CNT                       0x00000046U
-#define _reg_PHY_WRLVL_DQ_MASK                             0x00000047U
-#define _reg_PHY_GTLVL_CAPTURE_CNT                         0x00000048U
-#define _reg_PHY_GTLVL_UPDT_WAIT_CNT                       0x00000049U
-#define _reg_PHY_RDLVL_CAPTURE_CNT                         0x0000004aU
-#define _reg_PHY_RDLVL_UPDT_WAIT_CNT                       0x0000004bU
-#define _reg_PHY_RDLVL_OP_MODE                             0x0000004cU
-#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT                 0x0000004dU
-#define _reg_PHY_RDLVL_DATA_MASK                           0x0000004eU
-#define _reg_PHY_RDLVL_DATA_SWIZZLE                        0x0000004fU
-#define _reg_PHY_WDQLVL_BURST_CNT                          0x00000050U
-#define _reg_PHY_WDQLVL_PATT                               0x00000051U
-#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET           0x00000052U
-#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT                      0x00000053U
-#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT                    0x00000054U
-#define _reg_PHY_WDQLVL_QTR_DLY_STEP                       0x00000055U
-#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS                0x00000056U
-#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS                   0x00000057U
-#define _reg_PHY_WDQLVL_DATADM_MASK                        0x00000058U
-#define _reg_PHY_USER_PATT0                                0x00000059U
-#define _reg_PHY_USER_PATT1                                0x0000005aU
-#define _reg_PHY_USER_PATT2                                0x0000005bU
-#define _reg_PHY_USER_PATT3                                0x0000005cU
-#define _reg_PHY_USER_PATT4                                0x0000005dU
-#define _reg_PHY_DQ_SWIZZLING                              0x0000005eU
-#define _reg_PHY_CALVL_VREF_DRIVING_SLICE                  0x0000005fU
-#define _reg_SC_PHY_MANUAL_CLEAR                           0x00000060U
-#define _reg_PHY_FIFO_PTR_OBS                              0x00000061U
-#define _reg_PHY_LPBK_RESULT_OBS                           0x00000062U
-#define _reg_PHY_LPBK_ERROR_COUNT_OBS                      0x00000063U
-#define _reg_PHY_MASTER_DLY_LOCK_OBS                       0x00000064U
-#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS                      0x00000065U
-#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS                0x00000066U
-#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS       0x00000067U
-#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS       0x00000068U
-#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS                0x00000069U
-#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS                0x0000006aU
-#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS                 0x0000006bU
-#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS                  0x0000006cU
-#define _reg_PHY_WR_SHIFT_OBS                              0x0000006dU
-#define _reg_PHY_WRLVL_HARD0_DELAY_OBS                     0x0000006eU
-#define _reg_PHY_WRLVL_HARD1_DELAY_OBS                     0x0000006fU
-#define _reg_PHY_WRLVL_STATUS_OBS                          0x00000070U
-#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS                0x00000071U
-#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS                0x00000072U
-#define _reg_PHY_WRLVL_ERROR_OBS                           0x00000073U
-#define _reg_PHY_GTLVL_HARD0_DELAY_OBS                     0x00000074U
-#define _reg_PHY_GTLVL_HARD1_DELAY_OBS                     0x00000075U
-#define _reg_PHY_GTLVL_STATUS_OBS                          0x00000076U
-#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS                 0x00000077U
-#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS                 0x00000078U
-#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS            0x00000079U
-#define _reg_PHY_RDLVL_STATUS_OBS                          0x0000007aU
-#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS                    0x0000007bU
-#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS                    0x0000007cU
-#define _reg_PHY_WDQLVL_STATUS_OBS                         0x0000007dU
-#define _reg_PHY_DDL_MODE                                  0x0000007eU
-#define _reg_PHY_DDL_TEST_OBS                              0x0000007fU
-#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS                     0x00000080U
-#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD                   0x00000081U
-#define _reg_PHY_LP4_WDQS_OE_EXTEND                        0x00000082U
-#define _reg_SC_PHY_RX_CAL_START                           0x00000083U
-#define _reg_PHY_RX_CAL_OVERRIDE                           0x00000084U
-#define _reg_PHY_RX_CAL_SAMPLE_WAIT                        0x00000085U
-#define _reg_PHY_RX_CAL_DQ0                                0x00000086U
-#define _reg_PHY_RX_CAL_DQ1                                0x00000087U
-#define _reg_PHY_RX_CAL_DQ2                                0x00000088U
-#define _reg_PHY_RX_CAL_DQ3                                0x00000089U
-#define _reg_PHY_RX_CAL_DQ4                                0x0000008aU
-#define _reg_PHY_RX_CAL_DQ5                                0x0000008bU
-#define _reg_PHY_RX_CAL_DQ6                                0x0000008cU
-#define _reg_PHY_RX_CAL_DQ7                                0x0000008dU
-#define _reg_PHY_RX_CAL_DM                                 0x0000008eU
-#define _reg_PHY_RX_CAL_DQS                                0x0000008fU
-#define _reg_PHY_RX_CAL_FDBK                               0x00000090U
-#define _reg_PHY_RX_CAL_OBS                                0x00000091U
-#define _reg_PHY_RX_CAL_LOCK_OBS                           0x00000092U
-#define _reg_PHY_RX_CAL_DISABLE                            0x00000093U
-#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY                     0x00000094U
-#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY                     0x00000095U
-#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY                     0x00000096U
-#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY                     0x00000097U
-#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY                     0x00000098U
-#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY                     0x00000099U
-#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY                     0x0000009aU
-#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY                     0x0000009bU
-#define _reg_PHY_CLK_WRDM_SLAVE_DELAY                      0x0000009cU
-#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY                     0x0000009dU
-#define _reg_PHY_WRLVL_THRESHOLD_ADJUST                    0x0000009eU
-#define _reg_PHY_RDDQ0_SLAVE_DELAY                         0x0000009fU
-#define _reg_PHY_RDDQ1_SLAVE_DELAY                         0x000000a0U
-#define _reg_PHY_RDDQ2_SLAVE_DELAY                         0x000000a1U
-#define _reg_PHY_RDDQ3_SLAVE_DELAY                         0x000000a2U
-#define _reg_PHY_RDDQ4_SLAVE_DELAY                         0x000000a3U
-#define _reg_PHY_RDDQ5_SLAVE_DELAY                         0x000000a4U
-#define _reg_PHY_RDDQ6_SLAVE_DELAY                         0x000000a5U
-#define _reg_PHY_RDDQ7_SLAVE_DELAY                         0x000000a6U
-#define _reg_PHY_RDDM_SLAVE_DELAY                          0x000000a7U
-#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY                0x000000a8U
-#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY                0x000000a9U
-#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY                0x000000aaU
-#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY                0x000000abU
-#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY                0x000000acU
-#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY                0x000000adU
-#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY                0x000000aeU
-#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY                0x000000afU
-#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY                0x000000b0U
-#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY                0x000000b1U
-#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY                0x000000b2U
-#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY                0x000000b3U
-#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY                0x000000b4U
-#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY                0x000000b5U
-#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY                0x000000b6U
-#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY                0x000000b7U
-#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY                 0x000000b8U
-#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY                 0x000000b9U
-#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY                    0x000000baU
-#define _reg_PHY_RDDQS_LATENCY_ADJUST                      0x000000bbU
-#define _reg_PHY_WRITE_PATH_LAT_ADD                        0x000000bcU
-#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD               0x000000bdU
-#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD              0x000000beU
-#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO                    0x000000bfU
-#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START                 0x000000c0U
-#define _reg_PHY_GTLVL_LAT_ADJ_START                       0x000000c1U
-#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START                 0x000000c2U
-#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START              0x000000c3U
-#define _reg_PHY_FDBK_PWR_CTRL                             0x000000c4U
-#define _reg_PHY_DQ_OE_TIMING                              0x000000c5U
-#define _reg_PHY_DQ_TSEL_RD_TIMING                         0x000000c6U
-#define _reg_PHY_DQ_TSEL_WR_TIMING                         0x000000c7U
-#define _reg_PHY_DQS_OE_TIMING                             0x000000c8U
-#define _reg_PHY_DQS_TSEL_RD_TIMING                        0x000000c9U
-#define _reg_PHY_DQS_OE_RD_TIMING                          0x000000caU
-#define _reg_PHY_DQS_TSEL_WR_TIMING                        0x000000cbU
-#define _reg_PHY_PER_CS_TRAINING_EN                        0x000000ccU
-#define _reg_PHY_DQ_IE_TIMING                              0x000000cdU
-#define _reg_PHY_DQS_IE_TIMING                             0x000000ceU
-#define _reg_PHY_RDDATA_EN_IE_DLY                          0x000000cfU
-#define _reg_PHY_IE_MODE                                   0x000000d0U
-#define _reg_PHY_RDDATA_EN_DLY                             0x000000d1U
-#define _reg_PHY_RDDATA_EN_TSEL_DLY                        0x000000d2U
-#define _reg_PHY_RDDATA_EN_OE_DLY                          0x000000d3U
-#define _reg_PHY_SW_MASTER_MODE                            0x000000d4U
-#define _reg_PHY_MASTER_DELAY_START                        0x000000d5U
-#define _reg_PHY_MASTER_DELAY_STEP                         0x000000d6U
-#define _reg_PHY_MASTER_DELAY_WAIT                         0x000000d7U
-#define _reg_PHY_MASTER_DELAY_HALF_MEASURE                 0x000000d8U
-#define _reg_PHY_RPTR_UPDATE                               0x000000d9U
-#define _reg_PHY_WRLVL_DLY_STEP                            0x000000daU
-#define _reg_PHY_WRLVL_RESP_WAIT_CNT                       0x000000dbU
-#define _reg_PHY_GTLVL_DLY_STEP                            0x000000dcU
-#define _reg_PHY_GTLVL_RESP_WAIT_CNT                       0x000000ddU
-#define _reg_PHY_GTLVL_BACK_STEP                           0x000000deU
-#define _reg_PHY_GTLVL_FINAL_STEP                          0x000000dfU
-#define _reg_PHY_WDQLVL_DLY_STEP                           0x000000e0U
-#define _reg_PHY_TOGGLE_PRE_SUPPORT                        0x000000e1U
-#define _reg_PHY_RDLVL_DLY_STEP                            0x000000e2U
-#define _reg_PHY_WRPATH_GATE_DISABLE                       0x000000e3U
-#define _reg_PHY_WRPATH_GATE_TIMING                        0x000000e4U
-#define _reg_PHY_ADR0_SW_WRADDR_SHIFT                      0x000000e5U
-#define _reg_PHY_ADR1_SW_WRADDR_SHIFT                      0x000000e6U
-#define _reg_PHY_ADR2_SW_WRADDR_SHIFT                      0x000000e7U
-#define _reg_PHY_ADR3_SW_WRADDR_SHIFT                      0x000000e8U
-#define _reg_PHY_ADR4_SW_WRADDR_SHIFT                      0x000000e9U
-#define _reg_PHY_ADR5_SW_WRADDR_SHIFT                      0x000000eaU
-#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY             0x000000ebU
-#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE                   0x000000ecU
-#define _reg_SC_PHY_ADR_MANUAL_CLEAR                       0x000000edU
-#define _reg_PHY_ADR_LPBK_RESULT_OBS                       0x000000eeU
-#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS                  0x000000efU
-#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT            0x000000f0U
-#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS                   0x000000f1U
-#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS                  0x000000f2U
-#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS                 0x000000f3U
-#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE                 0x000000f4U
-#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT                0x000000f5U
-#define _reg_SC_PHY_ADR_SNAP_OBS_REGS                      0x000000f6U
-#define _reg_PHY_ADR_TSEL_ENABLE                           0x000000f7U
-#define _reg_PHY_ADR_LPBK_CONTROL                          0x000000f8U
-#define _reg_PHY_ADR_PRBS_PATTERN_START                    0x000000f9U
-#define _reg_PHY_ADR_PRBS_PATTERN_MASK                     0x000000faU
-#define _reg_PHY_ADR_PWR_RDC_DISABLE                       0x000000fbU
-#define _reg_PHY_ADR_TYPE                                  0x000000fcU
-#define _reg_PHY_ADR_WRADDR_SHIFT_OBS                      0x000000fdU
-#define _reg_PHY_ADR_IE_MODE                               0x000000feU
-#define _reg_PHY_ADR_DDL_MODE                              0x000000ffU
-#define _reg_PHY_ADR_DDL_TEST_OBS                          0x00000100U
-#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS                 0x00000101U
-#define _reg_PHY_ADR_CALVL_START                           0x00000102U
-#define _reg_PHY_ADR_CALVL_COARSE_DLY                      0x00000103U
-#define _reg_PHY_ADR_CALVL_QTR                             0x00000104U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0                        0x00000105U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1                        0x00000106U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0_0                      0x00000107U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1_0                      0x00000108U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0_1                      0x00000109U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1_1                      0x0000010aU
-#define _reg_PHY_ADR_CALVL_DEVICE_MAP                      0x0000010bU
-#define _reg_PHY_ADR_CALVL_RANK_CTRL                       0x0000010cU
-#define _reg_PHY_ADR_CALVL_NUM_PATTERNS                    0x0000010dU
-#define _reg_PHY_ADR_CALVL_CAPTURE_CNT                     0x0000010eU
-#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT                   0x0000010fU
-#define _reg_PHY_ADR_CALVL_DEBUG_MODE                      0x00000110U
-#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT                   0x00000111U
-#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR                    0x00000112U
-#define _reg_PHY_ADR_CALVL_OBS_SELECT                      0x00000113U
-#define _reg_PHY_ADR_CALVL_OBS0                            0x00000114U
-#define _reg_PHY_ADR_CALVL_OBS1                            0x00000115U
-#define _reg_PHY_ADR_CALVL_RESULT                          0x00000116U
-#define _reg_PHY_ADR_CALVL_FG_0                            0x00000117U
-#define _reg_PHY_ADR_CALVL_BG_0                            0x00000118U
-#define _reg_PHY_ADR_CALVL_FG_1                            0x00000119U
-#define _reg_PHY_ADR_CALVL_BG_1                            0x0000011aU
-#define _reg_PHY_ADR_CALVL_FG_2                            0x0000011bU
-#define _reg_PHY_ADR_CALVL_BG_2                            0x0000011cU
-#define _reg_PHY_ADR_CALVL_FG_3                            0x0000011dU
-#define _reg_PHY_ADR_CALVL_BG_3                            0x0000011eU
-#define _reg_PHY_ADR_ADDR_SEL                              0x0000011fU
-#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY                    0x00000120U
-#define _reg_PHY_ADR_BIT_MASK                              0x00000121U
-#define _reg_PHY_ADR_SEG_MASK                              0x00000122U
-#define _reg_PHY_ADR_CALVL_TRAIN_MASK                      0x00000123U
-#define _reg_PHY_ADR_CSLVL_TRAIN_MASK                      0x00000124U
-#define _reg_PHY_ADR_SW_TXIO_CTRL                          0x00000125U
-#define _reg_PHY_ADR_TSEL_SELECT                           0x00000126U
-#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY                   0x00000127U
-#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY                   0x00000128U
-#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY                   0x00000129U
-#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY                   0x0000012aU
-#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY                   0x0000012bU
-#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY                   0x0000012cU
-#define _reg_PHY_ADR_SW_MASTER_MODE                        0x0000012dU
-#define _reg_PHY_ADR_MASTER_DELAY_START                    0x0000012eU
-#define _reg_PHY_ADR_MASTER_DELAY_STEP                     0x0000012fU
-#define _reg_PHY_ADR_MASTER_DELAY_WAIT                     0x00000130U
-#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE             0x00000131U
-#define _reg_PHY_ADR_CALVL_DLY_STEP                        0x00000132U
-#define _reg_PHY_FREQ_SEL                                  0x00000133U
-#define _reg_PHY_FREQ_SEL_FROM_REGIF                       0x00000134U
-#define _reg_PHY_FREQ_SEL_MULTICAST_EN                     0x00000135U
-#define _reg_PHY_FREQ_SEL_INDEX                            0x00000136U
-#define _reg_PHY_SW_GRP_SHIFT_0                            0x00000137U
-#define _reg_PHY_SW_GRP_SHIFT_1                            0x00000138U
-#define _reg_PHY_SW_GRP_SHIFT_2                            0x00000139U
-#define _reg_PHY_SW_GRP_SHIFT_3                            0x0000013aU
-#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY                    0x0000013bU
-#define _reg_PHY_SW_GRP_BYPASS_SHIFT                       0x0000013cU
-#define _reg_PHY_GRP_BYPASS_OVERRIDE                       0x0000013dU
-#define _reg_SC_PHY_MANUAL_UPDATE                          0x0000013eU
-#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE            0x0000013fU
-#define _reg_PHY_LP4_BOOT_DISABLE                          0x00000140U
-#define _reg_PHY_CSLVL_ENABLE                              0x00000141U
-#define _reg_PHY_CSLVL_CS_MAP                              0x00000142U
-#define _reg_PHY_CSLVL_START                               0x00000143U
-#define _reg_PHY_CSLVL_QTR                                 0x00000144U
-#define _reg_PHY_CSLVL_COARSE_CHK                          0x00000145U
-#define _reg_PHY_CSLVL_CAPTURE_CNT                         0x00000146U
-#define _reg_PHY_CSLVL_COARSE_DLY                          0x00000147U
-#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT                  0x00000148U
-#define _reg_PHY_CSLVL_DEBUG_MODE                          0x00000149U
-#define _reg_SC_PHY_CSLVL_DEBUG_CONT                       0x0000014aU
-#define _reg_SC_PHY_CSLVL_ERROR_CLR                        0x0000014bU
-#define _reg_PHY_CSLVL_OBS0                                0x0000014cU
-#define _reg_PHY_CSLVL_OBS1                                0x0000014dU
-#define _reg_PHY_CALVL_CS_MAP                              0x0000014eU
-#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT                0x0000014fU
-#define _reg_PHY_GRP_SHIFT_OBS_SELECT                      0x00000150U
-#define _reg_PHY_GRP_SLV_DLY_ENC_OBS                       0x00000151U
-#define _reg_PHY_GRP_SHIFT_OBS                             0x00000152U
-#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE              0x00000153U
-#define _reg_PHY_ADRCTL_SNAP_OBS_REGS                      0x00000154U
-#define _reg_PHY_DFI_PHYUPD_TYPE                           0x00000155U
-#define _reg_PHY_ADRCTL_LPDDR                              0x00000156U
-#define _reg_PHY_LP4_ACTIVE                                0x00000157U
-#define _reg_PHY_LPDDR3_CS                                 0x00000158U
-#define _reg_PHY_CALVL_RESULT_MASK                         0x00000159U
-#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES                  0x0000015aU
-#define _reg_PHY_SW_TXIO_CTRL_0                            0x0000015bU
-#define _reg_PHY_SW_TXIO_CTRL_1                            0x0000015cU
-#define _reg_PHY_SW_TXIO_CTRL_2                            0x0000015dU
-#define _reg_PHY_SW_TXIO_CTRL_3                            0x0000015eU
-#define _reg_PHY_MEMCLK_SW_TXIO_CTRL                       0x0000015fU
-#define _reg_PHY_CA_SW_TXPWR_CTRL                          0x00000160U
-#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL                      0x00000161U
-#define _reg_PHY_USER_DEF_REG_AC_0                         0x00000162U
-#define _reg_PHY_USER_DEF_REG_AC_1                         0x00000163U
-#define _reg_PHY_USER_DEF_REG_AC_2                         0x00000164U
-#define _reg_PHY_USER_DEF_REG_AC_3                         0x00000165U
-#define _reg_PHY_UPDATE_CLK_CAL_VALUES                     0x00000166U
-#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE                 0x00000167U
-#define _reg_PHY_PLL_CTRL                                  0x00000168U
-#define _reg_PHY_PLL_CTRL_TOP                              0x00000169U
-#define _reg_PHY_PLL_CTRL_CA                               0x0000016aU
-#define _reg_PHY_PLL_BYPASS                                0x0000016bU
-#define _reg_PHY_LOW_FREQ_SEL                              0x0000016cU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_0                        0x0000016dU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_1                        0x0000016eU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_2                        0x0000016fU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_3                        0x00000170U
-#define _reg_PHY_PAD_VREF_CTRL_AC                          0x00000171U
-#define _reg_PHY_CSLVL_DLY_STEP                            0x00000172U
-#define _reg_PHY_SET_DFI_INPUT_0                           0x00000173U
-#define _reg_PHY_SET_DFI_INPUT_1                           0x00000174U
-#define _reg_PHY_SET_DFI_INPUT_2                           0x00000175U
-#define _reg_PHY_SET_DFI_INPUT_3                           0x00000176U
-#define _reg_PHY_GRP_SLAVE_DELAY_0                         0x00000177U
-#define _reg_PHY_GRP_SLAVE_DELAY_1                         0x00000178U
-#define _reg_PHY_GRP_SLAVE_DELAY_2                         0x00000179U
-#define _reg_PHY_GRP_SLAVE_DELAY_3                         0x0000017aU
-#define _reg_PHY_CS_ACS_ALLOCATION_0                       0x0000017bU
-#define _reg_PHY_CS_ACS_ALLOCATION_1                       0x0000017cU
-#define _reg_PHY_CS_ACS_ALLOCATION_2                       0x0000017dU
-#define _reg_PHY_CS_ACS_ALLOCATION_3                       0x0000017eU
-#define _reg_PHY_LP4_BOOT_PLL_CTRL                         0x0000017fU
-#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA                      0x00000180U
-#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL                     0x00000181U
-#define _reg_PHY_PLL_CTRL_OVERRIDE                         0x00000182U
-#define _reg_PHY_PLL_WAIT                                  0x00000183U
-#define _reg_PHY_PLL_WAIT_TOP                              0x00000184U
-#define _reg_PHY_PLL_OBS_0                                 0x00000185U
-#define _reg_PHY_PLL_OBS_1                                 0x00000186U
-#define _reg_PHY_PLL_OBS_2                                 0x00000187U
-#define _reg_PHY_PLL_OBS_3                                 0x00000188U
-#define _reg_PHY_PLL_OBS_4                                 0x00000189U
-#define _reg_PHY_PLL_TESTOUT_SEL                           0x0000018aU
-#define _reg_PHY_TCKSRE_WAIT                               0x0000018bU
-#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL                     0x0000018cU
-#define _reg_PHY_LP_WAKEUP                                 0x0000018dU
-#define _reg_PHY_LS_IDLE_EN                                0x0000018eU
-#define _reg_PHY_LP_CTRLUPD_CNTR_CFG                       0x0000018fU
-#define _reg_PHY_TDFI_PHY_WRDELAY                          0x00000190U
-#define _reg_PHY_PAD_FDBK_DRIVE                            0x00000191U
-#define _reg_PHY_PAD_DATA_DRIVE                            0x00000192U
-#define _reg_PHY_PAD_DQS_DRIVE                             0x00000193U
-#define _reg_PHY_PAD_ADDR_DRIVE                            0x00000194U
-#define _reg_PHY_PAD_CLK_DRIVE                             0x00000195U
-#define _reg_PHY_PAD_FDBK_TERM                             0x00000196U
-#define _reg_PHY_PAD_DATA_TERM                             0x00000197U
-#define _reg_PHY_PAD_DQS_TERM                              0x00000198U
-#define _reg_PHY_PAD_ADDR_TERM                             0x00000199U
-#define _reg_PHY_PAD_CLK_TERM                              0x0000019aU
-#define _reg_PHY_PAD_CKE_DRIVE                             0x0000019bU
-#define _reg_PHY_PAD_CKE_TERM                              0x0000019cU
-#define _reg_PHY_PAD_RST_DRIVE                             0x0000019dU
-#define _reg_PHY_PAD_RST_TERM                              0x0000019eU
-#define _reg_PHY_PAD_CS_DRIVE                              0x0000019fU
-#define _reg_PHY_PAD_CS_TERM                               0x000001a0U
-#define _reg_PHY_PAD_ODT_DRIVE                             0x000001a1U
-#define _reg_PHY_PAD_ODT_TERM                              0x000001a2U
-#define _reg_PHY_ADRCTL_RX_CAL                             0x000001a3U
-#define _reg_PHY_ADRCTL_LP3_RX_CAL                         0x000001a4U
-#define _reg_PHY_TST_CLK_PAD_CTRL                          0x000001a5U
-#define _reg_PHY_TST_CLK_PAD_CTRL2                         0x000001a6U
-#define _reg_PHY_CAL_MODE_0                                0x000001a7U
-#define _reg_PHY_CAL_CLEAR_0                               0x000001a8U
-#define _reg_PHY_CAL_START_0                               0x000001a9U
-#define _reg_PHY_CAL_INTERVAL_COUNT_0                      0x000001aaU
-#define _reg_PHY_CAL_SAMPLE_WAIT_0                         0x000001abU
-#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0                 0x000001acU
-#define _reg_PHY_CAL_CLK_SELECT_0                          0x000001adU
-#define _reg_PHY_CAL_RESULT_OBS_0                          0x000001aeU
-#define _reg_PHY_CAL_RESULT2_OBS_0                         0x000001afU
-#define _reg_PHY_CAL_CPTR_CNT_0                            0x000001b0U
-#define _reg_PHY_CAL_SETTLING_PRD_0                        0x000001b1U
-#define _reg_PHY_CAL_PU_FINE_ADJ_0                         0x000001b2U
-#define _reg_PHY_CAL_PD_FINE_ADJ_0                         0x000001b3U
-#define _reg_PHY_CAL_RCV_FINE_ADJ_0                        0x000001b4U
-#define _reg_PHY_CAL_DBG_CFG_0                             0x000001b5U
-#define _reg_SC_PHY_PAD_DBG_CONT_0                         0x000001b6U
-#define _reg_PHY_CAL_RESULT3_OBS_0                         0x000001b7U
-#define _reg_PHY_ADRCTL_PVT_MAP_0                          0x000001b8U
-#define _reg_PHY_CAL_SLOPE_ADJ_0                           0x000001b9U
-#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0                     0x000001baU
-#define _reg_PHY_CAL_TWO_PASS_CFG_0                        0x000001bbU
-#define _reg_PHY_CAL_SW_CAL_CFG_0                          0x000001bcU
-#define _reg_PHY_CAL_RANGE_MIN_0                           0x000001bdU
-#define _reg_PHY_CAL_RANGE_MAX_0                           0x000001beU
-#define _reg_PHY_PAD_ATB_CTRL                              0x000001bfU
-#define _reg_PHY_ADRCTL_MANUAL_UPDATE                      0x000001c0U
-#define _reg_PHY_AC_LPBK_ERR_CLEAR                         0x000001c1U
-#define _reg_PHY_AC_LPBK_OBS_SELECT                        0x000001c2U
-#define _reg_PHY_AC_LPBK_ENABLE                            0x000001c3U
-#define _reg_PHY_AC_LPBK_CONTROL                           0x000001c4U
-#define _reg_PHY_AC_PRBS_PATTERN_START                     0x000001c5U
-#define _reg_PHY_AC_PRBS_PATTERN_MASK                      0x000001c6U
-#define _reg_PHY_AC_LPBK_RESULT_OBS                        0x000001c7U
-#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT                    0x000001c8U
-#define _reg_PHY_AC_CLK_LPBK_ENABLE                        0x000001c9U
-#define _reg_PHY_AC_CLK_LPBK_CONTROL                       0x000001caU
-#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS                    0x000001cbU
-#define _reg_PHY_AC_PWR_RDC_DISABLE                        0x000001ccU
-#define _reg_PHY_DATA_BYTE_ORDER_SEL                       0x000001cdU
-#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH                  0x000001ceU
-#define _reg_PHY_LPDDR4_CONNECT                            0x000001cfU
-#define _reg_PHY_CALVL_DEVICE_MAP                          0x000001d0U
-#define _reg_PHY_ADR_DISABLE                               0x000001d1U
-#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL                   0x000001d2U
-#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE                   0x000001d3U
-#define _reg_PHY_DDL_AC_ENABLE                             0x000001d4U
-#define _reg_PHY_DDL_AC_MODE                               0x000001d5U
-#define _reg_PHY_PAD_BACKGROUND_CAL                        0x000001d6U
-#define _reg_PHY_INIT_UPDATE_CONFIG                        0x000001d7U
-#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC                0x000001d8U
-#define _reg_PHY_DLL_RST_EN                                0x000001d9U
-#define _reg_PHY_AC_INIT_COMPLETE_OBS                      0x000001daU
-#define _reg_PHY_DS_INIT_COMPLETE_OBS                      0x000001dbU
-#define _reg_PHY_UPDATE_MASK                               0x000001dcU
-#define _reg_PHY_PLL_SWITCH_CNT                            0x000001ddU
-#define _reg_PI_START                                      0x000001deU
-#define _reg_PI_DRAM_CLASS                                 0x000001dfU
-#define _reg_PI_VERSION                                    0x000001e0U
-#define _reg_PI_NORMAL_LVL_SEQ                             0x000001e1U
-#define _reg_PI_INIT_LVL_EN                                0x000001e2U
-#define _reg_PI_NOTCARE_PHYUPD                             0x000001e3U
-#define _reg_PI_ONBUS_MBIST                                0x000001e4U
-#define _reg_PI_TCMD_GAP                                   0x000001e5U
-#define _reg_PI_MASTER_ACK_DURATION_MIN                    0x000001e6U
-#define _reg_PI_DFI_VERSION                                0x000001e7U
-#define _reg_PI_TDFI_PHYMSTR_TYPE0                         0x000001e8U
-#define _reg_PI_TDFI_PHYMSTR_TYPE1                         0x000001e9U
-#define _reg_PI_TDFI_PHYMSTR_TYPE2                         0x000001eaU
-#define _reg_PI_TDFI_PHYMSTR_TYPE3                         0x000001ebU
-#define _reg_PI_DFI_PHYMSTR_TYPE                           0x000001ecU
-#define _reg_PI_DFI_PHYMSTR_CS_STATE_R                     0x000001edU
-#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R                    0x000001eeU
-#define _reg_PI_TDFI_PHYMSTR_MAX_F0                        0x000001efU
-#define _reg_PI_TDFI_PHYMSTR_RESP_F0                       0x000001f0U
-#define _reg_PI_TDFI_PHYMSTR_MAX_F1                        0x000001f1U
-#define _reg_PI_TDFI_PHYMSTR_RESP_F1                       0x000001f2U
-#define _reg_PI_TDFI_PHYMSTR_MAX_F2                        0x000001f3U
-#define _reg_PI_TDFI_PHYMSTR_RESP_F2                       0x000001f4U
-#define _reg_PI_TDFI_PHYUPD_RESP_F0                        0x000001f5U
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F0                       0x000001f6U
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F0                       0x000001f7U
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F0                       0x000001f8U
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F0                       0x000001f9U
-#define _reg_PI_TDFI_PHYUPD_RESP_F1                        0x000001faU
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F1                       0x000001fbU
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F1                       0x000001fcU
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F1                       0x000001fdU
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F1                       0x000001feU
-#define _reg_PI_TDFI_PHYUPD_RESP_F2                        0x000001ffU
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F2                       0x00000200U
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F2                       0x00000201U
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F2                       0x00000202U
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F2                       0x00000203U
-#define _reg_PI_CONTROL_ERROR_STATUS                       0x00000204U
-#define _reg_PI_EXIT_AFTER_INIT_CALVL                      0x00000205U
-#define _reg_PI_FREQ_MAP                                   0x00000206U
-#define _reg_PI_INIT_WORK_FREQ                             0x00000207U
-#define _reg_PI_INIT_DFS_CALVL_ONLY                        0x00000208U
-#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY                  0x00000209U
-#define _reg_PI_POWER_ON_SEQ_END_ARRAY                     0x0000020aU
-#define _reg_PI_SEQ1_PAT                                   0x0000020bU
-#define _reg_PI_SEQ1_PAT_MASK                              0x0000020cU
-#define _reg_PI_SEQ2_PAT                                   0x0000020dU
-#define _reg_PI_SEQ2_PAT_MASK                              0x0000020eU
-#define _reg_PI_SEQ3_PAT                                   0x0000020fU
-#define _reg_PI_SEQ3_PAT_MASK                              0x00000210U
-#define _reg_PI_SEQ4_PAT                                   0x00000211U
-#define _reg_PI_SEQ4_PAT_MASK                              0x00000212U
-#define _reg_PI_SEQ5_PAT                                   0x00000213U
-#define _reg_PI_SEQ5_PAT_MASK                              0x00000214U
-#define _reg_PI_SEQ6_PAT                                   0x00000215U
-#define _reg_PI_SEQ6_PAT_MASK                              0x00000216U
-#define _reg_PI_SEQ7_PAT                                   0x00000217U
-#define _reg_PI_SEQ7_PAT_MASK                              0x00000218U
-#define _reg_PI_SEQ8_PAT                                   0x00000219U
-#define _reg_PI_SEQ8_PAT_MASK                              0x0000021aU
-#define _reg_PI_WDT_DISABLE                                0x0000021bU
-#define _reg_PI_SW_RST_N                                   0x0000021cU
-#define _reg_RESERVED_R0                                   0x0000021dU
-#define _reg_PI_CS_MAP                                     0x0000021eU
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0                  0x0000021fU
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1                  0x00000220U
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2                  0x00000221U
-#define _reg_PI_TMRR                                       0x00000222U
-#define _reg_PI_WRLAT_F0                                   0x00000223U
-#define _reg_PI_ADDITIVE_LAT_F0                            0x00000224U
-#define _reg_PI_CASLAT_LIN_F0                              0x00000225U
-#define _reg_PI_WRLAT_F1                                   0x00000226U
-#define _reg_PI_ADDITIVE_LAT_F1                            0x00000227U
-#define _reg_PI_CASLAT_LIN_F1                              0x00000228U
-#define _reg_PI_WRLAT_F2                                   0x00000229U
-#define _reg_PI_ADDITIVE_LAT_F2                            0x0000022aU
-#define _reg_PI_CASLAT_LIN_F2                              0x0000022bU
-#define _reg_PI_PREAMBLE_SUPPORT                           0x0000022cU
-#define _reg_PI_AREFRESH                                   0x0000022dU
-#define _reg_PI_MCAREF_FORWARD_ONLY                        0x0000022eU
-#define _reg_PI_TRFC_F0                                    0x0000022fU
-#define _reg_PI_TREF_F0                                    0x00000230U
-#define _reg_PI_TRFC_F1                                    0x00000231U
-#define _reg_PI_TREF_F1                                    0x00000232U
-#define _reg_PI_TRFC_F2                                    0x00000233U
-#define _reg_PI_TREF_F2                                    0x00000234U
-#define _reg_RESERVED_H3VER2                               0x00000235U
-#define _reg_PI_TREF_INTERVAL                              0x00000236U
-#define _reg_PI_FREQ_CHANGE_REG_COPY                       0x00000237U
-#define _reg_PI_FREQ_SEL_FROM_REGIF                        0x00000238U
-#define _reg_PI_SWLVL_LOAD                                 0x00000239U
-#define _reg_PI_SWLVL_OP_DONE                              0x0000023aU
-#define _reg_PI_SW_WRLVL_RESP_0                            0x0000023bU
-#define _reg_PI_SW_WRLVL_RESP_1                            0x0000023cU
-#define _reg_PI_SW_WRLVL_RESP_2                            0x0000023dU
-#define _reg_PI_SW_WRLVL_RESP_3                            0x0000023eU
-#define _reg_PI_SW_RDLVL_RESP_0                            0x0000023fU
-#define _reg_PI_SW_RDLVL_RESP_1                            0x00000240U
-#define _reg_PI_SW_RDLVL_RESP_2                            0x00000241U
-#define _reg_PI_SW_RDLVL_RESP_3                            0x00000242U
-#define _reg_PI_SW_CALVL_RESP_0                            0x00000243U
-#define _reg_PI_SW_LEVELING_MODE                           0x00000244U
-#define _reg_PI_SWLVL_START                                0x00000245U
-#define _reg_PI_SWLVL_EXIT                                 0x00000246U
-#define _reg_PI_SWLVL_WR_SLICE_0                           0x00000247U
-#define _reg_PI_SWLVL_RD_SLICE_0                           0x00000248U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0                  0x00000249U
-#define _reg_PI_SW_WDQLVL_RESP_0                           0x0000024aU
-#define _reg_PI_SWLVL_WR_SLICE_1                           0x0000024bU
-#define _reg_PI_SWLVL_RD_SLICE_1                           0x0000024cU
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1                  0x0000024dU
-#define _reg_PI_SW_WDQLVL_RESP_1                           0x0000024eU
-#define _reg_PI_SWLVL_WR_SLICE_2                           0x0000024fU
-#define _reg_PI_SWLVL_RD_SLICE_2                           0x00000250U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2                  0x00000251U
-#define _reg_PI_SW_WDQLVL_RESP_2                           0x00000252U
-#define _reg_PI_SWLVL_WR_SLICE_3                           0x00000253U
-#define _reg_PI_SWLVL_RD_SLICE_3                           0x00000254U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3                  0x00000255U
-#define _reg_PI_SW_WDQLVL_RESP_3                           0x00000256U
-#define _reg_PI_SW_WDQLVL_VREF                             0x00000257U
-#define _reg_PI_SWLVL_SM2_START                            0x00000258U
-#define _reg_PI_SWLVL_SM2_WR                               0x00000259U
-#define _reg_PI_SWLVL_SM2_RD                               0x0000025aU
-#define _reg_PI_SEQUENTIAL_LVL_REQ                         0x0000025bU
-#define _reg_PI_DFS_PERIOD_EN                              0x0000025cU
-#define _reg_PI_SRE_PERIOD_EN                              0x0000025dU
-#define _reg_PI_DFI40_POLARITY                             0x0000025eU
-#define _reg_PI_16BIT_DRAM_CONNECT                         0x0000025fU
-#define _reg_PI_TDFI_CTRL_DELAY_F0                         0x00000260U
-#define _reg_PI_TDFI_CTRL_DELAY_F1                         0x00000261U
-#define _reg_PI_TDFI_CTRL_DELAY_F2                         0x00000262U
-#define _reg_PI_WRLVL_REQ                                  0x00000263U
-#define _reg_PI_WRLVL_CS                                   0x00000264U
-#define _reg_PI_WLDQSEN                                    0x00000265U
-#define _reg_PI_WLMRD                                      0x00000266U
-#define _reg_PI_WRLVL_EN_F0                                0x00000267U
-#define _reg_PI_WRLVL_EN_F1                                0x00000268U
-#define _reg_PI_WRLVL_EN_F2                                0x00000269U
-#define _reg_PI_WRLVL_EN                                   0x0000026aU
-#define _reg_PI_WRLVL_INTERVAL                             0x0000026bU
-#define _reg_PI_WRLVL_PERIODIC                             0x0000026cU
-#define _reg_PI_WRLVL_ON_SREF_EXIT                         0x0000026dU
-#define _reg_PI_WRLVL_DISABLE_DFS                          0x0000026eU
-#define _reg_PI_WRLVL_RESP_MASK                            0x0000026fU
-#define _reg_PI_WRLVL_ROTATE                               0x00000270U
-#define _reg_PI_WRLVL_CS_MAP                               0x00000271U
-#define _reg_PI_WRLVL_ERROR_STATUS                         0x00000272U
-#define _reg_PI_TDFI_WRLVL_EN                              0x00000273U
-#define _reg_PI_TDFI_WRLVL_WW_F0                           0x00000274U
-#define _reg_PI_TDFI_WRLVL_WW_F1                           0x00000275U
-#define _reg_PI_TDFI_WRLVL_WW_F2                           0x00000276U
-#define _reg_PI_TDFI_WRLVL_WW                              0x00000277U
-#define _reg_PI_TDFI_WRLVL_RESP                            0x00000278U
-#define _reg_PI_TDFI_WRLVL_MAX                             0x00000279U
-#define _reg_PI_WRLVL_STROBE_NUM                           0x0000027aU
-#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ                    0x0000027bU
-#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR                    0x0000027cU
-#define _reg_PI_TODTL_2CMD_F0                              0x0000027dU
-#define _reg_PI_ODT_EN_F0                                  0x0000027eU
-#define _reg_PI_TODTL_2CMD_F1                              0x0000027fU
-#define _reg_PI_ODT_EN_F1                                  0x00000280U
-#define _reg_PI_TODTL_2CMD_F2                              0x00000281U
-#define _reg_PI_ODT_EN_F2                                  0x00000282U
-#define _reg_PI_TODTH_WR                                   0x00000283U
-#define _reg_PI_TODTH_RD                                   0x00000284U
-#define _reg_PI_ODT_RD_MAP_CS0                             0x00000285U
-#define _reg_PI_ODT_WR_MAP_CS0                             0x00000286U
-#define _reg_PI_ODT_RD_MAP_CS1                             0x00000287U
-#define _reg_PI_ODT_WR_MAP_CS1                             0x00000288U
-#define _reg_PI_ODT_RD_MAP_CS2                             0x00000289U
-#define _reg_PI_ODT_WR_MAP_CS2                             0x0000028aU
-#define _reg_PI_ODT_RD_MAP_CS3                             0x0000028bU
-#define _reg_PI_ODT_WR_MAP_CS3                             0x0000028cU
-#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD                    0x0000028dU
-#define _reg_PI_ODTLON_F0                                  0x0000028eU
-#define _reg_PI_TODTON_MIN_F0                              0x0000028fU
-#define _reg_PI_ODTLON_F1                                  0x00000290U
-#define _reg_PI_TODTON_MIN_F1                              0x00000291U
-#define _reg_PI_ODTLON_F2                                  0x00000292U
-#define _reg_PI_TODTON_MIN_F2                              0x00000293U
-#define _reg_PI_WR_TO_ODTH_F0                              0x00000294U
-#define _reg_PI_WR_TO_ODTH_F1                              0x00000295U
-#define _reg_PI_WR_TO_ODTH_F2                              0x00000296U
-#define _reg_PI_RD_TO_ODTH_F0                              0x00000297U
-#define _reg_PI_RD_TO_ODTH_F1                              0x00000298U
-#define _reg_PI_RD_TO_ODTH_F2                              0x00000299U
-#define _reg_PI_ADDRESS_MIRRORING                          0x0000029aU
-#define _reg_PI_RDLVL_REQ                                  0x0000029bU
-#define _reg_PI_RDLVL_GATE_REQ                             0x0000029cU
-#define _reg_PI_RDLVL_CS                                   0x0000029dU
-#define _reg_PI_RDLVL_PAT_0                                0x0000029eU
-#define _reg_PI_RDLVL_PAT_1                                0x0000029fU
-#define _reg_PI_RDLVL_PAT_2                                0x000002a0U
-#define _reg_PI_RDLVL_PAT_3                                0x000002a1U
-#define _reg_PI_RDLVL_PAT_4                                0x000002a2U
-#define _reg_PI_RDLVL_PAT_5                                0x000002a3U
-#define _reg_PI_RDLVL_PAT_6                                0x000002a4U
-#define _reg_PI_RDLVL_PAT_7                                0x000002a5U
-#define _reg_PI_RDLVL_SEQ_EN                               0x000002a6U
-#define _reg_PI_RDLVL_GATE_SEQ_EN                          0x000002a7U
-#define _reg_PI_RDLVL_PERIODIC                             0x000002a8U
-#define _reg_PI_RDLVL_ON_SREF_EXIT                         0x000002a9U
-#define _reg_PI_RDLVL_DISABLE_DFS                          0x000002aaU
-#define _reg_PI_RDLVL_GATE_PERIODIC                        0x000002abU
-#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT                    0x000002acU
-#define _reg_PI_RDLVL_GATE_DISABLE_DFS                     0x000002adU
-#define _reg_RESERVED_R1                                   0x000002aeU
-#define _reg_PI_RDLVL_ROTATE                               0x000002afU
-#define _reg_PI_RDLVL_GATE_ROTATE                          0x000002b0U
-#define _reg_PI_RDLVL_CS_MAP                               0x000002b1U
-#define _reg_PI_RDLVL_GATE_CS_MAP                          0x000002b2U
-#define _reg_PI_TDFI_RDLVL_RR                              0x000002b3U
-#define _reg_PI_TDFI_RDLVL_RESP                            0x000002b4U
-#define _reg_PI_RDLVL_RESP_MASK                            0x000002b5U
-#define _reg_PI_TDFI_RDLVL_EN                              0x000002b6U
-#define _reg_PI_RDLVL_EN_F0                                0x000002b7U
-#define _reg_PI_RDLVL_GATE_EN_F0                           0x000002b8U
-#define _reg_PI_RDLVL_EN_F1                                0x000002b9U
-#define _reg_PI_RDLVL_GATE_EN_F1                           0x000002baU
-#define _reg_PI_RDLVL_EN_F2                                0x000002bbU
-#define _reg_PI_RDLVL_GATE_EN_F2                           0x000002bcU
-#define _reg_PI_RDLVL_EN                                   0x000002bdU
-#define _reg_PI_RDLVL_GATE_EN                              0x000002beU
-#define _reg_PI_TDFI_RDLVL_MAX                             0x000002bfU
-#define _reg_PI_RDLVL_ERROR_STATUS                         0x000002c0U
-#define _reg_PI_RDLVL_INTERVAL                             0x000002c1U
-#define _reg_PI_RDLVL_GATE_INTERVAL                        0x000002c2U
-#define _reg_PI_RDLVL_PATTERN_START                        0x000002c3U
-#define _reg_PI_RDLVL_PATTERN_NUM                          0x000002c4U
-#define _reg_PI_RDLVL_STROBE_NUM                           0x000002c5U
-#define _reg_PI_RDLVL_GATE_STROBE_NUM                      0x000002c6U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_8                     0x000002c7U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_9                     0x000002c8U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_10                    0x000002c9U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_11                    0x000002caU
-#define _reg_PI_RD_PREAMBLE_TRAINING_EN                    0x000002cbU
-#define _reg_PI_REG_DIMM_ENABLE                            0x000002ccU
-#define _reg_PI_RDLAT_ADJ_F0                               0x000002cdU
-#define _reg_PI_RDLAT_ADJ_F1                               0x000002ceU
-#define _reg_PI_RDLAT_ADJ_F2                               0x000002cfU
-#define _reg_PI_TDFI_RDDATA_EN                             0x000002d0U
-#define _reg_PI_WRLAT_ADJ_F0                               0x000002d1U
-#define _reg_PI_WRLAT_ADJ_F1                               0x000002d2U
-#define _reg_PI_WRLAT_ADJ_F2                               0x000002d3U
-#define _reg_PI_TDFI_PHY_WRLAT                             0x000002d4U
-#define _reg_PI_TDFI_WRCSLAT_F0                            0x000002d5U
-#define _reg_PI_TDFI_WRCSLAT_F1                            0x000002d6U
-#define _reg_PI_TDFI_WRCSLAT_F2                            0x000002d7U
-#define _reg_PI_TDFI_RDCSLAT_F0                            0x000002d8U
-#define _reg_PI_TDFI_RDCSLAT_F1                            0x000002d9U
-#define _reg_PI_TDFI_RDCSLAT_F2                            0x000002daU
-#define _reg_PI_TDFI_PHY_WRDATA_F0                         0x000002dbU
-#define _reg_PI_TDFI_PHY_WRDATA_F1                         0x000002dcU
-#define _reg_PI_TDFI_PHY_WRDATA_F2                         0x000002ddU
-#define _reg_PI_TDFI_PHY_WRDATA                            0x000002deU
-#define _reg_PI_CALVL_REQ                                  0x000002dfU
-#define _reg_PI_CALVL_CS                                   0x000002e0U
-#define _reg_RESERVED_R2                                   0x000002e1U
-#define _reg_RESERVED_R3                                   0x000002e2U
-#define _reg_PI_CALVL_SEQ_EN                               0x000002e3U
-#define _reg_PI_CALVL_PERIODIC                             0x000002e4U
-#define _reg_PI_CALVL_ON_SREF_EXIT                         0x000002e5U
-#define _reg_PI_CALVL_DISABLE_DFS                          0x000002e6U
-#define _reg_PI_CALVL_ROTATE                               0x000002e7U
-#define _reg_PI_CALVL_CS_MAP                               0x000002e8U
-#define _reg_PI_TDFI_CALVL_EN                              0x000002e9U
-#define _reg_PI_TDFI_CALVL_CC_F0                           0x000002eaU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F0                      0x000002ebU
-#define _reg_PI_TDFI_CALVL_CC_F1                           0x000002ecU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F1                      0x000002edU
-#define _reg_PI_TDFI_CALVL_CC_F2                           0x000002eeU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F2                      0x000002efU
-#define _reg_PI_TDFI_CALVL_RESP                            0x000002f0U
-#define _reg_PI_TDFI_CALVL_MAX                             0x000002f1U
-#define _reg_PI_CALVL_RESP_MASK                            0x000002f2U
-#define _reg_PI_CALVL_EN_F0                                0x000002f3U
-#define _reg_PI_CALVL_EN_F1                                0x000002f4U
-#define _reg_PI_CALVL_EN_F2                                0x000002f5U
-#define _reg_PI_CALVL_EN                                   0x000002f6U
-#define _reg_PI_CALVL_ERROR_STATUS                         0x000002f7U
-#define _reg_PI_CALVL_INTERVAL                             0x000002f8U
-#define _reg_PI_TCACKEL                                    0x000002f9U
-#define _reg_PI_TCAMRD                                     0x000002faU
-#define _reg_PI_TCACKEH                                    0x000002fbU
-#define _reg_PI_TMRZ_F0                                    0x000002fcU
-#define _reg_PI_TCAENT_F0                                  0x000002fdU
-#define _reg_PI_TMRZ_F1                                    0x000002feU
-#define _reg_PI_TCAENT_F1                                  0x000002ffU
-#define _reg_PI_TMRZ_F2                                    0x00000300U
-#define _reg_PI_TCAENT_F2                                  0x00000301U
-#define _reg_PI_TCAEXT                                     0x00000302U
-#define _reg_PI_CA_TRAIN_VREF_EN                           0x00000303U
-#define _reg_PI_TDFI_CACSCA_F0                             0x00000304U
-#define _reg_PI_TDFI_CASEL_F0                              0x00000305U
-#define _reg_PI_TVREF_SHORT_F0                             0x00000306U
-#define _reg_PI_TVREF_LONG_F0                              0x00000307U
-#define _reg_PI_TDFI_CACSCA_F1                             0x00000308U
-#define _reg_PI_TDFI_CASEL_F1                              0x00000309U
-#define _reg_PI_TVREF_SHORT_F1                             0x0000030aU
-#define _reg_PI_TVREF_LONG_F1                              0x0000030bU
-#define _reg_PI_TDFI_CACSCA_F2                             0x0000030cU
-#define _reg_PI_TDFI_CASEL_F2                              0x0000030dU
-#define _reg_PI_TVREF_SHORT_F2                             0x0000030eU
-#define _reg_PI_TVREF_LONG_F2                              0x0000030fU
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0          0x00000310U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0           0x00000311U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1          0x00000312U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1           0x00000313U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2          0x00000314U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2           0x00000315U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT             0x00000316U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT              0x00000317U
-#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE                0x00000318U
-#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE                 0x00000319U
-#define _reg_PI_CALVL_VREF_DELTA_F0                        0x0000031aU
-#define _reg_PI_CALVL_VREF_DELTA_F1                        0x0000031bU
-#define _reg_PI_CALVL_VREF_DELTA_F2                        0x0000031cU
-#define _reg_PI_CALVL_VREF_DELTA                           0x0000031dU
-#define _reg_PI_TDFI_INIT_START_MIN                        0x0000031eU
-#define _reg_PI_TDFI_INIT_COMPLETE_MIN                     0x0000031fU
-#define _reg_PI_TDFI_CALVL_STROBE_F0                       0x00000320U
-#define _reg_PI_TXP_F0                                     0x00000321U
-#define _reg_PI_TMRWCKEL_F0                                0x00000322U
-#define _reg_PI_TCKELCK_F0                                 0x00000323U
-#define _reg_PI_TDFI_CALVL_STROBE_F1                       0x00000324U
-#define _reg_PI_TXP_F1                                     0x00000325U
-#define _reg_PI_TMRWCKEL_F1                                0x00000326U
-#define _reg_PI_TCKELCK_F1                                 0x00000327U
-#define _reg_PI_TDFI_CALVL_STROBE_F2                       0x00000328U
-#define _reg_PI_TXP_F2                                     0x00000329U
-#define _reg_PI_TMRWCKEL_F2                                0x0000032aU
-#define _reg_PI_TCKELCK_F2                                 0x0000032bU
-#define _reg_PI_TCKCKEH                                    0x0000032cU
-#define _reg_PI_CALVL_STROBE_NUM                           0x0000032dU
-#define _reg_PI_SW_CA_TRAIN_VREF                           0x0000032eU
-#define _reg_PI_TDFI_INIT_START_F0                         0x0000032fU
-#define _reg_PI_TDFI_INIT_COMPLETE_F0                      0x00000330U
-#define _reg_PI_TDFI_INIT_START_F1                         0x00000331U
-#define _reg_PI_TDFI_INIT_COMPLETE_F1                      0x00000332U
-#define _reg_PI_TDFI_INIT_START_F2                         0x00000333U
-#define _reg_PI_TDFI_INIT_COMPLETE_F2                      0x00000334U
-#define _reg_PI_CLKDISABLE_2_INIT_START                    0x00000335U
-#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE          0x00000336U
-#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL              0x00000337U
-#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE            0x00000338U
-#define _reg_PI_TCKEHDQS_F0                                0x00000339U
-#define _reg_PI_TCKEHDQS_F1                                0x0000033aU
-#define _reg_PI_TCKEHDQS_F2                                0x0000033bU
-#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE                  0x0000033cU
-#define _reg_PI_WDQLVL_VREF_EN                             0x0000033dU
-#define _reg_PI_WDQLVL_BST_NUM                             0x0000033eU
-#define _reg_PI_TDFI_WDQLVL_WR_F0                          0x0000033fU
-#define _reg_PI_TDFI_WDQLVL_WR_F1                          0x00000340U
-#define _reg_PI_TDFI_WDQLVL_WR_F2                          0x00000341U
-#define _reg_PI_TDFI_WDQLVL_WR                             0x00000342U
-#define _reg_PI_TDFI_WDQLVL_RW                             0x00000343U
-#define _reg_PI_WDQLVL_RESP_MASK                           0x00000344U
-#define _reg_PI_WDQLVL_ROTATE                              0x00000345U
-#define _reg_PI_WDQLVL_CS_MAP                              0x00000346U
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0         0x00000347U
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0          0x00000348U
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1         0x00000349U
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1          0x0000034aU
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2         0x0000034bU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2          0x0000034cU
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT            0x0000034dU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT             0x0000034eU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE               0x0000034fU
-#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE                0x00000350U
-#define _reg_PI_WDQLVL_VREF_DELTA_F0                       0x00000351U
-#define _reg_PI_WDQLVL_VREF_DELTA_F1                       0x00000352U
-#define _reg_PI_WDQLVL_VREF_DELTA_F2                       0x00000353U
-#define _reg_PI_WDQLVL_VREF_DELTA                          0x00000354U
-#define _reg_PI_WDQLVL_PERIODIC                            0x00000355U
-#define _reg_PI_WDQLVL_REQ                                 0x00000356U
-#define _reg_PI_WDQLVL_CS                                  0x00000357U
-#define _reg_PI_TDFI_WDQLVL_EN                             0x00000358U
-#define _reg_PI_TDFI_WDQLVL_RESP                           0x00000359U
-#define _reg_PI_TDFI_WDQLVL_MAX                            0x0000035aU
-#define _reg_PI_WDQLVL_INTERVAL                            0x0000035bU
-#define _reg_PI_WDQLVL_EN_F0                               0x0000035cU
-#define _reg_PI_WDQLVL_EN_F1                               0x0000035dU
-#define _reg_PI_WDQLVL_EN_F2                               0x0000035eU
-#define _reg_PI_WDQLVL_EN                                  0x0000035fU
-#define _reg_PI_WDQLVL_ON_SREF_EXIT                        0x00000360U
-#define _reg_PI_WDQLVL_DISABLE_DFS                         0x00000361U
-#define _reg_PI_WDQLVL_ERROR_STATUS                        0x00000362U
-#define _reg_PI_MR1_DATA_F0_0                              0x00000363U
-#define _reg_PI_MR2_DATA_F0_0                              0x00000364U
-#define _reg_PI_MR3_DATA_F0_0                              0x00000365U
-#define _reg_PI_MR11_DATA_F0_0                             0x00000366U
-#define _reg_PI_MR12_DATA_F0_0                             0x00000367U
-#define _reg_PI_MR14_DATA_F0_0                             0x00000368U
-#define _reg_PI_MR22_DATA_F0_0                             0x00000369U
-#define _reg_PI_MR1_DATA_F1_0                              0x0000036aU
-#define _reg_PI_MR2_DATA_F1_0                              0x0000036bU
-#define _reg_PI_MR3_DATA_F1_0                              0x0000036cU
-#define _reg_PI_MR11_DATA_F1_0                             0x0000036dU
-#define _reg_PI_MR12_DATA_F1_0                             0x0000036eU
-#define _reg_PI_MR14_DATA_F1_0                             0x0000036fU
-#define _reg_PI_MR22_DATA_F1_0                             0x00000370U
-#define _reg_PI_MR1_DATA_F2_0                              0x00000371U
-#define _reg_PI_MR2_DATA_F2_0                              0x00000372U
-#define _reg_PI_MR3_DATA_F2_0                              0x00000373U
-#define _reg_PI_MR11_DATA_F2_0                             0x00000374U
-#define _reg_PI_MR12_DATA_F2_0                             0x00000375U
-#define _reg_PI_MR14_DATA_F2_0                             0x00000376U
-#define _reg_PI_MR22_DATA_F2_0                             0x00000377U
-#define _reg_PI_MR13_DATA_0                                0x00000378U
-#define _reg_PI_MR1_DATA_F0_1                              0x00000379U
-#define _reg_PI_MR2_DATA_F0_1                              0x0000037aU
-#define _reg_PI_MR3_DATA_F0_1                              0x0000037bU
-#define _reg_PI_MR11_DATA_F0_1                             0x0000037cU
-#define _reg_PI_MR12_DATA_F0_1                             0x0000037dU
-#define _reg_PI_MR14_DATA_F0_1                             0x0000037eU
-#define _reg_PI_MR22_DATA_F0_1                             0x0000037fU
-#define _reg_PI_MR1_DATA_F1_1                              0x00000380U
-#define _reg_PI_MR2_DATA_F1_1                              0x00000381U
-#define _reg_PI_MR3_DATA_F1_1                              0x00000382U
-#define _reg_PI_MR11_DATA_F1_1                             0x00000383U
-#define _reg_PI_MR12_DATA_F1_1                             0x00000384U
-#define _reg_PI_MR14_DATA_F1_1                             0x00000385U
-#define _reg_PI_MR22_DATA_F1_1                             0x00000386U
-#define _reg_PI_MR1_DATA_F2_1                              0x00000387U
-#define _reg_PI_MR2_DATA_F2_1                              0x00000388U
-#define _reg_PI_MR3_DATA_F2_1                              0x00000389U
-#define _reg_PI_MR11_DATA_F2_1                             0x0000038aU
-#define _reg_PI_MR12_DATA_F2_1                             0x0000038bU
-#define _reg_PI_MR14_DATA_F2_1                             0x0000038cU
-#define _reg_PI_MR22_DATA_F2_1                             0x0000038dU
-#define _reg_PI_MR13_DATA_1                                0x0000038eU
-#define _reg_PI_MR1_DATA_F0_2                              0x0000038fU
-#define _reg_PI_MR2_DATA_F0_2                              0x00000390U
-#define _reg_PI_MR3_DATA_F0_2                              0x00000391U
-#define _reg_PI_MR11_DATA_F0_2                             0x00000392U
-#define _reg_PI_MR12_DATA_F0_2                             0x00000393U
-#define _reg_PI_MR14_DATA_F0_2                             0x00000394U
-#define _reg_PI_MR22_DATA_F0_2                             0x00000395U
-#define _reg_PI_MR1_DATA_F1_2                              0x00000396U
-#define _reg_PI_MR2_DATA_F1_2                              0x00000397U
-#define _reg_PI_MR3_DATA_F1_2                              0x00000398U
-#define _reg_PI_MR11_DATA_F1_2                             0x00000399U
-#define _reg_PI_MR12_DATA_F1_2                             0x0000039aU
-#define _reg_PI_MR14_DATA_F1_2                             0x0000039bU
-#define _reg_PI_MR22_DATA_F1_2                             0x0000039cU
-#define _reg_PI_MR1_DATA_F2_2                              0x0000039dU
-#define _reg_PI_MR2_DATA_F2_2                              0x0000039eU
-#define _reg_PI_MR3_DATA_F2_2                              0x0000039fU
-#define _reg_PI_MR11_DATA_F2_2                             0x000003a0U
-#define _reg_PI_MR12_DATA_F2_2                             0x000003a1U
-#define _reg_PI_MR14_DATA_F2_2                             0x000003a2U
-#define _reg_PI_MR22_DATA_F2_2                             0x000003a3U
-#define _reg_PI_MR13_DATA_2                                0x000003a4U
-#define _reg_PI_MR1_DATA_F0_3                              0x000003a5U
-#define _reg_PI_MR2_DATA_F0_3                              0x000003a6U
-#define _reg_PI_MR3_DATA_F0_3                              0x000003a7U
-#define _reg_PI_MR11_DATA_F0_3                             0x000003a8U
-#define _reg_PI_MR12_DATA_F0_3                             0x000003a9U
-#define _reg_PI_MR14_DATA_F0_3                             0x000003aaU
-#define _reg_PI_MR22_DATA_F0_3                             0x000003abU
-#define _reg_PI_MR1_DATA_F1_3                              0x000003acU
-#define _reg_PI_MR2_DATA_F1_3                              0x000003adU
-#define _reg_PI_MR3_DATA_F1_3                              0x000003aeU
-#define _reg_PI_MR11_DATA_F1_3                             0x000003afU
-#define _reg_PI_MR12_DATA_F1_3                             0x000003b0U
-#define _reg_PI_MR14_DATA_F1_3                             0x000003b1U
-#define _reg_PI_MR22_DATA_F1_3                             0x000003b2U
-#define _reg_PI_MR1_DATA_F2_3                              0x000003b3U
-#define _reg_PI_MR2_DATA_F2_3                              0x000003b4U
-#define _reg_PI_MR3_DATA_F2_3                              0x000003b5U
-#define _reg_PI_MR11_DATA_F2_3                             0x000003b6U
-#define _reg_PI_MR12_DATA_F2_3                             0x000003b7U
-#define _reg_PI_MR14_DATA_F2_3                             0x000003b8U
-#define _reg_PI_MR22_DATA_F2_3                             0x000003b9U
-#define _reg_PI_MR13_DATA_3                                0x000003baU
-#define _reg_PI_BANK_DIFF                                  0x000003bbU
-#define _reg_PI_ROW_DIFF                                   0x000003bcU
-#define _reg_PI_TFC_F0                                     0x000003bdU
-#define _reg_PI_TFC_F1                                     0x000003beU
-#define _reg_PI_TFC_F2                                     0x000003bfU
-#define _reg_PI_TCCD                                       0x000003c0U
-#define _reg_PI_TRTP_F0                                    0x000003c1U
-#define _reg_PI_TRP_F0                                     0x000003c2U
-#define _reg_PI_TRCD_F0                                    0x000003c3U
-#define _reg_PI_TWTR_F0                                    0x000003c4U
-#define _reg_PI_TWR_F0                                     0x000003c5U
-#define _reg_PI_TRAS_MAX_F0                                0x000003c6U
-#define _reg_PI_TRAS_MIN_F0                                0x000003c7U
-#define _reg_PI_TDQSCK_MAX_F0                              0x000003c8U
-#define _reg_PI_TCCDMW_F0                                  0x000003c9U
-#define _reg_PI_TSR_F0                                     0x000003caU
-#define _reg_PI_TMRD_F0                                    0x000003cbU
-#define _reg_PI_TMRW_F0                                    0x000003ccU
-#define _reg_PI_TMOD_F0                                    0x000003cdU
-#define _reg_PI_TRTP_F1                                    0x000003ceU
-#define _reg_PI_TRP_F1                                     0x000003cfU
-#define _reg_PI_TRCD_F1                                    0x000003d0U
-#define _reg_PI_TWTR_F1                                    0x000003d1U
-#define _reg_PI_TWR_F1                                     0x000003d2U
-#define _reg_PI_TRAS_MAX_F1                                0x000003d3U
-#define _reg_PI_TRAS_MIN_F1                                0x000003d4U
-#define _reg_PI_TDQSCK_MAX_F1                              0x000003d5U
-#define _reg_PI_TCCDMW_F1                                  0x000003d6U
-#define _reg_PI_TSR_F1                                     0x000003d7U
-#define _reg_PI_TMRD_F1                                    0x000003d8U
-#define _reg_PI_TMRW_F1                                    0x000003d9U
-#define _reg_PI_TMOD_F1                                    0x000003daU
-#define _reg_PI_TRTP_F2                                    0x000003dbU
-#define _reg_PI_TRP_F2                                     0x000003dcU
-#define _reg_PI_TRCD_F2                                    0x000003ddU
-#define _reg_PI_TWTR_F2                                    0x000003deU
-#define _reg_PI_TWR_F2                                     0x000003dfU
-#define _reg_PI_TRAS_MAX_F2                                0x000003e0U
-#define _reg_PI_TRAS_MIN_F2                                0x000003e1U
-#define _reg_PI_TDQSCK_MAX_F2                              0x000003e2U
-#define _reg_PI_TCCDMW_F2                                  0x000003e3U
-#define _reg_PI_TSR_F2                                     0x000003e4U
-#define _reg_PI_TMRD_F2                                    0x000003e5U
-#define _reg_PI_TMRW_F2                                    0x000003e6U
-#define _reg_PI_TMOD_F2                                    0x000003e7U
-#define _reg_RESERVED_R4                                   0x000003e8U
-#define _reg_RESERVED_R5                                   0x000003e9U
-#define _reg_RESERVED_R6                                   0x000003eaU
-#define _reg_RESERVED_R7                                   0x000003ebU
-#define _reg_RESERVED_R8                                   0x000003ecU
-#define _reg_RESERVED_R9                                   0x000003edU
-#define _reg_RESERVED_R10                                  0x000003eeU
-#define _reg_RESERVED_R11                                  0x000003efU
-#define _reg_RESERVED_R12                                  0x000003f0U
-#define _reg_RESERVED_R13                                  0x000003f1U
-#define _reg_RESERVED_R14                                  0x000003f2U
-#define _reg_RESERVED_R15                                  0x000003f3U
-#define _reg_RESERVED_R16                                  0x000003f4U
-#define _reg_RESERVED_R17                                  0x000003f5U
-#define _reg_RESERVED_R18                                  0x000003f6U
-#define _reg_RESERVED_R19                                  0x000003f7U
-#define _reg_RESERVED_R20                                  0x000003f8U
-#define _reg_RESERVED_R21                                  0x000003f9U
-#define _reg_RESERVED_R22                                  0x000003faU
-#define _reg_RESERVED_R23                                  0x000003fbU
-#define _reg_PI_INT_STATUS                                 0x000003fcU
-#define _reg_PI_INT_ACK                                    0x000003fdU
-#define _reg_PI_INT_MASK                                   0x000003feU
-#define _reg_PI_BIST_EXP_DATA_P0                           0x000003ffU
-#define _reg_PI_BIST_EXP_DATA_P1                           0x00000400U
-#define _reg_PI_BIST_EXP_DATA_P2                           0x00000401U
-#define _reg_PI_BIST_EXP_DATA_P3                           0x00000402U
-#define _reg_PI_BIST_FAIL_DATA_P0                          0x00000403U
-#define _reg_PI_BIST_FAIL_DATA_P1                          0x00000404U
-#define _reg_PI_BIST_FAIL_DATA_P2                          0x00000405U
-#define _reg_PI_BIST_FAIL_DATA_P3                          0x00000406U
-#define _reg_PI_BIST_FAIL_ADDR_P0                          0x00000407U
-#define _reg_PI_BIST_FAIL_ADDR_P1                          0x00000408U
-#define _reg_PI_BSTLEN                                     0x00000409U
-#define _reg_PI_LONG_COUNT_MASK                            0x0000040aU
-#define _reg_PI_CMD_SWAP_EN                                0x0000040bU
-#define _reg_PI_CKE_MUX_0                                  0x0000040cU
-#define _reg_PI_CKE_MUX_1                                  0x0000040dU
-#define _reg_PI_CKE_MUX_2                                  0x0000040eU
-#define _reg_PI_CKE_MUX_3                                  0x0000040fU
-#define _reg_PI_CS_MUX_0                                   0x00000410U
-#define _reg_PI_CS_MUX_1                                   0x00000411U
-#define _reg_PI_CS_MUX_2                                   0x00000412U
-#define _reg_PI_CS_MUX_3                                   0x00000413U
-#define _reg_PI_RAS_N_MUX                                  0x00000414U
-#define _reg_PI_CAS_N_MUX                                  0x00000415U
-#define _reg_PI_WE_N_MUX                                   0x00000416U
-#define _reg_PI_BANK_MUX_0                                 0x00000417U
-#define _reg_PI_BANK_MUX_1                                 0x00000418U
-#define _reg_PI_BANK_MUX_2                                 0x00000419U
-#define _reg_PI_ODT_MUX_0                                  0x0000041aU
-#define _reg_PI_ODT_MUX_1                                  0x0000041bU
-#define _reg_PI_ODT_MUX_2                                  0x0000041cU
-#define _reg_PI_ODT_MUX_3                                  0x0000041dU
-#define _reg_PI_RESET_N_MUX_0                              0x0000041eU
-#define _reg_PI_RESET_N_MUX_1                              0x0000041fU
-#define _reg_PI_RESET_N_MUX_2                              0x00000420U
-#define _reg_PI_RESET_N_MUX_3                              0x00000421U
-#define _reg_PI_DATA_BYTE_SWAP_EN                          0x00000422U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE0                      0x00000423U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE1                      0x00000424U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE2                      0x00000425U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE3                      0x00000426U
-#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN                    0x00000427U
-#define _reg_PI_TDFI_CTRLUPD_MIN                           0x00000428U
-#define _reg_PI_TDFI_CTRLUPD_MAX_F0                        0x00000429U
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0                   0x0000042aU
-#define _reg_PI_TDFI_CTRLUPD_MAX_F1                        0x0000042bU
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1                   0x0000042cU
-#define _reg_PI_TDFI_CTRLUPD_MAX_F2                        0x0000042dU
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2                   0x0000042eU
-#define _reg_PI_UPDATE_ERROR_STATUS                        0x0000042fU
-#define _reg_PI_BIST_GO                                    0x00000430U
-#define _reg_PI_BIST_RESULT                                0x00000431U
-#define _reg_PI_ADDR_SPACE                                 0x00000432U
-#define _reg_PI_BIST_DATA_CHECK                            0x00000433U
-#define _reg_PI_BIST_ADDR_CHECK                            0x00000434U
-#define _reg_PI_BIST_START_ADDRESS_P0                      0x00000435U
-#define _reg_PI_BIST_START_ADDRESS_P1                      0x00000436U
-#define _reg_PI_BIST_DATA_MASK_P0                          0x00000437U
-#define _reg_PI_BIST_DATA_MASK_P1                          0x00000438U
-#define _reg_PI_BIST_ERR_COUNT                             0x00000439U
-#define _reg_PI_BIST_ERR_STOP                              0x0000043aU
-#define _reg_PI_BIST_ADDR_MASK_0_P0                        0x0000043bU
-#define _reg_PI_BIST_ADDR_MASK_0_P1                        0x0000043cU
-#define _reg_PI_BIST_ADDR_MASK_1_P0                        0x0000043dU
-#define _reg_PI_BIST_ADDR_MASK_1_P1                        0x0000043eU
-#define _reg_PI_BIST_ADDR_MASK_2_P0                        0x0000043fU
-#define _reg_PI_BIST_ADDR_MASK_2_P1                        0x00000440U
-#define _reg_PI_BIST_ADDR_MASK_3_P0                        0x00000441U
-#define _reg_PI_BIST_ADDR_MASK_3_P1                        0x00000442U
-#define _reg_PI_BIST_ADDR_MASK_4_P0                        0x00000443U
-#define _reg_PI_BIST_ADDR_MASK_4_P1                        0x00000444U
-#define _reg_PI_BIST_ADDR_MASK_5_P0                        0x00000445U
-#define _reg_PI_BIST_ADDR_MASK_5_P1                        0x00000446U
-#define _reg_PI_BIST_ADDR_MASK_6_P0                        0x00000447U
-#define _reg_PI_BIST_ADDR_MASK_6_P1                        0x00000448U
-#define _reg_PI_BIST_ADDR_MASK_7_P0                        0x00000449U
-#define _reg_PI_BIST_ADDR_MASK_7_P1                        0x0000044aU
-#define _reg_PI_BIST_ADDR_MASK_8_P0                        0x0000044bU
-#define _reg_PI_BIST_ADDR_MASK_8_P1                        0x0000044cU
-#define _reg_PI_BIST_ADDR_MASK_9_P0                        0x0000044dU
-#define _reg_PI_BIST_ADDR_MASK_9_P1                        0x0000044eU
-#define _reg_PI_BIST_MODE                                  0x0000044fU
-#define _reg_PI_BIST_ADDR_MODE                             0x00000450U
-#define _reg_PI_BIST_PAT_MODE                              0x00000451U
-#define _reg_PI_BIST_USER_PAT_P0                           0x00000452U
-#define _reg_PI_BIST_USER_PAT_P1                           0x00000453U
-#define _reg_PI_BIST_USER_PAT_P2                           0x00000454U
-#define _reg_PI_BIST_USER_PAT_P3                           0x00000455U
-#define _reg_PI_BIST_PAT_NUM                               0x00000456U
-#define _reg_PI_BIST_STAGE_0                               0x00000457U
-#define _reg_PI_BIST_STAGE_1                               0x00000458U
-#define _reg_PI_BIST_STAGE_2                               0x00000459U
-#define _reg_PI_BIST_STAGE_3                               0x0000045aU
-#define _reg_PI_BIST_STAGE_4                               0x0000045bU
-#define _reg_PI_BIST_STAGE_5                               0x0000045cU
-#define _reg_PI_BIST_STAGE_6                               0x0000045dU
-#define _reg_PI_BIST_STAGE_7                               0x0000045eU
-#define _reg_PI_COL_DIFF                                   0x0000045fU
-#define _reg_PI_SELF_REFRESH_EN                            0x00000460U
-#define _reg_PI_TXSR_F0                                    0x00000461U
-#define _reg_PI_TXSR_F1                                    0x00000462U
-#define _reg_PI_TXSR_F2                                    0x00000463U
-#define _reg_PI_MONITOR_SRC_SEL_0                          0x00000464U
-#define _reg_PI_MONITOR_CAP_SEL_0                          0x00000465U
-#define _reg_PI_MONITOR_0                                  0x00000466U
-#define _reg_PI_MONITOR_SRC_SEL_1                          0x00000467U
-#define _reg_PI_MONITOR_CAP_SEL_1                          0x00000468U
-#define _reg_PI_MONITOR_1                                  0x00000469U
-#define _reg_PI_MONITOR_SRC_SEL_2                          0x0000046aU
-#define _reg_PI_MONITOR_CAP_SEL_2                          0x0000046bU
-#define _reg_PI_MONITOR_2                                  0x0000046cU
-#define _reg_PI_MONITOR_SRC_SEL_3                          0x0000046dU
-#define _reg_PI_MONITOR_CAP_SEL_3                          0x0000046eU
-#define _reg_PI_MONITOR_3                                  0x0000046fU
-#define _reg_PI_MONITOR_SRC_SEL_4                          0x00000470U
-#define _reg_PI_MONITOR_CAP_SEL_4                          0x00000471U
-#define _reg_PI_MONITOR_4                                  0x00000472U
-#define _reg_PI_MONITOR_SRC_SEL_5                          0x00000473U
-#define _reg_PI_MONITOR_CAP_SEL_5                          0x00000474U
-#define _reg_PI_MONITOR_5                                  0x00000475U
-#define _reg_PI_MONITOR_SRC_SEL_6                          0x00000476U
-#define _reg_PI_MONITOR_CAP_SEL_6                          0x00000477U
-#define _reg_PI_MONITOR_6                                  0x00000478U
-#define _reg_PI_MONITOR_SRC_SEL_7                          0x00000479U
-#define _reg_PI_MONITOR_CAP_SEL_7                          0x0000047aU
-#define _reg_PI_MONITOR_7                                  0x0000047bU
-#define _reg_PI_MONITOR_STROBE                             0x0000047cU
-#define _reg_PI_DLL_LOCK                                   0x0000047dU
-#define _reg_PI_FREQ_NUMBER_STATUS                         0x0000047eU
-#define _reg_RESERVED_R24                                  0x0000047fU
-#define _reg_PI_PHYMSTR_TYPE                               0x00000480U
-#define _reg_PI_POWER_REDUC_EN                             0x00000481U
-#define _reg_RESERVED_R25                                  0x00000482U
-#define _reg_RESERVED_R26                                  0x00000483U
-#define _reg_RESERVED_R27                                  0x00000484U
-#define _reg_RESERVED_R28                                  0x00000485U
-#define _reg_RESERVED_R29                                  0x00000486U
-#define _reg_RESERVED_R30                                  0x00000487U
-#define _reg_RESERVED_R31                                  0x00000488U
-#define _reg_RESERVED_R32                                  0x00000489U
-#define _reg_RESERVED_R33                                  0x0000048aU
-#define _reg_RESERVED_R34                                  0x0000048bU
-#define _reg_RESERVED_R35                                  0x0000048cU
-#define _reg_RESERVED_R36                                  0x0000048dU
-#define _reg_RESERVED_R37                                  0x0000048eU
-#define _reg_RESERVED_R38                                  0x0000048fU
-#define _reg_RESERVED_R39                                  0x00000490U
-#define _reg_PI_WRLVL_MAX_STROBE_PEND                      0x00000491U
-#define _reg_PI_TSDO_F0                                    0x00000492U
-#define _reg_PI_TSDO_F1                                    0x00000493U
-#define _reg_PI_TSDO_F2                                    0x00000494U
-
-#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffffU)
-#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xffU)
-#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xffU)
-
-static const uint32_t DDR_REGDEF_TBL[4][1173] = {
-	{
-/*0000*/ 0xffffffffU,
-/*0001*/ 0xffffffffU,
-/*0002*/ 0x000b0400U,
-/*0003*/ 0xffffffffU,
-/*0004*/ 0xffffffffU,
-/*0005*/ 0x10010400U,
-/*0006*/ 0x18050400U,
-/*0007*/ 0x00050401U,
-/*0008*/ 0x08050401U,
-/*0009*/ 0x10050401U,
-/*000a*/ 0x18050401U,
-/*000b*/ 0x00050402U,
-/*000c*/ 0x08050402U,
-/*000d*/ 0x10050402U,
-/*000e*/ 0x18050402U,
-/*000f*/ 0x00040403U,
-/*0010*/ 0x08030403U,
-/*0011*/ 0x00180404U,
-/*0012*/ 0x18030404U,
-/*0013*/ 0x00180405U,
-/*0014*/ 0x18020405U,
-/*0015*/ 0x00010406U,
-/*0016*/ 0x08020406U,
-/*0017*/ 0x10010406U,
-/*0018*/ 0x18010406U,
-/*0019*/ 0x00020407U,
-/*001a*/ 0x08040407U,
-/*001b*/ 0x10040407U,
-/*001c*/ 0x18040407U,
-/*001d*/ 0x000a0408U,
-/*001e*/ 0x10040408U,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x18070408U,
-/*0022*/ 0xffffffffU,
-/*0023*/ 0xffffffffU,
-/*0024*/ 0xffffffffU,
-/*0025*/ 0xffffffffU,
-/*0026*/ 0xffffffffU,
-/*0027*/ 0xffffffffU,
-/*0028*/ 0x000a0409U,
-/*0029*/ 0x10040409U,
-/*002a*/ 0x18010409U,
-/*002b*/ 0x0001040aU,
-/*002c*/ 0x0802040aU,
-/*002d*/ 0x1009040aU,
-/*002e*/ 0x0009040bU,
-/*002f*/ 0x1002040bU,
-/*0030*/ 0x0020040cU,
-/*0031*/ 0xffffffffU,
-/*0032*/ 0x0001040dU,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x0020040eU,
-/*0038*/ 0x0020040fU,
-/*0039*/ 0x00200410U,
-/*003a*/ 0x00200411U,
-/*003b*/ 0x00030412U,
-/*003c*/ 0x08010412U,
-/*003d*/ 0x10030412U,
-/*003e*/ 0x18030412U,
-/*003f*/ 0x00040413U,
-/*0040*/ 0x08040413U,
-/*0041*/ 0x10040413U,
-/*0042*/ 0x18040413U,
-/*0043*/ 0x00010414U,
-/*0044*/ 0x08010414U,
-/*0045*/ 0x10060414U,
-/*0046*/ 0x18040414U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x00060415U,
-/*0049*/ 0x08040415U,
-/*004a*/ 0x10060415U,
-/*004b*/ 0x18040415U,
-/*004c*/ 0x00020416U,
-/*004d*/ 0x08050416U,
-/*004e*/ 0x10080416U,
-/*004f*/ 0x00200417U,
-/*0050*/ 0x00060418U,
-/*0051*/ 0x08030418U,
-/*0052*/ 0x100b0418U,
-/*0053*/ 0x00040419U,
-/*0054*/ 0x08040419U,
-/*0055*/ 0x10040419U,
-/*0056*/ 0xffffffffU,
-/*0057*/ 0x18010419U,
-/*0058*/ 0x0009041aU,
-/*0059*/ 0x0020041bU,
-/*005a*/ 0x0020041cU,
-/*005b*/ 0x0020041dU,
-/*005c*/ 0x0020041eU,
-/*005d*/ 0x0010041fU,
-/*005e*/ 0x00200420U,
-/*005f*/ 0x00010421U,
-/*0060*/ 0x08060421U,
-/*0061*/ 0x10080421U,
-/*0062*/ 0x00200422U,
-/*0063*/ 0xffffffffU,
-/*0064*/ 0x000a0423U,
-/*0065*/ 0x10060423U,
-/*0066*/ 0x18070423U,
-/*0067*/ 0x00080424U,
-/*0068*/ 0x08080424U,
-/*0069*/ 0x100a0424U,
-/*006a*/ 0x00070425U,
-/*006b*/ 0x08080425U,
-/*006c*/ 0x10080425U,
-/*006d*/ 0x18030425U,
-/*006e*/ 0x000a0426U,
-/*006f*/ 0x100a0426U,
-/*0070*/ 0x00110427U,
-/*0071*/ 0x00090428U,
-/*0072*/ 0x10090428U,
-/*0073*/ 0x00100429U,
-/*0074*/ 0x100e0429U,
-/*0075*/ 0x000e042aU,
-/*0076*/ 0x100c042aU,
-/*0077*/ 0x000a042bU,
-/*0078*/ 0x100a042bU,
-/*0079*/ 0x0002042cU,
-/*007a*/ 0x0020042dU,
-/*007b*/ 0x000b042eU,
-/*007c*/ 0x100b042eU,
-/*007d*/ 0x0020042fU,
-/*007e*/ 0x00120430U,
-/*007f*/ 0x00200431U,
-/*0080*/ 0x00200432U,
-/*0081*/ 0xffffffffU,
-/*0082*/ 0xffffffffU,
-/*0083*/ 0x00010433U,
-/*0084*/ 0x08010433U,
-/*0085*/ 0x10080433U,
-/*0086*/ 0x000c0434U,
-/*0087*/ 0x100c0434U,
-/*0088*/ 0x000c0435U,
-/*0089*/ 0x100c0435U,
-/*008a*/ 0x000c0436U,
-/*008b*/ 0x100c0436U,
-/*008c*/ 0x000c0437U,
-/*008d*/ 0x100c0437U,
-/*008e*/ 0x000c0438U,
-/*008f*/ 0x100c0438U,
-/*0090*/ 0x000c0439U,
-/*0091*/ 0x100b0439U,
-/*0092*/ 0xffffffffU,
-/*0093*/ 0xffffffffU,
-/*0094*/ 0x000b043aU,
-/*0095*/ 0x100b043aU,
-/*0096*/ 0x000b043bU,
-/*0097*/ 0x100b043bU,
-/*0098*/ 0x000b043cU,
-/*0099*/ 0x100b043cU,
-/*009a*/ 0x000b043dU,
-/*009b*/ 0x100b043dU,
-/*009c*/ 0x000b043eU,
-/*009d*/ 0x100a043eU,
-/*009e*/ 0xffffffffU,
-/*009f*/ 0x000a043fU,
-/*00a0*/ 0x100a043fU,
-/*00a1*/ 0x000a0440U,
-/*00a2*/ 0x100a0440U,
-/*00a3*/ 0x000a0441U,
-/*00a4*/ 0x100a0441U,
-/*00a5*/ 0x000a0442U,
-/*00a6*/ 0x100a0442U,
-/*00a7*/ 0xffffffffU,
-/*00a8*/ 0x000a0443U,
-/*00a9*/ 0x100a0443U,
-/*00aa*/ 0x000a0444U,
-/*00ab*/ 0x100a0444U,
-/*00ac*/ 0x000a0445U,
-/*00ad*/ 0x100a0445U,
-/*00ae*/ 0x000a0446U,
-/*00af*/ 0x100a0446U,
-/*00b0*/ 0x000a0447U,
-/*00b1*/ 0x100a0447U,
-/*00b2*/ 0x000a0448U,
-/*00b3*/ 0x100a0448U,
-/*00b4*/ 0x000a0449U,
-/*00b5*/ 0x100a0449U,
-/*00b6*/ 0x000a044aU,
-/*00b7*/ 0x100a044aU,
-/*00b8*/ 0x000a044bU,
-/*00b9*/ 0x100a044bU,
-/*00ba*/ 0x000a044cU,
-/*00bb*/ 0x1004044cU,
-/*00bc*/ 0x1803044cU,
-/*00bd*/ 0x000a044dU,
-/*00be*/ 0x100a044dU,
-/*00bf*/ 0x0001044eU,
-/*00c0*/ 0x080a044eU,
-/*00c1*/ 0x1804044eU,
-/*00c2*/ 0x000b044fU,
-/*00c3*/ 0x100a044fU,
-/*00c4*/ 0xffffffffU,
-/*00c5*/ 0x00080450U,
-/*00c6*/ 0x08080450U,
-/*00c7*/ 0x10080450U,
-/*00c8*/ 0x18080450U,
-/*00c9*/ 0x00080451U,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x08080451U,
-/*00cc*/ 0x10010451U,
-/*00cd*/ 0x18080451U,
-/*00ce*/ 0x00080452U,
-/*00cf*/ 0x08020452U,
-/*00d0*/ 0x10020452U,
-/*00d1*/ 0x18040452U,
-/*00d2*/ 0x00040453U,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x08040453U,
-/*00d5*/ 0x100a0453U,
-/*00d6*/ 0x00060454U,
-/*00d7*/ 0x08080454U,
-/*00d8*/ 0xffffffffU,
-/*00d9*/ 0x10040454U,
-/*00da*/ 0x18040454U,
-/*00db*/ 0x00050455U,
-/*00dc*/ 0x08040455U,
-/*00dd*/ 0x10050455U,
-/*00de*/ 0x000a0456U,
-/*00df*/ 0x100a0456U,
-/*00e0*/ 0x00080457U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040457U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050600U,
-/*00e6*/ 0x08050600U,
-/*00e7*/ 0x10050600U,
-/*00e8*/ 0x18050600U,
-/*00e9*/ 0x00050601U,
-/*00ea*/ 0x08050601U,
-/*00eb*/ 0x100b0601U,
-/*00ec*/ 0x00010602U,
-/*00ed*/ 0x08030602U,
-/*00ee*/ 0x00200603U,
-/*00ef*/ 0xffffffffU,
-/*00f0*/ 0x00030604U,
-/*00f1*/ 0x080a0604U,
-/*00f2*/ 0xffffffffU,
-/*00f3*/ 0xffffffffU,
-/*00f4*/ 0x18030604U,
-/*00f5*/ 0x00030605U,
-/*00f6*/ 0x08010605U,
-/*00f7*/ 0x10010605U,
-/*00f8*/ 0x18060605U,
-/*00f9*/ 0xffffffffU,
-/*00fa*/ 0xffffffffU,
-/*00fb*/ 0xffffffffU,
-/*00fc*/ 0x00020606U,
-/*00fd*/ 0x08030606U,
-/*00fe*/ 0x10010606U,
-/*00ff*/ 0x000f0607U,
-/*0100*/ 0x00200608U,
-/*0101*/ 0x00200609U,
-/*0102*/ 0x000b060aU,
-/*0103*/ 0x100b060aU,
-/*0104*/ 0x000b060bU,
-/*0105*/ 0xffffffffU,
-/*0106*/ 0xffffffffU,
-/*0107*/ 0x0018060cU,
-/*0108*/ 0x0018060dU,
-/*0109*/ 0x0018060eU,
-/*010a*/ 0x0018060fU,
-/*010b*/ 0x1804060fU,
-/*010c*/ 0x00050610U,
-/*010d*/ 0x08020610U,
-/*010e*/ 0x10040610U,
-/*010f*/ 0x18040610U,
-/*0110*/ 0x00010611U,
-/*0111*/ 0x08010611U,
-/*0112*/ 0x10010611U,
-/*0113*/ 0x18030611U,
-/*0114*/ 0x00200612U,
-/*0115*/ 0x00200613U,
-/*0116*/ 0x00010614U,
-/*0117*/ 0x08140614U,
-/*0118*/ 0x00140615U,
-/*0119*/ 0x00140616U,
-/*011a*/ 0x00140617U,
-/*011b*/ 0x00140618U,
-/*011c*/ 0x00140619U,
-/*011d*/ 0x0014061aU,
-/*011e*/ 0x0014061bU,
-/*011f*/ 0x0018061cU,
-/*0120*/ 0x000a061dU,
-/*0121*/ 0x1006061dU,
-/*0122*/ 0x1806061dU,
-/*0123*/ 0x0006061eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0xffffffffU,
-/*0126*/ 0x0008061fU,
-/*0127*/ 0x080b061fU,
-/*0128*/ 0x000b0620U,
-/*0129*/ 0x100b0620U,
-/*012a*/ 0x000b0621U,
-/*012b*/ 0x100b0621U,
-/*012c*/ 0x000b0622U,
-/*012d*/ 0x10040622U,
-/*012e*/ 0x000a0623U,
-/*012f*/ 0x10060623U,
-/*0130*/ 0x18080623U,
-/*0131*/ 0xffffffffU,
-/*0132*/ 0x00040624U,
-/*0133*/ 0xffffffffU,
-/*0134*/ 0xffffffffU,
-/*0135*/ 0x00010700U,
-/*0136*/ 0x08020700U,
-/*0137*/ 0x10050700U,
-/*0138*/ 0x18050700U,
-/*0139*/ 0x00050701U,
-/*013a*/ 0x08050701U,
-/*013b*/ 0x100b0701U,
-/*013c*/ 0x00050702U,
-/*013d*/ 0x08010702U,
-/*013e*/ 0x10010702U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x18010702U,
-/*0141*/ 0x00010703U,
-/*0142*/ 0x08040703U,
-/*0143*/ 0x100b0703U,
-/*0144*/ 0x000b0704U,
-/*0145*/ 0xffffffffU,
-/*0146*/ 0x10040704U,
-/*0147*/ 0x000b0705U,
-/*0148*/ 0x10040705U,
-/*0149*/ 0x18010705U,
-/*014a*/ 0x00010706U,
-/*014b*/ 0x08010706U,
-/*014c*/ 0x00200707U,
-/*014d*/ 0x00200708U,
-/*014e*/ 0x00080709U,
-/*014f*/ 0x080a0709U,
-/*0150*/ 0x18050709U,
-/*0151*/ 0x000a070aU,
-/*0152*/ 0x1003070aU,
-/*0153*/ 0x1803070aU,
-/*0154*/ 0x0001070bU,
-/*0155*/ 0x0802070bU,
-/*0156*/ 0x1001070bU,
-/*0157*/ 0x1801070bU,
-/*0158*/ 0x0001070cU,
-/*0159*/ 0x0802070cU,
-/*015a*/ 0xffffffffU,
-/*015b*/ 0xffffffffU,
-/*015c*/ 0xffffffffU,
-/*015d*/ 0xffffffffU,
-/*015e*/ 0xffffffffU,
-/*015f*/ 0xffffffffU,
-/*0160*/ 0xffffffffU,
-/*0161*/ 0xffffffffU,
-/*0162*/ 0xffffffffU,
-/*0163*/ 0xffffffffU,
-/*0164*/ 0xffffffffU,
-/*0165*/ 0xffffffffU,
-/*0166*/ 0x1001070cU,
-/*0167*/ 0x1801070cU,
-/*0168*/ 0x000d070dU,
-/*0169*/ 0xffffffffU,
-/*016a*/ 0xffffffffU,
-/*016b*/ 0x0005070eU,
-/*016c*/ 0x0001070fU,
-/*016d*/ 0x080e070fU,
-/*016e*/ 0x000e0710U,
-/*016f*/ 0x100e0710U,
-/*0170*/ 0x000e0711U,
-/*0171*/ 0x100e0711U,
-/*0172*/ 0x00040712U,
-/*0173*/ 0xffffffffU,
-/*0174*/ 0xffffffffU,
-/*0175*/ 0xffffffffU,
-/*0176*/ 0xffffffffU,
-/*0177*/ 0x080b0712U,
-/*0178*/ 0x000b0713U,
-/*0179*/ 0x100b0713U,
-/*017a*/ 0x000b0714U,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d0715U,
-/*0180*/ 0xffffffffU,
-/*0181*/ 0xffffffffU,
-/*0182*/ 0x10100715U,
-/*0183*/ 0x00080716U,
-/*0184*/ 0xffffffffU,
-/*0185*/ 0x08100716U,
-/*0186*/ 0x00100717U,
-/*0187*/ 0x10100717U,
-/*0188*/ 0x00100718U,
-/*0189*/ 0x10100718U,
-/*018a*/ 0x00030719U,
-/*018b*/ 0x08040719U,
-/*018c*/ 0x10010719U,
-/*018d*/ 0x18040719U,
-/*018e*/ 0xffffffffU,
-/*018f*/ 0xffffffffU,
-/*0190*/ 0x0001071aU,
-/*0191*/ 0x0812071aU,
-/*0192*/ 0x000a071bU,
-/*0193*/ 0x100c071bU,
-/*0194*/ 0x0012071cU,
-/*0195*/ 0x0014071dU,
-/*0196*/ 0x0012071eU,
-/*0197*/ 0x0011071fU,
-/*0198*/ 0x00110720U,
-/*0199*/ 0x00120721U,
-/*019a*/ 0x00120722U,
-/*019b*/ 0x00120723U,
-/*019c*/ 0x00120724U,
-/*019d*/ 0x00120725U,
-/*019e*/ 0x00120726U,
-/*019f*/ 0x00120727U,
-/*01a0*/ 0x00120728U,
-/*01a1*/ 0xffffffffU,
-/*01a2*/ 0xffffffffU,
-/*01a3*/ 0x00190729U,
-/*01a4*/ 0x0019072aU,
-/*01a5*/ 0x0020072bU,
-/*01a6*/ 0x0017072cU,
-/*01a7*/ 0x1808072cU,
-/*01a8*/ 0x0001072dU,
-/*01a9*/ 0x0801072dU,
-/*01aa*/ 0x0020072eU,
-/*01ab*/ 0x0008072fU,
-/*01ac*/ 0xffffffffU,
-/*01ad*/ 0x0803072fU,
-/*01ae*/ 0x00180730U,
-/*01af*/ 0x00180731U,
-/*01b0*/ 0xffffffffU,
-/*01b1*/ 0xffffffffU,
-/*01b2*/ 0xffffffffU,
-/*01b3*/ 0xffffffffU,
-/*01b4*/ 0xffffffffU,
-/*01b5*/ 0xffffffffU,
-/*01b6*/ 0xffffffffU,
-/*01b7*/ 0xffffffffU,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x00100732U,
-/*01c0*/ 0x10010732U,
-/*01c1*/ 0x18010732U,
-/*01c2*/ 0x00050733U,
-/*01c3*/ 0x00200734U,
-/*01c4*/ 0x00090735U,
-/*01c5*/ 0xffffffffU,
-/*01c6*/ 0xffffffffU,
-/*01c7*/ 0x00200736U,
-/*01c8*/ 0x00040737U,
-/*01c9*/ 0x08100737U,
-/*01ca*/ 0x18060737U,
-/*01cb*/ 0x00100738U,
-/*01cc*/ 0xffffffffU,
-/*01cd*/ 0xffffffffU,
-/*01ce*/ 0xffffffffU,
-/*01cf*/ 0xffffffffU,
-/*01d0*/ 0xffffffffU,
-/*01d1*/ 0xffffffffU,
-/*01d2*/ 0xffffffffU,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200739U,
-/*01d5*/ 0x000b073aU,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0xffffffffU,
-/*01d8*/ 0xffffffffU,
-/*01d9*/ 0xffffffffU,
-/*01da*/ 0xffffffffU,
-/*01db*/ 0xffffffffU,
-/*01dc*/ 0xffffffffU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0xffffffffU,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x10100201U,
-/*01e6*/ 0xffffffffU,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200202U,
-/*01f0*/ 0x00100203U,
-/*01f1*/ 0x00200204U,
-/*01f2*/ 0x00100205U,
-/*01f3*/ 0x00200206U,
-/*01f4*/ 0x00100207U,
-/*01f5*/ 0x10100207U,
-/*01f6*/ 0x00200208U,
-/*01f7*/ 0x00200209U,
-/*01f8*/ 0x0020020aU,
-/*01f9*/ 0x0020020bU,
-/*01fa*/ 0x0010020cU,
-/*01fb*/ 0x0020020dU,
-/*01fc*/ 0x0020020eU,
-/*01fd*/ 0x0020020fU,
-/*01fe*/ 0x00200210U,
-/*01ff*/ 0x00100211U,
-/*0200*/ 0x00200212U,
-/*0201*/ 0x00200213U,
-/*0202*/ 0x00200214U,
-/*0203*/ 0x00200215U,
-/*0204*/ 0x00090216U,
-/*0205*/ 0x10010216U,
-/*0206*/ 0x00200217U,
-/*0207*/ 0x00050218U,
-/*0208*/ 0x08010218U,
-/*0209*/ 0x10080218U,
-/*020a*/ 0x18080218U,
-/*020b*/ 0x001c0219U,
-/*020c*/ 0x001c021aU,
-/*020d*/ 0x001c021bU,
-/*020e*/ 0x001c021cU,
-/*020f*/ 0x001c021dU,
-/*0210*/ 0x001c021eU,
-/*0211*/ 0x001c021fU,
-/*0212*/ 0x001c0220U,
-/*0213*/ 0x001c0221U,
-/*0214*/ 0x001c0222U,
-/*0215*/ 0x001c0223U,
-/*0216*/ 0x001c0224U,
-/*0217*/ 0x001c0225U,
-/*0218*/ 0x001c0226U,
-/*0219*/ 0x001c0227U,
-/*021a*/ 0x001c0228U,
-/*021b*/ 0x00010229U,
-/*021c*/ 0x08010229U,
-/*021d*/ 0x10010229U,
-/*021e*/ 0x18040229U,
-/*021f*/ 0x0008022aU,
-/*0220*/ 0x0808022aU,
-/*0221*/ 0x1008022aU,
-/*0222*/ 0x1804022aU,
-/*0223*/ 0x0006022bU,
-/*0224*/ 0xffffffffU,
-/*0225*/ 0x0807022bU,
-/*0226*/ 0x1006022bU,
-/*0227*/ 0xffffffffU,
-/*0228*/ 0x1807022bU,
-/*0229*/ 0x0006022cU,
-/*022a*/ 0xffffffffU,
-/*022b*/ 0x0807022cU,
-/*022c*/ 0x1002022cU,
-/*022d*/ 0x1801022cU,
-/*022e*/ 0xffffffffU,
-/*022f*/ 0x000a022dU,
-/*0230*/ 0x1010022dU,
-/*0231*/ 0x000a022eU,
-/*0232*/ 0x1010022eU,
-/*0233*/ 0x000a022fU,
-/*0234*/ 0x1010022fU,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0x00100230U,
-/*0237*/ 0xffffffffU,
-/*0238*/ 0xffffffffU,
-/*0239*/ 0x10010230U,
-/*023a*/ 0x18010230U,
-/*023b*/ 0x00010231U,
-/*023c*/ 0x08010231U,
-/*023d*/ 0x10010231U,
-/*023e*/ 0x18010231U,
-/*023f*/ 0x00020232U,
-/*0240*/ 0x08020232U,
-/*0241*/ 0x10020232U,
-/*0242*/ 0x18020232U,
-/*0243*/ 0x00020233U,
-/*0244*/ 0x08030233U,
-/*0245*/ 0x10010233U,
-/*0246*/ 0x18010233U,
-/*0247*/ 0x00010234U,
-/*0248*/ 0x08010234U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x10020234U,
-/*024b*/ 0x18010234U,
-/*024c*/ 0x00010235U,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x08020235U,
-/*024f*/ 0x10010235U,
-/*0250*/ 0x18010235U,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x00020236U,
-/*0253*/ 0x08010236U,
-/*0254*/ 0x10010236U,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x18020236U,
-/*0257*/ 0x00070237U,
-/*0258*/ 0x08010237U,
-/*0259*/ 0x10010237U,
-/*025a*/ 0x18010237U,
-/*025b*/ 0x00010238U,
-/*025c*/ 0x08010238U,
-/*025d*/ 0x10010238U,
-/*025e*/ 0xffffffffU,
-/*025f*/ 0x18010238U,
-/*0260*/ 0x00040239U,
-/*0261*/ 0x08040239U,
-/*0262*/ 0x10040239U,
-/*0263*/ 0x18010239U,
-/*0264*/ 0x0002023aU,
-/*0265*/ 0x0806023aU,
-/*0266*/ 0x1006023aU,
-/*0267*/ 0xffffffffU,
-/*0268*/ 0xffffffffU,
-/*0269*/ 0xffffffffU,
-/*026a*/ 0x1802023aU,
-/*026b*/ 0x0010023bU,
-/*026c*/ 0x1001023bU,
-/*026d*/ 0x1801023bU,
-/*026e*/ 0xffffffffU,
-/*026f*/ 0x0004023cU,
-/*0270*/ 0x0801023cU,
-/*0271*/ 0x1004023cU,
-/*0272*/ 0x1802023cU,
-/*0273*/ 0x0008023dU,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x080a023dU,
-/*0278*/ 0x0020023eU,
-/*0279*/ 0x0020023fU,
-/*027a*/ 0x00050240U,
-/*027b*/ 0x08010240U,
-/*027c*/ 0x10050240U,
-/*027d*/ 0x18080240U,
-/*027e*/ 0x00010241U,
-/*027f*/ 0x08080241U,
-/*0280*/ 0x10010241U,
-/*0281*/ 0x18080241U,
-/*0282*/ 0x00010242U,
-/*0283*/ 0x08040242U,
-/*0284*/ 0x10040242U,
-/*0285*/ 0x18040242U,
-/*0286*/ 0x00040243U,
-/*0287*/ 0x08040243U,
-/*0288*/ 0x10040243U,
-/*0289*/ 0x18040243U,
-/*028a*/ 0x00040244U,
-/*028b*/ 0x08040244U,
-/*028c*/ 0x10040244U,
-/*028d*/ 0x18010244U,
-/*028e*/ 0x00040245U,
-/*028f*/ 0x08040245U,
-/*0290*/ 0x10040245U,
-/*0291*/ 0x18040245U,
-/*0292*/ 0x00040246U,
-/*0293*/ 0x08040246U,
-/*0294*/ 0x10060246U,
-/*0295*/ 0x18060246U,
-/*0296*/ 0x00060247U,
-/*0297*/ 0x08060247U,
-/*0298*/ 0x10060247U,
-/*0299*/ 0x18060247U,
-/*029a*/ 0xffffffffU,
-/*029b*/ 0x00010248U,
-/*029c*/ 0x08010248U,
-/*029d*/ 0x10020248U,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x18040248U,
-/*02a7*/ 0x00040249U,
-/*02a8*/ 0x08010249U,
-/*02a9*/ 0x10010249U,
-/*02aa*/ 0xffffffffU,
-/*02ab*/ 0x18010249U,
-/*02ac*/ 0x0001024aU,
-/*02ad*/ 0xffffffffU,
-/*02ae*/ 0x0801024aU,
-/*02af*/ 0x1001024aU,
-/*02b0*/ 0x1801024aU,
-/*02b1*/ 0x0004024bU,
-/*02b2*/ 0x0804024bU,
-/*02b3*/ 0x100a024bU,
-/*02b4*/ 0x0020024cU,
-/*02b5*/ 0x0004024dU,
-/*02b6*/ 0x0808024dU,
-/*02b7*/ 0xffffffffU,
-/*02b8*/ 0xffffffffU,
-/*02b9*/ 0xffffffffU,
-/*02ba*/ 0xffffffffU,
-/*02bb*/ 0xffffffffU,
-/*02bc*/ 0xffffffffU,
-/*02bd*/ 0x1002024dU,
-/*02be*/ 0x1802024dU,
-/*02bf*/ 0x0020024eU,
-/*02c0*/ 0x0002024fU,
-/*02c1*/ 0x0810024fU,
-/*02c2*/ 0x00100250U,
-/*02c3*/ 0x10040250U,
-/*02c4*/ 0x18040250U,
-/*02c5*/ 0x00050251U,
-/*02c6*/ 0x08050251U,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x10010251U,
-/*02cc*/ 0x18010251U,
-/*02cd*/ 0x00070252U,
-/*02ce*/ 0x08070252U,
-/*02cf*/ 0x10070252U,
-/*02d0*/ 0x18070252U,
-/*02d1*/ 0x00070253U,
-/*02d2*/ 0x08070253U,
-/*02d3*/ 0x10070253U,
-/*02d4*/ 0x18070253U,
-/*02d5*/ 0x00070254U,
-/*02d6*/ 0x08070254U,
-/*02d7*/ 0x10070254U,
-/*02d8*/ 0xffffffffU,
-/*02d9*/ 0xffffffffU,
-/*02da*/ 0xffffffffU,
-/*02db*/ 0xffffffffU,
-/*02dc*/ 0xffffffffU,
-/*02dd*/ 0xffffffffU,
-/*02de*/ 0x18030254U,
-/*02df*/ 0x00010255U,
-/*02e0*/ 0x08020255U,
-/*02e1*/ 0x10010255U,
-/*02e2*/ 0x18040255U,
-/*02e3*/ 0x00020256U,
-/*02e4*/ 0x08010256U,
-/*02e5*/ 0x10010256U,
-/*02e6*/ 0xffffffffU,
-/*02e7*/ 0x18010256U,
-/*02e8*/ 0x00040257U,
-/*02e9*/ 0x08080257U,
-/*02ea*/ 0x100a0257U,
-/*02eb*/ 0x000a0258U,
-/*02ec*/ 0x100a0258U,
-/*02ed*/ 0x000a0259U,
-/*02ee*/ 0x100a0259U,
-/*02ef*/ 0x000a025aU,
-/*02f0*/ 0x0020025bU,
-/*02f1*/ 0x0020025cU,
-/*02f2*/ 0x0001025dU,
-/*02f3*/ 0xffffffffU,
-/*02f4*/ 0xffffffffU,
-/*02f5*/ 0xffffffffU,
-/*02f6*/ 0x0802025dU,
-/*02f7*/ 0x1002025dU,
-/*02f8*/ 0x0010025eU,
-/*02f9*/ 0x1005025eU,
-/*02fa*/ 0x1806025eU,
-/*02fb*/ 0x0005025fU,
-/*02fc*/ 0x0805025fU,
-/*02fd*/ 0x100e025fU,
-/*02fe*/ 0x00050260U,
-/*02ff*/ 0x080e0260U,
-/*0300*/ 0x18050260U,
-/*0301*/ 0x000e0261U,
-/*0302*/ 0x10050261U,
-/*0303*/ 0x18010261U,
-/*0304*/ 0x00050262U,
-/*0305*/ 0x08050262U,
-/*0306*/ 0x100a0262U,
-/*0307*/ 0x000a0263U,
-/*0308*/ 0x10050263U,
-/*0309*/ 0x18050263U,
-/*030a*/ 0x000a0264U,
-/*030b*/ 0x100a0264U,
-/*030c*/ 0x00050265U,
-/*030d*/ 0x08050265U,
-/*030e*/ 0x100a0265U,
-/*030f*/ 0x000a0266U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070266U,
-/*0317*/ 0x18070266U,
-/*0318*/ 0x00040267U,
-/*0319*/ 0x08040267U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040267U,
-/*031e*/ 0x18080267U,
-/*031f*/ 0x00080268U,
-/*0320*/ 0x08040268U,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x10040268U,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x18040268U,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x00040269U,
-/*032d*/ 0x08050269U,
-/*032e*/ 0x10070269U,
-/*032f*/ 0x18080269U,
-/*0330*/ 0x0010026aU,
-/*0331*/ 0x1008026aU,
-/*0332*/ 0x0010026bU,
-/*0333*/ 0x1008026bU,
-/*0334*/ 0x0010026cU,
-/*0335*/ 0x1008026cU,
-/*0336*/ 0x1808026cU,
-/*0337*/ 0x0001026dU,
-/*0338*/ 0x0801026dU,
-/*0339*/ 0x1006026dU,
-/*033a*/ 0x1806026dU,
-/*033b*/ 0x0006026eU,
-/*033c*/ 0xffffffffU,
-/*033d*/ 0x0801026eU,
-/*033e*/ 0x1003026eU,
-/*033f*/ 0xffffffffU,
-/*0340*/ 0xffffffffU,
-/*0341*/ 0xffffffffU,
-/*0342*/ 0x000a026fU,
-/*0343*/ 0x100a026fU,
-/*0344*/ 0x00040270U,
-/*0345*/ 0x08010270U,
-/*0346*/ 0x10040270U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070270U,
-/*034e*/ 0x00070271U,
-/*034f*/ 0x08050271U,
-/*0350*/ 0x10050271U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040271U,
-/*0355*/ 0x00010272U,
-/*0356*/ 0x08010272U,
-/*0357*/ 0x10020272U,
-/*0358*/ 0x18080272U,
-/*0359*/ 0x00200273U,
-/*035a*/ 0x00200274U,
-/*035b*/ 0x00100275U,
-/*035c*/ 0xffffffffU,
-/*035d*/ 0xffffffffU,
-/*035e*/ 0xffffffffU,
-/*035f*/ 0x10020275U,
-/*0360*/ 0x18010275U,
-/*0361*/ 0xffffffffU,
-/*0362*/ 0x00020276U,
-/*0363*/ 0x08080276U,
-/*0364*/ 0x10080276U,
-/*0365*/ 0x18080276U,
-/*0366*/ 0x00080277U,
-/*0367*/ 0x08080277U,
-/*0368*/ 0x10080277U,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x18080277U,
-/*036b*/ 0x00080278U,
-/*036c*/ 0x08080278U,
-/*036d*/ 0x10080278U,
-/*036e*/ 0x18080278U,
-/*036f*/ 0x00080279U,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x08080279U,
-/*0372*/ 0x10080279U,
-/*0373*/ 0x18080279U,
-/*0374*/ 0x0008027aU,
-/*0375*/ 0x0808027aU,
-/*0376*/ 0x1008027aU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1808027aU,
-/*0379*/ 0x0008027bU,
-/*037a*/ 0x0808027bU,
-/*037b*/ 0x1008027bU,
-/*037c*/ 0x1808027bU,
-/*037d*/ 0x0008027cU,
-/*037e*/ 0x0808027cU,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x1008027cU,
-/*0381*/ 0x1808027cU,
-/*0382*/ 0x0008027dU,
-/*0383*/ 0x0808027dU,
-/*0384*/ 0x1008027dU,
-/*0385*/ 0x1808027dU,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x0008027eU,
-/*0388*/ 0x0808027eU,
-/*0389*/ 0x1008027eU,
-/*038a*/ 0x1808027eU,
-/*038b*/ 0x0008027fU,
-/*038c*/ 0x0808027fU,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x1008027fU,
-/*038f*/ 0x1808027fU,
-/*0390*/ 0x00080280U,
-/*0391*/ 0x08080280U,
-/*0392*/ 0x10080280U,
-/*0393*/ 0x18080280U,
-/*0394*/ 0x00080281U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x08080281U,
-/*0397*/ 0x10080281U,
-/*0398*/ 0x18080281U,
-/*0399*/ 0x00080282U,
-/*039a*/ 0x08080282U,
-/*039b*/ 0x10080282U,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x18080282U,
-/*039e*/ 0x00080283U,
-/*039f*/ 0x08080283U,
-/*03a0*/ 0x10080283U,
-/*03a1*/ 0x18080283U,
-/*03a2*/ 0x00080284U,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x08080284U,
-/*03a5*/ 0x10080284U,
-/*03a6*/ 0x18080284U,
-/*03a7*/ 0x00080285U,
-/*03a8*/ 0x08080285U,
-/*03a9*/ 0x10080285U,
-/*03aa*/ 0x18080285U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x00080286U,
-/*03ad*/ 0x08080286U,
-/*03ae*/ 0x10080286U,
-/*03af*/ 0x18080286U,
-/*03b0*/ 0x00080287U,
-/*03b1*/ 0x08080287U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x10080287U,
-/*03b4*/ 0x18080287U,
-/*03b5*/ 0x00080288U,
-/*03b6*/ 0x08080288U,
-/*03b7*/ 0x10080288U,
-/*03b8*/ 0x18080288U,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x00080289U,
-/*03bb*/ 0x08020289U,
-/*03bc*/ 0x10030289U,
-/*03bd*/ 0x000a028aU,
-/*03be*/ 0x100a028aU,
-/*03bf*/ 0x000a028bU,
-/*03c0*/ 0x1005028bU,
-/*03c1*/ 0x1804028bU,
-/*03c2*/ 0x0008028cU,
-/*03c3*/ 0x0808028cU,
-/*03c4*/ 0x1006028cU,
-/*03c5*/ 0x1806028cU,
-/*03c6*/ 0x0011028dU,
-/*03c7*/ 0x1808028dU,
-/*03c8*/ 0x0004028eU,
-/*03c9*/ 0x0806028eU,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x1006028eU,
-/*03cc*/ 0x1808028eU,
-/*03cd*/ 0xffffffffU,
-/*03ce*/ 0x0004028fU,
-/*03cf*/ 0x0808028fU,
-/*03d0*/ 0x1008028fU,
-/*03d1*/ 0x1806028fU,
-/*03d2*/ 0x00060290U,
-/*03d3*/ 0x08110290U,
-/*03d4*/ 0x00080291U,
-/*03d5*/ 0x08040291U,
-/*03d6*/ 0x10060291U,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x18060291U,
-/*03d9*/ 0x00080292U,
-/*03da*/ 0xffffffffU,
-/*03db*/ 0x08040292U,
-/*03dc*/ 0x10080292U,
-/*03dd*/ 0x18080292U,
-/*03de*/ 0x00060293U,
-/*03df*/ 0x08060293U,
-/*03e0*/ 0x00110294U,
-/*03e1*/ 0x18080294U,
-/*03e2*/ 0x00040295U,
-/*03e3*/ 0x08060295U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x10060295U,
-/*03e6*/ 0x18080295U,
-/*03e7*/ 0xffffffffU,
-/*03e8*/ 0x00040296U,
-/*03e9*/ 0x08040296U,
-/*03ea*/ 0x10040296U,
-/*03eb*/ 0x18040296U,
-/*03ec*/ 0x00040297U,
-/*03ed*/ 0x08040297U,
-/*03ee*/ 0x10040297U,
-/*03ef*/ 0x18040297U,
-/*03f0*/ 0x00040298U,
-/*03f1*/ 0x08040298U,
-/*03f2*/ 0x10040298U,
-/*03f3*/ 0x18040298U,
-/*03f4*/ 0x00040299U,
-/*03f5*/ 0x08040299U,
-/*03f6*/ 0x10040299U,
-/*03f7*/ 0x18040299U,
-/*03f8*/ 0x0004029aU,
-/*03f9*/ 0x0804029aU,
-/*03fa*/ 0x1004029aU,
-/*03fb*/ 0x1804029aU,
-/*03fc*/ 0x0011029bU,
-/*03fd*/ 0x0010029cU,
-/*03fe*/ 0x0011029dU,
-/*03ff*/ 0x0020029eU,
-/*0400*/ 0x0020029fU,
-/*0401*/ 0x002002a0U,
-/*0402*/ 0x002002a1U,
-/*0403*/ 0x002002a2U,
-/*0404*/ 0x002002a3U,
-/*0405*/ 0x002002a4U,
-/*0406*/ 0x002002a5U,
-/*0407*/ 0x002002a6U,
-/*0408*/ 0x000202a7U,
-/*0409*/ 0x080502a7U,
-/*040a*/ 0x100502a7U,
-/*040b*/ 0xffffffffU,
-/*040c*/ 0xffffffffU,
-/*040d*/ 0xffffffffU,
-/*040e*/ 0xffffffffU,
-/*040f*/ 0xffffffffU,
-/*0410*/ 0xffffffffU,
-/*0411*/ 0xffffffffU,
-/*0412*/ 0xffffffffU,
-/*0413*/ 0xffffffffU,
-/*0414*/ 0xffffffffU,
-/*0415*/ 0xffffffffU,
-/*0416*/ 0xffffffffU,
-/*0417*/ 0xffffffffU,
-/*0418*/ 0xffffffffU,
-/*0419*/ 0xffffffffU,
-/*041a*/ 0xffffffffU,
-/*041b*/ 0xffffffffU,
-/*041c*/ 0xffffffffU,
-/*041d*/ 0xffffffffU,
-/*041e*/ 0xffffffffU,
-/*041f*/ 0xffffffffU,
-/*0420*/ 0xffffffffU,
-/*0421*/ 0xffffffffU,
-/*0422*/ 0xffffffffU,
-/*0423*/ 0xffffffffU,
-/*0424*/ 0xffffffffU,
-/*0425*/ 0xffffffffU,
-/*0426*/ 0xffffffffU,
-/*0427*/ 0x180102a7U,
-/*0428*/ 0x000402a8U,
-/*0429*/ 0x081002a8U,
-/*042a*/ 0x002002a9U,
-/*042b*/ 0x001002aaU,
-/*042c*/ 0x002002abU,
-/*042d*/ 0x001002acU,
-/*042e*/ 0x002002adU,
-/*042f*/ 0x000702aeU,
-/*0430*/ 0x080102aeU,
-/*0431*/ 0x100202aeU,
-/*0432*/ 0x180602aeU,
-/*0433*/ 0x000102afU,
-/*0434*/ 0x080102afU,
-/*0435*/ 0x002002b0U,
-/*0436*/ 0x000202b1U,
-/*0437*/ 0x002002b2U,
-/*0438*/ 0x002002b3U,
-/*0439*/ 0xffffffffU,
-/*043a*/ 0xffffffffU,
-/*043b*/ 0xffffffffU,
-/*043c*/ 0xffffffffU,
-/*043d*/ 0xffffffffU,
-/*043e*/ 0xffffffffU,
-/*043f*/ 0xffffffffU,
-/*0440*/ 0xffffffffU,
-/*0441*/ 0xffffffffU,
-/*0442*/ 0xffffffffU,
-/*0443*/ 0xffffffffU,
-/*0444*/ 0xffffffffU,
-/*0445*/ 0xffffffffU,
-/*0446*/ 0xffffffffU,
-/*0447*/ 0xffffffffU,
-/*0448*/ 0xffffffffU,
-/*0449*/ 0xffffffffU,
-/*044a*/ 0xffffffffU,
-/*044b*/ 0xffffffffU,
-/*044c*/ 0xffffffffU,
-/*044d*/ 0xffffffffU,
-/*044e*/ 0xffffffffU,
-/*044f*/ 0xffffffffU,
-/*0450*/ 0xffffffffU,
-/*0451*/ 0xffffffffU,
-/*0452*/ 0xffffffffU,
-/*0453*/ 0xffffffffU,
-/*0454*/ 0xffffffffU,
-/*0455*/ 0xffffffffU,
-/*0456*/ 0xffffffffU,
-/*0457*/ 0xffffffffU,
-/*0458*/ 0xffffffffU,
-/*0459*/ 0xffffffffU,
-/*045a*/ 0xffffffffU,
-/*045b*/ 0xffffffffU,
-/*045c*/ 0xffffffffU,
-/*045d*/ 0xffffffffU,
-/*045e*/ 0xffffffffU,
-/*045f*/ 0x000402b4U,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0xffffffffU,
-/*0465*/ 0xffffffffU,
-/*0466*/ 0xffffffffU,
-/*0467*/ 0xffffffffU,
-/*0468*/ 0xffffffffU,
-/*0469*/ 0xffffffffU,
-/*046a*/ 0xffffffffU,
-/*046b*/ 0xffffffffU,
-/*046c*/ 0xffffffffU,
-/*046d*/ 0xffffffffU,
-/*046e*/ 0xffffffffU,
-/*046f*/ 0xffffffffU,
-/*0470*/ 0xffffffffU,
-/*0471*/ 0xffffffffU,
-/*0472*/ 0xffffffffU,
-/*0473*/ 0xffffffffU,
-/*0474*/ 0xffffffffU,
-/*0475*/ 0xffffffffU,
-/*0476*/ 0xffffffffU,
-/*0477*/ 0xffffffffU,
-/*0478*/ 0xffffffffU,
-/*0479*/ 0xffffffffU,
-/*047a*/ 0xffffffffU,
-/*047b*/ 0xffffffffU,
-/*047c*/ 0xffffffffU,
-/*047d*/ 0xffffffffU,
-/*047e*/ 0xffffffffU,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
-	 },
-	{
-/*0000*/ 0x00200800U,
-/*0001*/ 0x00040801U,
-/*0002*/ 0x080b0801U,
-/*0003*/ 0xffffffffU,
-/*0004*/ 0xffffffffU,
-/*0005*/ 0x18010801U,
-/*0006*/ 0x00050802U,
-/*0007*/ 0x08050802U,
-/*0008*/ 0x10050802U,
-/*0009*/ 0x18050802U,
-/*000a*/ 0x00050803U,
-/*000b*/ 0x08050803U,
-/*000c*/ 0x10050803U,
-/*000d*/ 0x18050803U,
-/*000e*/ 0x00050804U,
-/*000f*/ 0x08040804U,
-/*0010*/ 0x10030804U,
-/*0011*/ 0x00180805U,
-/*0012*/ 0x18030805U,
-/*0013*/ 0x00180806U,
-/*0014*/ 0x18020806U,
-/*0015*/ 0x00010807U,
-/*0016*/ 0x08020807U,
-/*0017*/ 0x10010807U,
-/*0018*/ 0x18010807U,
-/*0019*/ 0x00020808U,
-/*001a*/ 0x08040808U,
-/*001b*/ 0x10040808U,
-/*001c*/ 0x18040808U,
-/*001d*/ 0x000a0809U,
-/*001e*/ 0x10040809U,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x18070809U,
-/*0022*/ 0xffffffffU,
-/*0023*/ 0xffffffffU,
-/*0024*/ 0xffffffffU,
-/*0025*/ 0xffffffffU,
-/*0026*/ 0xffffffffU,
-/*0027*/ 0xffffffffU,
-/*0028*/ 0x000a080aU,
-/*0029*/ 0x1005080aU,
-/*002a*/ 0x1801080aU,
-/*002b*/ 0x0001080bU,
-/*002c*/ 0x0802080bU,
-/*002d*/ 0x1009080bU,
-/*002e*/ 0x0009080cU,
-/*002f*/ 0x1002080cU,
-/*0030*/ 0x0020080dU,
-/*0031*/ 0xffffffffU,
-/*0032*/ 0x0001080eU,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x0020080fU,
-/*0038*/ 0x00200810U,
-/*0039*/ 0x00200811U,
-/*003a*/ 0x00200812U,
-/*003b*/ 0x00030813U,
-/*003c*/ 0x08010813U,
-/*003d*/ 0x10030813U,
-/*003e*/ 0x18030813U,
-/*003f*/ 0x00040814U,
-/*0040*/ 0x08040814U,
-/*0041*/ 0x10040814U,
-/*0042*/ 0x18040814U,
-/*0043*/ 0x00010815U,
-/*0044*/ 0x08010815U,
-/*0045*/ 0x10060815U,
-/*0046*/ 0x18040815U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x00060816U,
-/*0049*/ 0x08040816U,
-/*004a*/ 0x10060816U,
-/*004b*/ 0x18040816U,
-/*004c*/ 0x00020817U,
-/*004d*/ 0x08050817U,
-/*004e*/ 0x10080817U,
-/*004f*/ 0x00200818U,
-/*0050*/ 0x00060819U,
-/*0051*/ 0x08030819U,
-/*0052*/ 0x100b0819U,
-/*0053*/ 0x0004081aU,
-/*0054*/ 0x0804081aU,
-/*0055*/ 0x1004081aU,
-/*0056*/ 0xffffffffU,
-/*0057*/ 0x1801081aU,
-/*0058*/ 0x0009081bU,
-/*0059*/ 0x0020081cU,
-/*005a*/ 0x0020081dU,
-/*005b*/ 0x0020081eU,
-/*005c*/ 0x0020081fU,
-/*005d*/ 0x00100820U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010820U,
-/*0060*/ 0x18060820U,
-/*0061*/ 0x00080821U,
-/*0062*/ 0x00200822U,
-/*0063*/ 0xffffffffU,
-/*0064*/ 0x000a0823U,
-/*0065*/ 0x10060823U,
-/*0066*/ 0x18070823U,
-/*0067*/ 0x00080824U,
-/*0068*/ 0x08080824U,
-/*0069*/ 0x100a0824U,
-/*006a*/ 0x00070825U,
-/*006b*/ 0x08080825U,
-/*006c*/ 0x10080825U,
-/*006d*/ 0x18030825U,
-/*006e*/ 0x000a0826U,
-/*006f*/ 0x100a0826U,
-/*0070*/ 0x00110827U,
-/*0071*/ 0x00090828U,
-/*0072*/ 0x10090828U,
-/*0073*/ 0x00100829U,
-/*0074*/ 0x100e0829U,
-/*0075*/ 0x000e082aU,
-/*0076*/ 0x100c082aU,
-/*0077*/ 0x000a082bU,
-/*0078*/ 0x100a082bU,
-/*0079*/ 0x0002082cU,
-/*007a*/ 0x0020082dU,
-/*007b*/ 0x000b082eU,
-/*007c*/ 0x100b082eU,
-/*007d*/ 0x0020082fU,
-/*007e*/ 0x00120830U,
-/*007f*/ 0x00200831U,
-/*0080*/ 0x00200832U,
-/*0081*/ 0xffffffffU,
-/*0082*/ 0xffffffffU,
-/*0083*/ 0x00010833U,
-/*0084*/ 0x08010833U,
-/*0085*/ 0x10080833U,
-/*0086*/ 0x000c0834U,
-/*0087*/ 0x100c0834U,
-/*0088*/ 0x000c0835U,
-/*0089*/ 0x100c0835U,
-/*008a*/ 0x000c0836U,
-/*008b*/ 0x100c0836U,
-/*008c*/ 0x000c0837U,
-/*008d*/ 0x100c0837U,
-/*008e*/ 0x000c0838U,
-/*008f*/ 0x100c0838U,
-/*0090*/ 0x000c0839U,
-/*0091*/ 0x100b0839U,
-/*0092*/ 0xffffffffU,
-/*0093*/ 0xffffffffU,
-/*0094*/ 0x000b083aU,
-/*0095*/ 0x100b083aU,
-/*0096*/ 0x000b083bU,
-/*0097*/ 0x100b083bU,
-/*0098*/ 0x000b083cU,
-/*0099*/ 0x100b083cU,
-/*009a*/ 0x000b083dU,
-/*009b*/ 0x100b083dU,
-/*009c*/ 0x000b083eU,
-/*009d*/ 0x100a083eU,
-/*009e*/ 0xffffffffU,
-/*009f*/ 0x000a083fU,
-/*00a0*/ 0x100a083fU,
-/*00a1*/ 0x000a0840U,
-/*00a2*/ 0x100a0840U,
-/*00a3*/ 0x000a0841U,
-/*00a4*/ 0x100a0841U,
-/*00a5*/ 0x000a0842U,
-/*00a6*/ 0x100a0842U,
-/*00a7*/ 0x000a0843U,
-/*00a8*/ 0x100a0843U,
-/*00a9*/ 0x000a0844U,
-/*00aa*/ 0x100a0844U,
-/*00ab*/ 0x000a0845U,
-/*00ac*/ 0x100a0845U,
-/*00ad*/ 0x000a0846U,
-/*00ae*/ 0x100a0846U,
-/*00af*/ 0x000a0847U,
-/*00b0*/ 0x100a0847U,
-/*00b1*/ 0x000a0848U,
-/*00b2*/ 0x100a0848U,
-/*00b3*/ 0x000a0849U,
-/*00b4*/ 0x100a0849U,
-/*00b5*/ 0x000a084aU,
-/*00b6*/ 0x100a084aU,
-/*00b7*/ 0x000a084bU,
-/*00b8*/ 0x100a084bU,
-/*00b9*/ 0x000a084cU,
-/*00ba*/ 0x100a084cU,
-/*00bb*/ 0x0004084dU,
-/*00bc*/ 0x0803084dU,
-/*00bd*/ 0x100a084dU,
-/*00be*/ 0x000a084eU,
-/*00bf*/ 0x1001084eU,
-/*00c0*/ 0x000a084fU,
-/*00c1*/ 0x1004084fU,
-/*00c2*/ 0x000b0850U,
-/*00c3*/ 0x100a0850U,
-/*00c4*/ 0xffffffffU,
-/*00c5*/ 0x00080851U,
-/*00c6*/ 0x08080851U,
-/*00c7*/ 0x10080851U,
-/*00c8*/ 0x18080851U,
-/*00c9*/ 0x00080852U,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x08080852U,
-/*00cc*/ 0x10010852U,
-/*00cd*/ 0x18080852U,
-/*00ce*/ 0x00080853U,
-/*00cf*/ 0x08020853U,
-/*00d0*/ 0x10020853U,
-/*00d1*/ 0x18040853U,
-/*00d2*/ 0x00040854U,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x08040854U,
-/*00d5*/ 0x100a0854U,
-/*00d6*/ 0x00060855U,
-/*00d7*/ 0x08080855U,
-/*00d8*/ 0xffffffffU,
-/*00d9*/ 0x10040855U,
-/*00da*/ 0x18040855U,
-/*00db*/ 0x00050856U,
-/*00dc*/ 0x08040856U,
-/*00dd*/ 0x10050856U,
-/*00de*/ 0x000a0857U,
-/*00df*/ 0x100a0857U,
-/*00e0*/ 0x00080858U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040858U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050a00U,
-/*00e6*/ 0x08050a00U,
-/*00e7*/ 0x10050a00U,
-/*00e8*/ 0x18050a00U,
-/*00e9*/ 0x00050a01U,
-/*00ea*/ 0x08050a01U,
-/*00eb*/ 0x100b0a01U,
-/*00ec*/ 0x00010a02U,
-/*00ed*/ 0x08030a02U,
-/*00ee*/ 0x00200a03U,
-/*00ef*/ 0xffffffffU,
-/*00f0*/ 0x00030a04U,
-/*00f1*/ 0x080a0a04U,
-/*00f2*/ 0xffffffffU,
-/*00f3*/ 0xffffffffU,
-/*00f4*/ 0x18030a04U,
-/*00f5*/ 0x00030a05U,
-/*00f6*/ 0x08010a05U,
-/*00f7*/ 0x10010a05U,
-/*00f8*/ 0x18060a05U,
-/*00f9*/ 0xffffffffU,
-/*00fa*/ 0xffffffffU,
-/*00fb*/ 0xffffffffU,
-/*00fc*/ 0x00020a06U,
-/*00fd*/ 0x08030a06U,
-/*00fe*/ 0x10010a06U,
-/*00ff*/ 0x000f0a07U,
-/*0100*/ 0x00200a08U,
-/*0101*/ 0x00200a09U,
-/*0102*/ 0x000b0a0aU,
-/*0103*/ 0x100b0a0aU,
-/*0104*/ 0x000b0a0bU,
-/*0105*/ 0xffffffffU,
-/*0106*/ 0xffffffffU,
-/*0107*/ 0x00180a0cU,
-/*0108*/ 0x00180a0dU,
-/*0109*/ 0x00180a0eU,
-/*010a*/ 0x00180a0fU,
-/*010b*/ 0x18040a0fU,
-/*010c*/ 0x00020a10U,
-/*010d*/ 0x08020a10U,
-/*010e*/ 0x10040a10U,
-/*010f*/ 0x18040a10U,
-/*0110*/ 0x00010a11U,
-/*0111*/ 0x08010a11U,
-/*0112*/ 0x10010a11U,
-/*0113*/ 0x18030a11U,
-/*0114*/ 0x00200a12U,
-/*0115*/ 0x00200a13U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140a14U,
-/*0118*/ 0x00140a15U,
-/*0119*/ 0x00140a16U,
-/*011a*/ 0x00140a17U,
-/*011b*/ 0x00140a18U,
-/*011c*/ 0x00140a19U,
-/*011d*/ 0x00140a1aU,
-/*011e*/ 0x00140a1bU,
-/*011f*/ 0x001e0a1cU,
-/*0120*/ 0x000a0a1dU,
-/*0121*/ 0x10060a1dU,
-/*0122*/ 0x18060a1dU,
-/*0123*/ 0x00060a1eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0x08060a1eU,
-/*0126*/ 0x00080a1fU,
-/*0127*/ 0x080b0a1fU,
-/*0128*/ 0x000b0a20U,
-/*0129*/ 0x100b0a20U,
-/*012a*/ 0x000b0a21U,
-/*012b*/ 0x100b0a21U,
-/*012c*/ 0x000b0a22U,
-/*012d*/ 0x10040a22U,
-/*012e*/ 0x000a0a23U,
-/*012f*/ 0x10060a23U,
-/*0130*/ 0x18080a23U,
-/*0131*/ 0xffffffffU,
-/*0132*/ 0x00040a24U,
-/*0133*/ 0xffffffffU,
-/*0134*/ 0xffffffffU,
-/*0135*/ 0x00010b80U,
-/*0136*/ 0x08020b80U,
-/*0137*/ 0x10050b80U,
-/*0138*/ 0x18050b80U,
-/*0139*/ 0x00050b81U,
-/*013a*/ 0x08050b81U,
-/*013b*/ 0x100b0b81U,
-/*013c*/ 0x00050b82U,
-/*013d*/ 0x08010b82U,
-/*013e*/ 0x10010b82U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x18010b82U,
-/*0141*/ 0x00010b83U,
-/*0142*/ 0x08040b83U,
-/*0143*/ 0x100b0b83U,
-/*0144*/ 0x000b0b84U,
-/*0145*/ 0xffffffffU,
-/*0146*/ 0x10040b84U,
-/*0147*/ 0x000b0b85U,
-/*0148*/ 0x10040b85U,
-/*0149*/ 0x18010b85U,
-/*014a*/ 0x00010b86U,
-/*014b*/ 0x08010b86U,
-/*014c*/ 0x00200b87U,
-/*014d*/ 0x00200b88U,
-/*014e*/ 0x00080b89U,
-/*014f*/ 0x080a0b89U,
-/*0150*/ 0x18050b89U,
-/*0151*/ 0x000a0b8aU,
-/*0152*/ 0x10030b8aU,
-/*0153*/ 0x18030b8aU,
-/*0154*/ 0x00010b8bU,
-/*0155*/ 0x08020b8bU,
-/*0156*/ 0x10010b8bU,
-/*0157*/ 0x18010b8bU,
-/*0158*/ 0x00010b8cU,
-/*0159*/ 0x08030b8cU,
-/*015a*/ 0xffffffffU,
-/*015b*/ 0x10040b8cU,
-/*015c*/ 0x18040b8cU,
-/*015d*/ 0x00040b8dU,
-/*015e*/ 0x08040b8dU,
-/*015f*/ 0xffffffffU,
-/*0160*/ 0xffffffffU,
-/*0161*/ 0xffffffffU,
-/*0162*/ 0xffffffffU,
-/*0163*/ 0xffffffffU,
-/*0164*/ 0xffffffffU,
-/*0165*/ 0xffffffffU,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0xffffffffU,
-/*0168*/ 0x000d0b8eU,
-/*0169*/ 0x100d0b8eU,
-/*016a*/ 0x000d0b8fU,
-/*016b*/ 0x00050b90U,
-/*016c*/ 0x00010b91U,
-/*016d*/ 0x080e0b91U,
-/*016e*/ 0x000e0b92U,
-/*016f*/ 0x100e0b92U,
-/*0170*/ 0x000e0b93U,
-/*0171*/ 0x100e0b93U,
-/*0172*/ 0x00040b94U,
-/*0173*/ 0x08040b94U,
-/*0174*/ 0x10040b94U,
-/*0175*/ 0x18040b94U,
-/*0176*/ 0x00040b95U,
-/*0177*/ 0x080b0b95U,
-/*0178*/ 0x000b0b96U,
-/*0179*/ 0x100b0b96U,
-/*017a*/ 0x000b0b97U,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d0b98U,
-/*0180*/ 0x100d0b98U,
-/*0181*/ 0x000d0b99U,
-/*0182*/ 0x10100b99U,
-/*0183*/ 0x10080b8dU,
-/*0184*/ 0x18080b8dU,
-/*0185*/ 0x00100b9aU,
-/*0186*/ 0x10100b9aU,
-/*0187*/ 0x00100b9bU,
-/*0188*/ 0x10100b9bU,
-/*0189*/ 0x00100b9cU,
-/*018a*/ 0x10030b9cU,
-/*018b*/ 0x18040b9cU,
-/*018c*/ 0x00010b9dU,
-/*018d*/ 0x08040b9dU,
-/*018e*/ 0xffffffffU,
-/*018f*/ 0xffffffffU,
-/*0190*/ 0x10010b9dU,
-/*0191*/ 0x00140b9eU,
-/*0192*/ 0x000a0b9fU,
-/*0193*/ 0x100c0b9fU,
-/*0194*/ 0x00120ba0U,
-/*0195*/ 0x00140ba1U,
-/*0196*/ 0x00120ba2U,
-/*0197*/ 0x00110ba3U,
-/*0198*/ 0x00110ba4U,
-/*0199*/ 0x00120ba5U,
-/*019a*/ 0x00120ba6U,
-/*019b*/ 0x00120ba7U,
-/*019c*/ 0x00120ba8U,
-/*019d*/ 0x00120ba9U,
-/*019e*/ 0x00120baaU,
-/*019f*/ 0x00120babU,
-/*01a0*/ 0x00120bacU,
-/*01a1*/ 0xffffffffU,
-/*01a2*/ 0xffffffffU,
-/*01a3*/ 0x00190badU,
-/*01a4*/ 0x00190baeU,
-/*01a5*/ 0x00200bafU,
-/*01a6*/ 0x00170bb0U,
-/*01a7*/ 0x18080bb0U,
-/*01a8*/ 0x00010bb1U,
-/*01a9*/ 0x08010bb1U,
-/*01aa*/ 0x00200bb2U,
-/*01ab*/ 0x00080bb3U,
-/*01ac*/ 0xffffffffU,
-/*01ad*/ 0x08030bb3U,
-/*01ae*/ 0x00180bb4U,
-/*01af*/ 0x00180bb5U,
-/*01b0*/ 0xffffffffU,
-/*01b1*/ 0xffffffffU,
-/*01b2*/ 0xffffffffU,
-/*01b3*/ 0xffffffffU,
-/*01b4*/ 0xffffffffU,
-/*01b5*/ 0xffffffffU,
-/*01b6*/ 0xffffffffU,
-/*01b7*/ 0xffffffffU,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x00100bb6U,
-/*01c0*/ 0x10010bb6U,
-/*01c1*/ 0x18010bb6U,
-/*01c2*/ 0x00050bb7U,
-/*01c3*/ 0x00200bb8U,
-/*01c4*/ 0x00090bb9U,
-/*01c5*/ 0xffffffffU,
-/*01c6*/ 0xffffffffU,
-/*01c7*/ 0x00200bbaU,
-/*01c8*/ 0x00040bbbU,
-/*01c9*/ 0x08100bbbU,
-/*01ca*/ 0x18060bbbU,
-/*01cb*/ 0x00100bbcU,
-/*01cc*/ 0xffffffffU,
-/*01cd*/ 0x10080bbcU,
-/*01ce*/ 0xffffffffU,
-/*01cf*/ 0xffffffffU,
-/*01d0*/ 0xffffffffU,
-/*01d1*/ 0x18030bbcU,
-/*01d2*/ 0x00020bbdU,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200bbeU,
-/*01d5*/ 0x000b0bbfU,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0xffffffffU,
-/*01d8*/ 0xffffffffU,
-/*01d9*/ 0x10020bbfU,
-/*01da*/ 0xffffffffU,
-/*01db*/ 0xffffffffU,
-/*01dc*/ 0xffffffffU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0xffffffffU,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x10100201U,
-/*01e6*/ 0xffffffffU,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200202U,
-/*01f0*/ 0x00100203U,
-/*01f1*/ 0x00200204U,
-/*01f2*/ 0x00100205U,
-/*01f3*/ 0x00200206U,
-/*01f4*/ 0x00100207U,
-/*01f5*/ 0x10100207U,
-/*01f6*/ 0x00200208U,
-/*01f7*/ 0x00200209U,
-/*01f8*/ 0x0020020aU,
-/*01f9*/ 0x0020020bU,
-/*01fa*/ 0x0010020cU,
-/*01fb*/ 0x0020020dU,
-/*01fc*/ 0x0020020eU,
-/*01fd*/ 0x0020020fU,
-/*01fe*/ 0x00200210U,
-/*01ff*/ 0x00100211U,
-/*0200*/ 0x00200212U,
-/*0201*/ 0x00200213U,
-/*0202*/ 0x00200214U,
-/*0203*/ 0x00200215U,
-/*0204*/ 0x00090216U,
-/*0205*/ 0x10010216U,
-/*0206*/ 0x00200217U,
-/*0207*/ 0x00050218U,
-/*0208*/ 0x08010218U,
-/*0209*/ 0x10080218U,
-/*020a*/ 0x18080218U,
-/*020b*/ 0x001e0219U,
-/*020c*/ 0x001e021aU,
-/*020d*/ 0x001e021bU,
-/*020e*/ 0x001e021cU,
-/*020f*/ 0x001e021dU,
-/*0210*/ 0x001e021eU,
-/*0211*/ 0x001e021fU,
-/*0212*/ 0x001e0220U,
-/*0213*/ 0x001e0221U,
-/*0214*/ 0x001e0222U,
-/*0215*/ 0x001e0223U,
-/*0216*/ 0x001e0224U,
-/*0217*/ 0x001e0225U,
-/*0218*/ 0x001e0226U,
-/*0219*/ 0x001e0227U,
-/*021a*/ 0x001e0228U,
-/*021b*/ 0x00010229U,
-/*021c*/ 0x08010229U,
-/*021d*/ 0x10010229U,
-/*021e*/ 0x18040229U,
-/*021f*/ 0x0008022aU,
-/*0220*/ 0x0808022aU,
-/*0221*/ 0x1008022aU,
-/*0222*/ 0x1804022aU,
-/*0223*/ 0x0005022bU,
-/*0224*/ 0x0806022bU,
-/*0225*/ 0x1007022bU,
-/*0226*/ 0x1805022bU,
-/*0227*/ 0x0006022cU,
-/*0228*/ 0x0807022cU,
-/*0229*/ 0x1005022cU,
-/*022a*/ 0x1806022cU,
-/*022b*/ 0x0007022dU,
-/*022c*/ 0x0802022dU,
-/*022d*/ 0x1001022dU,
-/*022e*/ 0xffffffffU,
-/*022f*/ 0x000a022eU,
-/*0230*/ 0x1010022eU,
-/*0231*/ 0x000a022fU,
-/*0232*/ 0x1010022fU,
-/*0233*/ 0x000a0230U,
-/*0234*/ 0x10100230U,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0x00100231U,
-/*0237*/ 0xffffffffU,
-/*0238*/ 0xffffffffU,
-/*0239*/ 0x10010231U,
-/*023a*/ 0x18010231U,
-/*023b*/ 0x00010232U,
-/*023c*/ 0x08010232U,
-/*023d*/ 0x10010232U,
-/*023e*/ 0x18010232U,
-/*023f*/ 0x00020233U,
-/*0240*/ 0x08020233U,
-/*0241*/ 0x10020233U,
-/*0242*/ 0x18020233U,
-/*0243*/ 0x00020234U,
-/*0244*/ 0x08030234U,
-/*0245*/ 0x10010234U,
-/*0246*/ 0x18010234U,
-/*0247*/ 0x00010235U,
-/*0248*/ 0x08010235U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x10020235U,
-/*024b*/ 0x18010235U,
-/*024c*/ 0x00010236U,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x08020236U,
-/*024f*/ 0x10010236U,
-/*0250*/ 0x18010236U,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x00020237U,
-/*0253*/ 0x08010237U,
-/*0254*/ 0x10010237U,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x18020237U,
-/*0257*/ 0x00070238U,
-/*0258*/ 0x08010238U,
-/*0259*/ 0x10010238U,
-/*025a*/ 0x18010238U,
-/*025b*/ 0x00010239U,
-/*025c*/ 0x08010239U,
-/*025d*/ 0x10010239U,
-/*025e*/ 0xffffffffU,
-/*025f*/ 0x18010239U,
-/*0260*/ 0x0004023aU,
-/*0261*/ 0x0804023aU,
-/*0262*/ 0x1004023aU,
-/*0263*/ 0x1801023aU,
-/*0264*/ 0x0002023bU,
-/*0265*/ 0x0806023bU,
-/*0266*/ 0x1006023bU,
-/*0267*/ 0xffffffffU,
-/*0268*/ 0xffffffffU,
-/*0269*/ 0xffffffffU,
-/*026a*/ 0x1802023bU,
-/*026b*/ 0x0010023cU,
-/*026c*/ 0x1001023cU,
-/*026d*/ 0x1801023cU,
-/*026e*/ 0xffffffffU,
-/*026f*/ 0x0004023dU,
-/*0270*/ 0x0801023dU,
-/*0271*/ 0x1004023dU,
-/*0272*/ 0x1802023dU,
-/*0273*/ 0x0008023eU,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x080a023eU,
-/*0278*/ 0x0020023fU,
-/*0279*/ 0x00200240U,
-/*027a*/ 0x00050241U,
-/*027b*/ 0x08010241U,
-/*027c*/ 0x10050241U,
-/*027d*/ 0x18080241U,
-/*027e*/ 0x00010242U,
-/*027f*/ 0x08080242U,
-/*0280*/ 0x10010242U,
-/*0281*/ 0x18080242U,
-/*0282*/ 0x00010243U,
-/*0283*/ 0x08040243U,
-/*0284*/ 0x10040243U,
-/*0285*/ 0x18040243U,
-/*0286*/ 0x00040244U,
-/*0287*/ 0x08040244U,
-/*0288*/ 0x10040244U,
-/*0289*/ 0x18040244U,
-/*028a*/ 0x00040245U,
-/*028b*/ 0x08040245U,
-/*028c*/ 0x10040245U,
-/*028d*/ 0x18010245U,
-/*028e*/ 0x00040246U,
-/*028f*/ 0x08040246U,
-/*0290*/ 0x10040246U,
-/*0291*/ 0x18040246U,
-/*0292*/ 0x00040247U,
-/*0293*/ 0x08040247U,
-/*0294*/ 0x10060247U,
-/*0295*/ 0x18060247U,
-/*0296*/ 0x00060248U,
-/*0297*/ 0x08060248U,
-/*0298*/ 0x10060248U,
-/*0299*/ 0x18060248U,
-/*029a*/ 0x00040249U,
-/*029b*/ 0x08010249U,
-/*029c*/ 0x10010249U,
-/*029d*/ 0x18020249U,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x0004024aU,
-/*02a7*/ 0x0804024aU,
-/*02a8*/ 0x1001024aU,
-/*02a9*/ 0x1801024aU,
-/*02aa*/ 0xffffffffU,
-/*02ab*/ 0x0001024bU,
-/*02ac*/ 0x0801024bU,
-/*02ad*/ 0xffffffffU,
-/*02ae*/ 0x1001024bU,
-/*02af*/ 0x1801024bU,
-/*02b0*/ 0x0001024cU,
-/*02b1*/ 0x0804024cU,
-/*02b2*/ 0x1004024cU,
-/*02b3*/ 0x000a024dU,
-/*02b4*/ 0x0020024eU,
-/*02b5*/ 0x0004024fU,
-/*02b6*/ 0x0808024fU,
-/*02b7*/ 0xffffffffU,
-/*02b8*/ 0xffffffffU,
-/*02b9*/ 0xffffffffU,
-/*02ba*/ 0xffffffffU,
-/*02bb*/ 0xffffffffU,
-/*02bc*/ 0xffffffffU,
-/*02bd*/ 0x1002024fU,
-/*02be*/ 0x1802024fU,
-/*02bf*/ 0x00200250U,
-/*02c0*/ 0x00020251U,
-/*02c1*/ 0x08100251U,
-/*02c2*/ 0x00100252U,
-/*02c3*/ 0x10040252U,
-/*02c4*/ 0x18040252U,
-/*02c5*/ 0x00050253U,
-/*02c6*/ 0x08050253U,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x10010253U,
-/*02cc*/ 0x18010253U,
-/*02cd*/ 0x00080254U,
-/*02ce*/ 0x08080254U,
-/*02cf*/ 0x10080254U,
-/*02d0*/ 0x18080254U,
-/*02d1*/ 0x00080255U,
-/*02d2*/ 0x08080255U,
-/*02d3*/ 0x10080255U,
-/*02d4*/ 0x18080255U,
-/*02d5*/ 0x00080256U,
-/*02d6*/ 0x08080256U,
-/*02d7*/ 0x10080256U,
-/*02d8*/ 0xffffffffU,
-/*02d9*/ 0xffffffffU,
-/*02da*/ 0xffffffffU,
-/*02db*/ 0xffffffffU,
-/*02dc*/ 0xffffffffU,
-/*02dd*/ 0xffffffffU,
-/*02de*/ 0x18030256U,
-/*02df*/ 0x00010257U,
-/*02e0*/ 0x08020257U,
-/*02e1*/ 0x10010257U,
-/*02e2*/ 0x18040257U,
-/*02e3*/ 0x00020258U,
-/*02e4*/ 0x08010258U,
-/*02e5*/ 0x10010258U,
-/*02e6*/ 0xffffffffU,
-/*02e7*/ 0x18010258U,
-/*02e8*/ 0x00040259U,
-/*02e9*/ 0x08080259U,
-/*02ea*/ 0x100a0259U,
-/*02eb*/ 0x000a025aU,
-/*02ec*/ 0x100a025aU,
-/*02ed*/ 0x000a025bU,
-/*02ee*/ 0x100a025bU,
-/*02ef*/ 0x000a025cU,
-/*02f0*/ 0x0020025dU,
-/*02f1*/ 0x0020025eU,
-/*02f2*/ 0x0001025fU,
-/*02f3*/ 0xffffffffU,
-/*02f4*/ 0xffffffffU,
-/*02f5*/ 0xffffffffU,
-/*02f6*/ 0x0802025fU,
-/*02f7*/ 0x1002025fU,
-/*02f8*/ 0x00100260U,
-/*02f9*/ 0x10050260U,
-/*02fa*/ 0x18060260U,
-/*02fb*/ 0x00050261U,
-/*02fc*/ 0x08050261U,
-/*02fd*/ 0x100e0261U,
-/*02fe*/ 0x00050262U,
-/*02ff*/ 0x080e0262U,
-/*0300*/ 0x18050262U,
-/*0301*/ 0x000e0263U,
-/*0302*/ 0x10050263U,
-/*0303*/ 0x18010263U,
-/*0304*/ 0x00050264U,
-/*0305*/ 0x08050264U,
-/*0306*/ 0x100a0264U,
-/*0307*/ 0x000a0265U,
-/*0308*/ 0x10050265U,
-/*0309*/ 0x18050265U,
-/*030a*/ 0x000a0266U,
-/*030b*/ 0x100a0266U,
-/*030c*/ 0x00050267U,
-/*030d*/ 0x08050267U,
-/*030e*/ 0x100a0267U,
-/*030f*/ 0x000a0268U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070268U,
-/*0317*/ 0x18070268U,
-/*0318*/ 0x00040269U,
-/*0319*/ 0x08040269U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040269U,
-/*031e*/ 0x18080269U,
-/*031f*/ 0x0008026aU,
-/*0320*/ 0x0804026aU,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x1004026aU,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x1804026aU,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x0004026bU,
-/*032d*/ 0x0805026bU,
-/*032e*/ 0x1007026bU,
-/*032f*/ 0x1808026bU,
-/*0330*/ 0x0010026cU,
-/*0331*/ 0x1008026cU,
-/*0332*/ 0x0010026dU,
-/*0333*/ 0x1008026dU,
-/*0334*/ 0x0010026eU,
-/*0335*/ 0x1008026eU,
-/*0336*/ 0x1808026eU,
-/*0337*/ 0x0001026fU,
-/*0338*/ 0x0801026fU,
-/*0339*/ 0x1006026fU,
-/*033a*/ 0x1806026fU,
-/*033b*/ 0x00060270U,
-/*033c*/ 0xffffffffU,
-/*033d*/ 0x08010270U,
-/*033e*/ 0x10030270U,
-/*033f*/ 0xffffffffU,
-/*0340*/ 0xffffffffU,
-/*0341*/ 0xffffffffU,
-/*0342*/ 0x000a0271U,
-/*0343*/ 0x100a0271U,
-/*0344*/ 0x00040272U,
-/*0345*/ 0x08010272U,
-/*0346*/ 0x10040272U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070272U,
-/*034e*/ 0x00070273U,
-/*034f*/ 0x08050273U,
-/*0350*/ 0x10050273U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040273U,
-/*0355*/ 0x00010274U,
-/*0356*/ 0x08010274U,
-/*0357*/ 0x10020274U,
-/*0358*/ 0x18080274U,
-/*0359*/ 0x00200275U,
-/*035a*/ 0x00200276U,
-/*035b*/ 0x00100277U,
-/*035c*/ 0xffffffffU,
-/*035d*/ 0xffffffffU,
-/*035e*/ 0xffffffffU,
-/*035f*/ 0x10020277U,
-/*0360*/ 0x18010277U,
-/*0361*/ 0xffffffffU,
-/*0362*/ 0x00020278U,
-/*0363*/ 0x08100278U,
-/*0364*/ 0x00100279U,
-/*0365*/ 0x10100279U,
-/*0366*/ 0x0008027aU,
-/*0367*/ 0x0808027aU,
-/*0368*/ 0x1008027aU,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x0010027bU,
-/*036b*/ 0x1010027bU,
-/*036c*/ 0x0010027cU,
-/*036d*/ 0x1008027cU,
-/*036e*/ 0x1808027cU,
-/*036f*/ 0x0008027dU,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x0810027dU,
-/*0372*/ 0x0010027eU,
-/*0373*/ 0x1010027eU,
-/*0374*/ 0x0008027fU,
-/*0375*/ 0x0808027fU,
-/*0376*/ 0x1008027fU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1808027fU,
-/*0379*/ 0x00100280U,
-/*037a*/ 0x10100280U,
-/*037b*/ 0x00100281U,
-/*037c*/ 0x10080281U,
-/*037d*/ 0x18080281U,
-/*037e*/ 0x00080282U,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x08100282U,
-/*0381*/ 0x00100283U,
-/*0382*/ 0x10100283U,
-/*0383*/ 0x00080284U,
-/*0384*/ 0x08080284U,
-/*0385*/ 0x10080284U,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x00100285U,
-/*0388*/ 0x10100285U,
-/*0389*/ 0x00100286U,
-/*038a*/ 0x10080286U,
-/*038b*/ 0x18080286U,
-/*038c*/ 0x00080287U,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x08080287U,
-/*038f*/ 0x10100287U,
-/*0390*/ 0x00100288U,
-/*0391*/ 0x10100288U,
-/*0392*/ 0x00080289U,
-/*0393*/ 0x08080289U,
-/*0394*/ 0x10080289U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x0010028aU,
-/*0397*/ 0x1010028aU,
-/*0398*/ 0x0010028bU,
-/*0399*/ 0x1008028bU,
-/*039a*/ 0x1808028bU,
-/*039b*/ 0x0008028cU,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x0810028cU,
-/*039e*/ 0x0010028dU,
-/*039f*/ 0x1010028dU,
-/*03a0*/ 0x0008028eU,
-/*03a1*/ 0x0808028eU,
-/*03a2*/ 0x1008028eU,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x1808028eU,
-/*03a5*/ 0x0010028fU,
-/*03a6*/ 0x1010028fU,
-/*03a7*/ 0x00100290U,
-/*03a8*/ 0x10080290U,
-/*03a9*/ 0x18080290U,
-/*03aa*/ 0x00080291U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x08100291U,
-/*03ad*/ 0x00100292U,
-/*03ae*/ 0x10100292U,
-/*03af*/ 0x00080293U,
-/*03b0*/ 0x08080293U,
-/*03b1*/ 0x10080293U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x00100294U,
-/*03b4*/ 0x10100294U,
-/*03b5*/ 0x00100295U,
-/*03b6*/ 0x10080295U,
-/*03b7*/ 0x18080295U,
-/*03b8*/ 0x00080296U,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x08080296U,
-/*03bb*/ 0x10020296U,
-/*03bc*/ 0x18030296U,
-/*03bd*/ 0x000a0297U,
-/*03be*/ 0x100a0297U,
-/*03bf*/ 0x000a0298U,
-/*03c0*/ 0x10050298U,
-/*03c1*/ 0x18040298U,
-/*03c2*/ 0x00080299U,
-/*03c3*/ 0x08080299U,
-/*03c4*/ 0x10060299U,
-/*03c5*/ 0x18060299U,
-/*03c6*/ 0x0011029aU,
-/*03c7*/ 0x1808029aU,
-/*03c8*/ 0x0004029bU,
-/*03c9*/ 0x0806029bU,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x1006029bU,
-/*03cc*/ 0x1808029bU,
-/*03cd*/ 0x0008029cU,
-/*03ce*/ 0x0804029cU,
-/*03cf*/ 0x1008029cU,
-/*03d0*/ 0x1808029cU,
-/*03d1*/ 0x0006029dU,
-/*03d2*/ 0x0806029dU,
-/*03d3*/ 0x0011029eU,
-/*03d4*/ 0x1808029eU,
-/*03d5*/ 0x0004029fU,
-/*03d6*/ 0x0806029fU,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x1006029fU,
-/*03d9*/ 0x1808029fU,
-/*03da*/ 0x000802a0U,
-/*03db*/ 0x080402a0U,
-/*03dc*/ 0x100802a0U,
-/*03dd*/ 0x180802a0U,
-/*03de*/ 0x000602a1U,
-/*03df*/ 0x080602a1U,
-/*03e0*/ 0x001102a2U,
-/*03e1*/ 0x180802a2U,
-/*03e2*/ 0x000402a3U,
-/*03e3*/ 0x080602a3U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x100602a3U,
-/*03e6*/ 0x180802a3U,
-/*03e7*/ 0x000802a4U,
-/*03e8*/ 0x080402a4U,
-/*03e9*/ 0x100402a4U,
-/*03ea*/ 0x180402a4U,
-/*03eb*/ 0x000402a5U,
-/*03ec*/ 0x080402a5U,
-/*03ed*/ 0x100402a5U,
-/*03ee*/ 0x180402a5U,
-/*03ef*/ 0x000402a6U,
-/*03f0*/ 0x080402a6U,
-/*03f1*/ 0x100402a6U,
-/*03f2*/ 0x180402a6U,
-/*03f3*/ 0x000402a7U,
-/*03f4*/ 0x080402a7U,
-/*03f5*/ 0x100402a7U,
-/*03f6*/ 0x180402a7U,
-/*03f7*/ 0x000402a8U,
-/*03f8*/ 0x080402a8U,
-/*03f9*/ 0x100402a8U,
-/*03fa*/ 0x180402a8U,
-/*03fb*/ 0x000402a9U,
-/*03fc*/ 0x081202a9U,
-/*03fd*/ 0x001102aaU,
-/*03fe*/ 0x001202abU,
-/*03ff*/ 0x002002acU,
-/*0400*/ 0x002002adU,
-/*0401*/ 0x002002aeU,
-/*0402*/ 0x002002afU,
-/*0403*/ 0x002002b0U,
-/*0404*/ 0x002002b1U,
-/*0405*/ 0x002002b2U,
-/*0406*/ 0x002002b3U,
-/*0407*/ 0x002002b4U,
-/*0408*/ 0x000302b5U,
-/*0409*/ 0x080502b5U,
-/*040a*/ 0x100502b5U,
-/*040b*/ 0x180102b5U,
-/*040c*/ 0x000502b6U,
-/*040d*/ 0x080502b6U,
-/*040e*/ 0x100502b6U,
-/*040f*/ 0x180502b6U,
-/*0410*/ 0x000502b7U,
-/*0411*/ 0x080502b7U,
-/*0412*/ 0x100502b7U,
-/*0413*/ 0x180502b7U,
-/*0414*/ 0x000502b8U,
-/*0415*/ 0x080502b8U,
-/*0416*/ 0x100502b8U,
-/*0417*/ 0x180502b8U,
-/*0418*/ 0x000502b9U,
-/*0419*/ 0x080502b9U,
-/*041a*/ 0x100502b9U,
-/*041b*/ 0x180502b9U,
-/*041c*/ 0x000502baU,
-/*041d*/ 0x080502baU,
-/*041e*/ 0x100502baU,
-/*041f*/ 0x180502baU,
-/*0420*/ 0x000502bbU,
-/*0421*/ 0x080502bbU,
-/*0422*/ 0x100102bbU,
-/*0423*/ 0x180202bbU,
-/*0424*/ 0x000202bcU,
-/*0425*/ 0x080202bcU,
-/*0426*/ 0x100202bcU,
-/*0427*/ 0x180102bcU,
-/*0428*/ 0x000402bdU,
-/*0429*/ 0x081002bdU,
-/*042a*/ 0x002002beU,
-/*042b*/ 0x001002bfU,
-/*042c*/ 0x002002c0U,
-/*042d*/ 0x001002c1U,
-/*042e*/ 0x002002c2U,
-/*042f*/ 0x000702c3U,
-/*0430*/ 0x080102c3U,
-/*0431*/ 0x100202c3U,
-/*0432*/ 0x180602c3U,
-/*0433*/ 0x000102c4U,
-/*0434*/ 0x080102c4U,
-/*0435*/ 0x002002c5U,
-/*0436*/ 0x000302c6U,
-/*0437*/ 0x002002c7U,
-/*0438*/ 0x002002c8U,
-/*0439*/ 0xffffffffU,
-/*043a*/ 0xffffffffU,
-/*043b*/ 0xffffffffU,
-/*043c*/ 0xffffffffU,
-/*043d*/ 0xffffffffU,
-/*043e*/ 0xffffffffU,
-/*043f*/ 0xffffffffU,
-/*0440*/ 0xffffffffU,
-/*0441*/ 0xffffffffU,
-/*0442*/ 0xffffffffU,
-/*0443*/ 0xffffffffU,
-/*0444*/ 0xffffffffU,
-/*0445*/ 0xffffffffU,
-/*0446*/ 0xffffffffU,
-/*0447*/ 0xffffffffU,
-/*0448*/ 0xffffffffU,
-/*0449*/ 0xffffffffU,
-/*044a*/ 0xffffffffU,
-/*044b*/ 0xffffffffU,
-/*044c*/ 0xffffffffU,
-/*044d*/ 0xffffffffU,
-/*044e*/ 0xffffffffU,
-/*044f*/ 0xffffffffU,
-/*0450*/ 0xffffffffU,
-/*0451*/ 0xffffffffU,
-/*0452*/ 0xffffffffU,
-/*0453*/ 0xffffffffU,
-/*0454*/ 0xffffffffU,
-/*0455*/ 0xffffffffU,
-/*0456*/ 0xffffffffU,
-/*0457*/ 0xffffffffU,
-/*0458*/ 0xffffffffU,
-/*0459*/ 0xffffffffU,
-/*045a*/ 0xffffffffU,
-/*045b*/ 0xffffffffU,
-/*045c*/ 0xffffffffU,
-/*045d*/ 0xffffffffU,
-/*045e*/ 0xffffffffU,
-/*045f*/ 0x000402c9U,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0xffffffffU,
-/*0465*/ 0xffffffffU,
-/*0466*/ 0xffffffffU,
-/*0467*/ 0xffffffffU,
-/*0468*/ 0xffffffffU,
-/*0469*/ 0xffffffffU,
-/*046a*/ 0xffffffffU,
-/*046b*/ 0xffffffffU,
-/*046c*/ 0xffffffffU,
-/*046d*/ 0xffffffffU,
-/*046e*/ 0xffffffffU,
-/*046f*/ 0xffffffffU,
-/*0470*/ 0xffffffffU,
-/*0471*/ 0xffffffffU,
-/*0472*/ 0xffffffffU,
-/*0473*/ 0xffffffffU,
-/*0474*/ 0xffffffffU,
-/*0475*/ 0xffffffffU,
-/*0476*/ 0xffffffffU,
-/*0477*/ 0xffffffffU,
-/*0478*/ 0xffffffffU,
-/*0479*/ 0xffffffffU,
-/*047a*/ 0xffffffffU,
-/*047b*/ 0xffffffffU,
-/*047c*/ 0xffffffffU,
-/*047d*/ 0xffffffffU,
-/*047e*/ 0xffffffffU,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
-	 },
-	{
-/*0000*/ 0x00200400U,
-/*0001*/ 0x00040401U,
-/*0002*/ 0x080b0401U,
-/*0003*/ 0x000a0402U,
-/*0004*/ 0x10020402U,
-/*0005*/ 0x18010402U,
-/*0006*/ 0x00050403U,
-/*0007*/ 0x08050403U,
-/*0008*/ 0x10050403U,
-/*0009*/ 0x18050403U,
-/*000a*/ 0x00050404U,
-/*000b*/ 0x08050404U,
-/*000c*/ 0x10050404U,
-/*000d*/ 0x18050404U,
-/*000e*/ 0x00050405U,
-/*000f*/ 0x08040405U,
-/*0010*/ 0x10030405U,
-/*0011*/ 0x00180406U,
-/*0012*/ 0x18030406U,
-/*0013*/ 0x00180407U,
-/*0014*/ 0x18020407U,
-/*0015*/ 0x00010408U,
-/*0016*/ 0x08020408U,
-/*0017*/ 0x10010408U,
-/*0018*/ 0x18010408U,
-/*0019*/ 0x00020409U,
-/*001a*/ 0x08040409U,
-/*001b*/ 0x10040409U,
-/*001c*/ 0x18040409U,
-/*001d*/ 0xffffffffU,
-/*001e*/ 0x0004040aU,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x0809040aU,
-/*0022*/ 0x1801040aU,
-/*0023*/ 0x0020040bU,
-/*0024*/ 0x001c040cU,
-/*0025*/ 0x0001040dU,
-/*0026*/ 0x0807040dU,
-/*0027*/ 0x1009040dU,
-/*0028*/ 0x000a040eU,
-/*0029*/ 0x1005040eU,
-/*002a*/ 0x1801040eU,
-/*002b*/ 0x1001040fU,
-/*002c*/ 0x1802040fU,
-/*002d*/ 0x0009040fU,
-/*002e*/ 0x00090410U,
-/*002f*/ 0x10020410U,
-/*0030*/ 0x00200411U,
-/*0031*/ 0x00010412U,
-/*0032*/ 0x08020412U,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x00200413U,
-/*0038*/ 0x00200414U,
-/*0039*/ 0x00200415U,
-/*003a*/ 0x00200416U,
-/*003b*/ 0x00030417U,
-/*003c*/ 0x08010417U,
-/*003d*/ 0x10040417U,
-/*003e*/ 0x18030417U,
-/*003f*/ 0x00040418U,
-/*0040*/ 0x08040418U,
-/*0041*/ 0x10040418U,
-/*0042*/ 0x18040418U,
-/*0043*/ 0x00010419U,
-/*0044*/ 0x08010419U,
-/*0045*/ 0x10060419U,
-/*0046*/ 0x18040419U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x0006041aU,
-/*0049*/ 0x0804041aU,
-/*004a*/ 0x1006041aU,
-/*004b*/ 0x1804041aU,
-/*004c*/ 0x0002041bU,
-/*004d*/ 0x0805041bU,
-/*004e*/ 0x1008041bU,
-/*004f*/ 0xffffffffU,
-/*0050*/ 0x1806041bU,
-/*0051*/ 0x0003041cU,
-/*0052*/ 0x080b041cU,
-/*0053*/ 0x1804041cU,
-/*0054*/ 0x0004041dU,
-/*0055*/ 0x0804041dU,
-/*0056*/ 0x1001041dU,
-/*0057*/ 0xffffffffU,
-/*0058*/ 0x0009041eU,
-/*0059*/ 0x0020041fU,
-/*005a*/ 0x00200420U,
-/*005b*/ 0x00200421U,
-/*005c*/ 0x00200422U,
-/*005d*/ 0x00100423U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010423U,
-/*0060*/ 0x18060423U,
-/*0061*/ 0x00080424U,
-/*0062*/ 0x00200425U,
-/*0063*/ 0x00100426U,
-/*0064*/ 0x100a0426U,
-/*0065*/ 0x00060427U,
-/*0066*/ 0x08070427U,
-/*0067*/ 0x10080427U,
-/*0068*/ 0x18080427U,
-/*0069*/ 0x000a0428U,
-/*006a*/ 0x10070428U,
-/*006b*/ 0x18080428U,
-/*006c*/ 0x00080429U,
-/*006d*/ 0x08030429U,
-/*006e*/ 0x100a0429U,
-/*006f*/ 0x000a042aU,
-/*0070*/ 0x0011042bU,
-/*0071*/ 0x0009042cU,
-/*0072*/ 0x1009042cU,
-/*0073*/ 0x0010042dU,
-/*0074*/ 0x100e042dU,
-/*0075*/ 0x000e042eU,
-/*0076*/ 0x0012042fU,
-/*0077*/ 0x000a0430U,
-/*0078*/ 0x100a0430U,
-/*0079*/ 0x00020431U,
-/*007a*/ 0x00200432U,
-/*007b*/ 0x000b0433U,
-/*007c*/ 0x100b0433U,
-/*007d*/ 0x00200434U,
-/*007e*/ 0x00120435U,
-/*007f*/ 0x00200436U,
-/*0080*/ 0x00200437U,
-/*0081*/ 0x00080438U,
-/*0082*/ 0x08010438U,
-/*0083*/ 0x10010438U,
-/*0084*/ 0x18010438U,
-/*0085*/ 0x00080439U,
-/*0086*/ 0x080c0439U,
-/*0087*/ 0x000c043aU,
-/*0088*/ 0x100c043aU,
-/*0089*/ 0x000c043bU,
-/*008a*/ 0x100c043bU,
-/*008b*/ 0x000c043cU,
-/*008c*/ 0x100c043cU,
-/*008d*/ 0x000c043dU,
-/*008e*/ 0x100c043dU,
-/*008f*/ 0x000c043eU,
-/*0090*/ 0x100c043eU,
-/*0091*/ 0x000b043fU,
-/*0092*/ 0x1009043fU,
-/*0093*/ 0x00010440U,
-/*0094*/ 0x000b0441U,
-/*0095*/ 0x100b0441U,
-/*0096*/ 0x000b0442U,
-/*0097*/ 0x100b0442U,
-/*0098*/ 0x000b0443U,
-/*0099*/ 0x100b0443U,
-/*009a*/ 0x000b0444U,
-/*009b*/ 0x100b0444U,
-/*009c*/ 0x000b0445U,
-/*009d*/ 0x100a0445U,
-/*009e*/ 0x00020446U,
-/*009f*/ 0x080a0446U,
-/*00a0*/ 0x000a0447U,
-/*00a1*/ 0x100a0447U,
-/*00a2*/ 0x000a0448U,
-/*00a3*/ 0x100a0448U,
-/*00a4*/ 0x000a0449U,
-/*00a5*/ 0x100a0449U,
-/*00a6*/ 0x000a044aU,
-/*00a7*/ 0x100a044aU,
-/*00a8*/ 0x000a044bU,
-/*00a9*/ 0x100a044bU,
-/*00aa*/ 0x000a044cU,
-/*00ab*/ 0x100a044cU,
-/*00ac*/ 0x000a044dU,
-/*00ad*/ 0x100a044dU,
-/*00ae*/ 0x000a044eU,
-/*00af*/ 0x100a044eU,
-/*00b0*/ 0x000a044fU,
-/*00b1*/ 0x100a044fU,
-/*00b2*/ 0x000a0450U,
-/*00b3*/ 0x100a0450U,
-/*00b4*/ 0x000a0451U,
-/*00b5*/ 0x100a0451U,
-/*00b6*/ 0x000a0452U,
-/*00b7*/ 0x100a0452U,
-/*00b8*/ 0x000a0453U,
-/*00b9*/ 0x100a0453U,
-/*00ba*/ 0x000a0454U,
-/*00bb*/ 0x10040454U,
-/*00bc*/ 0x18030454U,
-/*00bd*/ 0x000a0455U,
-/*00be*/ 0x100a0455U,
-/*00bf*/ 0x00010456U,
-/*00c0*/ 0x080a0456U,
-/*00c1*/ 0x18040456U,
-/*00c2*/ 0x000b0457U,
-/*00c3*/ 0x100a0457U,
-/*00c4*/ 0x00030458U,
-/*00c5*/ 0x00080459U,
-/*00c6*/ 0x08080459U,
-/*00c7*/ 0x10080459U,
-/*00c8*/ 0x18080459U,
-/*00c9*/ 0x0008045aU,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x0808045aU,
-/*00cc*/ 0x1001045aU,
-/*00cd*/ 0x1808045aU,
-/*00ce*/ 0x0008045bU,
-/*00cf*/ 0x0802045bU,
-/*00d0*/ 0x1002045bU,
-/*00d1*/ 0x1805045bU,
-/*00d2*/ 0x0005045cU,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x0804045cU,
-/*00d5*/ 0x100a045cU,
-/*00d6*/ 0x0006045dU,
-/*00d7*/ 0x0808045dU,
-/*00d8*/ 0x1008045dU,
-/*00d9*/ 0x1804045dU,
-/*00da*/ 0x0004045eU,
-/*00db*/ 0x0805045eU,
-/*00dc*/ 0x1004045eU,
-/*00dd*/ 0x1805045eU,
-/*00de*/ 0x000a045fU,
-/*00df*/ 0x100a045fU,
-/*00e0*/ 0x00080460U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040460U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050600U,
-/*00e6*/ 0x08050600U,
-/*00e7*/ 0x10050600U,
-/*00e8*/ 0x18050600U,
-/*00e9*/ 0x00050601U,
-/*00ea*/ 0x08050601U,
-/*00eb*/ 0x100b0601U,
-/*00ec*/ 0x00010602U,
-/*00ed*/ 0x08030602U,
-/*00ee*/ 0x00200603U,
-/*00ef*/ 0x00100604U,
-/*00f0*/ 0x10040604U,
-/*00f1*/ 0x000a0605U,
-/*00f2*/ 0x10090605U,
-/*00f3*/ 0x00080606U,
-/*00f4*/ 0x08030606U,
-/*00f5*/ 0x10030606U,
-/*00f6*/ 0x18010606U,
-/*00f7*/ 0x00010607U,
-/*00f8*/ 0x08070607U,
-/*00f9*/ 0x10070607U,
-/*00fa*/ 0x18050607U,
-/*00fb*/ 0x00010608U,
-/*00fc*/ 0x08020608U,
-/*00fd*/ 0x10030608U,
-/*00fe*/ 0x18010608U,
-/*00ff*/ 0x000f0609U,
-/*0100*/ 0x0020060aU,
-/*0101*/ 0x0020060bU,
-/*0102*/ 0x000b060cU,
-/*0103*/ 0x100b060cU,
-/*0104*/ 0x000b060dU,
-/*0105*/ 0x0018060eU,
-/*0106*/ 0x0018060fU,
-/*0107*/ 0xffffffffU,
-/*0108*/ 0xffffffffU,
-/*0109*/ 0xffffffffU,
-/*010a*/ 0xffffffffU,
-/*010b*/ 0xffffffffU,
-/*010c*/ 0x1802060fU,
-/*010d*/ 0x00020610U,
-/*010e*/ 0x08040610U,
-/*010f*/ 0x10040610U,
-/*0110*/ 0x18010610U,
-/*0111*/ 0x00010611U,
-/*0112*/ 0x08010611U,
-/*0113*/ 0x10030611U,
-/*0114*/ 0x00200612U,
-/*0115*/ 0x00200613U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140614U,
-/*0118*/ 0x00140615U,
-/*0119*/ 0x00140616U,
-/*011a*/ 0x00140617U,
-/*011b*/ 0x00140618U,
-/*011c*/ 0x00140619U,
-/*011d*/ 0x0014061aU,
-/*011e*/ 0x0014061bU,
-/*011f*/ 0x0018061cU,
-/*0120*/ 0x000a061dU,
-/*0121*/ 0x1006061dU,
-/*0122*/ 0x1806061dU,
-/*0123*/ 0x0006061eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0x0806061eU,
-/*0126*/ 0x0008061fU,
-/*0127*/ 0x080b061fU,
-/*0128*/ 0x000b0620U,
-/*0129*/ 0x100b0620U,
-/*012a*/ 0x000b0621U,
-/*012b*/ 0x100b0621U,
-/*012c*/ 0x000b0622U,
-/*012d*/ 0x10040622U,
-/*012e*/ 0x000a0623U,
-/*012f*/ 0x10060623U,
-/*0130*/ 0x18080623U,
-/*0131*/ 0x00080624U,
-/*0132*/ 0x08040624U,
-/*0133*/ 0x00020680U,
-/*0134*/ 0x00010681U,
-/*0135*/ 0x08010681U,
-/*0136*/ 0x10020681U,
-/*0137*/ 0x18050681U,
-/*0138*/ 0x00050682U,
-/*0139*/ 0x08050682U,
-/*013a*/ 0x10050682U,
-/*013b*/ 0x000b0683U,
-/*013c*/ 0x10050683U,
-/*013d*/ 0x18010683U,
-/*013e*/ 0x00010684U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x08010684U,
-/*0141*/ 0x10010684U,
-/*0142*/ 0x18040684U,
-/*0143*/ 0x000b0685U,
-/*0144*/ 0x100b0685U,
-/*0145*/ 0x000b0686U,
-/*0146*/ 0x10040686U,
-/*0147*/ 0x000b0687U,
-/*0148*/ 0x10040687U,
-/*0149*/ 0x18010687U,
-/*014a*/ 0x00010688U,
-/*014b*/ 0x08010688U,
-/*014c*/ 0x00200689U,
-/*014d*/ 0x0020068aU,
-/*014e*/ 0x0008068bU,
-/*014f*/ 0x080a068bU,
-/*0150*/ 0x1805068bU,
-/*0151*/ 0x000a068cU,
-/*0152*/ 0x1003068cU,
-/*0153*/ 0x1803068cU,
-/*0154*/ 0x0001068dU,
-/*0155*/ 0x0802068dU,
-/*0156*/ 0x1001068dU,
-/*0157*/ 0x1801068dU,
-/*0158*/ 0x0001068eU,
-/*0159*/ 0x0802068eU,
-/*015a*/ 0x1001068eU,
-/*015b*/ 0x0004068fU,
-/*015c*/ 0x0804068fU,
-/*015d*/ 0x1004068fU,
-/*015e*/ 0x1804068fU,
-/*015f*/ 0x00010690U,
-/*0160*/ 0x08010690U,
-/*0161*/ 0x10010690U,
-/*0162*/ 0x00200691U,
-/*0163*/ 0x00200692U,
-/*0164*/ 0x00200693U,
-/*0165*/ 0x00200694U,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0x1801068eU,
-/*0168*/ 0x000d0696U,
-/*0169*/ 0x100d0696U,
-/*016a*/ 0x000d0697U,
-/*016b*/ 0x00050698U,
-/*016c*/ 0x00010699U,
-/*016d*/ 0x080e0699U,
-/*016e*/ 0x000e069aU,
-/*016f*/ 0x100e069aU,
-/*0170*/ 0x000e069bU,
-/*0171*/ 0x100e069bU,
-/*0172*/ 0x0004069cU,
-/*0173*/ 0x0804069cU,
-/*0174*/ 0x1004069cU,
-/*0175*/ 0x1804069cU,
-/*0176*/ 0x0004069dU,
-/*0177*/ 0x080b069dU,
-/*0178*/ 0x000b069eU,
-/*0179*/ 0x100b069eU,
-/*017a*/ 0x000b069fU,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d06a0U,
-/*0180*/ 0x100d06a0U,
-/*0181*/ 0x000d06a1U,
-/*0182*/ 0x101006a1U,
-/*0183*/ 0x00080695U,
-/*0184*/ 0x08080695U,
-/*0185*/ 0x001006a2U,
-/*0186*/ 0x101006a2U,
-/*0187*/ 0x001006a3U,
-/*0188*/ 0x101006a3U,
-/*0189*/ 0x001006a4U,
-/*018a*/ 0x100306a4U,
-/*018b*/ 0x180406a4U,
-/*018c*/ 0x000106a5U,
-/*018d*/ 0x080806a5U,
-/*018e*/ 0x100106a5U,
-/*018f*/ 0x180506a5U,
-/*0190*/ 0x000106a6U,
-/*0191*/ 0x081406a6U,
-/*0192*/ 0x000a06a7U,
-/*0193*/ 0x100c06a7U,
-/*0194*/ 0x001206a8U,
-/*0195*/ 0x001406a9U,
-/*0196*/ 0x001206aaU,
-/*0197*/ 0x001106abU,
-/*0198*/ 0x001106acU,
-/*0199*/ 0x001206adU,
-/*019a*/ 0x001206aeU,
-/*019b*/ 0x001206afU,
-/*019c*/ 0x001206b0U,
-/*019d*/ 0x001206b1U,
-/*019e*/ 0x001206b2U,
-/*019f*/ 0x001206b3U,
-/*01a0*/ 0x001206b4U,
-/*01a1*/ 0x001206b5U,
-/*01a2*/ 0x001206b6U,
-/*01a3*/ 0x000e06b7U,
-/*01a4*/ 0x100d06b7U,
-/*01a5*/ 0x002006b8U,
-/*01a6*/ 0x001706b9U,
-/*01a7*/ 0x000906baU,
-/*01a8*/ 0x100106baU,
-/*01a9*/ 0x180106baU,
-/*01aa*/ 0x002006bbU,
-/*01ab*/ 0x000806bcU,
-/*01ac*/ 0x080306bcU,
-/*01ad*/ 0x100306bcU,
-/*01ae*/ 0x001806bdU,
-/*01af*/ 0x001806beU,
-/*01b0*/ 0x180706beU,
-/*01b1*/ 0x000506bfU,
-/*01b2*/ 0x080806bfU,
-/*01b3*/ 0x100806bfU,
-/*01b4*/ 0x180806bfU,
-/*01b5*/ 0x000106c0U,
-/*01b6*/ 0x080106c0U,
-/*01b7*/ 0x002006c1U,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x001006c2U,
-/*01c0*/ 0x100106c2U,
-/*01c1*/ 0x180106c2U,
-/*01c2*/ 0x000206c3U,
-/*01c3*/ 0x080406c3U,
-/*01c4*/ 0x100906c3U,
-/*01c5*/ 0x000706c4U,
-/*01c6*/ 0x080406c4U,
-/*01c7*/ 0x002006c5U,
-/*01c8*/ 0x000106c6U,
-/*01c9*/ 0x080206c6U,
-/*01ca*/ 0x100606c6U,
-/*01cb*/ 0x001006c7U,
-/*01cc*/ 0x100106c7U,
-/*01cd*/ 0x002006c8U,
-/*01ce*/ 0x000806c9U,
-/*01cf*/ 0x080106c9U,
-/*01d0*/ 0x100506c9U,
-/*01d1*/ 0xffffffffU,
-/*01d2*/ 0x180206c9U,
-/*01d3*/ 0x000106caU,
-/*01d4*/ 0x002006cbU,
-/*01d5*/ 0x000b06ccU,
-/*01d6*/ 0x100106ccU,
-/*01d7*/ 0x180306ccU,
-/*01d8*/ 0x000806cdU,
-/*01d9*/ 0x080206cdU,
-/*01da*/ 0x100c06cdU,
-/*01db*/ 0x000406ceU,
-/*01dc*/ 0x080106ceU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0x10010201U,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x00100202U,
-/*01e6*/ 0x10080202U,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200203U,
-/*01f0*/ 0x00100204U,
-/*01f1*/ 0x00200205U,
-/*01f2*/ 0x00100206U,
-/*01f3*/ 0x00200207U,
-/*01f4*/ 0x00100208U,
-/*01f5*/ 0x00140209U,
-/*01f6*/ 0x0020020aU,
-/*01f7*/ 0x0020020bU,
-/*01f8*/ 0x0020020cU,
-/*01f9*/ 0x0020020dU,
-/*01fa*/ 0x0014020eU,
-/*01fb*/ 0x0020020fU,
-/*01fc*/ 0x00200210U,
-/*01fd*/ 0x00200211U,
-/*01fe*/ 0x00200212U,
-/*01ff*/ 0x00140213U,
-/*0200*/ 0x00200214U,
-/*0201*/ 0x00200215U,
-/*0202*/ 0x00200216U,
-/*0203*/ 0x00200217U,
-/*0204*/ 0x00090218U,
-/*0205*/ 0x10010218U,
-/*0206*/ 0x00200219U,
-/*0207*/ 0x0005021aU,
-/*0208*/ 0x0801021aU,
-/*0209*/ 0x1008021aU,
-/*020a*/ 0x1808021aU,
-/*020b*/ 0x001c021bU,
-/*020c*/ 0x001c021cU,
-/*020d*/ 0x001c021dU,
-/*020e*/ 0x001c021eU,
-/*020f*/ 0x001c021fU,
-/*0210*/ 0x001c0220U,
-/*0211*/ 0x001c0221U,
-/*0212*/ 0x001c0222U,
-/*0213*/ 0x001c0223U,
-/*0214*/ 0x001c0224U,
-/*0215*/ 0x001c0225U,
-/*0216*/ 0x001c0226U,
-/*0217*/ 0x001c0227U,
-/*0218*/ 0x001c0228U,
-/*0219*/ 0x001c0229U,
-/*021a*/ 0x001c022aU,
-/*021b*/ 0x0001022bU,
-/*021c*/ 0x0801022bU,
-/*021d*/ 0x1001022bU,
-/*021e*/ 0x1804022bU,
-/*021f*/ 0x0008022cU,
-/*0220*/ 0x0808022cU,
-/*0221*/ 0x1008022cU,
-/*0222*/ 0x1804022cU,
-/*0223*/ 0x0007022dU,
-/*0224*/ 0xffffffffU,
-/*0225*/ 0x0807022dU,
-/*0226*/ 0x1007022dU,
-/*0227*/ 0xffffffffU,
-/*0228*/ 0x1807022dU,
-/*0229*/ 0x0007022eU,
-/*022a*/ 0xffffffffU,
-/*022b*/ 0x0807022eU,
-/*022c*/ 0x1002022eU,
-/*022d*/ 0x1801022eU,
-/*022e*/ 0x0001022fU,
-/*022f*/ 0x080a022fU,
-/*0230*/ 0x00140230U,
-/*0231*/ 0x000a0231U,
-/*0232*/ 0x00140232U,
-/*0233*/ 0x000a0233U,
-/*0234*/ 0x00140234U,
-/*0235*/ 0x18010234U,
-/*0236*/ 0x00100235U,
-/*0237*/ 0x10050235U,
-/*0238*/ 0x18010235U,
-/*0239*/ 0x00010236U,
-/*023a*/ 0x08010236U,
-/*023b*/ 0x10010236U,
-/*023c*/ 0x18010236U,
-/*023d*/ 0x00010237U,
-/*023e*/ 0x08010237U,
-/*023f*/ 0x10020237U,
-/*0240*/ 0x18020237U,
-/*0241*/ 0x00020238U,
-/*0242*/ 0x08020238U,
-/*0243*/ 0x10020238U,
-/*0244*/ 0x18030238U,
-/*0245*/ 0x00010239U,
-/*0246*/ 0x08010239U,
-/*0247*/ 0x10010239U,
-/*0248*/ 0x18010239U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x0002023aU,
-/*024b*/ 0x0801023aU,
-/*024c*/ 0x1001023aU,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x1802023aU,
-/*024f*/ 0x0001023bU,
-/*0250*/ 0x0801023bU,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x1002023bU,
-/*0253*/ 0x1801023bU,
-/*0254*/ 0x0001023cU,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x0802023cU,
-/*0257*/ 0x1007023cU,
-/*0258*/ 0x1801023cU,
-/*0259*/ 0x0001023dU,
-/*025a*/ 0x0801023dU,
-/*025b*/ 0x1001023dU,
-/*025c*/ 0x1801023dU,
-/*025d*/ 0x0001023eU,
-/*025e*/ 0x0801023eU,
-/*025f*/ 0x1001023eU,
-/*0260*/ 0x1804023eU,
-/*0261*/ 0x0004023fU,
-/*0262*/ 0x0804023fU,
-/*0263*/ 0x1001023fU,
-/*0264*/ 0x1802023fU,
-/*0265*/ 0x00060240U,
-/*0266*/ 0x08060240U,
-/*0267*/ 0x10020240U,
-/*0268*/ 0x18020240U,
-/*0269*/ 0x00020241U,
-/*026a*/ 0xffffffffU,
-/*026b*/ 0x08100241U,
-/*026c*/ 0x18010241U,
-/*026d*/ 0x00010242U,
-/*026e*/ 0x08010242U,
-/*026f*/ 0x10040242U,
-/*0270*/ 0x18010242U,
-/*0271*/ 0x00040243U,
-/*0272*/ 0x08020243U,
-/*0273*/ 0x10080243U,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x000a0244U,
-/*0278*/ 0x00200245U,
-/*0279*/ 0x00200246U,
-/*027a*/ 0x00050247U,
-/*027b*/ 0x08010247U,
-/*027c*/ 0x10050247U,
-/*027d*/ 0x18080247U,
-/*027e*/ 0x00010248U,
-/*027f*/ 0x08080248U,
-/*0280*/ 0x10010248U,
-/*0281*/ 0x18080248U,
-/*0282*/ 0x00010249U,
-/*0283*/ 0x08040249U,
-/*0284*/ 0x10040249U,
-/*0285*/ 0x18040249U,
-/*0286*/ 0x0004024aU,
-/*0287*/ 0x0804024aU,
-/*0288*/ 0x1004024aU,
-/*0289*/ 0x1804024aU,
-/*028a*/ 0x0004024bU,
-/*028b*/ 0x0804024bU,
-/*028c*/ 0x1004024bU,
-/*028d*/ 0x1801024bU,
-/*028e*/ 0x0004024cU,
-/*028f*/ 0x0804024cU,
-/*0290*/ 0x1004024cU,
-/*0291*/ 0x1804024cU,
-/*0292*/ 0x0004024dU,
-/*0293*/ 0x0804024dU,
-/*0294*/ 0x1006024dU,
-/*0295*/ 0x1806024dU,
-/*0296*/ 0x0006024eU,
-/*0297*/ 0x0806024eU,
-/*0298*/ 0x1006024eU,
-/*0299*/ 0x1806024eU,
-/*029a*/ 0xffffffffU,
-/*029b*/ 0x0001024fU,
-/*029c*/ 0x0801024fU,
-/*029d*/ 0x1002024fU,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x1804024fU,
-/*02a7*/ 0x00040250U,
-/*02a8*/ 0x08010250U,
-/*02a9*/ 0x10010250U,
-/*02aa*/ 0x18010250U,
-/*02ab*/ 0x00010251U,
-/*02ac*/ 0x08010251U,
-/*02ad*/ 0x10010251U,
-/*02ae*/ 0x18010251U,
-/*02af*/ 0x00010252U,
-/*02b0*/ 0x08010252U,
-/*02b1*/ 0x10040252U,
-/*02b2*/ 0x18040252U,
-/*02b3*/ 0x000a0253U,
-/*02b4*/ 0x00200254U,
-/*02b5*/ 0x00040255U,
-/*02b6*/ 0x08080255U,
-/*02b7*/ 0x10020255U,
-/*02b8*/ 0x18020255U,
-/*02b9*/ 0x00020256U,
-/*02ba*/ 0x08020256U,
-/*02bb*/ 0x10020256U,
-/*02bc*/ 0x18020256U,
-/*02bd*/ 0xffffffffU,
-/*02be*/ 0xffffffffU,
-/*02bf*/ 0x00200257U,
-/*02c0*/ 0x00020258U,
-/*02c1*/ 0x08100258U,
-/*02c2*/ 0x00100259U,
-/*02c3*/ 0x10040259U,
-/*02c4*/ 0x18040259U,
-/*02c5*/ 0x0005025aU,
-/*02c6*/ 0x0805025aU,
-/*02c7*/ 0x0020025bU,
-/*02c8*/ 0x0020025cU,
-/*02c9*/ 0x0020025dU,
-/*02ca*/ 0x0020025eU,
-/*02cb*/ 0x0001025fU,
-/*02cc*/ 0x0801025fU,
-/*02cd*/ 0x1007025fU,
-/*02ce*/ 0x1807025fU,
-/*02cf*/ 0x00070260U,
-/*02d0*/ 0x08070260U,
-/*02d1*/ 0x10070260U,
-/*02d2*/ 0x18070260U,
-/*02d3*/ 0x00070261U,
-/*02d4*/ 0x08070261U,
-/*02d5*/ 0x10070261U,
-/*02d6*/ 0x18070261U,
-/*02d7*/ 0x00070262U,
-/*02d8*/ 0x08070262U,
-/*02d9*/ 0x10070262U,
-/*02da*/ 0x18070262U,
-/*02db*/ 0x00030263U,
-/*02dc*/ 0x08030263U,
-/*02dd*/ 0x10030263U,
-/*02de*/ 0xffffffffU,
-/*02df*/ 0x18010263U,
-/*02e0*/ 0x00020264U,
-/*02e1*/ 0x08010264U,
-/*02e2*/ 0x10040264U,
-/*02e3*/ 0x18020264U,
-/*02e4*/ 0x00010265U,
-/*02e5*/ 0x08010265U,
-/*02e6*/ 0x10010265U,
-/*02e7*/ 0x18010265U,
-/*02e8*/ 0x00040266U,
-/*02e9*/ 0x08080266U,
-/*02ea*/ 0x100a0266U,
-/*02eb*/ 0x000a0267U,
-/*02ec*/ 0x100a0267U,
-/*02ed*/ 0x000a0268U,
-/*02ee*/ 0x100a0268U,
-/*02ef*/ 0x000a0269U,
-/*02f0*/ 0x0020026aU,
-/*02f1*/ 0x0020026bU,
-/*02f2*/ 0x0001026cU,
-/*02f3*/ 0x0802026cU,
-/*02f4*/ 0x1002026cU,
-/*02f5*/ 0x1802026cU,
-/*02f6*/ 0xffffffffU,
-/*02f7*/ 0x0002026dU,
-/*02f8*/ 0x0810026dU,
-/*02f9*/ 0x1805026dU,
-/*02fa*/ 0x0006026eU,
-/*02fb*/ 0x0805026eU,
-/*02fc*/ 0x1005026eU,
-/*02fd*/ 0x000e026fU,
-/*02fe*/ 0x1005026fU,
-/*02ff*/ 0x000e0270U,
-/*0300*/ 0x10050270U,
-/*0301*/ 0x000e0271U,
-/*0302*/ 0x10050271U,
-/*0303*/ 0x18010271U,
-/*0304*/ 0x00050272U,
-/*0305*/ 0x08050272U,
-/*0306*/ 0x100a0272U,
-/*0307*/ 0x000a0273U,
-/*0308*/ 0x10050273U,
-/*0309*/ 0x18050273U,
-/*030a*/ 0x000a0274U,
-/*030b*/ 0x100a0274U,
-/*030c*/ 0x00050275U,
-/*030d*/ 0x08050275U,
-/*030e*/ 0x100a0275U,
-/*030f*/ 0x000a0276U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070276U,
-/*0317*/ 0x18070276U,
-/*0318*/ 0x00040277U,
-/*0319*/ 0x08040277U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040277U,
-/*031e*/ 0x18080277U,
-/*031f*/ 0x00080278U,
-/*0320*/ 0x08040278U,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x10040278U,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x18040278U,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x00040279U,
-/*032d*/ 0x08050279U,
-/*032e*/ 0x10070279U,
-/*032f*/ 0x18080279U,
-/*0330*/ 0x0010027aU,
-/*0331*/ 0x1008027aU,
-/*0332*/ 0x0010027bU,
-/*0333*/ 0x1008027bU,
-/*0334*/ 0x0010027cU,
-/*0335*/ 0x1008027cU,
-/*0336*/ 0x1808027cU,
-/*0337*/ 0x0001027dU,
-/*0338*/ 0x0801027dU,
-/*0339*/ 0x1006027dU,
-/*033a*/ 0x1806027dU,
-/*033b*/ 0x0006027eU,
-/*033c*/ 0x0801027eU,
-/*033d*/ 0x1001027eU,
-/*033e*/ 0x1803027eU,
-/*033f*/ 0x000a027fU,
-/*0340*/ 0x100a027fU,
-/*0341*/ 0x000a0280U,
-/*0342*/ 0xffffffffU,
-/*0343*/ 0x100a0280U,
-/*0344*/ 0x00040281U,
-/*0345*/ 0x08010281U,
-/*0346*/ 0x10040281U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070281U,
-/*034e*/ 0x00070282U,
-/*034f*/ 0x08050282U,
-/*0350*/ 0x10050282U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040282U,
-/*0355*/ 0x00010283U,
-/*0356*/ 0x08010283U,
-/*0357*/ 0x10020283U,
-/*0358*/ 0x18080283U,
-/*0359*/ 0x00200284U,
-/*035a*/ 0x00200285U,
-/*035b*/ 0x00100286U,
-/*035c*/ 0x10020286U,
-/*035d*/ 0x18020286U,
-/*035e*/ 0x00020287U,
-/*035f*/ 0xffffffffU,
-/*0360*/ 0x08010287U,
-/*0361*/ 0x10010287U,
-/*0362*/ 0x18020287U,
-/*0363*/ 0x00080288U,
-/*0364*/ 0x08080288U,
-/*0365*/ 0x10080288U,
-/*0366*/ 0x18080288U,
-/*0367*/ 0x00080289U,
-/*0368*/ 0x08080289U,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x10080289U,
-/*036b*/ 0x18080289U,
-/*036c*/ 0x0008028aU,
-/*036d*/ 0x0808028aU,
-/*036e*/ 0x1008028aU,
-/*036f*/ 0x1808028aU,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x0008028bU,
-/*0372*/ 0x0808028bU,
-/*0373*/ 0x1008028bU,
-/*0374*/ 0x1808028bU,
-/*0375*/ 0x0008028cU,
-/*0376*/ 0x0808028cU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1008028cU,
-/*0379*/ 0x1808028cU,
-/*037a*/ 0x0008028dU,
-/*037b*/ 0x0808028dU,
-/*037c*/ 0x1008028dU,
-/*037d*/ 0x1808028dU,
-/*037e*/ 0x0008028eU,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x0808028eU,
-/*0381*/ 0x1008028eU,
-/*0382*/ 0x1808028eU,
-/*0383*/ 0x0008028fU,
-/*0384*/ 0x0808028fU,
-/*0385*/ 0x1008028fU,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x1808028fU,
-/*0388*/ 0x00080290U,
-/*0389*/ 0x08080290U,
-/*038a*/ 0x10080290U,
-/*038b*/ 0x18080290U,
-/*038c*/ 0x00080291U,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x08080291U,
-/*038f*/ 0x10080291U,
-/*0390*/ 0x18080291U,
-/*0391*/ 0x00080292U,
-/*0392*/ 0x08080292U,
-/*0393*/ 0x10080292U,
-/*0394*/ 0x18080292U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x00080293U,
-/*0397*/ 0x08080293U,
-/*0398*/ 0x10080293U,
-/*0399*/ 0x18080293U,
-/*039a*/ 0x00080294U,
-/*039b*/ 0x08080294U,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x10080294U,
-/*039e*/ 0x18080294U,
-/*039f*/ 0x00080295U,
-/*03a0*/ 0x08080295U,
-/*03a1*/ 0x10080295U,
-/*03a2*/ 0x18080295U,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x00080296U,
-/*03a5*/ 0x08080296U,
-/*03a6*/ 0x10080296U,
-/*03a7*/ 0x18080296U,
-/*03a8*/ 0x00080297U,
-/*03a9*/ 0x08080297U,
-/*03aa*/ 0x10080297U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x18080297U,
-/*03ad*/ 0x00080298U,
-/*03ae*/ 0x08080298U,
-/*03af*/ 0x10080298U,
-/*03b0*/ 0x18080298U,
-/*03b1*/ 0x00080299U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x08080299U,
-/*03b4*/ 0x10080299U,
-/*03b5*/ 0x18080299U,
-/*03b6*/ 0x0008029aU,
-/*03b7*/ 0x0808029aU,
-/*03b8*/ 0x1008029aU,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x1808029aU,
-/*03bb*/ 0x0002029bU,
-/*03bc*/ 0x0803029bU,
-/*03bd*/ 0x100a029bU,
-/*03be*/ 0x000a029cU,
-/*03bf*/ 0x100a029cU,
-/*03c0*/ 0x0005029dU,
-/*03c1*/ 0x0808029dU,
-/*03c2*/ 0x1008029dU,
-/*03c3*/ 0x1808029dU,
-/*03c4*/ 0x0006029eU,
-/*03c5*/ 0x0806029eU,
-/*03c6*/ 0x0011029fU,
-/*03c7*/ 0x1808029fU,
-/*03c8*/ 0x000402a0U,
-/*03c9*/ 0x080602a0U,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x100602a0U,
-/*03cc*/ 0x180802a0U,
-/*03cd*/ 0xffffffffU,
-/*03ce*/ 0x000802a1U,
-/*03cf*/ 0x080802a1U,
-/*03d0*/ 0x100802a1U,
-/*03d1*/ 0x180602a1U,
-/*03d2*/ 0x000602a2U,
-/*03d3*/ 0x081102a2U,
-/*03d4*/ 0x000802a3U,
-/*03d5*/ 0x080402a3U,
-/*03d6*/ 0x100602a3U,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x180602a3U,
-/*03d9*/ 0x000802a4U,
-/*03da*/ 0xffffffffU,
-/*03db*/ 0x080802a4U,
-/*03dc*/ 0x100802a4U,
-/*03dd*/ 0x180802a4U,
-/*03de*/ 0x000602a5U,
-/*03df*/ 0x080602a5U,
-/*03e0*/ 0x001102a6U,
-/*03e1*/ 0x180802a6U,
-/*03e2*/ 0x000402a7U,
-/*03e3*/ 0x080602a7U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x100602a7U,
-/*03e6*/ 0x180802a7U,
-/*03e7*/ 0xffffffffU,
-/*03e8*/ 0x000402a8U,
-/*03e9*/ 0x080402a8U,
-/*03ea*/ 0x100402a8U,
-/*03eb*/ 0x180402a8U,
-/*03ec*/ 0x000402a9U,
-/*03ed*/ 0x080402a9U,
-/*03ee*/ 0x100402a9U,
-/*03ef*/ 0x180402a9U,
-/*03f0*/ 0x000402aaU,
-/*03f1*/ 0x080402aaU,
-/*03f2*/ 0x100402aaU,
-/*03f3*/ 0x180402aaU,
-/*03f4*/ 0x000402abU,
-/*03f5*/ 0x080402abU,
-/*03f6*/ 0x100402abU,
-/*03f7*/ 0x180402abU,
-/*03f8*/ 0x000402acU,
-/*03f9*/ 0x080402acU,
-/*03fa*/ 0x100402acU,
-/*03fb*/ 0x180402acU,
-/*03fc*/ 0x001202adU,
-/*03fd*/ 0x001102aeU,
-/*03fe*/ 0x001202afU,
-/*03ff*/ 0x002002b0U,
-/*0400*/ 0x002002b1U,
-/*0401*/ 0x002002b2U,
-/*0402*/ 0x002002b3U,
-/*0403*/ 0x002002b4U,
-/*0404*/ 0x002002b5U,
-/*0405*/ 0x002002b6U,
-/*0406*/ 0x002002b7U,
-/*0407*/ 0x002002b8U,
-/*0408*/ 0x000202b9U,
-/*0409*/ 0x080502b9U,
-/*040a*/ 0x100502b9U,
-/*040b*/ 0x180102b9U,
-/*040c*/ 0x000402baU,
-/*040d*/ 0x080402baU,
-/*040e*/ 0x100402baU,
-/*040f*/ 0x180402baU,
-/*0410*/ 0x000402bbU,
-/*0411*/ 0x080402bbU,
-/*0412*/ 0x100402bbU,
-/*0413*/ 0x180402bbU,
-/*0414*/ 0xffffffffU,
-/*0415*/ 0xffffffffU,
-/*0416*/ 0xffffffffU,
-/*0417*/ 0xffffffffU,
-/*0418*/ 0xffffffffU,
-/*0419*/ 0xffffffffU,
-/*041a*/ 0x000402bcU,
-/*041b*/ 0x080402bcU,
-/*041c*/ 0x100402bcU,
-/*041d*/ 0x180402bcU,
-/*041e*/ 0x000402bdU,
-/*041f*/ 0x080402bdU,
-/*0420*/ 0x100402bdU,
-/*0421*/ 0x180402bdU,
-/*0422*/ 0x000102beU,
-/*0423*/ 0x080202beU,
-/*0424*/ 0x100202beU,
-/*0425*/ 0x180202beU,
-/*0426*/ 0x000202bfU,
-/*0427*/ 0x080102bfU,
-/*0428*/ 0x100402bfU,
-/*0429*/ 0x001002c0U,
-/*042a*/ 0x002002c1U,
-/*042b*/ 0x001002c2U,
-/*042c*/ 0x002002c3U,
-/*042d*/ 0x001002c4U,
-/*042e*/ 0x002002c5U,
-/*042f*/ 0x000702c6U,
-/*0430*/ 0x080102c6U,
-/*0431*/ 0x100202c6U,
-/*0432*/ 0x180602c6U,
-/*0433*/ 0x000102c7U,
-/*0434*/ 0x080102c7U,
-/*0435*/ 0x002002c8U,
-/*0436*/ 0x000202c9U,
-/*0437*/ 0x002002caU,
-/*0438*/ 0x002002cbU,
-/*0439*/ 0x000c02ccU,
-/*043a*/ 0x100c02ccU,
-/*043b*/ 0x002002cdU,
-/*043c*/ 0x000302ceU,
-/*043d*/ 0x002002cfU,
-/*043e*/ 0x000302d0U,
-/*043f*/ 0x002002d1U,
-/*0440*/ 0x000302d2U,
-/*0441*/ 0x002002d3U,
-/*0442*/ 0x000302d4U,
-/*0443*/ 0x002002d5U,
-/*0444*/ 0x000302d6U,
-/*0445*/ 0x002002d7U,
-/*0446*/ 0x000302d8U,
-/*0447*/ 0x002002d9U,
-/*0448*/ 0x000302daU,
-/*0449*/ 0x002002dbU,
-/*044a*/ 0x000302dcU,
-/*044b*/ 0x002002ddU,
-/*044c*/ 0x000302deU,
-/*044d*/ 0x002002dfU,
-/*044e*/ 0x000302e0U,
-/*044f*/ 0x080302e0U,
-/*0450*/ 0x100202e0U,
-/*0451*/ 0x180202e0U,
-/*0452*/ 0x002002e1U,
-/*0453*/ 0x002002e2U,
-/*0454*/ 0x002002e3U,
-/*0455*/ 0x002002e4U,
-/*0456*/ 0x000402e5U,
-/*0457*/ 0x001e02e6U,
-/*0458*/ 0x001e02e7U,
-/*0459*/ 0x001e02e8U,
-/*045a*/ 0x001e02e9U,
-/*045b*/ 0x001e02eaU,
-/*045c*/ 0x001e02ebU,
-/*045d*/ 0x001e02ecU,
-/*045e*/ 0x001e02edU,
-/*045f*/ 0x000402eeU,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0x080402eeU,
-/*0465*/ 0x100102eeU,
-/*0466*/ 0x180802eeU,
-/*0467*/ 0x000402efU,
-/*0468*/ 0x080102efU,
-/*0469*/ 0x100802efU,
-/*046a*/ 0x180402efU,
-/*046b*/ 0x000102f0U,
-/*046c*/ 0x080802f0U,
-/*046d*/ 0x100402f0U,
-/*046e*/ 0x180102f0U,
-/*046f*/ 0x000802f1U,
-/*0470*/ 0x080402f1U,
-/*0471*/ 0x100102f1U,
-/*0472*/ 0x180802f1U,
-/*0473*/ 0x000402f2U,
-/*0474*/ 0x080102f2U,
-/*0475*/ 0x100802f2U,
-/*0476*/ 0x180402f2U,
-/*0477*/ 0x000102f3U,
-/*0478*/ 0x080802f3U,
-/*0479*/ 0x100402f3U,
-/*047a*/ 0x180102f3U,
-/*047b*/ 0x000802f4U,
-/*047c*/ 0x080802f4U,
-/*047d*/ 0x100102f4U,
-/*047e*/ 0x180502f4U,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
-	 },
-	{
-/*0000*/ 0x00200800U,
-/*0001*/ 0x00040801U,
-/*0002*/ 0x080b0801U,
-/*0003*/ 0x000a0802U,
-/*0004*/ 0x10020802U,
-/*0005*/ 0x18010802U,
-/*0006*/ 0x00060803U,
-/*0007*/ 0x08060803U,
-/*0008*/ 0x10060803U,
-/*0009*/ 0x18060803U,
-/*000a*/ 0x00060804U,
-/*000b*/ 0x08060804U,
-/*000c*/ 0x10050804U,
-/*000d*/ 0x18060804U,
-/*000e*/ 0x00060805U,
-/*000f*/ 0x08040805U,
-/*0010*/ 0x10030805U,
-/*0011*/ 0x00180806U,
-/*0012*/ 0x18030806U,
-/*0013*/ 0x00180807U,
-/*0014*/ 0x18020807U,
-/*0015*/ 0x0801085eU,
-/*0016*/ 0x00020808U,
-/*0017*/ 0x08010808U,
-/*0018*/ 0x10010808U,
-/*0019*/ 0x18020808U,
-/*001a*/ 0x00050809U,
-/*001b*/ 0x08050809U,
-/*001c*/ 0x10040809U,
-/*001d*/ 0xffffffffU,
-/*001e*/ 0x18040809U,
-/*001f*/ 0x0002080aU,
-/*0020*/ 0x0805080aU,
-/*0021*/ 0x1009080aU,
-/*0022*/ 0x0001080bU,
-/*0023*/ 0x0020080cU,
-/*0024*/ 0x001c080dU,
-/*0025*/ 0x0001080eU,
-/*0026*/ 0x0807080eU,
-/*0027*/ 0x1009080eU,
-/*0028*/ 0x000a080fU,
-/*0029*/ 0x1005080fU,
-/*002a*/ 0x1801080fU,
-/*002b*/ 0x10010810U,
-/*002c*/ 0x18020810U,
-/*002d*/ 0x00090810U,
-/*002e*/ 0x00090811U,
-/*002f*/ 0x10020811U,
-/*0030*/ 0x00200812U,
-/*0031*/ 0x00010813U,
-/*0032*/ 0x08020813U,
-/*0033*/ 0x00200814U,
-/*0034*/ 0x00200815U,
-/*0035*/ 0x00200816U,
-/*0036*/ 0x00200817U,
-/*0037*/ 0xffffffffU,
-/*0038*/ 0xffffffffU,
-/*0039*/ 0xffffffffU,
-/*003a*/ 0xffffffffU,
-/*003b*/ 0x00030818U,
-/*003c*/ 0x08010818U,
-/*003d*/ 0x10040818U,
-/*003e*/ 0x18030818U,
-/*003f*/ 0x00040819U,
-/*0040*/ 0x08040819U,
-/*0041*/ 0x10040819U,
-/*0042*/ 0x18040819U,
-/*0043*/ 0x0001081aU,
-/*0044*/ 0x0801081aU,
-/*0045*/ 0x1006081aU,
-/*0046*/ 0x1804081aU,
-/*0047*/ 0x0008081bU,
-/*0048*/ 0x0806081bU,
-/*0049*/ 0x1004081bU,
-/*004a*/ 0x1806081bU,
-/*004b*/ 0x0004081cU,
-/*004c*/ 0x0802081cU,
-/*004d*/ 0x1005081cU,
-/*004e*/ 0x1808081cU,
-/*004f*/ 0xffffffffU,
-/*0050*/ 0x0006081dU,
-/*0051*/ 0x0803081dU,
-/*0052*/ 0x100b081dU,
-/*0053*/ 0x0004081eU,
-/*0054*/ 0x0804081eU,
-/*0055*/ 0x1004081eU,
-/*0056*/ 0x1801081eU,
-/*0057*/ 0xffffffffU,
-/*0058*/ 0x0009081fU,
-/*0059*/ 0x00200820U,
-/*005a*/ 0x00200821U,
-/*005b*/ 0x00200822U,
-/*005c*/ 0x00200823U,
-/*005d*/ 0x00100824U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010824U,
-/*0060*/ 0x18060824U,
-/*0061*/ 0x00080825U,
-/*0062*/ 0x00200826U,
-/*0063*/ 0x00100827U,
-/*0064*/ 0x100b0827U,
-/*0065*/ 0x00070828U,
-/*0066*/ 0x08070828U,
-/*0067*/ 0x10090828U,
-/*0068*/ 0x00090829U,
-/*0069*/ 0x100b0829U,
-/*006a*/ 0x0007082aU,
-/*006b*/ 0x0808082aU,
-/*006c*/ 0x1009082aU,
-/*006d*/ 0x0003082bU,
-/*006e*/ 0x080a082bU,
-/*006f*/ 0x000a082cU,
-/*0070*/ 0x0011082dU,
-/*0071*/ 0x000a082eU,
-/*0072*/ 0x100a082eU,
-/*0073*/ 0x0010082fU,
-/*0074*/ 0x100e082fU,
-/*0075*/ 0x000e0830U,
-/*0076*/ 0x00120831U,
-/*0077*/ 0x000a0832U,
-/*0078*/ 0x100a0832U,
-/*0079*/ 0x00020833U,
-/*007a*/ 0x00200834U,
-/*007b*/ 0x000b0835U,
-/*007c*/ 0x100b0835U,
-/*007d*/ 0x00200836U,
-/*007e*/ 0x00130837U,
-/*007f*/ 0x00200838U,
-/*0080*/ 0x00200839U,
-/*0081*/ 0x0008083aU,
-/*0082*/ 0x0801083aU,
-/*0083*/ 0x1001083aU,
-/*0084*/ 0x1801083aU,
-/*0085*/ 0x0008083bU,
-/*0086*/ 0x080c083bU,
-/*0087*/ 0x000c083cU,
-/*0088*/ 0x100c083cU,
-/*0089*/ 0x000c083dU,
-/*008a*/ 0x100c083dU,
-/*008b*/ 0x000c083eU,
-/*008c*/ 0x100c083eU,
-/*008d*/ 0x000c083fU,
-/*008e*/ 0x100c083fU,
-/*008f*/ 0x000c0840U,
-/*0090*/ 0x100c0840U,
-/*0091*/ 0x000b0841U,
-/*0092*/ 0x10090841U,
-/*0093*/ 0x00010842U,
-/*0094*/ 0x000b0843U,
-/*0095*/ 0x100b0843U,
-/*0096*/ 0x000b0844U,
-/*0097*/ 0x100b0844U,
-/*0098*/ 0x000b0845U,
-/*0099*/ 0x100b0845U,
-/*009a*/ 0x000b0846U,
-/*009b*/ 0x100b0846U,
-/*009c*/ 0x000b0847U,
-/*009d*/ 0x100a0847U,
-/*009e*/ 0x00020848U,
-/*009f*/ 0x080a0848U,
-/*00a0*/ 0x000a0849U,
-/*00a1*/ 0x100a0849U,
-/*00a2*/ 0x000a084aU,
-/*00a3*/ 0x100a084aU,
-/*00a4*/ 0x000a084bU,
-/*00a5*/ 0x100a084bU,
-/*00a6*/ 0x000a084cU,
-/*00a7*/ 0x100a084cU,
-/*00a8*/ 0x000a084dU,
-/*00a9*/ 0x100a084dU,
-/*00aa*/ 0x000a084eU,
-/*00ab*/ 0x100a084eU,
-/*00ac*/ 0x000a084fU,
-/*00ad*/ 0x100a084fU,
-/*00ae*/ 0x000a0850U,
-/*00af*/ 0x100a0850U,
-/*00b0*/ 0x000a0851U,
-/*00b1*/ 0x100a0851U,
-/*00b2*/ 0x000a0852U,
-/*00b3*/ 0x100a0852U,
-/*00b4*/ 0x000a0853U,
-/*00b5*/ 0x100a0853U,
-/*00b6*/ 0x000a0854U,
-/*00b7*/ 0x100a0854U,
-/*00b8*/ 0x000a0855U,
-/*00b9*/ 0x100a0855U,
-/*00ba*/ 0x000a0856U,
-/*00bb*/ 0x10040856U,
-/*00bc*/ 0x18030856U,
-/*00bd*/ 0x000a0857U,
-/*00be*/ 0x100a0857U,
-/*00bf*/ 0x00010858U,
-/*00c0*/ 0x080a0858U,
-/*00c1*/ 0x18040858U,
-/*00c2*/ 0x000b0859U,
-/*00c3*/ 0x100a0859U,
-/*00c4*/ 0x0003085aU,
-/*00c5*/ 0x0008085bU,
-/*00c6*/ 0x0808085bU,
-/*00c7*/ 0x1008085bU,
-/*00c8*/ 0x1808085bU,
-/*00c9*/ 0x0008085cU,
-/*00ca*/ 0x0808085cU,
-/*00cb*/ 0x1008085cU,
-/*00cc*/ 0x1801085cU,
-/*00cd*/ 0x0008085dU,
-/*00ce*/ 0x0808085dU,
-/*00cf*/ 0x1002085dU,
-/*00d0*/ 0x1802085dU,
-/*00d1*/ 0x0005085eU,
-/*00d2*/ 0x1005085eU,
-/*00d3*/ 0x1805085eU,
-/*00d4*/ 0x0004085fU,
-/*00d5*/ 0x080b085fU,
-/*00d6*/ 0x1806085fU,
-/*00d7*/ 0x00080860U,
-/*00d8*/ 0x08080860U,
-/*00d9*/ 0x10040860U,
-/*00da*/ 0x18040860U,
-/*00db*/ 0x00060861U,
-/*00dc*/ 0x08040861U,
-/*00dd*/ 0x10050861U,
-/*00de*/ 0x000a0862U,
-/*00df*/ 0x100a0862U,
-/*00e0*/ 0x00080863U,
-/*00e1*/ 0x08010863U,
-/*00e2*/ 0x10040863U,
-/*00e3*/ 0x00020864U,
-/*00e4*/ 0x08030864U,
-/*00e5*/ 0x00050a00U,
-/*00e6*/ 0x08050a00U,
-/*00e7*/ 0x10050a00U,
-/*00e8*/ 0x18050a00U,
-/*00e9*/ 0x00050a01U,
-/*00ea*/ 0x08050a01U,
-/*00eb*/ 0x100b0a01U,
-/*00ec*/ 0x00010a02U,
-/*00ed*/ 0x08030a02U,
-/*00ee*/ 0x00200a03U,
-/*00ef*/ 0x00100a04U,
-/*00f0*/ 0x10040a04U,
-/*00f1*/ 0x000b0a05U,
-/*00f2*/ 0x10070a05U,
-/*00f3*/ 0x00090a06U,
-/*00f4*/ 0x10030a06U,
-/*00f5*/ 0x18030a06U,
-/*00f6*/ 0x00010a07U,
-/*00f7*/ 0x08010a07U,
-/*00f8*/ 0x10070a07U,
-/*00f9*/ 0x18070a07U,
-/*00fa*/ 0x00050a08U,
-/*00fb*/ 0x08010a08U,
-/*00fc*/ 0x10020a08U,
-/*00fd*/ 0x18030a08U,
-/*00fe*/ 0x00010a09U,
-/*00ff*/ 0x080f0a09U,
-/*0100*/ 0x00200a0aU,
-/*0101*/ 0x00200a0bU,
-/*0102*/ 0x000b0a0cU,
-/*0103*/ 0x100b0a0cU,
-/*0104*/ 0x000b0a0dU,
-/*0105*/ 0x00180a0eU,
-/*0106*/ 0x00180a0fU,
-/*0107*/ 0xffffffffU,
-/*0108*/ 0xffffffffU,
-/*0109*/ 0xffffffffU,
-/*010a*/ 0xffffffffU,
-/*010b*/ 0xffffffffU,
-/*010c*/ 0x18020a0fU,
-/*010d*/ 0x00020a10U,
-/*010e*/ 0x08040a10U,
-/*010f*/ 0x10040a10U,
-/*0110*/ 0x18010a10U,
-/*0111*/ 0x00010a11U,
-/*0112*/ 0x08010a11U,
-/*0113*/ 0x10030a11U,
-/*0114*/ 0x00200a12U,
-/*0115*/ 0x00200a13U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140a14U,
-/*0118*/ 0x00140a15U,
-/*0119*/ 0x00140a16U,
-/*011a*/ 0x00140a17U,
-/*011b*/ 0x00140a18U,
-/*011c*/ 0x00140a19U,
-/*011d*/ 0x00140a1aU,
-/*011e*/ 0x00140a1bU,
-/*011f*/ 0x001e0a1cU,
-/*0120*/ 0x000a0a1dU,
-/*0121*/ 0x10060a1dU,
-/*0122*/ 0x18060a1dU,
-/*0123*/ 0x00060a1eU,
-/*0124*/ 0x08060a1eU,
-/*0125*/ 0x10060a1eU,
-/*0126*/ 0x00080a1fU,
-/*0127*/ 0x080b0a1fU,
-/*0128*/ 0x000b0a20U,
-/*0129*/ 0x100b0a20U,
-/*012a*/ 0x000b0a21U,
-/*012b*/ 0x100b0a21U,
-/*012c*/ 0x000b0a22U,
-/*012d*/ 0x10040a22U,
-/*012e*/ 0x000b0a23U,
-/*012f*/ 0x10060a23U,
-/*0130*/ 0x18080a23U,
-/*0131*/ 0x00080a24U,
-/*0132*/ 0x08040a24U,
-/*0133*/ 0x00020b80U,
-/*0134*/ 0x00010b81U,
-/*0135*/ 0x08010b81U,
-/*0136*/ 0x10020b81U,
-/*0137*/ 0x18050b81U,
-/*0138*/ 0x00050b82U,
-/*0139*/ 0x08050b82U,
-/*013a*/ 0x10050b82U,
-/*013b*/ 0x000b0b83U,
-/*013c*/ 0x10050b83U,
-/*013d*/ 0x18010b83U,
-/*013e*/ 0x00010b84U,
-/*013f*/ 0x08010b84U,
-/*0140*/ 0x10010b84U,
-/*0141*/ 0x18010b84U,
-/*0142*/ 0x00040b85U,
-/*0143*/ 0x080b0b85U,
-/*0144*/ 0x000b0b86U,
-/*0145*/ 0x100b0b86U,
-/*0146*/ 0x00040b87U,
-/*0147*/ 0x080b0b87U,
-/*0148*/ 0x18040b87U,
-/*0149*/ 0x00010b88U,
-/*014a*/ 0x08010b88U,
-/*014b*/ 0x10010b88U,
-/*014c*/ 0x00200b89U,
-/*014d*/ 0x00200b8aU,
-/*014e*/ 0x00080b8bU,
-/*014f*/ 0x080a0b8bU,
-/*0150*/ 0x18050b8bU,
-/*0151*/ 0x000b0b8cU,
-/*0152*/ 0x10030b8cU,
-/*0153*/ 0x18030b8cU,
-/*0154*/ 0x00010b8dU,
-/*0155*/ 0x08020b8dU,
-/*0156*/ 0x10010b8dU,
-/*0157*/ 0x18010b8dU,
-/*0158*/ 0x00010b8eU,
-/*0159*/ 0xffffffffU,
-/*015a*/ 0x08010b8eU,
-/*015b*/ 0x18040b8eU,
-/*015c*/ 0x00040b8fU,
-/*015d*/ 0x08040b8fU,
-/*015e*/ 0x10040b8fU,
-/*015f*/ 0x18010b8fU,
-/*0160*/ 0x00010b90U,
-/*0161*/ 0x08010b90U,
-/*0162*/ 0x00200b91U,
-/*0163*/ 0x00200b92U,
-/*0164*/ 0x00200b93U,
-/*0165*/ 0x00200b94U,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0x10010b8eU,
-/*0168*/ 0x000d0b96U,
-/*0169*/ 0x100d0b96U,
-/*016a*/ 0x000d0b97U,
-/*016b*/ 0x00050b98U,
-/*016c*/ 0x00010b99U,
-/*016d*/ 0x080e0b99U,
-/*016e*/ 0x000e0b9aU,
-/*016f*/ 0x100e0b9aU,
-/*0170*/ 0x000e0b9bU,
-/*0171*/ 0x100e0b9bU,
-/*0172*/ 0x00040b9cU,
-/*0173*/ 0x08040b9cU,
-/*0174*/ 0x10040b9cU,
-/*0175*/ 0x18040b9cU,
-/*0176*/ 0x00040b9dU,
-/*0177*/ 0x080b0b9dU,
-/*0178*/ 0x000b0b9eU,
-/*0179*/ 0x100b0b9eU,
-/*017a*/ 0x000b0b9fU,
-/*017b*/ 0x00040ba0U,
-/*017c*/ 0x08040ba0U,
-/*017d*/ 0x10040ba0U,
-/*017e*/ 0x18040ba0U,
-/*017f*/ 0x000d0ba1U,
-/*0180*/ 0x100d0ba1U,
-/*0181*/ 0x000d0ba2U,
-/*0182*/ 0x10100ba2U,
-/*0183*/ 0x00080b95U,
-/*0184*/ 0x08080b95U,
-/*0185*/ 0x00100ba3U,
-/*0186*/ 0x10100ba3U,
-/*0187*/ 0x00100ba4U,
-/*0188*/ 0x10100ba4U,
-/*0189*/ 0x00100ba5U,
-/*018a*/ 0x10030ba5U,
-/*018b*/ 0x18040ba5U,
-/*018c*/ 0x00010ba6U,
-/*018d*/ 0x08080ba6U,
-/*018e*/ 0x10010ba6U,
-/*018f*/ 0x000a0ba7U,
-/*0190*/ 0x10010ba7U,
-/*0191*/ 0x00140ba8U,
-/*0192*/ 0x000b0ba9U,
-/*0193*/ 0x100c0ba9U,
-/*0194*/ 0x00120baaU,
-/*0195*/ 0x00140babU,
-/*0196*/ 0x00120bacU,
-/*0197*/ 0x00110badU,
-/*0198*/ 0x00110baeU,
-/*0199*/ 0x00120bafU,
-/*019a*/ 0x00120bb0U,
-/*019b*/ 0x00120bb1U,
-/*019c*/ 0x00120bb2U,
-/*019d*/ 0x00120bb3U,
-/*019e*/ 0x00120bb4U,
-/*019f*/ 0x00120bb5U,
-/*01a0*/ 0x00120bb6U,
-/*01a1*/ 0x00120bb7U,
-/*01a2*/ 0x00120bb8U,
-/*01a3*/ 0x000e0bb9U,
-/*01a4*/ 0x100d0bb9U,
-/*01a5*/ 0x00200bbaU,
-/*01a6*/ 0x00170bbbU,
-/*01a7*/ 0x000d0bbcU,
-/*01a8*/ 0x10010bbcU,
-/*01a9*/ 0x18010bbcU,
-/*01aa*/ 0x00200bbdU,
-/*01ab*/ 0x00080bbeU,
-/*01ac*/ 0x08030bbeU,
-/*01ad*/ 0x10030bbeU,
-/*01ae*/ 0x00180bbfU,
-/*01af*/ 0x00180bc0U,
-/*01b0*/ 0x18070bc0U,
-/*01b1*/ 0x00070bc1U,
-/*01b2*/ 0x08080bc1U,
-/*01b3*/ 0x10080bc1U,
-/*01b4*/ 0x18080bc1U,
-/*01b5*/ 0x00010bc2U,
-/*01b6*/ 0x08010bc2U,
-/*01b7*/ 0x00200bc3U,
-/*01b8*/ 0x00070bc4U,
-/*01b9*/ 0x08140bc4U,
-/*01ba*/ 0x00140bc5U,
-/*01bb*/ 0x00190bc6U,
-/*01bc*/ 0x00170bc7U,
-/*01bd*/ 0x00110bc8U,
-/*01be*/ 0x00110bc9U,
-/*01bf*/ 0x00100bcaU,
-/*01c0*/ 0x10010bcaU,
-/*01c1*/ 0x18010bcaU,
-/*01c2*/ 0x00020bcbU,
-/*01c3*/ 0x08040bcbU,
-/*01c4*/ 0x10090bcbU,
-/*01c5*/ 0x00070bccU,
-/*01c6*/ 0x08040bccU,
-/*01c7*/ 0x00200bcdU,
-/*01c8*/ 0x00010bceU,
-/*01c9*/ 0x08020bceU,
-/*01ca*/ 0x10060bceU,
-/*01cb*/ 0x00100bcfU,
-/*01cc*/ 0x10010bcfU,
-/*01cd*/ 0x00200bd0U,
-/*01ce*/ 0x00080bd1U,
-/*01cf*/ 0x08010bd1U,
-/*01d0*/ 0x10050bd1U,
-/*01d1*/ 0x18030bd1U,
-/*01d2*/ 0x00020bd2U,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200bd3U,
-/*01d5*/ 0x000b0bd4U,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0x10030bd4U,
-/*01d8*/ 0x18080bd4U,
-/*01d9*/ 0x00020bd5U,
-/*01da*/ 0x080c0bd5U,
-/*01db*/ 0x18040bd5U,
-/*01dc*/ 0x00010bd6U,
-/*01dd*/ 0x08050bd6U,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0x10010201U,
-/*01e4*/ 0x18010201U,
-/*01e5*/ 0x00100202U,
-/*01e6*/ 0x10080202U,
-/*01e7*/ 0x18010202U,
-/*01e8*/ 0x00200203U,
-/*01e9*/ 0x00200204U,
-/*01ea*/ 0x00200205U,
-/*01eb*/ 0x00200206U,
-/*01ec*/ 0x00020207U,
-/*01ed*/ 0x08010207U,
-/*01ee*/ 0x10010207U,
-/*01ef*/ 0x00200208U,
-/*01f0*/ 0x00140209U,
-/*01f1*/ 0x0020020aU,
-/*01f2*/ 0x0014020bU,
-/*01f3*/ 0x0020020cU,
-/*01f4*/ 0x0014020dU,
-/*01f5*/ 0x0014020eU,
-/*01f6*/ 0x0020020fU,
-/*01f7*/ 0x00200210U,
-/*01f8*/ 0x00200211U,
-/*01f9*/ 0x00200212U,
-/*01fa*/ 0x00140213U,
-/*01fb*/ 0x00200214U,
-/*01fc*/ 0x00200215U,
-/*01fd*/ 0x00200216U,
-/*01fe*/ 0x00200217U,
-/*01ff*/ 0x00140218U,
-/*0200*/ 0x00200219U,
-/*0201*/ 0x0020021aU,
-/*0202*/ 0x0020021bU,
-/*0203*/ 0x0020021cU,
-/*0204*/ 0x0009021dU,
-/*0205*/ 0x1001021dU,
-/*0206*/ 0x0020021eU,
-/*0207*/ 0x0005021fU,
-/*0208*/ 0x0801021fU,
-/*0209*/ 0x1008021fU,
-/*020a*/ 0x1808021fU,
-/*020b*/ 0x001e0220U,
-/*020c*/ 0x001e0221U,
-/*020d*/ 0x001e0222U,
-/*020e*/ 0x001e0223U,
-/*020f*/ 0x001e0224U,
-/*0210*/ 0x001e0225U,
-/*0211*/ 0x001e0226U,
-/*0212*/ 0x001e0227U,
-/*0213*/ 0x001e0228U,
-/*0214*/ 0x001e0229U,
-/*0215*/ 0x001e022aU,
-/*0216*/ 0x001e022bU,
-/*0217*/ 0x001e022cU,
-/*0218*/ 0x001e022dU,
-/*0219*/ 0x001e022eU,
-/*021a*/ 0x001e022fU,
-/*021b*/ 0x00010230U,
-/*021c*/ 0x08010230U,
-/*021d*/ 0x10010230U,
-/*021e*/ 0x18040230U,
-/*021f*/ 0x00080231U,
-/*0220*/ 0x08080231U,
-/*0221*/ 0x10080231U,
-/*0222*/ 0x18040231U,
-/*0223*/ 0x00070232U,
-/*0224*/ 0x08060232U,
-/*0225*/ 0x10070232U,
-/*0226*/ 0x18070232U,
-/*0227*/ 0x00060233U,
-/*0228*/ 0x08070233U,
-/*0229*/ 0x10070233U,
-/*022a*/ 0x18060233U,
-/*022b*/ 0x00070234U,
-/*022c*/ 0x08020234U,
-/*022d*/ 0x10010234U,
-/*022e*/ 0x18010234U,
-/*022f*/ 0x000a0235U,
-/*0230*/ 0x00140236U,
-/*0231*/ 0x000a0237U,
-/*0232*/ 0x00140238U,
-/*0233*/ 0x000a0239U,
-/*0234*/ 0x0014023aU,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0xffffffffU,
-/*0237*/ 0x0005023bU,
-/*0238*/ 0x0001023cU,
-/*0239*/ 0x1001023cU,
-/*023a*/ 0x1801023cU,
-/*023b*/ 0x0001023dU,
-/*023c*/ 0x0801023dU,
-/*023d*/ 0x1001023dU,
-/*023e*/ 0x1801023dU,
-/*023f*/ 0x0002023eU,
-/*0240*/ 0x0802023eU,
-/*0241*/ 0x1002023eU,
-/*0242*/ 0x1802023eU,
-/*0243*/ 0x0002023fU,
-/*0244*/ 0x0803023fU,
-/*0245*/ 0x1001023fU,
-/*0246*/ 0x1801023fU,
-/*0247*/ 0x00010240U,
-/*0248*/ 0x08010240U,
-/*0249*/ 0x10010240U,
-/*024a*/ 0x18020240U,
-/*024b*/ 0x00010241U,
-/*024c*/ 0x08010241U,
-/*024d*/ 0x10010241U,
-/*024e*/ 0x18020241U,
-/*024f*/ 0x00010242U,
-/*0250*/ 0x08010242U,
-/*0251*/ 0x10010242U,
-/*0252*/ 0x18020242U,
-/*0253*/ 0x00010243U,
-/*0254*/ 0x08010243U,
-/*0255*/ 0x10010243U,
-/*0256*/ 0x18020243U,
-/*0257*/ 0xffffffffU,
-/*0258*/ 0x00010244U,
-/*0259*/ 0x08010244U,
-/*025a*/ 0x10010244U,
-/*025b*/ 0x18010244U,
-/*025c*/ 0x00010245U,
-/*025d*/ 0x08010245U,
-/*025e*/ 0x10010245U,
-/*025f*/ 0x18010245U,
-/*0260*/ 0x00040246U,
-/*0261*/ 0x08040246U,
-/*0262*/ 0x10040246U,
-/*0263*/ 0x18010246U,
-/*0264*/ 0x00020247U,
-/*0265*/ 0x08060247U,
-/*0266*/ 0x10060247U,
-/*0267*/ 0x18020247U,
-/*0268*/ 0x00020248U,
-/*0269*/ 0x08020248U,
-/*026a*/ 0xffffffffU,
-/*026b*/ 0x10100248U,
-/*026c*/ 0x00010249U,
-/*026d*/ 0x08010249U,
-/*026e*/ 0x10010249U,
-/*026f*/ 0x18040249U,
-/*0270*/ 0x0001024aU,
-/*0271*/ 0x0804024aU,
-/*0272*/ 0x1003024aU,
-/*0273*/ 0x1808024aU,
-/*0274*/ 0x000a024bU,
-/*0275*/ 0x100a024bU,
-/*0276*/ 0x000a024cU,
-/*0277*/ 0xffffffffU,
-/*0278*/ 0x0020024dU,
-/*0279*/ 0x0020024eU,
-/*027a*/ 0x0005024fU,
-/*027b*/ 0x1801023aU,
-/*027c*/ 0x0805023cU,
-/*027d*/ 0x0808024fU,
-/*027e*/ 0x1001024fU,
-/*027f*/ 0x1808024fU,
-/*0280*/ 0x00010250U,
-/*0281*/ 0x08080250U,
-/*0282*/ 0x10010250U,
-/*0283*/ 0x18040250U,
-/*0284*/ 0x00040251U,
-/*0285*/ 0x08040251U,
-/*0286*/ 0x10040251U,
-/*0287*/ 0x18040251U,
-/*0288*/ 0x00040252U,
-/*0289*/ 0x08040252U,
-/*028a*/ 0x10040252U,
-/*028b*/ 0x18040252U,
-/*028c*/ 0x00040253U,
-/*028d*/ 0x08010253U,
-/*028e*/ 0x10040253U,
-/*028f*/ 0x18040253U,
-/*0290*/ 0x00040254U,
-/*0291*/ 0x08040254U,
-/*0292*/ 0x10040254U,
-/*0293*/ 0x18040254U,
-/*0294*/ 0x00060255U,
-/*0295*/ 0x08060255U,
-/*0296*/ 0x10060255U,
-/*0297*/ 0x18060255U,
-/*0298*/ 0x00060256U,
-/*0299*/ 0x08060256U,
-/*029a*/ 0x10040256U,
-/*029b*/ 0x18010256U,
-/*029c*/ 0x00010257U,
-/*029d*/ 0x08020257U,
-/*029e*/ 0x00200258U,
-/*029f*/ 0x00200259U,
-/*02a0*/ 0x0020025aU,
-/*02a1*/ 0x0020025bU,
-/*02a2*/ 0x0020025cU,
-/*02a3*/ 0x0020025dU,
-/*02a4*/ 0x0020025eU,
-/*02a5*/ 0x0020025fU,
-/*02a6*/ 0x00040260U,
-/*02a7*/ 0x08040260U,
-/*02a8*/ 0x10010260U,
-/*02a9*/ 0x18010260U,
-/*02aa*/ 0x00010261U,
-/*02ab*/ 0x08010261U,
-/*02ac*/ 0x10010261U,
-/*02ad*/ 0x18010261U,
-/*02ae*/ 0x00010262U,
-/*02af*/ 0x08010262U,
-/*02b0*/ 0x10010262U,
-/*02b1*/ 0x18040262U,
-/*02b2*/ 0x00040263U,
-/*02b3*/ 0x080a0263U,
-/*02b4*/ 0x00200264U,
-/*02b5*/ 0x00040265U,
-/*02b6*/ 0x08080265U,
-/*02b7*/ 0x10020265U,
-/*02b8*/ 0x18020265U,
-/*02b9*/ 0x00020266U,
-/*02ba*/ 0x08020266U,
-/*02bb*/ 0x10020266U,
-/*02bc*/ 0x18020266U,
-/*02bd*/ 0xffffffffU,
-/*02be*/ 0xffffffffU,
-/*02bf*/ 0x00200267U,
-/*02c0*/ 0x00030268U,
-/*02c1*/ 0x08100268U,
-/*02c2*/ 0x00100269U,
-/*02c3*/ 0x10040269U,
-/*02c4*/ 0x18040269U,
-/*02c5*/ 0x0005026aU,
-/*02c6*/ 0x0805026aU,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x1001026aU,
-/*02cc*/ 0x1801026aU,
-/*02cd*/ 0x0008026bU,
-/*02ce*/ 0x0808026bU,
-/*02cf*/ 0x1008026bU,
-/*02d0*/ 0x1808026bU,
-/*02d1*/ 0x0008026cU,
-/*02d2*/ 0x0808026cU,
-/*02d3*/ 0x1008026cU,
-/*02d4*/ 0x1808026cU,
-/*02d5*/ 0x0008026dU,
-/*02d6*/ 0x0808026dU,
-/*02d7*/ 0x1008026dU,
-/*02d8*/ 0x1808026dU,
-/*02d9*/ 0x0008026eU,
-/*02da*/ 0x0808026eU,
-/*02db*/ 0x1003026eU,
-/*02dc*/ 0x1803026eU,
-/*02dd*/ 0x0003026fU,
-/*02de*/ 0xffffffffU,
-/*02df*/ 0x0801026fU,
-/*02e0*/ 0x1002026fU,
-/*02e1*/ 0x1801026fU,
-/*02e2*/ 0x00040270U,
-/*02e3*/ 0x08020270U,
-/*02e4*/ 0x10010270U,
-/*02e5*/ 0x18010270U,
-/*02e6*/ 0x00010271U,
-/*02e7*/ 0x08010271U,
-/*02e8*/ 0x10040271U,
-/*02e9*/ 0x18080271U,
-/*02ea*/ 0x000a0272U,
-/*02eb*/ 0x100a0272U,
-/*02ec*/ 0x000a0273U,
-/*02ed*/ 0x100a0273U,
-/*02ee*/ 0x000a0274U,
-/*02ef*/ 0x100a0274U,
-/*02f0*/ 0x00200275U,
-/*02f1*/ 0x00200276U,
-/*02f2*/ 0x00010277U,
-/*02f3*/ 0x08020277U,
-/*02f4*/ 0x10020277U,
-/*02f5*/ 0x18020277U,
-/*02f6*/ 0xffffffffU,
-/*02f7*/ 0x00020278U,
-/*02f8*/ 0x08100278U,
-/*02f9*/ 0x18050278U,
-/*02fa*/ 0x00060279U,
-/*02fb*/ 0x08050279U,
-/*02fc*/ 0x10050279U,
-/*02fd*/ 0x000e027aU,
-/*02fe*/ 0x1005027aU,
-/*02ff*/ 0x000e027bU,
-/*0300*/ 0x1005027bU,
-/*0301*/ 0x000e027cU,
-/*0302*/ 0x1005027cU,
-/*0303*/ 0x1801027cU,
-/*0304*/ 0x0005027dU,
-/*0305*/ 0x0805027dU,
-/*0306*/ 0x100a027dU,
-/*0307*/ 0x000a027eU,
-/*0308*/ 0x1005027eU,
-/*0309*/ 0x1805027eU,
-/*030a*/ 0x000a027fU,
-/*030b*/ 0x100a027fU,
-/*030c*/ 0x00050280U,
-/*030d*/ 0x08050280U,
-/*030e*/ 0x100a0280U,
-/*030f*/ 0x000a0281U,
-/*0310*/ 0x10070281U,
-/*0311*/ 0x18070281U,
-/*0312*/ 0x00070282U,
-/*0313*/ 0x08070282U,
-/*0314*/ 0x10070282U,
-/*0315*/ 0x18070282U,
-/*0316*/ 0xffffffffU,
-/*0317*/ 0xffffffffU,
-/*0318*/ 0x00040283U,
-/*0319*/ 0x08040283U,
-/*031a*/ 0x10040283U,
-/*031b*/ 0x18040283U,
-/*031c*/ 0x00040284U,
-/*031d*/ 0xffffffffU,
-/*031e*/ 0x08080284U,
-/*031f*/ 0x10080284U,
-/*0320*/ 0x18040284U,
-/*0321*/ 0x00050285U,
-/*0322*/ 0x08080285U,
-/*0323*/ 0x10050285U,
-/*0324*/ 0x18040285U,
-/*0325*/ 0x00050286U,
-/*0326*/ 0x08080286U,
-/*0327*/ 0x10050286U,
-/*0328*/ 0x18040286U,
-/*0329*/ 0x00050287U,
-/*032a*/ 0x08080287U,
-/*032b*/ 0x10050287U,
-/*032c*/ 0x18040287U,
-/*032d*/ 0x00050288U,
-/*032e*/ 0x08070288U,
-/*032f*/ 0x10080288U,
-/*0330*/ 0x00100289U,
-/*0331*/ 0x10080289U,
-/*0332*/ 0x0010028aU,
-/*0333*/ 0x1008028aU,
-/*0334*/ 0x0010028bU,
-/*0335*/ 0x1008028bU,
-/*0336*/ 0x1808028bU,
-/*0337*/ 0x0001028cU,
-/*0338*/ 0x0801028cU,
-/*0339*/ 0x1006028cU,
-/*033a*/ 0x1806028cU,
-/*033b*/ 0x0006028dU,
-/*033c*/ 0x0801028dU,
-/*033d*/ 0x1001028dU,
-/*033e*/ 0x1803028dU,
-/*033f*/ 0x000a028eU,
-/*0340*/ 0x100a028eU,
-/*0341*/ 0x000a028fU,
-/*0342*/ 0xffffffffU,
-/*0343*/ 0x100a028fU,
-/*0344*/ 0x00040290U,
-/*0345*/ 0x08010290U,
-/*0346*/ 0x10040290U,
-/*0347*/ 0x18070290U,
-/*0348*/ 0x00070291U,
-/*0349*/ 0x08070291U,
-/*034a*/ 0x10070291U,
-/*034b*/ 0x18070291U,
-/*034c*/ 0x00070292U,
-/*034d*/ 0xffffffffU,
-/*034e*/ 0xffffffffU,
-/*034f*/ 0x08050292U,
-/*0350*/ 0x10050292U,
-/*0351*/ 0x18040292U,
-/*0352*/ 0x00040293U,
-/*0353*/ 0x08040293U,
-/*0354*/ 0xffffffffU,
-/*0355*/ 0x10010293U,
-/*0356*/ 0x18010293U,
-/*0357*/ 0x00020294U,
-/*0358*/ 0x08080294U,
-/*0359*/ 0x00200295U,
-/*035a*/ 0x00200296U,
-/*035b*/ 0x00100297U,
-/*035c*/ 0x10020297U,
-/*035d*/ 0x18020297U,
-/*035e*/ 0x00020298U,
-/*035f*/ 0xffffffffU,
-/*0360*/ 0x08010298U,
-/*0361*/ 0x10010298U,
-/*0362*/ 0x18020298U,
-/*0363*/ 0x00100299U,
-/*0364*/ 0x10100299U,
-/*0365*/ 0x0010029aU,
-/*0366*/ 0x1008029aU,
-/*0367*/ 0x1808029aU,
-/*0368*/ 0x0008029bU,
-/*0369*/ 0x0808029bU,
-/*036a*/ 0x1010029bU,
-/*036b*/ 0x0010029cU,
-/*036c*/ 0x1010029cU,
-/*036d*/ 0x0008029dU,
-/*036e*/ 0x0808029dU,
-/*036f*/ 0x1008029dU,
-/*0370*/ 0x1808029dU,
-/*0371*/ 0x0010029eU,
-/*0372*/ 0x1010029eU,
-/*0373*/ 0x0010029fU,
-/*0374*/ 0x1008029fU,
-/*0375*/ 0x1808029fU,
-/*0376*/ 0x000802a0U,
-/*0377*/ 0x080802a0U,
-/*0378*/ 0x100802a0U,
-/*0379*/ 0x001002a1U,
-/*037a*/ 0x101002a1U,
-/*037b*/ 0x001002a2U,
-/*037c*/ 0x100802a2U,
-/*037d*/ 0x180802a2U,
-/*037e*/ 0x000802a3U,
-/*037f*/ 0x080802a3U,
-/*0380*/ 0x101002a3U,
-/*0381*/ 0x001002a4U,
-/*0382*/ 0x101002a4U,
-/*0383*/ 0x000802a5U,
-/*0384*/ 0x080802a5U,
-/*0385*/ 0x100802a5U,
-/*0386*/ 0x180802a5U,
-/*0387*/ 0x001002a6U,
-/*0388*/ 0x101002a6U,
-/*0389*/ 0x001002a7U,
-/*038a*/ 0x100802a7U,
-/*038b*/ 0x180802a7U,
-/*038c*/ 0x000802a8U,
-/*038d*/ 0x080802a8U,
-/*038e*/ 0x100802a8U,
-/*038f*/ 0x001002a9U,
-/*0390*/ 0x101002a9U,
-/*0391*/ 0x001002aaU,
-/*0392*/ 0x100802aaU,
-/*0393*/ 0x180802aaU,
-/*0394*/ 0x000802abU,
-/*0395*/ 0x080802abU,
-/*0396*/ 0x101002abU,
-/*0397*/ 0x001002acU,
-/*0398*/ 0x101002acU,
-/*0399*/ 0x000802adU,
-/*039a*/ 0x080802adU,
-/*039b*/ 0x100802adU,
-/*039c*/ 0x180802adU,
-/*039d*/ 0x001002aeU,
-/*039e*/ 0x101002aeU,
-/*039f*/ 0x001002afU,
-/*03a0*/ 0x100802afU,
-/*03a1*/ 0x180802afU,
-/*03a2*/ 0x000802b0U,
-/*03a3*/ 0x080802b0U,
-/*03a4*/ 0x100802b0U,
-/*03a5*/ 0x001002b1U,
-/*03a6*/ 0x101002b1U,
-/*03a7*/ 0x001002b2U,
-/*03a8*/ 0x100802b2U,
-/*03a9*/ 0x180802b2U,
-/*03aa*/ 0x000802b3U,
-/*03ab*/ 0x080802b3U,
-/*03ac*/ 0x101002b3U,
-/*03ad*/ 0x001002b4U,
-/*03ae*/ 0x101002b4U,
-/*03af*/ 0x000802b5U,
-/*03b0*/ 0x080802b5U,
-/*03b1*/ 0x100802b5U,
-/*03b2*/ 0x180802b5U,
-/*03b3*/ 0x001002b6U,
-/*03b4*/ 0x101002b6U,
-/*03b5*/ 0x001002b7U,
-/*03b6*/ 0x100802b7U,
-/*03b7*/ 0x180802b7U,
-/*03b8*/ 0x000802b8U,
-/*03b9*/ 0x080802b8U,
-/*03ba*/ 0x100802b8U,
-/*03bb*/ 0x180202b8U,
-/*03bc*/ 0x000302b9U,
-/*03bd*/ 0x080a02b9U,
-/*03be*/ 0x000a02baU,
-/*03bf*/ 0x100a02baU,
-/*03c0*/ 0x000502bbU,
-/*03c1*/ 0x080802bbU,
-/*03c2*/ 0x100802bbU,
-/*03c3*/ 0x180802bbU,
-/*03c4*/ 0x000602bcU,
-/*03c5*/ 0x080602bcU,
-/*03c6*/ 0x001102bdU,
-/*03c7*/ 0x180802bdU,
-/*03c8*/ 0x000402beU,
-/*03c9*/ 0x080602beU,
-/*03ca*/ 0x100802beU,
-/*03cb*/ 0x180802beU,
-/*03cc*/ 0x000802bfU,
-/*03cd*/ 0x080802bfU,
-/*03ce*/ 0x100802bfU,
-/*03cf*/ 0x180802bfU,
-/*03d0*/ 0x000802c0U,
-/*03d1*/ 0x080602c0U,
-/*03d2*/ 0x100602c0U,
-/*03d3*/ 0x001102c1U,
-/*03d4*/ 0x180802c1U,
-/*03d5*/ 0x000402c2U,
-/*03d6*/ 0x080602c2U,
-/*03d7*/ 0x100802c2U,
-/*03d8*/ 0x180802c2U,
-/*03d9*/ 0x000802c3U,
-/*03da*/ 0x080802c3U,
-/*03db*/ 0x100802c3U,
-/*03dc*/ 0x180802c3U,
-/*03dd*/ 0x000802c4U,
-/*03de*/ 0x080602c4U,
-/*03df*/ 0x100602c4U,
-/*03e0*/ 0x001102c5U,
-/*03e1*/ 0x180802c5U,
-/*03e2*/ 0x000402c6U,
-/*03e3*/ 0x080602c6U,
-/*03e4*/ 0x100802c6U,
-/*03e5*/ 0x180802c6U,
-/*03e6*/ 0x000802c7U,
-/*03e7*/ 0x080802c7U,
-/*03e8*/ 0x100402c7U,
-/*03e9*/ 0x180402c7U,
-/*03ea*/ 0x000402c8U,
-/*03eb*/ 0x080402c8U,
-/*03ec*/ 0x100402c8U,
-/*03ed*/ 0x180402c8U,
-/*03ee*/ 0x000402c9U,
-/*03ef*/ 0x080402c9U,
-/*03f0*/ 0x100402c9U,
-/*03f1*/ 0x180402c9U,
-/*03f2*/ 0x000402caU,
-/*03f3*/ 0x080402caU,
-/*03f4*/ 0x100402caU,
-/*03f5*/ 0x180402caU,
-/*03f6*/ 0x000402cbU,
-/*03f7*/ 0x080402cbU,
-/*03f8*/ 0x100402cbU,
-/*03f9*/ 0x180402cbU,
-/*03fa*/ 0x000402ccU,
-/*03fb*/ 0x080402ccU,
-/*03fc*/ 0x001702cdU,
-/*03fd*/ 0x001602ceU,
-/*03fe*/ 0x001702cfU,
-/*03ff*/ 0x002002d0U,
-/*0400*/ 0x002002d1U,
-/*0401*/ 0x002002d2U,
-/*0402*/ 0x002002d3U,
-/*0403*/ 0x002002d4U,
-/*0404*/ 0x002002d5U,
-/*0405*/ 0x002002d6U,
-/*0406*/ 0x002002d7U,
-/*0407*/ 0x002002d8U,
-/*0408*/ 0x000202d9U,
-/*0409*/ 0x080502d9U,
-/*040a*/ 0x100502d9U,
-/*040b*/ 0x180102d9U,
-/*040c*/ 0x000502daU,
-/*040d*/ 0x080502daU,
-/*040e*/ 0x100502daU,
-/*040f*/ 0x180502daU,
-/*0410*/ 0x000502dbU,
-/*0411*/ 0x080502dbU,
-/*0412*/ 0x100502dbU,
-/*0413*/ 0x180502dbU,
-/*0414*/ 0x000502dcU,
-/*0415*/ 0x080502dcU,
-/*0416*/ 0x100502dcU,
-/*0417*/ 0x180502dcU,
-/*0418*/ 0x000502ddU,
-/*0419*/ 0x080502ddU,
-/*041a*/ 0x100502ddU,
-/*041b*/ 0x180502ddU,
-/*041c*/ 0x000502deU,
-/*041d*/ 0x080502deU,
-/*041e*/ 0x100502deU,
-/*041f*/ 0x180502deU,
-/*0420*/ 0x000502dfU,
-/*0421*/ 0x080502dfU,
-/*0422*/ 0x100102dfU,
-/*0423*/ 0x180202dfU,
-/*0424*/ 0x000202e0U,
-/*0425*/ 0x080202e0U,
-/*0426*/ 0x100202e0U,
-/*0427*/ 0x180102e0U,
-/*0428*/ 0x000802e1U,
-/*0429*/ 0x081502e1U,
-/*042a*/ 0x002002e2U,
-/*042b*/ 0x001502e3U,
-/*042c*/ 0x002002e4U,
-/*042d*/ 0x001502e5U,
-/*042e*/ 0x002002e6U,
-/*042f*/ 0x000702e7U,
-/*0430*/ 0x080102e7U,
-/*0431*/ 0x100202e7U,
-/*0432*/ 0x180602e7U,
-/*0433*/ 0x000102e8U,
-/*0434*/ 0x080102e8U,
-/*0435*/ 0x002002e9U,
-/*0436*/ 0x000202eaU,
-/*0437*/ 0x002002ebU,
-/*0438*/ 0x002002ecU,
-/*0439*/ 0x000c02edU,
-/*043a*/ 0x100c02edU,
-/*043b*/ 0x002002eeU,
-/*043c*/ 0x000302efU,
-/*043d*/ 0x002002f0U,
-/*043e*/ 0x000302f1U,
-/*043f*/ 0x002002f2U,
-/*0440*/ 0x000302f3U,
-/*0441*/ 0x002002f4U,
-/*0442*/ 0x000302f5U,
-/*0443*/ 0x002002f6U,
-/*0444*/ 0x000302f7U,
-/*0445*/ 0x002002f8U,
-/*0446*/ 0x000302f9U,
-/*0447*/ 0x002002faU,
-/*0448*/ 0x000302fbU,
-/*0449*/ 0x002002fcU,
-/*044a*/ 0x000302fdU,
-/*044b*/ 0x002002feU,
-/*044c*/ 0x000302ffU,
-/*044d*/ 0x00200300U,
-/*044e*/ 0x00030301U,
-/*044f*/ 0x08030301U,
-/*0450*/ 0x10020301U,
-/*0451*/ 0x18020301U,
-/*0452*/ 0x00200302U,
-/*0453*/ 0x00200303U,
-/*0454*/ 0x00200304U,
-/*0455*/ 0x00200305U,
-/*0456*/ 0x00040306U,
-/*0457*/ 0x001e0307U,
-/*0458*/ 0x001e0308U,
-/*0459*/ 0x001e0309U,
-/*045a*/ 0x001e030aU,
-/*045b*/ 0x001e030bU,
-/*045c*/ 0x001e030cU,
-/*045d*/ 0x001e030dU,
-/*045e*/ 0x001e030eU,
-/*045f*/ 0x0004030fU,
-/*0460*/ 0x0801030fU,
-/*0461*/ 0x1010030fU,
-/*0462*/ 0x00100310U,
-/*0463*/ 0x10100310U,
-/*0464*/ 0x00040311U,
-/*0465*/ 0x08010311U,
-/*0466*/ 0x10080311U,
-/*0467*/ 0x18040311U,
-/*0468*/ 0x00010312U,
-/*0469*/ 0x08080312U,
-/*046a*/ 0x10040312U,
-/*046b*/ 0x18010312U,
-/*046c*/ 0x00080313U,
-/*046d*/ 0x08040313U,
-/*046e*/ 0x10010313U,
-/*046f*/ 0x18080313U,
-/*0470*/ 0x00040314U,
-/*0471*/ 0x08010314U,
-/*0472*/ 0x10080314U,
-/*0473*/ 0x18040314U,
-/*0474*/ 0x00010315U,
-/*0475*/ 0x08080315U,
-/*0476*/ 0x10040315U,
-/*0477*/ 0x18010315U,
-/*0478*/ 0x00080316U,
-/*0479*/ 0x08040316U,
-/*047a*/ 0x10010316U,
-/*047b*/ 0x18080316U,
-/*047c*/ 0x00080317U,
-/*047d*/ 0x00010318U,
-/*047e*/ 0x08050318U,
-/*047f*/ 0x10010318U,
-/*0480*/ 0x18020318U,
-/*0481*/ 0x00010319U,
-/*0482*/ 0x08010319U,
-/*0483*/ 0x10010319U,
-/*0484*/ 0x18010319U,
-/*0485*/ 0x0001031aU,
-/*0486*/ 0x0801031aU,
-/*0487*/ 0x1001031aU,
-/*0488*/ 0x1801031aU,
-/*0489*/ 0x0001031bU,
-/*048a*/ 0x0801031bU,
-/*048b*/ 0x1001031bU,
-/*048c*/ 0x1801031bU,
-/*048d*/ 0x0001031cU,
-/*048e*/ 0x0801031cU,
-/*048f*/ 0x1001031cU,
-/*0490*/ 0x1801031cU,
-/*0491*/ 0x0008031dU,
-/*0492*/ 0x0808031dU,
-/*0493*/ 0x1008031dU,
-/*0494*/ 0x1808031dU,
-	}
-};
-
-#endif /* RZG_DDR_REGDEF_H */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h b/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h
deleted file mode 100644
index e10162a..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/*
- * Copyright (c) 2020U, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_INIT_DRAM_TABLE_G2M_H
-#define RZG_INIT_DRAM_TABLE_G2M_H
-
-#define DDR_PHY_SLICE_REGSET_OFS_G2M  0x0800U
-#define DDR_PHY_ADR_V_REGSET_OFS_G2M  0x0a00U
-#define DDR_PHY_ADR_I_REGSET_OFS_G2M  0x0a80U
-#define DDR_PHY_ADR_G_REGSET_OFS_G2M  0x0b80U
-#define DDR_PI_REGSET_OFS_G2M         0x0200U
-
-#define DDR_PHY_SLICE_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_V_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_I_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_G_REGSET_SIZE_G2M 0x80U
-#define DDR_PI_REGSET_SIZE_G2M        0x100U
-
-#define DDR_PHY_SLICE_REGSET_NUM_G2M  89
-#define DDR_PHY_ADR_V_REGSET_NUM_G2M  37
-#define DDR_PHY_ADR_I_REGSET_NUM_G2M  37
-#define DDR_PHY_ADR_G_REGSET_NUM_G2M  64
-#define DDR_PI_REGSET_NUM_G2M         202
-
-static const uint32_t DDR_PHY_SLICE_REGSET_G2M[DDR_PHY_SLICE_REGSET_NUM_G2M] = {
-	/*0800*/ 0x76543210U,
-	/*0801*/ 0x0004f008U,
-	/*0802*/ 0x00000000U,
-	/*0803*/ 0x00000000U,
-	/*0804*/ 0x00010000U,
-	/*0805*/ 0x036e6e0eU,
-	/*0806*/ 0x026e6e0eU,
-	/*0807*/ 0x00010300U,
-	/*0808*/ 0x04000100U,
-	/*0809*/ 0x00000300U,
-	/*080a*/ 0x001700c0U,
-	/*080b*/ 0x00b00201U,
-	/*080c*/ 0x00030020U,
-	/*080d*/ 0x00000000U,
-	/*080e*/ 0x00000000U,
-	/*080f*/ 0x00000000U,
-	/*0810*/ 0x00000000U,
-	/*0811*/ 0x00000000U,
-	/*0812*/ 0x00000000U,
-	/*0813*/ 0x00000000U,
-	/*0814*/ 0x09000000U,
-	/*0815*/ 0x04080000U,
-	/*0816*/ 0x04080400U,
-	/*0817*/ 0x00000000U,
-	/*0818*/ 0x32103210U,
-	/*0819*/ 0x00800708U,
-	/*081a*/ 0x000f000cU,
-	/*081b*/ 0x00000100U,
-	/*081c*/ 0x55aa55aaU,
-	/*081d*/ 0x33cc33ccU,
-	/*081e*/ 0x0ff00ff0U,
-	/*081f*/ 0x0f0ff0f0U,
-	/*0820*/ 0x00018e38U,
-	/*0821*/ 0x00000000U,
-	/*0822*/ 0x00000000U,
-	/*0823*/ 0x00000000U,
-	/*0824*/ 0x00000000U,
-	/*0825*/ 0x00000000U,
-	/*0826*/ 0x00000000U,
-	/*0827*/ 0x00000000U,
-	/*0828*/ 0x00000000U,
-	/*0829*/ 0x00000000U,
-	/*082a*/ 0x00000000U,
-	/*082b*/ 0x00000000U,
-	/*082c*/ 0x00000000U,
-	/*082d*/ 0x00000000U,
-	/*082e*/ 0x00000000U,
-	/*082f*/ 0x00000000U,
-	/*0830*/ 0x00000000U,
-	/*0831*/ 0x00000000U,
-	/*0832*/ 0x00000000U,
-	/*0833*/ 0x00200000U,
-	/*0834*/ 0x08200820U,
-	/*0835*/ 0x08200820U,
-	/*0836*/ 0x08200820U,
-	/*0837*/ 0x08200820U,
-	/*0838*/ 0x08200820U,
-	/*0839*/ 0x00000820U,
-	/*083a*/ 0x03000300U,
-	/*083b*/ 0x03000300U,
-	/*083c*/ 0x03000300U,
-	/*083d*/ 0x03000300U,
-	/*083e*/ 0x00000300U,
-	/*083f*/ 0x00000000U,
-	/*0840*/ 0x00000000U,
-	/*0841*/ 0x00000000U,
-	/*0842*/ 0x00000000U,
-	/*0843*/ 0x00a00000U,
-	/*0844*/ 0x00a000a0U,
-	/*0845*/ 0x00a000a0U,
-	/*0846*/ 0x00a000a0U,
-	/*0847*/ 0x00a000a0U,
-	/*0848*/ 0x00a000a0U,
-	/*0849*/ 0x00a000a0U,
-	/*084a*/ 0x00a000a0U,
-	/*084b*/ 0x00a000a0U,
-	/*084c*/ 0x010900a0U,
-	/*084d*/ 0x02000104U,
-	/*084e*/ 0x00000000U,
-	/*084f*/ 0x00010000U,
-	/*0850*/ 0x00000200U,
-	/*0851*/ 0x4041a151U,
-	/*0852*/ 0xc00141a0U,
-	/*0853*/ 0x0e0100c0U,
-	/*0854*/ 0x0010000cU,
-	/*0855*/ 0x0c064208U,
-	/*0856*/ 0x000f0c18U,
-	/*0857*/ 0x00e00140U,
-	/*0858*/ 0x00000c20U
-};
-
-static const uint32_t DDR_PHY_ADR_V_REGSET_G2M[DDR_PHY_ADR_V_REGSET_NUM_G2M] = {
-	/*0a00*/ 0x00000000U,
-	/*0a01*/ 0x00000000U,
-	/*0a02*/ 0x00000000U,
-	/*0a03*/ 0x00000000U,
-	/*0a04*/ 0x00000000U,
-	/*0a05*/ 0x00000000U,
-	/*0a06*/ 0x00000002U,
-	/*0a07*/ 0x00000000U,
-	/*0a08*/ 0x00000000U,
-	/*0a09*/ 0x00000000U,
-	/*0a0a*/ 0x00400320U,
-	/*0a0b*/ 0x00000040U,
-	/*0a0c*/ 0x00dcba98U,
-	/*0a0d*/ 0x00000000U,
-	/*0a0e*/ 0x00dcba98U,
-	/*0a0f*/ 0x01000000U,
-	/*0a10*/ 0x00020003U,
-	/*0a11*/ 0x00000000U,
-	/*0a12*/ 0x00000000U,
-	/*0a13*/ 0x00000000U,
-	/*0a14*/ 0x0000002aU,
-	/*0a15*/ 0x00000015U,
-	/*0a16*/ 0x00000015U,
-	/*0a17*/ 0x0000002aU,
-	/*0a18*/ 0x00000033U,
-	/*0a19*/ 0x0000000cU,
-	/*0a1a*/ 0x0000000cU,
-	/*0a1b*/ 0x00000033U,
-	/*0a1c*/ 0x0a418820U,
-	/*0a1d*/ 0x003f0000U,
-	/*0a1e*/ 0x0000003fU,
-	/*0a1f*/ 0x0002c06eU,
-	/*0a20*/ 0x02c002c0U,
-	/*0a21*/ 0x02c002c0U,
-	/*0a22*/ 0x000002c0U,
-	/*0a23*/ 0x42080010U,
-	/*0a24*/ 0x00000003U
-};
-
-static const uint32_t DDR_PHY_ADR_I_REGSET_G2M[DDR_PHY_ADR_I_REGSET_NUM_G2M] = {
-	/*0a80*/ 0x04040404U,
-	/*0a81*/ 0x00000404U,
-	/*0a82*/ 0x00000000U,
-	/*0a83*/ 0x00000000U,
-	/*0a84*/ 0x00000000U,
-	/*0a85*/ 0x00000000U,
-	/*0a86*/ 0x00000002U,
-	/*0a87*/ 0x00000000U,
-	/*0a88*/ 0x00000000U,
-	/*0a89*/ 0x00000000U,
-	/*0a8a*/ 0x00400320U,
-	/*0a8b*/ 0x00000040U,
-	/*0a8c*/ 0x00000000U,
-	/*0a8d*/ 0x00000000U,
-	/*0a8e*/ 0x00000000U,
-	/*0a8f*/ 0x01000000U,
-	/*0a90*/ 0x00020003U,
-	/*0a91*/ 0x00000000U,
-	/*0a92*/ 0x00000000U,
-	/*0a93*/ 0x00000000U,
-	/*0a94*/ 0x0000002aU,
-	/*0a95*/ 0x00000015U,
-	/*0a96*/ 0x00000015U,
-	/*0a97*/ 0x0000002aU,
-	/*0a98*/ 0x00000033U,
-	/*0a99*/ 0x0000000cU,
-	/*0a9a*/ 0x0000000cU,
-	/*0a9b*/ 0x00000033U,
-	/*0a9c*/ 0x00000000U,
-	/*0a9d*/ 0x00000000U,
-	/*0a9e*/ 0x00000000U,
-	/*0a9f*/ 0x0002c06eU,
-	/*0aa0*/ 0x02c002c0U,
-	/*0aa1*/ 0x02c002c0U,
-	/*0aa2*/ 0x000002c0U,
-	/*0aa3*/ 0x42080010U,
-	/*0aa4*/ 0x00000003U
-};
-
-static const uint32_t DDR_PHY_ADR_G_REGSET_G2M[DDR_PHY_ADR_G_REGSET_NUM_G2M] = {
-	/*0b80*/ 0x00000001U,
-	/*0b81*/ 0x00000000U,
-	/*0b82*/ 0x00000005U,
-	/*0b83*/ 0x04000f00U,
-	/*0b84*/ 0x00020080U,
-	/*0b85*/ 0x00020055U,
-	/*0b86*/ 0x00000000U,
-	/*0b87*/ 0x00000000U,
-	/*0b88*/ 0x00000000U,
-	/*0b89*/ 0x00000050U,
-	/*0b8a*/ 0x00000000U,
-	/*0b8b*/ 0x01010100U,
-	/*0b8c*/ 0x00000600U,
-	/*0b8d*/ 0x50640000U,
-	/*0b8e*/ 0x01421142U,
-	/*0b8f*/ 0x00000142U,
-	/*0b90*/ 0x00000000U,
-	/*0b91*/ 0x000f1600U,
-	/*0b92*/ 0x0f160f16U,
-	/*0b93*/ 0x0f160f16U,
-	/*0b94*/ 0x00000003U,
-	/*0b95*/ 0x0002c000U,
-	/*0b96*/ 0x02c002c0U,
-	/*0b97*/ 0x000002c0U,
-	/*0b98*/ 0x03421342U,
-	/*0b99*/ 0x00000342U,
-	/*0b9a*/ 0x00000000U,
-	/*0b9b*/ 0x00000000U,
-	/*0b9c*/ 0x05020000U,
-	/*0b9d*/ 0x00000000U,
-	/*0b9e*/ 0x00027f6eU,
-	/*0b9f*/ 0x047f027fU,
-	/*0ba0*/ 0x00027f6eU,
-	/*0ba1*/ 0x00047f6eU,
-	/*0ba2*/ 0x0003554fU,
-	/*0ba3*/ 0x0001554fU,
-	/*0ba4*/ 0x0001554fU,
-	/*0ba5*/ 0x0001554fU,
-	/*0ba6*/ 0x0001554fU,
-	/*0ba7*/ 0x00003feeU,
-	/*0ba8*/ 0x0001554fU,
-	/*0ba9*/ 0x00003feeU,
-	/*0baa*/ 0x0001554fU,
-	/*0bab*/ 0x00027f6eU,
-	/*0bac*/ 0x0001554fU,
-	/*0bad*/ 0x00000000U,
-	/*0bae*/ 0x00000000U,
-	/*0baf*/ 0x00000000U,
-	/*0bb0*/ 0x65000000U,
-	/*0bb1*/ 0x00000000U,
-	/*0bb2*/ 0x00000000U,
-	/*0bb3*/ 0x00000201U,
-	/*0bb4*/ 0x00000000U,
-	/*0bb5*/ 0x00000000U,
-	/*0bb6*/ 0x00000000U,
-	/*0bb7*/ 0x00000000U,
-	/*0bb8*/ 0x00000000U,
-	/*0bb9*/ 0x00000000U,
-	/*0bba*/ 0x00000000U,
-	/*0bbb*/ 0x00000000U,
-	/*0bbc*/ 0x06e40000U,
-	/*0bbd*/ 0x00000000U,
-	/*0bbe*/ 0x00000000U,
-	/*0bbf*/ 0x00010000U
-};
-
-static const uint32_t DDR_PI_REGSET_G2M[DDR_PI_REGSET_NUM_G2M] = {
-	/*0200*/ 0x00000b00U,
-	/*0201*/ 0x00000100U,
-	/*0202*/ 0x00000000U,
-	/*0203*/ 0x0000ffffU,
-	/*0204*/ 0x00000000U,
-	/*0205*/ 0x0000ffffU,
-	/*0206*/ 0x00000000U,
-	/*0207*/ 0x304cffffU,
-	/*0208*/ 0x00000200U,
-	/*0209*/ 0x00000200U,
-	/*020a*/ 0x00000200U,
-	/*020b*/ 0x00000200U,
-	/*020c*/ 0x0000304cU,
-	/*020d*/ 0x00000200U,
-	/*020e*/ 0x00000200U,
-	/*020f*/ 0x00000200U,
-	/*0210*/ 0x00000200U,
-	/*0211*/ 0x0000304cU,
-	/*0212*/ 0x00000200U,
-	/*0213*/ 0x00000200U,
-	/*0214*/ 0x00000200U,
-	/*0215*/ 0x00000200U,
-	/*0216*/ 0x00010000U,
-	/*0217*/ 0x00000003U,
-	/*0218*/ 0x01000001U,
-	/*0219*/ 0x00000000U,
-	/*021a*/ 0x00000000U,
-	/*021b*/ 0x00000000U,
-	/*021c*/ 0x00000000U,
-	/*021d*/ 0x00000000U,
-	/*021e*/ 0x00000000U,
-	/*021f*/ 0x00000000U,
-	/*0220*/ 0x00000000U,
-	/*0221*/ 0x00000000U,
-	/*0222*/ 0x00000000U,
-	/*0223*/ 0x00000000U,
-	/*0224*/ 0x00000000U,
-	/*0225*/ 0x00000000U,
-	/*0226*/ 0x00000000U,
-	/*0227*/ 0x00000000U,
-	/*0228*/ 0x00000000U,
-	/*0229*/ 0x0f000101U,
-	/*022a*/ 0x08492d25U,
-	/*022b*/ 0x0e0c0004U,
-	/*022c*/ 0x000e5000U,
-	/*022d*/ 0x00000250U,
-	/*022e*/ 0x00460003U,
-	/*022f*/ 0x182600cfU,
-	/*0230*/ 0x182600cfU,
-	/*0231*/ 0x00000005U,
-	/*0232*/ 0x00000000U,
-	/*0233*/ 0x00000000U,
-	/*0234*/ 0x00000000U,
-	/*0235*/ 0x00000000U,
-	/*0236*/ 0x00000000U,
-	/*0237*/ 0x00000000U,
-	/*0238*/ 0x00000000U,
-	/*0239*/ 0x01000000U,
-	/*023a*/ 0x00040404U,
-	/*023b*/ 0x01280a00U,
-	/*023c*/ 0x00000000U,
-	/*023d*/ 0x000f0000U,
-	/*023e*/ 0x00001803U,
-	/*023f*/ 0x00000000U,
-	/*0240*/ 0x00000000U,
-	/*0241*/ 0x00060002U,
-	/*0242*/ 0x00010001U,
-	/*0243*/ 0x01000101U,
-	/*0244*/ 0x04020201U,
-	/*0245*/ 0x00080804U,
-	/*0246*/ 0x00000000U,
-	/*0247*/ 0x08030000U,
-	/*0248*/ 0x15150408U,
-	/*0249*/ 0x00000000U,
-	/*024a*/ 0x00000000U,
-	/*024b*/ 0x00000000U,
-	/*024c*/ 0x000f0f00U,
-	/*024d*/ 0x0000001eU,
-	/*024e*/ 0x00000000U,
-	/*024f*/ 0x01000300U,
-	/*0250*/ 0x00000000U,
-	/*0251*/ 0x00000000U,
-	/*0252*/ 0x01000000U,
-	/*0253*/ 0x00010101U,
-	/*0254*/ 0x000e0e0eU,
-	/*0255*/ 0x000c0c0cU,
-	/*0256*/ 0x02060601U,
-	/*0257*/ 0x00000000U,
-	/*0258*/ 0x00000003U,
-	/*0259*/ 0x00181703U,
-	/*025a*/ 0x00280006U,
-	/*025b*/ 0x00280016U,
-	/*025c*/ 0x00000016U,
-	/*025d*/ 0x00000000U,
-	/*025e*/ 0x00000000U,
-	/*025f*/ 0x00000000U,
-	/*0260*/ 0x140a0000U,
-	/*0261*/ 0x0005010aU,
-	/*0262*/ 0x03018d03U,
-	/*0263*/ 0x000a018dU,
-	/*0264*/ 0x00060100U,
-	/*0265*/ 0x01000006U,
-	/*0266*/ 0x018e018eU,
-	/*0267*/ 0x018e0100U,
-	/*0268*/ 0x1111018eU,
-	/*0269*/ 0x10010204U,
-	/*026a*/ 0x09090650U,
-	/*026b*/ 0x20110202U,
-	/*026c*/ 0x00201000U,
-	/*026d*/ 0x00201000U,
-	/*026e*/ 0x04041000U,
-	/*026f*/ 0x18020100U,
-	/*0270*/ 0x00010118U,
-	/*0271*/ 0x004b004aU,
-	/*0272*/ 0x050f0000U,
-	/*0273*/ 0x0c01021eU,
-	/*0274*/ 0x34000000U,
-	/*0275*/ 0x00000000U,
-	/*0276*/ 0x00000000U,
-	/*0277*/ 0x00000000U,
-	/*0278*/ 0x0000d400U,
-	/*0279*/ 0x0031002eU,
-	/*027a*/ 0x00111136U,
-	/*027b*/ 0x002e00d4U,
-	/*027c*/ 0x11360031U,
-	/*027d*/ 0x0000d411U,
-	/*027e*/ 0x0031002eU,
-	/*027f*/ 0x00111136U,
-	/*0280*/ 0x002e00d4U,
-	/*0281*/ 0x11360031U,
-	/*0282*/ 0x0000d411U,
-	/*0283*/ 0x0031002eU,
-	/*0284*/ 0x00111136U,
-	/*0285*/ 0x002e00d4U,
-	/*0286*/ 0x11360031U,
-	/*0287*/ 0x00d40011U,
-	/*0288*/ 0x0031002eU,
-	/*0289*/ 0x00111136U,
-	/*028a*/ 0x002e00d4U,
-	/*028b*/ 0x11360031U,
-	/*028c*/ 0x0000d411U,
-	/*028d*/ 0x0031002eU,
-	/*028e*/ 0x00111136U,
-	/*028f*/ 0x002e00d4U,
-	/*0290*/ 0x11360031U,
-	/*0291*/ 0x0000d411U,
-	/*0292*/ 0x0031002eU,
-	/*0293*/ 0x00111136U,
-	/*0294*/ 0x002e00d4U,
-	/*0295*/ 0x11360031U,
-	/*0296*/ 0x02000011U,
-	/*0297*/ 0x018d018dU,
-	/*0298*/ 0x0c08018dU,
-	/*0299*/ 0x1f121d22U,
-	/*029a*/ 0x4301b344U,
-	/*029b*/ 0x10172006U,
-	/*029c*/ 0x1d220c10U,
-	/*029d*/ 0x00001f12U,
-	/*029e*/ 0x4301b344U,
-	/*029f*/ 0x10172006U,
-	/*02a0*/ 0x1d220c10U,
-	/*02a1*/ 0x00001f12U,
-	/*02a2*/ 0x4301b344U,
-	/*02a3*/ 0x10172006U,
-	/*02a4*/ 0x02000210U,
-	/*02a5*/ 0x02000200U,
-	/*02a6*/ 0x02000200U,
-	/*02a7*/ 0x02000200U,
-	/*02a8*/ 0x02000200U,
-	/*02a9*/ 0x00000000U,
-	/*02aa*/ 0x00000000U,
-	/*02ab*/ 0x00000000U,
-	/*02ac*/ 0x00000000U,
-	/*02ad*/ 0x00000000U,
-	/*02ae*/ 0x00000000U,
-	/*02af*/ 0x00000000U,
-	/*02b0*/ 0x00000000U,
-	/*02b1*/ 0x00000000U,
-	/*02b2*/ 0x00000000U,
-	/*02b3*/ 0x00000000U,
-	/*02b4*/ 0x00000000U,
-	/*02b5*/ 0x00000400U,
-	/*02b6*/ 0x15141312U,
-	/*02b7*/ 0x11100f0eU,
-	/*02b8*/ 0x080b0c0dU,
-	/*02b9*/ 0x05040a09U,
-	/*02ba*/ 0x01000706U,
-	/*02bb*/ 0x00000302U,
-	/*02bc*/ 0x01030201U,
-	/*02bd*/ 0x00304c00U,
-	/*02be*/ 0x0001e2f8U,
-	/*02bf*/ 0x0000304cU,
-	/*02c0*/ 0x0001e2f8U,
-	/*02c1*/ 0x0000304cU,
-	/*02c2*/ 0x0001e2f8U,
-	/*02c3*/ 0x08000000U,
-	/*02c4*/ 0x00000100U,
-	/*02c5*/ 0x00000000U,
-	/*02c6*/ 0x00000000U,
-	/*02c7*/ 0x00000000U,
-	/*02c8*/ 0x00000000U,
-	/*02c9*/ 0x00000002U
-};
-
-#endif /* RZG_INIT_DRAM_TABLE_G2M_H */
diff --git a/drivers/renesas/rzg/ddr/dram_sub_func.h b/drivers/renesas/rzg/ddr/dram_sub_func.h
deleted file mode 100644
index 7affb61..0000000
--- a/drivers/renesas/rzg/ddr/dram_sub_func.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef DRAM_SUB_FUNC_H
-#define DRAM_SUB_FUNC_H
-
-#define DRAM_UPDATE_STATUS_ERR	-1
-#define DRAM_BOOT_STATUS_COLD	0
-#define DRAM_BOOT_STATUS_WARM	1
-
-#endif /* DRAM_SUB_FUNC_H */
diff --git a/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
new file mode 100644
index 0000000..663df50
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
@@ -0,0 +1,700 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2e.h"
+#include "rcar_def.h"
+
+#include "../pfc_regs.h"
+
+/* PFC */
+#define GPSR0_SDA4		BIT(17)
+#define GPSR0_SCL4		BIT(16)
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_WE0		BIT(22)
+#define GPSR1_CS0		BIT(21)
+#define GPSR1_CLKOUT		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_BIT27_REVERSED	BIT(27)
+#define GPSR2_BIT26_REVERSED	BIT(26)
+#define GPSR2_EX_WAIT0		BIT(25)
+#define GPSR2_RD_WR		BIT(24)
+#define GPSR2_RD		BIT(23)
+#define GPSR2_BS		BIT(22)
+#define GPSR2_AVB_PHY_INT	BIT(21)
+#define GPSR2_AVB_TXCREFCLK	BIT(20)
+#define GPSR2_AVB_RD3		BIT(19)
+#define GPSR2_AVB_RD2		BIT(18)
+#define GPSR2_AVB_RD1		BIT(17)
+#define GPSR2_AVB_RD0		BIT(16)
+#define GPSR2_AVB_RXC		BIT(15)
+#define GPSR2_AVB_RX_CTL	BIT(14)
+#define GPSR2_RPC_RESET		BIT(13)
+#define GPSR2_RPC_RPC_INT	BIT(12)
+#define GPSR2_QSPI1_SSL		BIT(11)
+#define GPSR2_QSPI1_IO3		BIT(10)
+#define GPSR2_QSPI1_IO2		BIT(9)
+#define GPSR2_QSPI1_MISO_IO1	BIT(8)
+#define GPSR2_QSPI1_MOSI_IO0	BIT(7)
+#define GPSR2_QSPI1_SPCLK	BIT(6)
+#define GPSR2_QSPI0_SSL		BIT(5)
+#define GPSR2_QSPI0_IO3		BIT(4)
+#define GPSR2_QSPI0_IO2		BIT(3)
+#define GPSR2_QSPI0_MISO_IO1	BIT(2)
+#define GPSR2_QSPI0_MOSI_IO0	BIT(1)
+#define GPSR2_QSPI0_SPCLK	BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(10)
+#define GPSR4_SD3_DAT7		BIT(9)
+#define GPSR4_SD3_DAT6		BIT(8)
+#define GPSR4_SD3_DAT5		BIT(7)
+#define GPSR4_SD3_DAT4		BIT(6)
+#define GPSR4_SD3_DAT3		BIT(5)
+#define GPSR4_SD3_DAT2		BIT(4)
+#define GPSR4_SD3_DAT1		BIT(3)
+#define GPSR4_SD3_DAT0		BIT(2)
+#define GPSR4_SD3_CMD		BIT(1)
+#define GPSR4_SD3_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(19)
+#define GPSR5_MLB_SIG		BIT(18)
+#define GPSR5_MLB_CLK		BIT(17)
+#define GPSR5_SSI_SDATA9	BIT(16)
+#define GPSR5_MSIOF0_SS2	BIT(15)
+#define GPSR5_MSIOF0_SS1	BIT(14)
+#define GPSR5_MSIOF0_SYNC	BIT(13)
+#define GPSR5_MSIOF0_TXD	BIT(12)
+#define GPSR5_MSIOF0_RXD	BIT(11)
+#define GPSR5_MSIOF0_SCK	BIT(10)
+#define GPSR5_RX2_A		BIT(9)
+#define GPSR5_TX2_A		BIT(8)
+#define GPSR5_SCK2_A		BIT(7)
+#define GPSR5_TX1		BIT(6)
+#define GPSR5_RX1		BIT(5)
+#define GPSR5_RTS0_A		BIT(4)
+#define GPSR5_CTS0_A		BIT(3)
+#define GPSR5_TX0_A		BIT(2)
+#define GPSR5_RX0_A		BIT(1)
+#define GPSR5_SCK0_A		BIT(0)
+#define GPSR6_USB30_PWEN	BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_USB30_OVC		BIT(9)
+#define GPSR6_AUDIO_CLKA	BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS349		BIT(6)
+#define GPSR6_SSI_SCK349	BIT(5)
+#define GPSR6_SSI_SDATA2	BIT(4)
+#define GPSR6_SSI_SDATA1	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS01239	BIT(1)
+#define GPSR6_SSI_SCK01239	BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POCCTRL0_MASK		(0x0007F000U)
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define POCCTRL2_MASK		(0xFFFFFFFEU)
+#define POC2_VREF_33V		BIT(0)
+
+#define MOD_SEL0_ADGB_A			((uint32_t)0U << 29U)
+#define MOD_SEL0_ADGB_B			((uint32_t)1U << 29U)
+#define MOD_SEL0_ADGB_C			((uint32_t)2U << 29U)
+#define MOD_SEL0_DRIF0_A		((uint32_t)0U << 28U)
+#define MOD_SEL0_DRIF0_B		((uint32_t)1U << 28U)
+#define MOD_SEL0_FM_A			((uint32_t)0U << 26U)
+#define MOD_SEL0_FM_B			((uint32_t)1U << 26U)
+#define MOD_SEL0_FM_C			((uint32_t)2U << 26U)
+#define MOD_SEL0_FSO_A			((uint32_t)0U << 25U)
+#define MOD_SEL0_FSO_B			((uint32_t)1U << 25U)
+#define MOD_SEL0_HSCIF0_A		((uint32_t)0U << 24U)
+#define MOD_SEL0_HSCIF0_B		((uint32_t)1U << 24U)
+#define MOD_SEL0_HSCIF1_A		((uint32_t)0U << 23U)
+#define MOD_SEL0_HSCIF1_B		((uint32_t)1U << 23U)
+#define MOD_SEL0_HSCIF2_A		((uint32_t)0U << 22U)
+#define MOD_SEL0_HSCIF2_B		((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C1_A			((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B			((uint32_t)1U << 20U)
+#define MOD_SEL0_I2C1_C			((uint32_t)2U << 20U)
+#define MOD_SEL0_I2C1_D			((uint32_t)3U << 20U)
+#define MOD_SEL0_I2C2_A			((uint32_t)0U << 17U)
+#define MOD_SEL0_I2C2_B			((uint32_t)1U << 17U)
+#define MOD_SEL0_I2C2_C			((uint32_t)2U << 17U)
+#define MOD_SEL0_I2C2_D			((uint32_t)3U << 17U)
+#define MOD_SEL0_I2C2_E			((uint32_t)4U << 17U)
+#define MOD_SEL0_NDFC_A			((uint32_t)0U << 16U)
+#define MOD_SEL0_NDFC_B			((uint32_t)1U << 16U)
+#define MOD_SEL0_PWM0_A			((uint32_t)0U << 15U)
+#define MOD_SEL0_PWM0_B			((uint32_t)1U << 15U)
+#define MOD_SEL0_PWM1_A			((uint32_t)0U << 14U)
+#define MOD_SEL0_PWM1_B			((uint32_t)1U << 14U)
+#define MOD_SEL0_PWM2_A			((uint32_t)0U << 12U)
+#define MOD_SEL0_PWM2_B			((uint32_t)1U << 12U)
+#define MOD_SEL0_PWM2_C			((uint32_t)2U << 12U)
+#define MOD_SEL0_PWM3_A			((uint32_t)0U << 10U)
+#define MOD_SEL0_PWM3_B			((uint32_t)1U << 10U)
+#define MOD_SEL0_PWM3_C			((uint32_t)2U << 10U)
+#define MOD_SEL0_PWM4_A			((uint32_t)0U << 9U)
+#define MOD_SEL0_PWM4_B			((uint32_t)1U << 9U)
+#define MOD_SEL0_PWM5_A			((uint32_t)0U << 8U)
+#define MOD_SEL0_PWM5_B			((uint32_t)1U << 8U)
+#define MOD_SEL0_PWM6_A			((uint32_t)0U << 7U)
+#define MOD_SEL0_PWM6_B			((uint32_t)1U << 7U)
+#define MOD_SEL0_REMOCON_A		((uint32_t)0U << 5U)
+#define MOD_SEL0_REMOCON_B		((uint32_t)1U << 5U)
+#define MOD_SEL0_REMOCON_C		((uint32_t)2U << 5U)
+#define MOD_SEL0_SCIF_A			((uint32_t)0U << 4U)
+#define MOD_SEL0_SCIF_B			((uint32_t)1U << 4U)
+#define MOD_SEL0_SCIF0_A		((uint32_t)0U << 3U)
+#define MOD_SEL0_SCIF0_B		((uint32_t)1U << 3U)
+#define MOD_SEL0_SCIF2_A		((uint32_t)0U << 2U)
+#define MOD_SEL0_SCIF2_B		((uint32_t)1U << 2U)
+#define MOD_SEL0_SPEED_PULSE_IF_A	((uint32_t)0U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_B	((uint32_t)1U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_C	((uint32_t)2U << 0U)
+#define MOD_SEL1_SIMCARD_A		((uint32_t)0U << 31U)
+#define MOD_SEL1_SIMCARD_B		((uint32_t)1U << 31U)
+#define MOD_SEL1_SSI2_A			((uint32_t)0U << 30U)
+#define MOD_SEL1_SSI2_B			((uint32_t)1U << 30U)
+#define MOD_SEL1_TIMER_TMU_A		((uint32_t)0U << 29U)
+#define MOD_SEL1_TIMER_TMU_B		((uint32_t)1U << 29U)
+#define MOD_SEL1_USB20_CH0_A		((uint32_t)0U << 28U)
+#define MOD_SEL1_USB20_CH0_B		((uint32_t)1U << 28U)
+#define MOD_SEL1_DRIF2_A		((uint32_t)0U << 26U)
+#define MOD_SEL1_DRIF2_B		((uint32_t)1U << 26U)
+#define MOD_SEL1_DRIF3_A		((uint32_t)0U << 25U)
+#define MOD_SEL1_DRIF3_B		((uint32_t)1U << 25U)
+#define MOD_SEL1_HSCIF3_A		((uint32_t)0U << 22U)
+#define MOD_SEL1_HSCIF3_B		((uint32_t)1U << 22U)
+#define MOD_SEL1_HSCIF3_C		((uint32_t)2U << 22U)
+#define MOD_SEL1_HSCIF3_D		((uint32_t)3U << 22U)
+#define MOD_SEL1_HSCIF3_E		((uint32_t)4U << 22U)
+#define MOD_SEL1_HSCIF4_A		((uint32_t)0U << 19U)
+#define MOD_SEL1_HSCIF4_B		((uint32_t)1U << 19U)
+#define MOD_SEL1_HSCIF4_C		((uint32_t)2U << 19U)
+#define MOD_SEL1_HSCIF4_D		((uint32_t)3U << 19U)
+#define MOD_SEL1_HSCIF4_E		((uint32_t)4U << 19U)
+#define MOD_SEL1_I2C6_A			((uint32_t)0U << 18U)
+#define MOD_SEL1_I2C6_B			((uint32_t)1U << 18U)
+#define MOD_SEL1_I2C7_A			((uint32_t)0U << 17U)
+#define MOD_SEL1_I2C7_B			((uint32_t)1U << 17U)
+#define MOD_SEL1_MSIOF2_A		((uint32_t)0U << 16U)
+#define MOD_SEL1_MSIOF2_B		((uint32_t)1U << 16U)
+#define MOD_SEL1_MSIOF3_A		((uint32_t)0U << 15U)
+#define MOD_SEL1_MSIOF3_B		((uint32_t)1U << 15U)
+#define MOD_SEL1_SCIF3_A		((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B		((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF3_C		((uint32_t)2U << 13U)
+#define MOD_SEL1_SCIF4_A		((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF4_B		((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF4_C		((uint32_t)2U << 11U)
+#define MOD_SEL1_SCIF5_A		((uint32_t)0U << 9U)
+#define MOD_SEL1_SCIF5_B		((uint32_t)1U << 9U)
+#define MOD_SEL1_SCIF5_C		((uint32_t)2U << 9U)
+#define MOD_SEL1_VIN4_A			((uint32_t)0U << 8U)
+#define MOD_SEL1_VIN4_B			((uint32_t)1U << 8U)
+#define MOD_SEL1_VIN5_A			((uint32_t)0U << 7U)
+#define MOD_SEL1_VIN5_B			((uint32_t)1U << 7U)
+#define MOD_SEL1_ADGC_A			((uint32_t)0U << 5U)
+#define MOD_SEL1_ADGC_B			((uint32_t)1U << 5U)
+#define MOD_SEL1_ADGC_C			((uint32_t)2U << 5U)
+#define MOD_SEL1_SSI9_A			((uint32_t)0U << 4U)
+#define MOD_SEL1_SSI9_B			((uint32_t)1U << 4U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2e(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0,
+		      MOD_SEL0_ADGB_A |
+		      MOD_SEL0_DRIF0_A |
+		      MOD_SEL0_FM_A |
+		      MOD_SEL0_FSO_A |
+		      MOD_SEL0_HSCIF0_A |
+		      MOD_SEL0_HSCIF1_A |
+		      MOD_SEL0_HSCIF2_A |
+		      MOD_SEL0_I2C1_A |
+		      MOD_SEL0_I2C2_A |
+		      MOD_SEL0_NDFC_A |
+		      MOD_SEL0_PWM0_A |
+		      MOD_SEL0_PWM1_A |
+		      MOD_SEL0_PWM2_A |
+		      MOD_SEL0_PWM3_A |
+		      MOD_SEL0_PWM4_A |
+		      MOD_SEL0_PWM5_A |
+		      MOD_SEL0_PWM6_A |
+		      MOD_SEL0_REMOCON_A |
+		      MOD_SEL0_SCIF_A |
+		      MOD_SEL0_SCIF0_A |
+		      MOD_SEL0_SCIF2_A |
+		      MOD_SEL0_SPEED_PULSE_IF_A);
+
+	pfc_reg_write(PFC_MOD_SEL1,
+		      MOD_SEL1_SIMCARD_A |
+		      MOD_SEL1_SSI2_A |
+		      MOD_SEL1_TIMER_TMU_A |
+		      MOD_SEL1_USB20_CH0_B |
+		      MOD_SEL1_DRIF2_A |
+		      MOD_SEL1_DRIF3_A |
+		      MOD_SEL1_HSCIF3_C |
+		      MOD_SEL1_HSCIF4_B |
+		      MOD_SEL1_I2C6_A |
+		      MOD_SEL1_I2C7_A |
+		      MOD_SEL1_MSIOF2_A |
+		      MOD_SEL1_MSIOF3_A |
+		      MOD_SEL1_SCIF3_A |
+		      MOD_SEL1_SCIF4_A |
+		      MOD_SEL1_SCIF5_A |
+		      MOD_SEL1_VIN4_A |
+		      MOD_SEL1_VIN5_A |
+		      MOD_SEL1_ADGC_A |
+		      MOD_SEL1_SSI9_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0,
+		      IPSR_28_FUNC(2) |	/* HRX4_B */
+		      IPSR_24_FUNC(2) |	/* HTX4_B */
+		      IPSR_20_FUNC(0) |	/* QSPI1_SPCLK */
+		      IPSR_16_FUNC(0) |	/* QSPI0_IO3 */
+		      IPSR_12_FUNC(0) |	/* QSPI0_IO2 */
+		      IPSR_8_FUNC(0) |	/* QSPI0_MISO/IO1 */
+		      IPSR_4_FUNC(0) |	/* QSPI0_MOSI/IO0 */
+		      IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
+
+	pfc_reg_write(PFC_IPSR1,
+		      IPSR_28_FUNC(0) |	/* AVB_RD2 */
+		      IPSR_24_FUNC(0) |	/* AVB_RD1 */
+		      IPSR_20_FUNC(0) |	/* AVB_RD0 */
+		      IPSR_16_FUNC(0) |	/* RPC_RESET# */
+		      IPSR_12_FUNC(0) |	/* RPC_INT# */
+		      IPSR_8_FUNC(0) |	/* QSPI1_SSL */
+		      IPSR_4_FUNC(2) |	/* HRX3_C */
+		      IPSR_0_FUNC(2));	/* HTX3_C */
+
+	pfc_reg_write(PFC_IPSR2,
+		      IPSR_28_FUNC(1) |	/* IRQ0 */
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(2) |	/* AVB_LINK */
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |	/* AVB_MDC */
+		      IPSR_4_FUNC(0) |	/* AVB_MDIO */
+		      IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
+
+	pfc_reg_write(PFC_IPSR3,
+		      IPSR_28_FUNC(5) |	/* DU_HSYNC */
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(5) |	/* DU_DG4 */
+		      IPSR_8_FUNC(5) |	/* DU_DOTCLKOUT0 */
+		      IPSR_4_FUNC(5) |	/* DU_DISP */
+		      IPSR_0_FUNC(1));	/* IRQ1 */
+
+	pfc_reg_write(PFC_IPSR4,
+		      IPSR_28_FUNC(5) |	/* DU_DB5 */
+		      IPSR_24_FUNC(5) |	/* DU_DB4 */
+		      IPSR_20_FUNC(5) |	/* DU_DB3 */
+		      IPSR_16_FUNC(5) |	/* DU_DB2 */
+		      IPSR_12_FUNC(5) |	/* DU_DG6 */
+		      IPSR_8_FUNC(5) |	/* DU_VSYNC */
+		      IPSR_4_FUNC(5) |	/* DU_DG5 */
+		      IPSR_0_FUNC(5));	/* DU_DG7 */
+
+	pfc_reg_write(PFC_IPSR5,
+		      IPSR_28_FUNC(5) |	/* DU_DR3 */
+		      IPSR_24_FUNC(5) |	/* DU_DB7 */
+		      IPSR_20_FUNC(5) |	/* DU_DR2 */
+		      IPSR_16_FUNC(5) |	/* DU_DR1 */
+		      IPSR_12_FUNC(5) |	/* DU_DR0 */
+		      IPSR_8_FUNC(5) |	/* DU_DB1 */
+		      IPSR_4_FUNC(5) |	/* DU_DB0 */
+		      IPSR_0_FUNC(5));	/* DU_DB6 */
+
+	pfc_reg_write(PFC_IPSR6,
+		      IPSR_28_FUNC(5) |	/* DU_DG1 */
+		      IPSR_24_FUNC(5) |	/* DU_DG0 */
+		      IPSR_20_FUNC(5) |	/* DU_DR7 */
+		      IPSR_16_FUNC(1) |	/* CANFD1_RX */
+		      IPSR_12_FUNC(5) |	/* DU_DR6 */
+		      IPSR_8_FUNC(5) |	/* DU_DR5 */
+		      IPSR_4_FUNC(1) |	/* CANFD1_TX */
+		      IPSR_0_FUNC(5));	/* DU_DR4 */
+
+	pfc_reg_write(PFC_IPSR7,
+		      IPSR_28_FUNC(0) |	/* SD0_CLK */
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(5) |	/* DU_DOTCLKIN0 */
+		      IPSR_16_FUNC(5) |	/* DU_DG3 */
+		      IPSR_12_FUNC(1) |	/* CAN_CLK */
+		      IPSR_8_FUNC(1) |	/* CANFD0_RX */
+		      IPSR_4_FUNC(1) |	/* CANFD0_TX */
+		      IPSR_0_FUNC(5));	/* DU_DG2 */
+
+	pfc_reg_write(PFC_IPSR8,
+		      IPSR_28_FUNC(0) |	/* SD1_DAT0 */
+		      IPSR_24_FUNC(0) |	/* SD1_CMD */
+		      IPSR_20_FUNC(0) |	/* SD1_CLK */
+		      IPSR_16_FUNC(0) |	/* SD0_DAT3 */
+		      IPSR_12_FUNC(0) |	/* SD0_DAT2 */
+		      IPSR_8_FUNC(0) |	/* SD0_DAT1 */
+		      IPSR_4_FUNC(0) |	/* SD0_DAT0 */
+		      IPSR_0_FUNC(0));	/* SD0_CMD */
+
+	pfc_reg_write(PFC_IPSR9,
+		      IPSR_28_FUNC(0) |	/* SD3_DAT2 */
+		      IPSR_24_FUNC(0) |	/* SD3_DAT1 */
+		      IPSR_20_FUNC(0) |	/* SD3_DAT0 */
+		      IPSR_16_FUNC(0) |	/* SD3_CMD */
+		      IPSR_12_FUNC(0) |	/* SD3_CLK */
+		      IPSR_8_FUNC(0) |	/* SD1_DAT3 */
+		      IPSR_4_FUNC(0) |	/* SD1_DAT2 */
+		      IPSR_0_FUNC(0));	/* SD1_DAT1 */
+
+	pfc_reg_write(PFC_IPSR10,
+		      IPSR_24_FUNC(0) |	/* SD0_CD */
+		      IPSR_20_FUNC(0) |	/* SD3_DS */
+		      IPSR_16_FUNC(0) |	/* SD3_DAT7 */
+		      IPSR_12_FUNC(0) |	/* SD3_DAT6 */
+		      IPSR_8_FUNC(0) |	/* SD3_DAT5 */
+		      IPSR_4_FUNC(0) |	/* SD3_DAT4 */
+		      IPSR_0_FUNC(0));	/* SD3_DAT3 */
+
+	pfc_reg_write(PFC_IPSR11,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(8) |	/* USB0_ID */
+		      IPSR_20_FUNC(2) |	/* AUDIO_CLKOUT1_A */
+		      IPSR_16_FUNC(0) |	/* CTS0#_A */
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |	/* SD1_WP */
+		      IPSR_0_FUNC(0));	/* SD1_CD */
+
+	pfc_reg_write(PFC_IPSR12,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |	/* RX2_A */
+		      IPSR_8_FUNC(0) |	/* TX2_A */
+		      IPSR_4_FUNC(0) |	/* SCK2_A */
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR13,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(4) |	/* SDA1_B */
+		      IPSR_12_FUNC(4) |	/* SCL1_B */
+		      IPSR_8_FUNC(0) |	/* SSI_SDATA9 */
+		      IPSR_4_FUNC(1) |	/* HTX2_A */
+		      IPSR_0_FUNC(1));	/* HRX2_A */
+
+	pfc_reg_write(PFC_IPSR14,
+		      IPSR_28_FUNC(0) |	/* SSI_SCK5 */
+		      IPSR_24_FUNC(0) |	/* SSI_SDATA4 */
+		      IPSR_20_FUNC(0) |	/* SSI_SDATA3 */
+		      IPSR_16_FUNC(0) |	/* SSI_WS349 */
+		      IPSR_12_FUNC(0) |	/* SSI_SCK349 */
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |	/* SSI_SDATA1 */
+		      IPSR_0_FUNC(0));/* SSI_SDATA0 */
+
+	pfc_reg_write(PFC_IPSR15,
+		      IPSR_28_FUNC(0) |	/* USB30_OVC */
+		      IPSR_24_FUNC(0) |	/* USB30_PWEN */
+		      IPSR_20_FUNC(0) |	/* AUDIO_CLKA */
+		      IPSR_16_FUNC(1) |	/* HRTS2#_A */
+		      IPSR_12_FUNC(1) |	/* HCTS2#_A */
+		      IPSR_8_FUNC(3) |	/* TPU0TO1 */
+		      IPSR_4_FUNC(3) |	/* TPU0TO0 */
+		      IPSR_0_FUNC(0));	/* SSI_WS5 */
+
+	/* initialize GPIO/peripheral function select */
+	pfc_reg_write(PFC_GPSR0,
+		      GPSR0_SCL4 |
+		      GPSR0_D15 |
+		      GPSR0_D14 |
+		      GPSR0_D13 |
+		      GPSR0_D12 |
+		      GPSR0_D11 |
+		      GPSR0_D10 |
+		      GPSR0_D9 |
+		      GPSR0_D8 |
+		      GPSR0_D7 |
+		      GPSR0_D6 |
+		      GPSR0_D5 |
+		      GPSR0_D4 |
+		      GPSR0_D3 |
+		      GPSR0_D2 |
+		      GPSR0_D1 |
+		      GPSR0_D0);
+
+	pfc_reg_write(PFC_GPSR1,
+		      GPSR1_WE0 |
+		      GPSR1_CS0 |
+		      GPSR1_A19 |
+		      GPSR1_A18 |
+		      GPSR1_A17 |
+		      GPSR1_A16 |
+		      GPSR1_A15 |
+		      GPSR1_A14 |
+		      GPSR1_A13 |
+		      GPSR1_A12 |
+		      GPSR1_A11 |
+		      GPSR1_A10 |
+		      GPSR1_A9 |
+		      GPSR1_A8 |
+		      GPSR1_A4 |
+		      GPSR1_A3 |
+		      GPSR1_A2 |
+		      GPSR1_A1 |
+		      GPSR1_A0);
+
+	pfc_reg_write(PFC_GPSR2,
+		      GPSR2_BIT27_REVERSED |
+		      GPSR2_BIT26_REVERSED |
+		      GPSR2_AVB_PHY_INT |
+		      GPSR2_AVB_TXCREFCLK |
+		      GPSR2_AVB_RD3 |
+		      GPSR2_AVB_RD2 |
+		      GPSR2_AVB_RD1 |
+		      GPSR2_AVB_RD0 |
+		      GPSR2_AVB_RXC |
+		      GPSR2_AVB_RX_CTL |
+		      GPSR2_RPC_RESET |
+		      GPSR2_RPC_RPC_INT |
+		      GPSR2_QSPI1_IO3 |
+		      GPSR2_QSPI1_IO2 |
+		      GPSR2_QSPI1_MISO_IO1 |
+		      GPSR2_QSPI1_MOSI_IO0 |
+		      GPSR2_QSPI0_SSL |
+		      GPSR2_QSPI0_IO3 |
+		      GPSR2_QSPI0_IO2 |
+		      GPSR2_QSPI0_MISO_IO1 |
+		      GPSR2_QSPI0_MOSI_IO0 |
+		      GPSR2_QSPI0_SPCLK);
+
+	pfc_reg_write(PFC_GPSR3,
+		      GPSR3_SD0_CD |
+		      GPSR3_SD1_DAT3 |
+		      GPSR3_SD1_DAT2 |
+		      GPSR3_SD1_DAT1 |
+		      GPSR3_SD1_DAT0 |
+		      GPSR3_SD1_CMD |
+		      GPSR3_SD1_CLK |
+		      GPSR3_SD0_DAT3 |
+		      GPSR3_SD0_DAT2 |
+		      GPSR3_SD0_DAT1 |
+		      GPSR3_SD0_DAT0 |
+		      GPSR3_SD0_CMD |
+		      GPSR3_SD0_CLK);
+
+	pfc_reg_write(PFC_GPSR4,
+		      GPSR4_SD3_DAT3 |
+		      GPSR4_SD3_DAT2 |
+		      GPSR4_SD3_DAT1 |
+		      GPSR4_SD3_DAT0 |
+		      GPSR4_SD3_CMD |
+		      GPSR4_SD3_CLK);
+
+	pfc_reg_write(PFC_GPSR5,
+		      GPSR5_MLB_SIG |
+		      GPSR5_MLB_CLK |
+		      GPSR5_SSI_SDATA9 |
+		      GPSR5_MSIOF0_SS2 |
+		      GPSR5_MSIOF0_SS1 |
+		      GPSR5_MSIOF0_SYNC |
+		      GPSR5_MSIOF0_TXD |
+		      GPSR5_MSIOF0_RXD |
+		      GPSR5_MSIOF0_SCK |
+		      GPSR5_RX2_A |
+		      GPSR5_TX2_A |
+		      GPSR5_RTS0_A |
+		      GPSR5_SCK0_A);
+
+	pfc_reg_write(PFC_GPSR6,
+		      GPSR6_USB30_PWEN |
+		      GPSR6_SSI_SDATA6 |
+		      GPSR6_SSI_WS6 |
+		      GPSR6_SSI_SCK6 |
+		      GPSR6_SSI_SDATA5 |
+		      GPSR6_SSI_SCK5 |
+		      GPSR6_SSI_SDATA4 |
+		      GPSR6_USB30_OVC |
+		      GPSR6_AUDIO_CLKA |
+		      GPSR6_SSI_SDATA3 |
+		      GPSR6_SSI_WS349 |
+		      GPSR6_SSI_SCK349 |
+		      GPSR6_SSI_SDATA0 |
+		      GPSR6_SSI_WS01239 |
+		      GPSR6_SSI_SCK01239);
+
+	/* initialize POC control */
+	reg = mmio_read_32(PFC_POCCTRL0);
+	reg = (reg & POCCTRL0_MASK) |
+	      POC_SD1_DAT3_33V |
+	      POC_SD1_DAT2_33V |
+	      POC_SD1_DAT1_33V |
+	      POC_SD1_DAT0_33V |
+	      POC_SD1_CMD_33V |
+	      POC_SD1_CLK_33V |
+	      POC_SD0_DAT3_33V |
+	      POC_SD0_DAT2_33V |
+	      POC_SD0_DAT1_33V |
+	      POC_SD0_DAT0_33V |
+	      POC_SD0_CMD_33V |
+	      POC_SD0_CLK_33V;
+	pfc_reg_write(PFC_POCCTRL0, reg);
+
+	reg = mmio_read_32(PFC_POCCTRL2);
+	reg = ((reg & POCCTRL2_MASK) & ~POC2_VREF_33V);
+	pfc_reg_write(PFC_POCCTRL2, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00080000U);
+	pfc_reg_write(PFC_PUD1, 0xCE398464U);
+	pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
+	pfc_reg_write(PFC_PUD3, 0x0000079FU);
+	pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
+	pfc_reg_write(PFC_PUD5, 0x40000000U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000000U);
+	pfc_reg_write(PFC_PUEN1, 0x00300000U);
+	pfc_reg_write(PFC_PUEN2, 0x00400074U);
+	pfc_reg_write(PFC_PUEN3, 0x00000000U);
+	pfc_reg_write(PFC_PUEN4, 0x07900600U);
+	pfc_reg_write(PFC_PUEN5, 0x00000000U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT3, 0x00006000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT6, 0x00000000U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00020000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00100000U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000E000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000440U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00080000U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00000010U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h
new file mode 100644
index 0000000..677591a
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2E_H
+#define PFC_INIT_G2E_H
+
+void pfc_init_g2e(void);
+
+#endif /* PFC_INIT_G2E_H */
diff --git a/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
new file mode 100644
index 0000000..90a1c99
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
@@ -0,0 +1,1310 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2h.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15			BIT(15)
+#define GPSR0_D14			BIT(14)
+#define GPSR0_D13			BIT(13)
+#define GPSR0_D12			BIT(12)
+#define GPSR0_D11			BIT(11)
+#define GPSR0_D10			BIT(10)
+#define GPSR0_D9			BIT(9)
+#define GPSR0_D8			BIT(8)
+#define GPSR0_D7			BIT(7)
+#define GPSR0_D6			BIT(6)
+#define GPSR0_D5			BIT(5)
+#define GPSR0_D4			BIT(4)
+#define GPSR0_D3			BIT(3)
+#define GPSR0_D2			BIT(2)
+#define GPSR0_D1			BIT(1)
+#define GPSR0_D0			BIT(0)
+#define GPSR1_CLKOUT			BIT(28)
+#define GPSR1_EX_WAIT0_A		BIT(27)
+#define GPSR1_WE1			BIT(26)
+#define GPSR1_WE0			BIT(25)
+#define GPSR1_RD_WR			BIT(24)
+#define GPSR1_RD			BIT(23)
+#define GPSR1_BS			BIT(22)
+#define GPSR1_CS1_A26			BIT(21)
+#define GPSR1_CS0			BIT(20)
+#define GPSR1_A19			BIT(19)
+#define GPSR1_A18			BIT(18)
+#define GPSR1_A17			BIT(17)
+#define GPSR1_A16			BIT(16)
+#define GPSR1_A15			BIT(15)
+#define GPSR1_A14			BIT(14)
+#define GPSR1_A13			BIT(13)
+#define GPSR1_A12			BIT(12)
+#define GPSR1_A11			BIT(11)
+#define GPSR1_A10			BIT(10)
+#define GPSR1_A9			BIT(9)
+#define GPSR1_A8			BIT(8)
+#define GPSR1_A7			BIT(7)
+#define GPSR1_A6			BIT(6)
+#define GPSR1_A5			BIT(5)
+#define GPSR1_A4			BIT(4)
+#define GPSR1_A3			BIT(3)
+#define GPSR1_A2			BIT(2)
+#define GPSR1_A1			BIT(1)
+#define GPSR1_A0			BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A		BIT(13)
+#define GPSR2_AVB_LINK			BIT(12)
+#define GPSR2_AVB_PHY_INT		BIT(11)
+#define GPSR2_AVB_MAGIC			BIT(10)
+#define GPSR2_AVB_MDC			BIT(9)
+#define GPSR2_PWM2_A			BIT(8)
+#define GPSR2_PWM1_A			BIT(7)
+#define GPSR2_PWM0			BIT(6)
+#define GPSR2_IRQ5			BIT(5)
+#define GPSR2_IRQ4			BIT(4)
+#define GPSR2_IRQ3			BIT(3)
+#define GPSR2_IRQ2			BIT(2)
+#define GPSR2_IRQ1			BIT(1)
+#define GPSR2_IRQ0			BIT(0)
+#define GPSR3_SD1_WP			BIT(15)
+#define GPSR3_SD1_CD			BIT(14)
+#define GPSR3_SD0_WP			BIT(13)
+#define GPSR3_SD0_CD			BIT(12)
+#define GPSR3_SD1_DAT3			BIT(11)
+#define GPSR3_SD1_DAT2			BIT(10)
+#define GPSR3_SD1_DAT1			BIT(9)
+#define GPSR3_SD1_DAT0			BIT(8)
+#define GPSR3_SD1_CMD			BIT(7)
+#define GPSR3_SD1_CLK			BIT(6)
+#define GPSR3_SD0_DAT3			BIT(5)
+#define GPSR3_SD0_DAT2			BIT(4)
+#define GPSR3_SD0_DAT1			BIT(3)
+#define GPSR3_SD0_DAT0			BIT(2)
+#define GPSR3_SD0_CMD			BIT(1)
+#define GPSR3_SD0_CLK			BIT(0)
+#define GPSR4_SD3_DS			BIT(17)
+#define GPSR4_SD3_DAT7			BIT(16)
+#define GPSR4_SD3_DAT6			BIT(15)
+#define GPSR4_SD3_DAT5			BIT(14)
+#define GPSR4_SD3_DAT4			BIT(13)
+#define GPSR4_SD3_DAT3			BIT(12)
+#define GPSR4_SD3_DAT2			BIT(11)
+#define GPSR4_SD3_DAT1			BIT(10)
+#define GPSR4_SD3_DAT0			BIT(9)
+#define GPSR4_SD3_CMD			BIT(8)
+#define GPSR4_SD3_CLK			BIT(7)
+#define GPSR4_SD2_DS			BIT(6)
+#define GPSR4_SD2_DAT3			BIT(5)
+#define GPSR4_SD2_DAT2			BIT(4)
+#define GPSR4_SD2_DAT1			BIT(3)
+#define GPSR4_SD2_DAT0			BIT(2)
+#define GPSR4_SD2_CMD			BIT(1)
+#define GPSR4_SD2_CLK			BIT(0)
+#define GPSR5_MLB_DAT			BIT(25)
+#define GPSR5_MLB_SIG			BIT(24)
+#define GPSR5_MLB_CLK			BIT(23)
+#define GPSR5_MSIOF0_RXD		BIT(22)
+#define GPSR5_MSIOF0_SS2		BIT(21)
+#define GPSR5_MSIOF0_TXD		BIT(20)
+#define GPSR5_MSIOF0_SS1		BIT(19)
+#define GPSR5_MSIOF0_SYNC		BIT(18)
+#define GPSR5_MSIOF0_SCK		BIT(17)
+#define GPSR5_HRTS0			BIT(16)
+#define GPSR5_HCTS0			BIT(15)
+#define GPSR5_HTX0			BIT(14)
+#define GPSR5_HRX0			BIT(13)
+#define GPSR5_HSCK0			BIT(12)
+#define GPSR5_RX2_A			BIT(11)
+#define GPSR5_TX2_A			BIT(10)
+#define GPSR5_SCK2			BIT(9)
+#define GPSR5_RTS1			BIT(8)
+#define GPSR5_CTS1			BIT(7)
+#define GPSR5_TX1_A			BIT(6)
+#define GPSR5_RX1_A			BIT(5)
+#define GPSR5_RTS0			BIT(4)
+#define GPSR5_CTS0			BIT(3)
+#define GPSR5_TX0			BIT(2)
+#define GPSR5_RX0			BIT(1)
+#define GPSR5_SCK0			BIT(0)
+#define GPSR6_USB31_OVC			BIT(31)
+#define GPSR6_USB31_PWEN		BIT(30)
+#define GPSR6_USB30_OVC			BIT(29)
+#define GPSR6_USB30_PWEN		BIT(28)
+#define GPSR6_USB1_OVC			BIT(27)
+#define GPSR6_USB1_PWEN			BIT(26)
+#define GPSR6_USB0_OVC			BIT(25)
+#define GPSR6_USB0_PWEN			BIT(24)
+#define GPSR6_AUDIO_CLKB_B		BIT(23)
+#define GPSR6_AUDIO_CLKA_A		BIT(22)
+#define GPSR6_SSI_SDATA9_A		BIT(21)
+#define GPSR6_SSI_SDATA8		BIT(20)
+#define GPSR6_SSI_SDATA7		BIT(19)
+#define GPSR6_SSI_WS78			BIT(18)
+#define GPSR6_SSI_SCK78			BIT(17)
+#define GPSR6_SSI_SDATA6		BIT(16)
+#define GPSR6_SSI_WS6			BIT(15)
+#define GPSR6_SSI_SCK6			BIT(14)
+#define GPSR6_SSI_SDATA5		BIT(13)
+#define GPSR6_SSI_WS5			BIT(12)
+#define GPSR6_SSI_SCK5			BIT(11)
+#define GPSR6_SSI_SDATA4		BIT(10)
+#define GPSR6_SSI_WS4			BIT(9)
+#define GPSR6_SSI_SCK4			BIT(8)
+#define GPSR6_SSI_SDATA3		BIT(7)
+#define GPSR6_SSI_WS34			BIT(6)
+#define GPSR6_SSI_SCK34			BIT(5)
+#define GPSR6_SSI_SDATA2_A		BIT(4)
+#define GPSR6_SSI_SDATA1_A		BIT(3)
+#define GPSR6_SSI_SDATA0		BIT(2)
+#define GPSR6_SSI_WS0129		BIT(1)
+#define GPSR6_SSI_SCK0129		BIT(0)
+#define GPSR7_AVS2			BIT(1)
+#define GPSR7_AVS1			BIT(0)
+
+#define IPSR_28_FUNC(x)			((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)			((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)			((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)			((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)			((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)			((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)			((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)			((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V			BIT(29)
+#define POC_SD3_DAT7_33V		BIT(28)
+#define POC_SD3_DAT6_33V		BIT(27)
+#define POC_SD3_DAT5_33V		BIT(26)
+#define POC_SD3_DAT4_33V		BIT(25)
+#define POC_SD3_DAT3_33V		BIT(24)
+#define POC_SD3_DAT2_33V		BIT(23)
+#define POC_SD3_DAT1_33V		BIT(22)
+#define POC_SD3_DAT0_33V		BIT(21)
+#define POC_SD3_CMD_33V			BIT(20)
+#define POC_SD3_CLK_33V			BIT(19)
+#define POC_SD2_DS_33V			BIT(18)
+#define POC_SD2_DAT3_33V		BIT(17)
+#define POC_SD2_DAT2_33V		BIT(16)
+#define POC_SD2_DAT1_33V		BIT(15)
+#define POC_SD2_DAT0_33V		BIT(14)
+#define POC_SD2_CMD_33V			BIT(13)
+#define POC_SD2_CLK_33V			BIT(12)
+#define POC_SD1_DAT3_33V		BIT(11)
+#define POC_SD1_DAT2_33V		BIT(10)
+#define POC_SD1_DAT1_33V		BIT(9)
+#define POC_SD1_DAT0_33V		BIT(8)
+#define POC_SD1_CMD_33V			BIT(7)
+#define POC_SD1_CLK_33V			BIT(6)
+#define POC_SD0_DAT3_33V		BIT(5)
+#define POC_SD0_DAT2_33V		BIT(4)
+#define POC_SD0_DAT1_33V		BIT(3)
+#define POC_SD0_DAT0_33V		BIT(2)
+#define POC_SD0_CMD_33V			BIT(1)
+#define POC_SD0_CLK_33V			BIT(0)
+
+#define DRVCTRL0_MASK			(0xCCCCCCCCU)
+#define DRVCTRL1_MASK			(0xCCCCCCC8U)
+#define DRVCTRL2_MASK			(0x88888888U)
+#define DRVCTRL3_MASK			(0x88888888U)
+#define DRVCTRL4_MASK			(0x88888888U)
+#define DRVCTRL5_MASK			(0x88888888U)
+#define DRVCTRL6_MASK			(0x88888888U)
+#define DRVCTRL7_MASK			(0x88888888U)
+#define DRVCTRL8_MASK			(0x88888888U)
+#define DRVCTRL9_MASK			(0x88888888U)
+#define DRVCTRL10_MASK			(0x88888888U)
+#define DRVCTRL11_MASK			(0x888888CCU)
+#define DRVCTRL12_MASK			(0xCCCFFFCFU)
+#define DRVCTRL13_MASK			(0xCC888888U)
+#define DRVCTRL14_MASK			(0x88888888U)
+#define DRVCTRL15_MASK			(0x88888888U)
+#define DRVCTRL16_MASK			(0x88888888U)
+#define DRVCTRL17_MASK			(0x88888888U)
+#define DRVCTRL18_MASK			(0x88888888U)
+#define DRVCTRL19_MASK			(0x88888888U)
+#define DRVCTRL20_MASK			(0x88888888U)
+#define DRVCTRL21_MASK			(0x88888888U)
+#define DRVCTRL22_MASK			(0x88888888U)
+#define DRVCTRL23_MASK			(0x88888888U)
+#define DRVCTRL24_MASK			(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)		((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A		((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B		((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C		((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D		((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E		((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A		((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B		((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C		((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D		((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A		((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B		((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C		((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D		((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E		((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F		((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G		((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A			((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B			((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A		((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B		((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A			((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B			((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A			((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B			((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A		((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B		((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A		((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B		((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C		((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D		((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A		((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B		((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A			((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B			((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A		((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B		((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C		((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A		((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B		((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A		((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B		((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A		((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B		((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A		((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B		((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C		((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A		((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B		((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C		((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A		((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B		((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A		((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B		((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C		((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A		((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B		((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C		((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D		((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A		((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B		((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C		((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D		((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E		((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A		((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B		((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A		((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B		((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C		((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D		((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A		((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B		((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C		((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D		((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E		((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A			((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B			((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A		((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B		((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C		((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D		((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A		((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B		((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A		((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B		((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C		((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A		((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B		((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A		((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B		((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A		((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B		((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A			((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B			((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A		((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B		((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A		((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B		((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A			((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B			((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A			((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B			((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A			((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B			((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A			((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B			((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A			((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B			((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A			((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B			((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A		((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B		((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A		((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B		((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A		((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B		((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A			((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B			((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C			((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D			((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A		((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B		((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A			((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B			((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C			((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A			((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B			((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A			((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B			((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A			((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B			((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A		((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B		((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A		((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B		((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A		((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B		((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A			((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B			((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2h(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0,
+		      MOD_SEL0_MSIOF3_A |
+		      MOD_SEL0_MSIOF2_A |
+		      MOD_SEL0_MSIOF1_A |
+		      MOD_SEL0_LBSC_A |
+		      MOD_SEL0_IEBUS_A |
+		      MOD_SEL0_I2C2_A |
+		      MOD_SEL0_I2C1_A |
+		      MOD_SEL0_HSCIF4_A |
+		      MOD_SEL0_HSCIF3_A |
+		      MOD_SEL0_HSCIF1_A |
+		      MOD_SEL0_FSO_A |
+		      MOD_SEL0_HSCIF2_A |
+		      MOD_SEL0_ETHERAVB_A |
+		      MOD_SEL0_DRIF3_A |
+		      MOD_SEL0_DRIF2_A |
+		      MOD_SEL0_DRIF1_A |
+		      MOD_SEL0_DRIF0_A |
+		      MOD_SEL0_CANFD0_A |
+		      MOD_SEL0_ADG_A_A);
+
+	pfc_reg_write(PFC_MOD_SEL1,
+		      MOD_SEL1_TSIF1_A |
+		      MOD_SEL1_TSIF0_A |
+		      MOD_SEL1_TIMER_TMU_A |
+		      MOD_SEL1_SSP1_1_A |
+		      MOD_SEL1_SSP1_0_A |
+		      MOD_SEL1_SSI_A |
+		      MOD_SEL1_SPEED_PULSE_IF_A |
+		      MOD_SEL1_SIMCARD_A |
+		      MOD_SEL1_SDHI2_A |
+		      MOD_SEL1_SCIF4_A |
+		      MOD_SEL1_SCIF3_A |
+		      MOD_SEL1_SCIF2_A |
+		      MOD_SEL1_SCIF1_A |
+		      MOD_SEL1_SCIF_A |
+		      MOD_SEL1_REMOCON_A |
+		      MOD_SEL1_RCAN0_A |
+		      MOD_SEL1_PWM6_A |
+		      MOD_SEL1_PWM5_A |
+		      MOD_SEL1_PWM4_A |
+		      MOD_SEL1_PWM3_A |
+		      MOD_SEL1_PWM2_A |
+		      MOD_SEL1_PWM1_A);
+
+	pfc_reg_write(PFC_MOD_SEL2,
+		      MOD_SEL2_I2C_5_B |
+		      MOD_SEL2_I2C_3_B |
+		      MOD_SEL2_I2C_0_B |
+		      MOD_SEL2_FM_A |
+		      MOD_SEL2_SCIF5_A |
+		      MOD_SEL2_I2C6_A |
+		      MOD_SEL2_NDF_A |
+		      MOD_SEL2_SSI2_A |
+		      MOD_SEL2_SSI9_A |
+		      MOD_SEL2_TIMER_TMU2_A |
+		      MOD_SEL2_ADG_B_A |
+		      MOD_SEL2_ADG_C_A |
+		      MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR1,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(3) |
+		      IPSR_8_FUNC(3) |
+		      IPSR_4_FUNC(3) |
+		      IPSR_0_FUNC(3));
+
+	pfc_reg_write(PFC_IPSR2,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR3,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR4,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR5,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR6,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR7,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR8,
+		      IPSR_28_FUNC(1) |
+		      IPSR_24_FUNC(1) |
+		      IPSR_20_FUNC(1) |
+		      IPSR_16_FUNC(1) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR9,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR10,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR11,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(4) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR12,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(4) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR13,
+		      IPSR_28_FUNC(8) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(3) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR14,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(3) |
+		      IPSR_0_FUNC(8));
+
+	pfc_reg_write(PFC_IPSR15,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR16,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR17,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(1) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR18,
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	/* initialize GPIO/peripheral function select */
+	pfc_reg_write(PFC_GPSR0,
+		      GPSR0_D15 |
+		      GPSR0_D14 |
+		      GPSR0_D13 |
+		      GPSR0_D12 |
+		      GPSR0_D11 |
+		      GPSR0_D10 |
+		      GPSR0_D9 |
+		      GPSR0_D8 |
+		      GPSR0_D7 |
+		      GPSR0_D6 |
+		      GPSR0_D5 |
+		      GPSR0_D4 |
+		      GPSR0_D3 |
+		      GPSR0_D2 |
+		      GPSR0_D0);
+
+	pfc_reg_write(PFC_GPSR1,
+		      GPSR1_CLKOUT |
+		      GPSR1_EX_WAIT0_A |
+		      GPSR1_WE1 |
+		      GPSR1_RD |
+		      GPSR1_RD_WR |
+		      GPSR1_CS0 |
+		      GPSR1_A19 |
+		      GPSR1_A18 |
+		      GPSR1_A17 |
+		      GPSR1_A16 |
+		      GPSR1_A15 |
+		      GPSR1_A14 |
+		      GPSR1_A13 |
+		      GPSR1_A12 |
+		      GPSR1_A7 |
+		      GPSR1_A6 |
+		      GPSR1_A5 |
+		      GPSR1_A4 |
+		      GPSR1_A3 |
+		      GPSR1_A2 |
+		      GPSR1_A1 |
+		      GPSR1_A0);
+
+	pfc_reg_write(PFC_GPSR2,
+		      GPSR2_AVB_AVTP_CAPTURE_A |
+		      GPSR2_AVB_AVTP_MATCH_A |
+		      GPSR2_AVB_LINK |
+		      GPSR2_AVB_PHY_INT |
+		      GPSR2_AVB_MDC |
+		      GPSR2_PWM2_A |
+		      GPSR2_PWM1_A |
+		      GPSR2_IRQ4 |
+		      GPSR2_IRQ3 |
+		      GPSR2_IRQ2 |
+		      GPSR2_IRQ1 |
+		      GPSR2_IRQ0);
+
+	pfc_reg_write(PFC_GPSR3,
+		      GPSR3_SD0_CD |
+		      GPSR3_SD1_DAT3 |
+		      GPSR3_SD1_DAT2 |
+		      GPSR3_SD1_DAT1 |
+		      GPSR3_SD1_DAT0 |
+		      GPSR3_SD0_DAT3 |
+		      GPSR3_SD0_DAT2 |
+		      GPSR3_SD0_DAT1 |
+		      GPSR3_SD0_DAT0 |
+		      GPSR3_SD0_CMD |
+		      GPSR3_SD0_CLK);
+
+	pfc_reg_write(PFC_GPSR4,
+		      GPSR4_SD3_DS |
+		      GPSR4_SD3_DAT7 |
+		      GPSR4_SD3_DAT6 |
+		      GPSR4_SD3_DAT5 |
+		      GPSR4_SD3_DAT4 |
+		      GPSR4_SD3_DAT3 |
+		      GPSR4_SD3_DAT2 |
+		      GPSR4_SD3_DAT1 |
+		      GPSR4_SD3_DAT0 |
+		      GPSR4_SD3_CMD |
+		      GPSR4_SD3_CLK |
+		      GPSR4_SD2_DAT3 |
+		      GPSR4_SD2_DAT2 |
+		      GPSR4_SD2_DAT1 |
+		      GPSR4_SD2_DAT0 |
+		      GPSR4_SD2_CMD |
+		      GPSR4_SD2_CLK);
+
+	pfc_reg_write(PFC_GPSR5,
+		      GPSR5_MSIOF0_RXD |
+		      GPSR5_MSIOF0_TXD |
+		      GPSR5_MSIOF0_SYNC |
+		      GPSR5_MSIOF0_SCK |
+		      GPSR5_RX2_A |
+		      GPSR5_TX2_A |
+		      GPSR5_RTS1 |
+		      GPSR5_CTS1 |
+		      GPSR5_TX1_A |
+		      GPSR5_RX1_A |
+		      GPSR5_RTS0 |
+		      GPSR5_SCK0);
+
+	pfc_reg_write(PFC_GPSR6,
+		      GPSR6_AUDIO_CLKB_B |
+		      GPSR6_AUDIO_CLKA_A |
+		      GPSR6_SSI_WS6 |
+		      GPSR6_SSI_SCK6 |
+		      GPSR6_SSI_SDATA4 |
+		      GPSR6_SSI_WS4 |
+		      GPSR6_SSI_SCK4 |
+		      GPSR6_SSI_SDATA1_A |
+		      GPSR6_SSI_SDATA0 |
+		      GPSR6_SSI_WS0129 |
+		      GPSR6_SSI_SCK0129);
+
+	pfc_reg_write(PFC_GPSR7,
+		      GPSR7_AVS2 |
+		      GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0,
+		      POC_SD0_DAT3_33V |
+		      POC_SD0_DAT2_33V |
+		      POC_SD0_DAT1_33V |
+		      POC_SD0_DAT0_33V |
+		      POC_SD0_CMD_33V |
+		      POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = (reg & DRVCTRL0_MASK) |
+	      DRVCTRL0_QSPI0_SPCLK(3) |
+	      DRVCTRL0_QSPI0_MOSI_IO0(3) |
+	      DRVCTRL0_QSPI0_MISO_IO1(3) |
+	      DRVCTRL0_QSPI0_IO2(3) |
+	      DRVCTRL0_QSPI0_IO3(3) |
+	      DRVCTRL0_QSPI0_SSL(3) |
+	      DRVCTRL0_QSPI1_SPCLK(3) |
+	      DRVCTRL0_QSPI1_MOSI_IO0(3);
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = (reg & DRVCTRL1_MASK) |
+	      DRVCTRL1_QSPI1_MISO_IO1(3) |
+	      DRVCTRL1_QSPI1_IO2(3) |
+	      DRVCTRL1_QSPI1_IO3(3) |
+	      DRVCTRL1_QSPI1_SS(3) |
+	      DRVCTRL1_RPC_INT(3) |
+	      DRVCTRL1_RPC_WP(3) |
+	      DRVCTRL1_RPC_RESET(3) |
+	      DRVCTRL1_AVB_RX_CTL(7);
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = (reg & DRVCTRL2_MASK) |
+	      DRVCTRL2_AVB_RXC(7) |
+	      DRVCTRL2_AVB_RD0(7) |
+	      DRVCTRL2_AVB_RD1(7) |
+	      DRVCTRL2_AVB_RD2(7) |
+	      DRVCTRL2_AVB_RD3(7) |
+	      DRVCTRL2_AVB_TX_CTL(3) |
+	      DRVCTRL2_AVB_TXC(3) |
+	      DRVCTRL2_AVB_TD0(3);
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = (reg & DRVCTRL3_MASK) |
+	      DRVCTRL3_AVB_TD1(3) |
+	      DRVCTRL3_AVB_TD2(3) |
+	      DRVCTRL3_AVB_TD3(3) |
+	      DRVCTRL3_AVB_TXCREFCLK(7) |
+	      DRVCTRL3_AVB_MDIO(7) |
+	      DRVCTRL3_AVB_MDC(7) |
+	      DRVCTRL3_AVB_MAGIC(7) |
+	      DRVCTRL3_AVB_PHY_INT(7);
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = (reg & DRVCTRL4_MASK) |
+	      DRVCTRL4_AVB_LINK(7) |
+	      DRVCTRL4_AVB_AVTP_MATCH(7) |
+	      DRVCTRL4_AVB_AVTP_CAPTURE(7) |
+	      DRVCTRL4_IRQ0(7) |
+	      DRVCTRL4_IRQ1(7) |
+	      DRVCTRL4_IRQ2(7) |
+	      DRVCTRL4_IRQ3(7) |
+	      DRVCTRL4_IRQ4(7);
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = (reg & DRVCTRL5_MASK) |
+	      DRVCTRL5_IRQ5(7) |
+	      DRVCTRL5_PWM0(7) |
+	      DRVCTRL5_PWM1(7) |
+	      DRVCTRL5_PWM2(7) |
+	      DRVCTRL5_A0(3) |
+	      DRVCTRL5_A1(3) |
+	      DRVCTRL5_A2(3) |
+	      DRVCTRL5_A3(3);
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = (reg & DRVCTRL6_MASK) |
+	      DRVCTRL6_A4(3) |
+	      DRVCTRL6_A5(3) |
+	      DRVCTRL6_A6(3) |
+	      DRVCTRL6_A7(3) |
+	      DRVCTRL6_A8(7) |
+	      DRVCTRL6_A9(7) |
+	      DRVCTRL6_A10(7) |
+	      DRVCTRL6_A11(7);
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = (reg & DRVCTRL7_MASK) |
+	      DRVCTRL7_A12(3) |
+	      DRVCTRL7_A13(3) |
+	      DRVCTRL7_A14(3) |
+	      DRVCTRL7_A15(3) |
+	      DRVCTRL7_A16(3) |
+	      DRVCTRL7_A17(3) |
+	      DRVCTRL7_A18(3) |
+	      DRVCTRL7_A19(3);
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = (reg & DRVCTRL8_MASK) |
+	      DRVCTRL8_CLKOUT(7) |
+	      DRVCTRL8_CS0(7) |
+	      DRVCTRL8_CS1_A2(7) |
+	      DRVCTRL8_BS(7) |
+	      DRVCTRL8_RD(7) |
+	      DRVCTRL8_RD_W(7) |
+	      DRVCTRL8_WE0(7) |
+	      DRVCTRL8_WE1(7);
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = (reg & DRVCTRL9_MASK) |
+	      DRVCTRL9_EX_WAIT0(7) |
+	      DRVCTRL9_PRESETOU(7) |
+	      DRVCTRL9_D0(7) |
+	      DRVCTRL9_D1(7) |
+	      DRVCTRL9_D2(7) |
+	      DRVCTRL9_D3(7) |
+	      DRVCTRL9_D4(7) |
+	      DRVCTRL9_D5(7);
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = (reg & DRVCTRL10_MASK) |
+	      DRVCTRL10_D6(7) |
+	      DRVCTRL10_D7(7) |
+	      DRVCTRL10_D8(3) |
+	      DRVCTRL10_D9(3) |
+	      DRVCTRL10_D10(3) |
+	      DRVCTRL10_D11(3) |
+	      DRVCTRL10_D12(3) |
+	      DRVCTRL10_D13(3);
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = (reg & DRVCTRL11_MASK) |
+	      DRVCTRL11_D14(3) |
+	      DRVCTRL11_D15(3) |
+	      DRVCTRL11_AVS1(7) |
+	      DRVCTRL11_AVS2(7) |
+	      DRVCTRL11_GP7_02(7) |
+	      DRVCTRL11_GP7_03(7) |
+	      DRVCTRL11_DU_DOTCLKIN0(3) |
+	      DRVCTRL11_DU_DOTCLKIN1(3);
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = (reg & DRVCTRL12_MASK) |
+	      DRVCTRL12_DU_DOTCLKIN2(3) |
+	      DRVCTRL12_DU_DOTCLKIN3(3) |
+	      DRVCTRL12_DU_FSCLKST(3) |
+	      DRVCTRL12_DU_TMS(3);
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = (reg & DRVCTRL13_MASK) |
+	      DRVCTRL13_TDO(3) |
+	      DRVCTRL13_ASEBRK(3) |
+	      DRVCTRL13_SD0_CLK(7) |
+	      DRVCTRL13_SD0_CMD(7) |
+	      DRVCTRL13_SD0_DAT0(7) |
+	      DRVCTRL13_SD0_DAT1(7) |
+	      DRVCTRL13_SD0_DAT2(7) |
+	      DRVCTRL13_SD0_DAT3(7);
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = (reg & DRVCTRL14_MASK) |
+	      DRVCTRL14_SD1_CLK(7) |
+	      DRVCTRL14_SD1_CMD(7) |
+	      DRVCTRL14_SD1_DAT0(5) |
+	      DRVCTRL14_SD1_DAT1(5) |
+	      DRVCTRL14_SD1_DAT2(5) |
+	      DRVCTRL14_SD1_DAT3(5) |
+	      DRVCTRL14_SD2_CLK(5) |
+	      DRVCTRL14_SD2_CMD(5);
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = (reg & DRVCTRL15_MASK) |
+	      DRVCTRL15_SD2_DAT0(5) |
+	      DRVCTRL15_SD2_DAT1(5) |
+	      DRVCTRL15_SD2_DAT2(5) |
+	      DRVCTRL15_SD2_DAT3(5) |
+	      DRVCTRL15_SD2_DS(5) |
+	      DRVCTRL15_SD3_CLK(7) |
+	      DRVCTRL15_SD3_CMD(7) |
+	      DRVCTRL15_SD3_DAT0(7);
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = (reg & DRVCTRL16_MASK) |
+	      DRVCTRL16_SD3_DAT1(7) |
+	      DRVCTRL16_SD3_DAT2(7) |
+	      DRVCTRL16_SD3_DAT3(7) |
+	      DRVCTRL16_SD3_DAT4(7) |
+	      DRVCTRL16_SD3_DAT5(7) |
+	      DRVCTRL16_SD3_DAT6(7) |
+	      DRVCTRL16_SD3_DAT7(7) |
+	      DRVCTRL16_SD3_DS(7);
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = (reg & DRVCTRL17_MASK) |
+	      DRVCTRL17_SD0_CD(7) |
+	      DRVCTRL17_SD0_WP(7) |
+	      DRVCTRL17_SD1_CD(7) |
+	      DRVCTRL17_SD1_WP(7) |
+	      DRVCTRL17_SCK0(7) |
+	      DRVCTRL17_RX0(7) |
+	      DRVCTRL17_TX0(7) |
+	      DRVCTRL17_CTS0(7);
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = (reg & DRVCTRL18_MASK) |
+	      DRVCTRL18_RTS0_TANS(7) |
+	      DRVCTRL18_RX1(7) |
+	      DRVCTRL18_TX1(7) |
+	      DRVCTRL18_CTS1(7) |
+	      DRVCTRL18_RTS1_TANS(7) |
+	      DRVCTRL18_SCK2(7) |
+	      DRVCTRL18_TX2(7) |
+	      DRVCTRL18_RX2(7);
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = (reg & DRVCTRL19_MASK) |
+	      DRVCTRL19_HSCK0(7) |
+	      DRVCTRL19_HRX0(7) |
+	      DRVCTRL19_HTX0(7) |
+	      DRVCTRL19_HCTS0(7) |
+	      DRVCTRL19_HRTS0(7) |
+	      DRVCTRL19_MSIOF0_SCK(7) |
+	      DRVCTRL19_MSIOF0_SYNC(7) |
+	      DRVCTRL19_MSIOF0_SS1(7);
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = (reg & DRVCTRL20_MASK) |
+	      DRVCTRL20_MSIOF0_TXD(7) |
+	      DRVCTRL20_MSIOF0_SS2(7) |
+	      DRVCTRL20_MSIOF0_RXD(7) |
+	      DRVCTRL20_MLB_CLK(7) |
+	      DRVCTRL20_MLB_SIG(7) |
+	      DRVCTRL20_MLB_DAT(7) |
+	      DRVCTRL20_MLB_REF(7) |
+	      DRVCTRL20_SSI_SCK0129(7);
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = (reg & DRVCTRL21_MASK) |
+	      DRVCTRL21_SSI_WS0129(7) |
+	      DRVCTRL21_SSI_SDATA0(7) |
+	      DRVCTRL21_SSI_SDATA1(7) |
+	      DRVCTRL21_SSI_SDATA2(7) |
+	      DRVCTRL21_SSI_SCK34(7) |
+	      DRVCTRL21_SSI_WS34(7) |
+	      DRVCTRL21_SSI_SDATA3(7) |
+	      DRVCTRL21_SSI_SCK4(7);
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = (reg & DRVCTRL22_MASK) |
+	      DRVCTRL22_SSI_WS4(7) |
+	      DRVCTRL22_SSI_SDATA4(7) |
+	      DRVCTRL22_SSI_SCK5(7) |
+	      DRVCTRL22_SSI_WS5(7) |
+	      DRVCTRL22_SSI_SDATA5(7) |
+	      DRVCTRL22_SSI_SCK6(7) |
+	      DRVCTRL22_SSI_WS6(7) |
+	      DRVCTRL22_SSI_SDATA6(7);
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = (reg & DRVCTRL23_MASK) |
+	      DRVCTRL23_SSI_SCK78(7) |
+	      DRVCTRL23_SSI_WS78(7) |
+	      DRVCTRL23_SSI_SDATA7(7) |
+	      DRVCTRL23_SSI_SDATA8(7) |
+	      DRVCTRL23_SSI_SDATA9(7) |
+	      DRVCTRL23_AUDIO_CLKA(7) |
+	      DRVCTRL23_AUDIO_CLKB(7) |
+	      DRVCTRL23_USB0_PWEN(7);
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = (reg & DRVCTRL24_MASK) |
+	      DRVCTRL24_USB0_OVC(7) |
+	      DRVCTRL24_USB1_PWEN(7) |
+	      DRVCTRL24_USB1_OVC(7) |
+	      DRVCTRL24_USB30_PWEN(7) |
+	      DRVCTRL24_USB30_OVC(7) |
+	      DRVCTRL24_USB31_PWEN(7) |
+	      DRVCTRL24_USB31_OVC(7);
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300EFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000001U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003800U);
+	mmio_write_32(GPIO_OUTDT7, 0x00000003U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000001U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00100B00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000418U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00002000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000040U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00000208U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013F00U);
+	mmio_write_32(GPIO_INOUTSEL7, 0x00000003U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h
new file mode 100644
index 0000000..5efce45
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2H_H
+#define PFC_INIT_G2H_H
+
+void pfc_init_g2h(void);
+
+#endif /* PFC_INIT_G2H_H */
diff --git a/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
new file mode 100644
index 0000000..c951e0a
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
@@ -0,0 +1,1306 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2n.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15			BIT(15)
+#define GPSR0_D14			BIT(14)
+#define GPSR0_D13			BIT(13)
+#define GPSR0_D12			BIT(12)
+#define GPSR0_D11			BIT(11)
+#define GPSR0_D10			BIT(10)
+#define GPSR0_D9			BIT(9)
+#define GPSR0_D8			BIT(8)
+#define GPSR0_D7			BIT(7)
+#define GPSR0_D6			BIT(6)
+#define GPSR0_D5			BIT(5)
+#define GPSR0_D4			BIT(4)
+#define GPSR0_D3			BIT(3)
+#define GPSR0_D2			BIT(2)
+#define GPSR0_D1			BIT(1)
+#define GPSR0_D0			BIT(0)
+#define GPSR1_CLKOUT			BIT(28)
+#define GPSR1_EX_WAIT0_A		BIT(27)
+#define GPSR1_WE1			BIT(26)
+#define GPSR1_WE0			BIT(25)
+#define GPSR1_RD_WR			BIT(24)
+#define GPSR1_RD			BIT(23)
+#define GPSR1_BS			BIT(22)
+#define GPSR1_CS1_A26			BIT(21)
+#define GPSR1_CS0			BIT(20)
+#define GPSR1_A19			BIT(19)
+#define GPSR1_A18			BIT(18)
+#define GPSR1_A17			BIT(17)
+#define GPSR1_A16			BIT(16)
+#define GPSR1_A15			BIT(15)
+#define GPSR1_A14			BIT(14)
+#define GPSR1_A13			BIT(13)
+#define GPSR1_A12			BIT(12)
+#define GPSR1_A11			BIT(11)
+#define GPSR1_A10			BIT(10)
+#define GPSR1_A9			BIT(9)
+#define GPSR1_A8			BIT(8)
+#define GPSR1_A7			BIT(7)
+#define GPSR1_A6			BIT(6)
+#define GPSR1_A5			BIT(5)
+#define GPSR1_A4			BIT(4)
+#define GPSR1_A3			BIT(3)
+#define GPSR1_A2			BIT(2)
+#define GPSR1_A1			BIT(1)
+#define GPSR1_A0			BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A	BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A		BIT(13)
+#define GPSR2_AVB_LINK			BIT(12)
+#define GPSR2_AVB_PHY_INT		BIT(11)
+#define GPSR2_AVB_MAGIC			BIT(10)
+#define GPSR2_AVB_MDC			BIT(9)
+#define GPSR2_PWM2_A			BIT(8)
+#define GPSR2_PWM1_A			BIT(7)
+#define GPSR2_PWM0			BIT(6)
+#define GPSR2_IRQ5			BIT(5)
+#define GPSR2_IRQ4			BIT(4)
+#define GPSR2_IRQ3			BIT(3)
+#define GPSR2_IRQ2			BIT(2)
+#define GPSR2_IRQ1			BIT(1)
+#define GPSR2_IRQ0			BIT(0)
+#define GPSR3_SD1_WP			BIT(15)
+#define GPSR3_SD1_CD			BIT(14)
+#define GPSR3_SD0_WP			BIT(13)
+#define GPSR3_SD0_CD			BIT(12)
+#define GPSR3_SD1_DAT3			BIT(11)
+#define GPSR3_SD1_DAT2			BIT(10)
+#define GPSR3_SD1_DAT1			BIT(9)
+#define GPSR3_SD1_DAT0			BIT(8)
+#define GPSR3_SD1_CMD			BIT(7)
+#define GPSR3_SD1_CLK			BIT(6)
+#define GPSR3_SD0_DAT3			BIT(5)
+#define GPSR3_SD0_DAT2			BIT(4)
+#define GPSR3_SD0_DAT1			BIT(3)
+#define GPSR3_SD0_DAT0			BIT(2)
+#define GPSR3_SD0_CMD			BIT(1)
+#define GPSR3_SD0_CLK			BIT(0)
+#define GPSR4_SD3_DS			BIT(17)
+#define GPSR4_SD3_DAT7			BIT(16)
+#define GPSR4_SD3_DAT6			BIT(15)
+#define GPSR4_SD3_DAT5			BIT(14)
+#define GPSR4_SD3_DAT4			BIT(13)
+#define GPSR4_SD3_DAT3			BIT(12)
+#define GPSR4_SD3_DAT2			BIT(11)
+#define GPSR4_SD3_DAT1			BIT(10)
+#define GPSR4_SD3_DAT0			BIT(9)
+#define GPSR4_SD3_CMD			BIT(8)
+#define GPSR4_SD3_CLK			BIT(7)
+#define GPSR4_SD2_DS			BIT(6)
+#define GPSR4_SD2_DAT3			BIT(5)
+#define GPSR4_SD2_DAT2			BIT(4)
+#define GPSR4_SD2_DAT1			BIT(3)
+#define GPSR4_SD2_DAT0			BIT(2)
+#define GPSR4_SD2_CMD			BIT(1)
+#define GPSR4_SD2_CLK			BIT(0)
+#define GPSR5_MLB_DAT			BIT(25)
+#define GPSR5_MLB_SIG			BIT(24)
+#define GPSR5_MLB_CLK			BIT(23)
+#define GPSR5_MSIOF0_RXD		BIT(22)
+#define GPSR5_MSIOF0_SS2		BIT(21)
+#define GPSR5_MSIOF0_TXD		BIT(20)
+#define GPSR5_MSIOF0_SS1		BIT(19)
+#define GPSR5_MSIOF0_SYNC		BIT(18)
+#define GPSR5_MSIOF0_SCK		BIT(17)
+#define GPSR5_HRTS0			BIT(16)
+#define GPSR5_HCTS0			BIT(15)
+#define GPSR5_HTX0			BIT(14)
+#define GPSR5_HRX0			BIT(13)
+#define GPSR5_HSCK0			BIT(12)
+#define GPSR5_RX2_A			BIT(11)
+#define GPSR5_TX2_A			BIT(10)
+#define GPSR5_SCK2			BIT(9)
+#define GPSR5_RTS1			BIT(8)
+#define GPSR5_CTS1			BIT(7)
+#define GPSR5_TX1_A			BIT(6)
+#define GPSR5_RX1_A			BIT(5)
+#define GPSR5_RTS0			BIT(4)
+#define GPSR5_CTS0			BIT(3)
+#define GPSR5_TX0			BIT(2)
+#define GPSR5_RX0			BIT(1)
+#define GPSR5_SCK0			BIT(0)
+#define GPSR6_USB31_OVC			BIT(31)
+#define GPSR6_USB31_PWEN		BIT(30)
+#define GPSR6_USB30_OVC			BIT(29)
+#define GPSR6_USB30_PWEN		BIT(28)
+#define GPSR6_USB1_OVC			BIT(27)
+#define GPSR6_USB1_PWEN			BIT(26)
+#define GPSR6_USB0_OVC			BIT(25)
+#define GPSR6_USB0_PWEN			BIT(24)
+#define GPSR6_AUDIO_CLKB_B		BIT(23)
+#define GPSR6_AUDIO_CLKA_A		BIT(22)
+#define GPSR6_SSI_SDATA9_A		BIT(21)
+#define GPSR6_SSI_SDATA8		BIT(20)
+#define GPSR6_SSI_SDATA7		BIT(19)
+#define GPSR6_SSI_WS78			BIT(18)
+#define GPSR6_SSI_SCK78			BIT(17)
+#define GPSR6_SSI_SDATA6		BIT(16)
+#define GPSR6_SSI_WS6			BIT(15)
+#define GPSR6_SSI_SCK6			BIT(14)
+#define GPSR6_SSI_SDATA5		BIT(13)
+#define GPSR6_SSI_WS5			BIT(12)
+#define GPSR6_SSI_SCK5			BIT(11)
+#define GPSR6_SSI_SDATA4		BIT(10)
+#define GPSR6_SSI_WS4			BIT(9)
+#define GPSR6_SSI_SCK4			BIT(8)
+#define GPSR6_SSI_SDATA3		BIT(7)
+#define GPSR6_SSI_WS34			BIT(6)
+#define GPSR6_SSI_SCK34			BIT(5)
+#define GPSR6_SSI_SDATA2_A		BIT(4)
+#define GPSR6_SSI_SDATA1_A		BIT(3)
+#define GPSR6_SSI_SDATA0		BIT(2)
+#define GPSR6_SSI_WS0129		BIT(1)
+#define GPSR6_SSI_SCK0129		BIT(0)
+#define GPSR7_AVS2			BIT(1)
+#define GPSR7_AVS1			BIT(0)
+
+#define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD2_DS_33V		BIT(18)
+#define POC_SD2_DAT3_33V	BIT(17)
+#define POC_SD2_DAT2_33V	BIT(16)
+#define POC_SD2_DAT1_33V	BIT(15)
+#define POC_SD2_DAT0_33V	BIT(14)
+#define POC_SD2_CMD_33V		BIT(13)
+#define POC_SD2_CLK_33V		BIT(12)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
+
+#define DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define DRVCTRL2_MASK		(0x88888888U)
+#define DRVCTRL3_MASK		(0x88888888U)
+#define DRVCTRL4_MASK		(0x88888888U)
+#define DRVCTRL5_MASK		(0x88888888U)
+#define DRVCTRL6_MASK		(0x88888888U)
+#define DRVCTRL7_MASK		(0x88888888U)
+#define DRVCTRL8_MASK		(0x88888888U)
+#define DRVCTRL9_MASK		(0x88888888U)
+#define DRVCTRL10_MASK		(0x88888888U)
+#define DRVCTRL11_MASK		(0x888888CCU)
+#define DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define DRVCTRL13_MASK		(0xCC888888U)
+#define DRVCTRL14_MASK		(0x88888888U)
+#define DRVCTRL15_MASK		(0x88888888U)
+#define DRVCTRL16_MASK		(0x88888888U)
+#define DRVCTRL17_MASK		(0x88888888U)
+#define DRVCTRL18_MASK		(0x88888888U)
+#define DRVCTRL19_MASK		(0x88888888U)
+#define DRVCTRL20_MASK		(0x88888888U)
+#define DRVCTRL21_MASK		(0x88888888U)
+#define DRVCTRL22_MASK		(0x88888888U)
+#define DRVCTRL23_MASK		(0x88888888U)
+#define DRVCTRL24_MASK		(0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x)			((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x)			((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x)			((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x)			((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x)			((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x)			((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x)			((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x)			((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x)		((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x)		((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x)		((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x)		((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x)		((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x)		((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x)		((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x)		((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x)		((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A		((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B		((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C		((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D		((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E		((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A		((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B		((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C		((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D		((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A		((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B		((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C		((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D		((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E		((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F		((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G		((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A			((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B			((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A		((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B		((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A			((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B			((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A			((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B			((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A		((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B		((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A		((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B		((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C		((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D		((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A		((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B		((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A			((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B			((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A		((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B		((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C		((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A		((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B		((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A		((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B		((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A		((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B		((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A		((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B		((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C		((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A		((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B		((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C		((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A		((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B		((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A		((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B		((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C		((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A		((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B		((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C		((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D		((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A		((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B		((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C		((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D		((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E		((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A		((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B		((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A		((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B		((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C		((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D		((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A		((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B		((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C		((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D		((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E		((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A			((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B			((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A		((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B		((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C		((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D		((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A		((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B		((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A		((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B		((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C		((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A		((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B		((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A		((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B		((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A		((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B		((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A			((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B			((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A		((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B		((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A		((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B		((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A			((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B			((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A			((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B			((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A			((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B			((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A			((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B			((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A			((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B			((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A			((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B			((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A		((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B		((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A		((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B		((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A		((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B		((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A			((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B			((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C			((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D			((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A		((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B		((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A			((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B			((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C			((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A			((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B			((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A			((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B			((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A			((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B			((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A		((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B		((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A		((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B		((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A		((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B		((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A			((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B			((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2n(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0,
+		      MOD_SEL0_MSIOF3_A |
+		      MOD_SEL0_MSIOF2_A |
+		      MOD_SEL0_MSIOF1_A |
+		      MOD_SEL0_LBSC_A |
+		      MOD_SEL0_IEBUS_A |
+		      MOD_SEL0_I2C2_A |
+		      MOD_SEL0_I2C1_A |
+		      MOD_SEL0_HSCIF4_A |
+		      MOD_SEL0_HSCIF3_A |
+		      MOD_SEL0_HSCIF1_A |
+		      MOD_SEL0_FSO_A |
+		      MOD_SEL0_HSCIF2_A |
+		      MOD_SEL0_ETHERAVB_A |
+		      MOD_SEL0_DRIF3_A |
+		      MOD_SEL0_DRIF2_A |
+		      MOD_SEL0_DRIF1_A |
+		      MOD_SEL0_DRIF0_A |
+		      MOD_SEL0_CANFD0_A |
+		      MOD_SEL0_ADG_A_A);
+
+	pfc_reg_write(PFC_MOD_SEL1,
+		      MOD_SEL1_TSIF1_A |
+		      MOD_SEL1_TSIF0_A |
+		      MOD_SEL1_TIMER_TMU_A |
+		      MOD_SEL1_SSP1_1_A |
+		      MOD_SEL1_SSP1_0_A |
+		      MOD_SEL1_SSI_A |
+		      MOD_SEL1_SPEED_PULSE_IF_A |
+		      MOD_SEL1_SIMCARD_A |
+		      MOD_SEL1_SDHI2_A |
+		      MOD_SEL1_SCIF4_A |
+		      MOD_SEL1_SCIF3_A |
+		      MOD_SEL1_SCIF2_A |
+		      MOD_SEL1_SCIF1_A |
+		      MOD_SEL1_SCIF_A |
+		      MOD_SEL1_REMOCON_A |
+		      MOD_SEL1_RCAN0_A |
+		      MOD_SEL1_PWM6_A |
+		      MOD_SEL1_PWM5_A |
+		      MOD_SEL1_PWM4_A |
+		      MOD_SEL1_PWM3_A |
+		      MOD_SEL1_PWM2_A |
+		      MOD_SEL1_PWM1_A);
+
+	pfc_reg_write(PFC_MOD_SEL2,
+		      MOD_SEL2_I2C_5_B |
+		      MOD_SEL2_I2C_3_B |
+		      MOD_SEL2_I2C_0_B |
+		      MOD_SEL2_FM_A |
+		      MOD_SEL2_SCIF5_A |
+		      MOD_SEL2_I2C6_A |
+		      MOD_SEL2_NDF_A |
+		      MOD_SEL2_SSI2_A |
+		      MOD_SEL2_SSI9_A |
+		      MOD_SEL2_TIMER_TMU2_A |
+		      MOD_SEL2_ADG_B_A |
+		      MOD_SEL2_ADG_C_A |
+		      MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR1,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(3) |
+		      IPSR_8_FUNC(3) |
+		      IPSR_4_FUNC(3) |
+		      IPSR_0_FUNC(3));
+
+	pfc_reg_write(PFC_IPSR2,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR3,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR4,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR5,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR6,
+		      IPSR_28_FUNC(6) |
+		      IPSR_24_FUNC(6) |
+		      IPSR_20_FUNC(6) |
+		      IPSR_16_FUNC(6) |
+		      IPSR_12_FUNC(6) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR7,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(6) |
+		      IPSR_4_FUNC(6) |
+		      IPSR_0_FUNC(6));
+
+	pfc_reg_write(PFC_IPSR8,
+		      IPSR_28_FUNC(1) |
+		      IPSR_24_FUNC(1) |
+		      IPSR_20_FUNC(1) |
+		      IPSR_16_FUNC(1) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR9,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR10,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR11,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(4) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR12,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(4) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR13,
+		      IPSR_28_FUNC(8) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(3) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR14,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(3) |
+		      IPSR_0_FUNC(8));
+
+	pfc_reg_write(PFC_IPSR15,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR16,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(0) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR17,
+		      IPSR_28_FUNC(0) |
+		      IPSR_24_FUNC(0) |
+		      IPSR_20_FUNC(0) |
+		      IPSR_16_FUNC(0) |
+		      IPSR_12_FUNC(0) |
+		      IPSR_8_FUNC(0) |
+		      IPSR_4_FUNC(1) |
+		      IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0) | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/peripheral function select */
+	pfc_reg_write(PFC_GPSR0,
+		      GPSR0_D15 |
+		      GPSR0_D14 |
+		      GPSR0_D13 |
+		      GPSR0_D12 |
+		      GPSR0_D11 |
+		      GPSR0_D10 |
+		      GPSR0_D9 |
+		      GPSR0_D8 |
+		      GPSR0_D7 |
+		      GPSR0_D6 |
+		      GPSR0_D5 |
+		      GPSR0_D4 |
+		      GPSR0_D3 |
+		      GPSR0_D2 |
+		      GPSR0_D0);
+
+	pfc_reg_write(PFC_GPSR1,
+		      GPSR1_CLKOUT |
+		      GPSR1_EX_WAIT0_A |
+		      GPSR1_WE1 |
+		      GPSR1_RD |
+		      GPSR1_RD_WR |
+		      GPSR1_CS0 |
+		      GPSR1_A19 |
+		      GPSR1_A18 |
+		      GPSR1_A17 |
+		      GPSR1_A16 |
+		      GPSR1_A15 |
+		      GPSR1_A14 |
+		      GPSR1_A13 |
+		      GPSR1_A12 |
+		      GPSR1_A7 |
+		      GPSR1_A6 |
+		      GPSR1_A5 |
+		      GPSR1_A4 |
+		      GPSR1_A3 |
+		      GPSR1_A2 |
+		      GPSR1_A1 |
+		      GPSR1_A0);
+
+	pfc_reg_write(PFC_GPSR2,
+		      GPSR2_AVB_AVTP_CAPTURE_A |
+		      GPSR2_AVB_AVTP_MATCH_A |
+		      GPSR2_AVB_LINK |
+		      GPSR2_AVB_PHY_INT |
+		      GPSR2_AVB_MDC |
+		      GPSR2_PWM2_A |
+		      GPSR2_PWM1_A |
+		      GPSR2_IRQ4 |
+		      GPSR2_IRQ3 |
+		      GPSR2_IRQ2 |
+		      GPSR2_IRQ1 |
+		      GPSR2_IRQ0);
+
+	pfc_reg_write(PFC_GPSR3,
+		      GPSR3_SD0_CD |
+		      GPSR3_SD1_DAT3 |
+		      GPSR3_SD1_DAT2 |
+		      GPSR3_SD1_DAT1 |
+		      GPSR3_SD1_DAT0 |
+		      GPSR3_SD0_DAT3 |
+		      GPSR3_SD0_DAT2 |
+		      GPSR3_SD0_DAT1 |
+		      GPSR3_SD0_DAT0 |
+		      GPSR3_SD0_CMD |
+		      GPSR3_SD0_CLK);
+
+	pfc_reg_write(PFC_GPSR4,
+		      GPSR4_SD3_DS |
+		      GPSR4_SD3_DAT7 |
+		      GPSR4_SD3_DAT6 |
+		      GPSR4_SD3_DAT5 |
+		      GPSR4_SD3_DAT4 |
+		      GPSR4_SD3_DAT3 |
+		      GPSR4_SD3_DAT2 |
+		      GPSR4_SD3_DAT1 |
+		      GPSR4_SD3_DAT0 |
+		      GPSR4_SD3_CMD |
+		      GPSR4_SD3_CLK |
+		      GPSR4_SD2_DAT3 |
+		      GPSR4_SD2_DAT2 |
+		      GPSR4_SD2_DAT1 |
+		      GPSR4_SD2_DAT0 |
+		      GPSR4_SD2_CMD |
+		      GPSR4_SD2_CLK);
+
+	pfc_reg_write(PFC_GPSR5,
+		      GPSR5_MSIOF0_RXD |
+		      GPSR5_MSIOF0_TXD |
+		      GPSR5_MSIOF0_SYNC |
+		      GPSR5_MSIOF0_SCK |
+		      GPSR5_RX2_A |
+		      GPSR5_TX2_A |
+		      GPSR5_RTS1 |
+		      GPSR5_CTS1 |
+		      GPSR5_TX1_A |
+		      GPSR5_RX1_A |
+		      GPSR5_RTS0 |
+		      GPSR5_SCK0);
+
+	pfc_reg_write(PFC_GPSR6,
+		      GPSR6_AUDIO_CLKB_B |
+		      GPSR6_AUDIO_CLKA_A |
+		      GPSR6_SSI_WS6 |
+		      GPSR6_SSI_SCK6 |
+		      GPSR6_SSI_SDATA4 |
+		      GPSR6_SSI_WS4 |
+		      GPSR6_SSI_SCK4 |
+		      GPSR6_SSI_SDATA1_A |
+		      GPSR6_SSI_SDATA0 |
+		      GPSR6_SSI_WS0129 |
+		      GPSR6_SSI_SCK0129);
+
+	pfc_reg_write(PFC_GPSR7, GPSR7_AVS2 | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0,
+		      POC_SD0_DAT3_33V |
+		      POC_SD0_DAT2_33V |
+		      POC_SD0_DAT1_33V |
+		      POC_SD0_DAT0_33V |
+		      POC_SD0_CMD_33V |
+		      POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = (reg & DRVCTRL0_MASK) |
+	      DRVCTRL0_QSPI0_SPCLK(3) |
+	      DRVCTRL0_QSPI0_MOSI_IO0(3) |
+	      DRVCTRL0_QSPI0_MISO_IO1(3) |
+	      DRVCTRL0_QSPI0_IO2(3) |
+	      DRVCTRL0_QSPI0_IO3(3) |
+	      DRVCTRL0_QSPI0_SSL(3) |
+	      DRVCTRL0_QSPI1_SPCLK(3) |
+	      DRVCTRL0_QSPI1_MOSI_IO0(3);
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = (reg & DRVCTRL1_MASK) |
+	      DRVCTRL1_QSPI1_MISO_IO1(3) |
+	      DRVCTRL1_QSPI1_IO2(3) |
+	      DRVCTRL1_QSPI1_IO3(3) |
+	      DRVCTRL1_QSPI1_SS(3) |
+	      DRVCTRL1_RPC_INT(3) |
+	      DRVCTRL1_RPC_WP(3) |
+	      DRVCTRL1_RPC_RESET(3) |
+	      DRVCTRL1_AVB_RX_CTL(7);
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = (reg & DRVCTRL2_MASK) |
+	      DRVCTRL2_AVB_RXC(7) |
+	      DRVCTRL2_AVB_RD0(7) |
+	      DRVCTRL2_AVB_RD1(7) |
+	      DRVCTRL2_AVB_RD2(7) |
+	      DRVCTRL2_AVB_RD3(7) |
+	      DRVCTRL2_AVB_TX_CTL(3) |
+	      DRVCTRL2_AVB_TXC(3) |
+	      DRVCTRL2_AVB_TD0(3);
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = (reg & DRVCTRL3_MASK) |
+	      DRVCTRL3_AVB_TD1(3) |
+	      DRVCTRL3_AVB_TD2(3) |
+	      DRVCTRL3_AVB_TD3(3) |
+	      DRVCTRL3_AVB_TXCREFCLK(7) |
+	      DRVCTRL3_AVB_MDIO(7) |
+	      DRVCTRL3_AVB_MDC(7) |
+	      DRVCTRL3_AVB_MAGIC(7) |
+	      DRVCTRL3_AVB_PHY_INT(7);
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = (reg & DRVCTRL4_MASK) |
+	      DRVCTRL4_AVB_LINK(7) |
+	      DRVCTRL4_AVB_AVTP_MATCH(7) |
+	      DRVCTRL4_AVB_AVTP_CAPTURE(7) |
+	      DRVCTRL4_IRQ0(7) |
+	      DRVCTRL4_IRQ1(7) |
+	      DRVCTRL4_IRQ2(7) |
+	      DRVCTRL4_IRQ3(7) |
+	      DRVCTRL4_IRQ4(7);
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = (reg & DRVCTRL5_MASK) |
+	      DRVCTRL5_IRQ5(7) |
+	      DRVCTRL5_PWM0(7) |
+	      DRVCTRL5_PWM1(7) |
+	      DRVCTRL5_PWM2(7) |
+	      DRVCTRL5_A0(3) |
+	      DRVCTRL5_A1(3) |
+	      DRVCTRL5_A2(3) |
+	      DRVCTRL5_A3(3);
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = (reg & DRVCTRL6_MASK) |
+	      DRVCTRL6_A4(3) |
+	      DRVCTRL6_A5(3) |
+	      DRVCTRL6_A6(3) |
+	      DRVCTRL6_A7(3) |
+	      DRVCTRL6_A8(7) |
+	      DRVCTRL6_A9(7) |
+	      DRVCTRL6_A10(7) |
+	      DRVCTRL6_A11(7);
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = (reg & DRVCTRL7_MASK) |
+	      DRVCTRL7_A12(3) |
+	      DRVCTRL7_A13(3) |
+	      DRVCTRL7_A14(3) |
+	      DRVCTRL7_A15(3) |
+	      DRVCTRL7_A16(3) |
+	      DRVCTRL7_A17(3) |
+	      DRVCTRL7_A18(3) |
+	      DRVCTRL7_A19(3);
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = (reg & DRVCTRL8_MASK) |
+	      DRVCTRL8_CLKOUT(7) |
+	      DRVCTRL8_CS0(7) |
+	      DRVCTRL8_CS1_A2(7) |
+	      DRVCTRL8_BS(7) |
+	      DRVCTRL8_RD(7) |
+	      DRVCTRL8_RD_W(7) |
+	      DRVCTRL8_WE0(7) |
+	      DRVCTRL8_WE1(7);
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = (reg & DRVCTRL9_MASK) |
+	      DRVCTRL9_EX_WAIT0(7) |
+	      DRVCTRL9_PRESETOU(7) |
+	      DRVCTRL9_D0(7) |
+	      DRVCTRL9_D1(7) |
+	      DRVCTRL9_D2(7) |
+	      DRVCTRL9_D3(7) |
+	      DRVCTRL9_D4(7) |
+	      DRVCTRL9_D5(7);
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = (reg & DRVCTRL10_MASK) |
+	      DRVCTRL10_D6(7) |
+	      DRVCTRL10_D7(7) |
+	      DRVCTRL10_D8(3) |
+	      DRVCTRL10_D9(3) |
+	      DRVCTRL10_D10(3) |
+	      DRVCTRL10_D11(3) |
+	      DRVCTRL10_D12(3) |
+	      DRVCTRL10_D13(3);
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = (reg & DRVCTRL11_MASK) |
+	      DRVCTRL11_D14(3) |
+	      DRVCTRL11_D15(3) |
+	      DRVCTRL11_AVS1(7) |
+	      DRVCTRL11_AVS2(7) |
+	      DRVCTRL11_GP7_02(7) |
+	      DRVCTRL11_GP7_03(7) |
+	      DRVCTRL11_DU_DOTCLKIN0(3) |
+	      DRVCTRL11_DU_DOTCLKIN1(3);
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = (reg & DRVCTRL12_MASK) |
+	      DRVCTRL12_DU_DOTCLKIN2(3) |
+	      DRVCTRL12_DU_DOTCLKIN3(3) |
+	      DRVCTRL12_DU_FSCLKST(3) |
+	      DRVCTRL12_DU_TMS(3);
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = (reg & DRVCTRL13_MASK) |
+	      DRVCTRL13_TDO(3) |
+	      DRVCTRL13_ASEBRK(3) |
+	      DRVCTRL13_SD0_CLK(7) |
+	      DRVCTRL13_SD0_CMD(7) |
+	      DRVCTRL13_SD0_DAT0(7) |
+	      DRVCTRL13_SD0_DAT1(7) |
+	      DRVCTRL13_SD0_DAT2(7) |
+	      DRVCTRL13_SD0_DAT3(7);
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = (reg & DRVCTRL14_MASK) |
+	      DRVCTRL14_SD1_CLK(7) |
+	      DRVCTRL14_SD1_CMD(7) |
+	      DRVCTRL14_SD1_DAT0(5) |
+	      DRVCTRL14_SD1_DAT1(5) |
+	      DRVCTRL14_SD1_DAT2(5) |
+	      DRVCTRL14_SD1_DAT3(5) |
+	      DRVCTRL14_SD2_CLK(5) |
+	      DRVCTRL14_SD2_CMD(5);
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = (reg & DRVCTRL15_MASK) |
+	      DRVCTRL15_SD2_DAT0(5) |
+	      DRVCTRL15_SD2_DAT1(5) |
+	      DRVCTRL15_SD2_DAT2(5) |
+	      DRVCTRL15_SD2_DAT3(5) |
+	      DRVCTRL15_SD2_DS(5) |
+	      DRVCTRL15_SD3_CLK(7) |
+	      DRVCTRL15_SD3_CMD(7) |
+	      DRVCTRL15_SD3_DAT0(7);
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = (reg & DRVCTRL16_MASK) |
+	      DRVCTRL16_SD3_DAT1(7) |
+	      DRVCTRL16_SD3_DAT2(7) |
+	      DRVCTRL16_SD3_DAT3(7) |
+	      DRVCTRL16_SD3_DAT4(7) |
+	      DRVCTRL16_SD3_DAT5(7) |
+	      DRVCTRL16_SD3_DAT6(7) |
+	      DRVCTRL16_SD3_DAT7(7) |
+	      DRVCTRL16_SD3_DS(7);
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = (reg & DRVCTRL17_MASK) |
+	      DRVCTRL17_SD0_CD(7) |
+	      DRVCTRL17_SD0_WP(7) |
+	      DRVCTRL17_SD1_CD(7) |
+	      DRVCTRL17_SD1_WP(7) |
+	      DRVCTRL17_SCK0(7) |
+	      DRVCTRL17_RX0(7) |
+	      DRVCTRL17_TX0(7) |
+	      DRVCTRL17_CTS0(7);
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = (reg & DRVCTRL18_MASK) |
+	      DRVCTRL18_RTS0_TANS(7) |
+	      DRVCTRL18_RX1(7) |
+	      DRVCTRL18_TX1(7) |
+	      DRVCTRL18_CTS1(7) |
+	      DRVCTRL18_RTS1_TANS(7) |
+	      DRVCTRL18_SCK2(7) |
+	      DRVCTRL18_TX2(7) |
+	      DRVCTRL18_RX2(7);
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = (reg & DRVCTRL19_MASK) |
+	      DRVCTRL19_HSCK0(7) |
+	      DRVCTRL19_HRX0(7) |
+	      DRVCTRL19_HTX0(7) |
+	      DRVCTRL19_HCTS0(7) |
+	      DRVCTRL19_HRTS0(7) |
+	      DRVCTRL19_MSIOF0_SCK(7) |
+	      DRVCTRL19_MSIOF0_SYNC(7) |
+	      DRVCTRL19_MSIOF0_SS1(7);
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = (reg & DRVCTRL20_MASK) |
+	      DRVCTRL20_MSIOF0_TXD(7) |
+	      DRVCTRL20_MSIOF0_SS2(7) |
+	      DRVCTRL20_MSIOF0_RXD(7) |
+	      DRVCTRL20_MLB_CLK(7) |
+	      DRVCTRL20_MLB_SIG(7) |
+	      DRVCTRL20_MLB_DAT(7) |
+	      DRVCTRL20_MLB_REF(7) |
+	      DRVCTRL20_SSI_SCK0129(7);
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = (reg & DRVCTRL21_MASK) |
+	      DRVCTRL21_SSI_WS0129(7) |
+	      DRVCTRL21_SSI_SDATA0(7) |
+	      DRVCTRL21_SSI_SDATA1(7) |
+	      DRVCTRL21_SSI_SDATA2(7) |
+	      DRVCTRL21_SSI_SCK34(7) |
+	      DRVCTRL21_SSI_WS34(7) |
+	      DRVCTRL21_SSI_SDATA3(7) |
+	      DRVCTRL21_SSI_SCK4(7);
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = (reg & DRVCTRL22_MASK) |
+	      DRVCTRL22_SSI_WS4(7) |
+	      DRVCTRL22_SSI_SDATA4(7) |
+	      DRVCTRL22_SSI_SCK5(7) |
+	      DRVCTRL22_SSI_WS5(7) |
+	      DRVCTRL22_SSI_SDATA5(7) |
+	      DRVCTRL22_SSI_SCK6(7) |
+	      DRVCTRL22_SSI_WS6(7) |
+	      DRVCTRL22_SSI_SDATA6(7);
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = (reg & DRVCTRL23_MASK) |
+	      DRVCTRL23_SSI_SCK78(7) |
+	      DRVCTRL23_SSI_WS78(7) |
+	      DRVCTRL23_SSI_SDATA7(7) |
+	      DRVCTRL23_SSI_SDATA8(7) |
+	      DRVCTRL23_SSI_SDATA9(7) |
+	      DRVCTRL23_AUDIO_CLKA(7) |
+	      DRVCTRL23_AUDIO_CLKB(7) |
+	      DRVCTRL23_USB0_PWEN(7);
+
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = (reg & DRVCTRL24_MASK) |
+	      DRVCTRL24_USB0_OVC(7) |
+	      DRVCTRL24_USB1_PWEN(7) |
+	      DRVCTRL24_USB1_OVC(7) |
+	      DRVCTRL24_USB30_PWEN(7) |
+	      DRVCTRL24_USB30_OVC(7) |
+	      DRVCTRL24_USB31_PWEN(7) |
+	      DRVCTRL24_USB31_OVC(7);
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300EFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000001U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003800U);
+	mmio_write_32(GPIO_OUTDT7, 0x00000003U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000001U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00100B00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000418U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00002000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000040U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00000208U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013F00U);
+	mmio_write_32(GPIO_INOUTSEL7, 0x00000003U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h
new file mode 100644
index 0000000..f0616b6
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2N_H
+#define PFC_INIT_G2N_H
+
+void pfc_init_g2n(void);
+
+#endif /* PFC_INIT_G2N_H */
diff --git a/drivers/renesas/rzg/pfc/pfc.mk b/drivers/renesas/rzg/pfc/pfc.mk
index 5cae658..15d0e8d 100644
--- a/drivers/renesas/rzg/pfc/pfc.mk
+++ b/drivers/renesas/rzg/pfc/pfc.mk
@@ -1,20 +1,41 @@
 #
-# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 ifeq (${RCAR_LSI},${RCAR_AUTO})
     BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
 
 else ifdef RCAR_LSI_CUT_COMPAT
   ifeq (${RCAR_LSI},${RZ_G2M})
     BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
   endif
+  ifeq (${RCAR_LSI},${RZ_G2H})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2N})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2E})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
+  endif
 else
   ifeq (${RCAR_LSI},${RZ_G2M})
     BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
   endif
+  ifeq (${RCAR_LSI},${RZ_G2H})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2N})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2E})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
+  endif
 endif
 
 BL2_SOURCES += drivers/renesas/rzg/pfc/pfc_init.c
diff --git a/drivers/renesas/rzg/pfc/pfc_init.c b/drivers/renesas/rzg/pfc/pfc_init.c
index f51992d..762450c 100644
--- a/drivers/renesas/rzg/pfc/pfc_init.c
+++ b/drivers/renesas/rzg/pfc/pfc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,11 +9,23 @@
 #include <lib/mmio.h>
 
 #if RCAR_LSI == RCAR_AUTO
+#include "G2E/pfc_init_g2e.h"
+#include "G2H/pfc_init_g2h.h"
 #include "G2M/pfc_init_g2m.h"
+#include "G2N/pfc_init_g2n.h"
 #endif /* RCAR_LSI == RCAR_AUTO */
+#if (RCAR_LSI == RZ_G2E)
+#include "G2E/pfc_init_g2e.h"
+#endif /* RCAR_LSI == RZ_G2N */
+#if (RCAR_LSI == RZ_G2H)
+#include "G2H/pfc_init_g2h.h"
+#endif /* RCAR_LSI == RZ_G2H */
 #if (RCAR_LSI == RZ_G2M)
 #include "G2M/pfc_init_g2m.h"
 #endif /* RCAR_LSI == RZ_G2M */
+#if (RCAR_LSI == RZ_G2N)
+#include "G2N/pfc_init_g2n.h"
+#endif /* RCAR_LSI == RZ_G2N */
 #include "rcar_def.h"
 
 #define PRR_PRODUCT_ERR(reg)				\
@@ -40,6 +52,15 @@
 	case PRR_PRODUCT_M3:
 		pfc_init_g2m();
 		break;
+	case PRR_PRODUCT_H3:
+		pfc_init_g2h();
+		break;
+	case PRR_PRODUCT_M3N:
+		pfc_init_g2n();
+		break;
+	case PRR_PRODUCT_E3:
+		pfc_init_g2e();
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -54,6 +75,27 @@
 		pfc_init_g2m();
 #endif /* RCAR_LSI != RZ_G2M */
 		break;
+	case PRR_PRODUCT_H3:
+#if (RCAR_LSI != RZ_G2H)
+		PRR_PRODUCT_ERR(reg);
+#else /* RCAR_LSI != RZ_G2H */
+		pfc_init_g2h();
+#endif /* RCAR_LSI != RZ_G2H */
+		break;
+	case PRR_PRODUCT_M3N:
+#if RCAR_LSI != RZ_G2N
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_g2n();
+#endif /* RCAR_LSI != RZ_G2N */
+		break;
+	case PRR_PRODUCT_E3:
+#if RCAR_LSI != RZ_G2E
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_g2e();
+#endif
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -65,6 +107,21 @@
 		PRR_PRODUCT_ERR(reg);
 	}
 	pfc_init_m3();
+#elif (RCAR_LSI == RZ_G2H)
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_H3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_g2h();
+#elif (RCAR_LSI == RZ_G2N)	/* G2N */
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_M3N) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_g2n();
+#elif (RCAR_LSI == RZ_G2E)
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_E3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_g2e();
 #else /* RCAR_LSI == RZ_G2M */
 #error "Don't have PFC initialize routine(unknown)."
 #endif /* RCAR_LSI == RZ_G2M */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
new file mode 100644
index 0000000..14ccc21
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2e_v10.h"
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION	"rev.0.05"
+
+#define REF_ARS_ARBSTOPCYCLE_G2E	(((SL_INIT_SSLOTCLK_G2E) - 5U) << 16U)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2e_v10_mstat390.h"
+#else
+#include "qos_init_g2e_v10_mstat780.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */
+
+static const struct rcar_gen3_dbsc_qos_settings g2e_qos[] = {
+	/* BUFCAM settings */
+	{ DBSC_DBCAM0CNF1, 0x00043218U },
+	{ DBSC_DBCAM0CNF2, 0x000000F4U },
+	{ DBSC_DBSCHCNT0, 0x000F0037U },
+	{ DBSC_DBSCHSZ0, 0x00000001U },
+	{ DBSC_DBSCHRW0, 0x22421111U },
+
+	/* DDR3 */
+	{ DBSC_SCFCTST2, 0x012F1123U },
+
+	/* QoS Settings */
+	{ DBSC_DBSCHQOS00, 0x00000F00U },
+	{ DBSC_DBSCHQOS01, 0x00000B00U },
+	{ DBSC_DBSCHQOS02, 0x00000000U },
+	{ DBSC_DBSCHQOS03, 0x00000000U },
+	{ DBSC_DBSCHQOS40, 0x00000300U },
+	{ DBSC_DBSCHQOS41, 0x000002F0U },
+	{ DBSC_DBSCHQOS42, 0x00000200U },
+	{ DBSC_DBSCHQOS43, 0x00000100U },
+	{ DBSC_DBSCHQOS90, 0x00000100U },
+	{ DBSC_DBSCHQOS91, 0x000000F0U },
+	{ DBSC_DBSCHQOS92, 0x000000A0U },
+	{ DBSC_DBSCHQOS93, 0x00000040U },
+	{ DBSC_DBSCHQOS130, 0x00000100U },
+	{ DBSC_DBSCHQOS131, 0x000000F0U },
+	{ DBSC_DBSCHQOS132, 0x000000A0U },
+	{ DBSC_DBSCHQOS133, 0x00000040U },
+	{ DBSC_DBSCHQOS140, 0x000000C0U },
+	{ DBSC_DBSCHQOS141, 0x000000B0U },
+	{ DBSC_DBSCHQOS142, 0x00000080U },
+	{ DBSC_DBSCHQOS143, 0x00000040U },
+	{ DBSC_DBSCHQOS150, 0x00000040U },
+	{ DBSC_DBSCHQOS151, 0x00000030U },
+	{ DBSC_DBSCHQOS152, 0x00000020U },
+	{ DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2e_v10(void)
+{
+	rzg_qos_dbsc_setting(g2e_qos, ARRAY_SIZE(g2e_qos), true);
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_RZ_G2E
+#error "Don't set DRAM Split 4ch(G2E)"
+#else
+	ERROR("DRAM Split 4ch not supported.(G2E)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RCAR_RZ_G2E
+#error "Don't set DRAM Split 2ch(G2E)"
+#else
+	ERROR("DRAM Split 2ch not supported.(G2E)");
+	panic();
+#endif
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 7.8 usec\n");
+#endif
+
+	mmio_write_32(QOSCTRL_RAS, 0x00000020U);
+	mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+	mmio_write_32(QOSCTRL_DANT, 0x00100804U);
+	mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+	mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+	mmio_write_32(QOSCTRL_EARLYR, 0x00000000U);
+	mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+		      SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2E);
+	mmio_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_G2E);
+
+	/* QOSBW SRAM setting */
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+		mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+		mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+	}
+
+	/* RT bus Leaf setting */
+	mmio_write_32(RT_ACT0, 0x00000000U);
+	mmio_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	mmio_write_32(CPU_ACT0, 0x00000003U);
+	mmio_write_32(CPU_ACT1, 0x00000003U);
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+	mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif
+}
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h
new file mode 100644
index 0000000..d27de1b
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_H
+#define QOS_INIT_G2E_V10_H
+
+void qos_init_g2e_v10(void);
+
+#endif /* QOS_INIT_G2E_V10_H */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h
new file mode 100644
index 0000000..63b08c4
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_MSTAT390_H
+#define QOS_INIT_G2E_V10_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008620000FFFFUL,
+	/* 0x0038, */ 0x001008620000FFFFUL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x001415260000FFFFUL,
+	/* 0x0060, */ 0x001415260000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001414930000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08380000FFFFUL,
+	/* 0x00a8, */ 0x000C04110000FFFFUL,
+	/* 0x00b0, */ 0x000C04150000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08380000FFFFUL,
+	/* 0x00c8, */ 0x000C04110000FFFFUL,
+	/* 0x00d0, */ 0x000C04150000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x000C084F0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x000C21E40000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001008530000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00100C960000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x001008530000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0010042A0000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00101D8D0000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x001008530000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x001410040000FFFFUL,
+	/* 0x0270, */ 0x001404020000FFFFUL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFFFUL,
+	/* 0x0298, */ 0x001404020000FFFFUL,
+	/* 0x02a0, */ 0x000C04090000FFFFUL,
+	/* 0x02a8, */ 0x000C04090000FFFFUL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04090000FFFFUL,
+	/* 0x02d8, */ 0x000C04090000FFFFUL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04020000FFFFUL,
+	/* 0x0378, */ 0x000C04020000FFFFUL,
+	/* 0x0380, */ 0x000C04090000FFFFUL,
+	/* 0x0388, */ 0x000C04090000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005F03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060005FFFC01UL,
+	/* 0x01c8, */ 0x0021060005FFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0011010005F79801UL,
+	/* 0x0220, */ 0x0011010005F79801UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010005F79801UL,
+	/* 0x0238, */ 0x0011010005F79801UL,
+	/* 0x0240, */ 0x0012010005F79801UL,
+	/* 0x0248, */ 0x0011010005F79801UL,
+	/* 0x0250, */ 0x0012010005F79801UL,
+	/* 0x0258, */ 0x0011010005F79801UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060005FFFC01UL,
+	/* 0x02f8, */ 0x0011060005FFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001005F03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060005FFFC01UL,
+	/* 0x0360, */ 0x0012060005FFFC01UL,
+	/* 0x0368, */ 0x0012001005F03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001005F03401UL,
+};
+#endif /* QOS_INIT_G2E_V10_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h
new file mode 100644
index 0000000..3b888ea
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_MSTAT780_H
+#define QOS_INIT_G2E_V10_MSTAT780_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001010C40000FFFFUL,
+	/* 0x0038, */ 0x001010C40000FFFFUL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00142A4B0000FFFFUL,
+	/* 0x0060, */ 0x00142A4B0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001429260000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C10700000FFFFUL,
+	/* 0x00a8, */ 0x000C08210000FFFFUL,
+	/* 0x00b0, */ 0x000C082A0000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C10700000FFFFUL,
+	/* 0x00c8, */ 0x000C08210000FFFFUL,
+	/* 0x00d0, */ 0x000C082A0000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x00102CAF0000FFFFUL,
+	/* 0x00f8, */ 0x000C0C9D0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100CAF0000FFFFUL,
+	/* 0x0118, */ 0x000C43C80000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100CA50000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010152C0000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x00100CA50000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008530000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001037190000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x00100CA50000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04040000FFFFUL,
+	/* 0x01f0, */ 0x000C08110000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04110000FFFFUL,
+	/* 0x0210, */ 0x000C08110000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C18530000FFFFUL,
+	/* 0x0268, */ 0x00141C070000FFFFUL,
+	/* 0x0270, */ 0x001404040000FFFFUL,
+	/* 0x0278, */ 0x000C0C210000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x00141C070000FFFFUL,
+	/* 0x0298, */ 0x001404040000FFFFUL,
+	/* 0x02a0, */ 0x000C04110000FFFFUL,
+	/* 0x02a8, */ 0x000C04110000FFFFUL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x000C04040000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04110000FFFFUL,
+	/* 0x02d8, */ 0x000C04110000FFFFUL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x000C04040000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04040000FFFFUL,
+	/* 0x0378, */ 0x000C04040000FFFFUL,
+	/* 0x0380, */ 0x000C04110000FFFFUL,
+	/* 0x0388, */ 0x000C04110000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001002F03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060002FFFC01UL,
+	/* 0x01c8, */ 0x0021060002FFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021010002F3CC01UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021010002F3CC01UL,
+	/* 0x0218, */ 0x0011010002F3CC01UL,
+	/* 0x0220, */ 0x0011010002F3CC01UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010002F3CC01UL,
+	/* 0x0238, */ 0x0011010002F3CC01UL,
+	/* 0x0240, */ 0x0012010002F3CC01UL,
+	/* 0x0248, */ 0x0011010002F3CC01UL,
+	/* 0x0250, */ 0x0012010002F3CC01UL,
+	/* 0x0258, */ 0x0011010002F3CC01UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060002FFFC01UL,
+	/* 0x02f8, */ 0x0011060002FFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001002F03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060002FFFC01UL,
+	/* 0x0360, */ 0x0012060002FFFC01UL,
+	/* 0x0368, */ 0x0012001002F03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001002F03401UL,
+};
+
+#endif /* QOS_INIT_G2E_V10_MSTAT780_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h
new file mode 100644
index 0000000..7bb34aa
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_MSTAT195_H
+#define QOS_INIT_G2H_MSTAT195_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000FFFFUL,
+	/* 0x0038, */ 0x001008070000FFFFUL,
+	/* 0x0040, */ 0x001410070000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404010000FFFFUL,
+	/* 0x0058, */ 0x0014100D0000FFFFUL,
+	/* 0x0060, */ 0x0014100D0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404010000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001410070000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C04020000FFFFUL,
+	/* 0x00a8, */ 0x000C04010000FFFFUL,
+	/* 0x00b0, */ 0x000C04010000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C04020000FFFFUL,
+	/* 0x00c8, */ 0x000C04010000FFFFUL,
+	/* 0x00d0, */ 0x000C04010000FFFFUL,
+	/* 0x00d8, */ 0x001024090000FFFFUL,
+	/* 0x00e0, */ 0x00100C090000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001024090000FFFFUL,
+	/* 0x00f8, */ 0x000C100D0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100C090000FFFFUL,
+	/* 0x0118, */ 0x000C1C1B0000FFFFUL,
+	/* 0x0120, */ 0x000C1C1B0000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100C0B0000FFFFUL,
+	/* 0x0140, */ 0x00100C0B0000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010100D0000FFFFUL,
+	/* 0x0158, */ 0x0010100D0000FFFFUL,
+	/* 0x0160, */ 0x00100C0B0000FFFFUL,
+	/* 0x0168, */ 0x00100C0B0000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008060000FFFFUL,
+	/* 0x0180, */ 0x001008060000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00102C2C0000FFFFUL,
+	/* 0x0198, */ 0x00102C2C0000FFFFUL,
+	/* 0x01a0, */ 0x00100C0B0000FFFFUL,
+	/* 0x01a8, */ 0x00100C0B0000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFFFUL,
+	/* 0x0268, */ 0x001408010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C04010000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x001408010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x001408010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x001200600BDFFC01UL,
+	/* 0x0008, */ 0x001200600BDFFC01UL,
+	/* 0x0010, */ 0x001200600BDFFC01UL,
+	/* 0x0018, */ 0x001200600BDFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002100600BDFFC01UL,
+	/* 0x01c8, */ 0x002100600BDFFC01UL,
+	/* 0x01d0, */ 0x002100600BDFFC01UL,
+	/* 0x01d8, */ 0x002100600BDFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x002100100BDF2401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x002100100BDF2401UL,
+	/* 0x0218, */ 0x001100100BDF2401UL,
+	/* 0x0220, */ 0x001100100BDF2401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001100100BDF2401UL,
+	/* 0x0238, */ 0x001100100BDF2401UL,
+	/* 0x0240, */ 0x001200100BDF2401UL,
+	/* 0x0248, */ 0x001100100BDF2401UL,
+	/* 0x0250, */ 0x001200100BDF2401UL,
+	/* 0x0258, */ 0x001100100BDF2401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001100600BDFFC01UL,
+	/* 0x02f8, */ 0x001100600BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x001100600BDFFC01UL,
+	/* 0x0310, */ 0x001100600BDFFC01UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x001100600BDFFC01UL,
+	/* 0x0328, */ 0x001100600BDFFC01UL,
+	/* 0x0330, */ 0x001100600BDFFC01UL,
+	/* 0x0338, */ 0x001100600BDFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x001200100BD0FC01UL,
+};
+
+#endif /* QOS_INIT_G2H_MSTAT195_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h
new file mode 100644
index 0000000..9696a40
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_MSTAT390_H
+#define QOS_INIT_G2H_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000FFFFUL,
+	/* 0x0038, */ 0x0010100D0000FFFFUL,
+	/* 0x0040, */ 0x00141C0E0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001408010000FFFFUL,
+	/* 0x0058, */ 0x00141C190000FFFFUL,
+	/* 0x0060, */ 0x00141C190000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001408010000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x00141C0E0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08040000FFFFUL,
+	/* 0x00a8, */ 0x000C04020000FFFFUL,
+	/* 0x00b0, */ 0x000C04020000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08040000FFFFUL,
+	/* 0x00c8, */ 0x000C04020000FFFFUL,
+	/* 0x00d0, */ 0x000C04020000FFFFUL,
+	/* 0x00d8, */ 0x001044110000FFFFUL,
+	/* 0x00e0, */ 0x001014110000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001044110000FFFFUL,
+	/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001014110000FFFFUL,
+	/* 0x0118, */ 0x000C38360000FFFFUL,
+	/* 0x0120, */ 0x000C38360000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001018150000FFFFUL,
+	/* 0x0140, */ 0x001018150000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101C190000FFFFUL,
+	/* 0x0158, */ 0x00101C190000FFFFUL,
+	/* 0x0160, */ 0x001018150000FFFFUL,
+	/* 0x0168, */ 0x001018150000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100C0B0000FFFFUL,
+	/* 0x0180, */ 0x00100C0B0000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001058570000FFFFUL,
+	/* 0x0198, */ 0x001058570000FFFFUL,
+	/* 0x01a0, */ 0x001018150000FFFFUL,
+	/* 0x01a8, */ 0x001018150000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFFFUL,
+	/* 0x0268, */ 0x001410010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C08020000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x00140C010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x00140C010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0012006005EFFC01UL,
+	/* 0x0008, */ 0x0012006005EFFC01UL,
+	/* 0x0010, */ 0x0012006005EFFC01UL,
+	/* 0x0018, */ 0x0012006005EFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021006005EFFC01UL,
+	/* 0x01c8, */ 0x0021006005EFFC01UL,
+	/* 0x01d0, */ 0x0021006005EFFC01UL,
+	/* 0x01d8, */ 0x0021006005EFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021001005E79401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021001005E79401UL,
+	/* 0x0218, */ 0x0011001005E79401UL,
+	/* 0x0220, */ 0x0011001005E79401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011001005E79401UL,
+	/* 0x0238, */ 0x0011001005E79401UL,
+	/* 0x0240, */ 0x0012001005E79401UL,
+	/* 0x0248, */ 0x0011001005E79401UL,
+	/* 0x0250, */ 0x0012001005E79401UL,
+	/* 0x0258, */ 0x0011001005E79401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011006005EFFC01UL,
+	/* 0x02f8, */ 0x0011006005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0011006005EFFC01UL,
+	/* 0x0310, */ 0x0011006005EFFC01UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0011006005EFFC01UL,
+	/* 0x0328, */ 0x0011006005EFFC01UL,
+	/* 0x0330, */ 0x0011006005EFFC01UL,
+	/* 0x0338, */ 0x0011006005EFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0012001005E0FC01UL,
+};
+
+#endif /* QOS_INIT_G2H_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h
new file mode 100644
index 0000000..044f246
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_QOSWT195_H
+#define QOS_INIT_G2H_QOSWT195_H
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000C010UL,
+	/* 0x0038, */ 0x001008070000C010UL,
+	/* 0x0040, */ 0x001410070000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0014100D0000C010UL,
+	/* 0x0060, */ 0x0014100D0000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001410070000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFF0UL,
+	/* 0x0268, */ 0x001408010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04010000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+#endif /* QOS_INIT_G2H_QOSWT195_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h
new file mode 100644
index 0000000..2ae07ab
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_QOSWT390_H
+#define QOS_INIT_G2H_QOSWT390_H
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000C010UL,
+	/* 0x0038, */ 0x0010100D0000C010UL,
+	/* 0x0040, */ 0x00141C0E0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00141C190000C010UL,
+	/* 0x0060, */ 0x00141C190000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x00141C0E0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFF0UL,
+	/* 0x0268, */ 0x001410010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C08020000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+#endif /* QOS_INIT_G2H_QOSWT390_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
new file mode 100644
index 0000000..7f466c8
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2h_v30.h"
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION			"rev.0.07"
+
+#define QOSWT_TIME_BANK0			20000000U	/* unit:ns */
+#define QOSWT_WTEN_ENABLE			0x1U
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2H	(SL_INIT_SSLOTCLK_G2H - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT		3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT		9U
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+						(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+						(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0			5U
+#define WT_BASE_SUB_SLOT_NUM0			12U
+#define QOSWT_WTSET0_PERIOD0_G2H		((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2H) - 1U)
+#define QOSWT_WTSET0_SSLOT0			(QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_G2H		(QOSWT_WTSET0_PERIOD0_G2H)
+#define QOSWT_WTSET1_SSLOT1			(QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SLOTSLOT1			(QOSWT_WTSET0_SLOTSLOT0)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2h_mstat195.h"
+#else
+#include "qos_init_g2h_mstat390.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2h_qoswt195.h"
+#else
+#include "qos_init_g2h_qoswt390.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif /* RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT */
+
+static const struct rcar_gen3_dbsc_qos_settings g2h_v30_qos[] = {
+	/* BUFCAM settings */
+	{ DBSC_DBCAM0CNF1, 0x00043218U },
+	{ DBSC_DBCAM0CNF2, 0x000000F4U },
+	{ DBSC_DBCAM0CNF3, 0x00000000U },
+	{ DBSC_DBSCHCNT0, 0x000F0037U },
+	{ DBSC_DBSCHSZ0, 0x00000001U },
+	{ DBSC_DBSCHRW0, 0x22421111U },
+
+	/* DDR3 */
+	{ DBSC_SCFCTST2, 0x012F1123U },
+
+	/* QoS Settings */
+	{ DBSC_DBSCHQOS00, 0x00000F00U },
+	{ DBSC_DBSCHQOS01, 0x00000B00U },
+	{ DBSC_DBSCHQOS02, 0x00000000U },
+	{ DBSC_DBSCHQOS03, 0x00000000U },
+	{ DBSC_DBSCHQOS40, 0x00000300U },
+	{ DBSC_DBSCHQOS41, 0x000002F0U },
+	{ DBSC_DBSCHQOS42, 0x00000200U },
+	{ DBSC_DBSCHQOS43, 0x00000100U },
+	{ DBSC_DBSCHQOS90, 0x00000100U },
+	{ DBSC_DBSCHQOS91, 0x000000F0U },
+	{ DBSC_DBSCHQOS92, 0x000000A0U },
+	{ DBSC_DBSCHQOS93, 0x00000040U },
+	{ DBSC_DBSCHQOS120, 0x00000040U },
+	{ DBSC_DBSCHQOS121, 0x00000030U },
+	{ DBSC_DBSCHQOS122, 0x00000020U },
+	{ DBSC_DBSCHQOS123, 0x00000010U },
+	{ DBSC_DBSCHQOS130, 0x00000100U },
+	{ DBSC_DBSCHQOS131, 0x000000F0U },
+	{ DBSC_DBSCHQOS132, 0x000000A0U },
+	{ DBSC_DBSCHQOS133, 0x00000040U },
+	{ DBSC_DBSCHQOS140, 0x000000C0U },
+	{ DBSC_DBSCHQOS141, 0x000000B0U },
+	{ DBSC_DBSCHQOS142, 0x00000080U },
+	{ DBSC_DBSCHQOS143, 0x00000040U },
+	{ DBSC_DBSCHQOS150, 0x00000040U },
+	{ DBSC_DBSCHQOS151, 0x00000030U },
+	{ DBSC_DBSCHQOS152, 0x00000020U },
+	{ DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2h_v30(void)
+{
+	unsigned int split_area;
+
+	rzg_qos_dbsc_setting(g2h_v30_qos, ARRAY_SIZE(g2h_v30_qos), true);
+
+	/* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for G2H */
+	split_area = 0x1CU;
+
+	/* DRAM split address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
+#if RCAR_LSI == RZ_G2H
+#error "Don't set DRAM Split 4ch(G2H)"
+#else /* RCAR_LSI == RZ_G2H */
+	ERROR("DRAM split 4ch not supported.(G2H)");
+	panic();
+#endif /* RCAR_LSI == RZ_G2H */
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+	(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+	mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+	mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
+		    ADSPLCR0_SPLITSEL(0xFFU) | ADSPLCR0_AREA(split_area) |
+		    ADSPLCR0_SWP);
+	mmio_write_32(AXI_ADSPLCR2, 0x00001004U);
+	mmio_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
+	mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+	NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+#endif /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	mmio_write_32(QOSCTRL_RAS, 0x00000044U);
+	mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+	mmio_write_32(QOSCTRL_DANT, 0x0020100AU);
+	mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+	mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+	mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	/* GPU Boost Mode */
+	mmio_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+	mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+		      SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2H);
+	mmio_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2H << 16)));
+
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+		mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+		mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+	}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+		mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]);
+		mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+		mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]);
+		mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]);
+	}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	/* AXI setting */
+	mmio_write_32(AXI_MMCR, 0x00010008U);
+	mmio_write_32(AXI_TR3CR, 0x00010000U);
+	mmio_write_32(AXI_TR4CR, 0x00010000U);
+
+	/* RT bus Leaf setting */
+	mmio_write_32(RT_ACT0, 0x00000000U);
+	mmio_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	mmio_write_32(CPU_ACT0, 0x00000003U);
+	mmio_write_32(CPU_ACT1, 0x00000003U);
+	mmio_write_32(CPU_ACT2, 0x00000003U);
+	mmio_write_32(CPU_ACT3, 0x00000003U);
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	mmio_write_32(QOSWT_WTREF,
+		      ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	mmio_write_32(QOSWT_WTSET0,
+		      ((QOSWT_WTSET0_PERIOD0_G2H << 16) |
+		      (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	mmio_write_32(QOSWT_WTSET1,
+		      ((QOSWT_WTSET1_PERIOD1_G2H << 16) |
+		      (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h
new file mode 100644
index 0000000..acd9627
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_V30_H
+#define QOS_INIT_G2H_V30_H
+
+void qos_init_g2h_v30(void);
+
+#endif /* QOS_INIT_G2H_V30_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
new file mode 100644
index 0000000..00b0948
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2n_v10.h"
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION			"rev.0.09"
+
+#define REF_ARS_ARBSTOPCYCLE_G2N		(((SL_INIT_SSLOTCLK_G2N) - 5U) << 16U)
+
+#define QOSWT_TIME_BANK0			20000000U	/* unit:ns */
+
+#define	QOSWT_WTEN_ENABLE			0x1U
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT		3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT		9U
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+						(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			QOSWT_WTREF_SLOT0_EN
+
+#define QOSWT_WTSET0_REQ_SSLOT0			5U
+#define WT_BASE_SUB_SLOT_NUM0			12U
+#define QOSWT_WTSET0_PERIOD0_G2N		((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2N) - 1U)
+#define QOSWT_WTSET0_SSLOT0			(QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_G2N		QOSWT_WTSET0_PERIOD0_G2N
+#define QOSWT_WTSET1_SSLOT1			QOSWT_WTSET0_SSLOT0
+#define QOSWT_WTSET1_SLOTSLOT1			QOSWT_WTSET0_SLOTSLOT0
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2n_v10_mstat195.h"
+#else
+#include "qos_init_g2n_v10_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2n_v10_qoswt195.h"
+#else
+#include "qos_init_g2n_v10_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+static const struct rcar_gen3_dbsc_qos_settings g2n_v10_qos[] = {
+	/* BUFCAM settings */
+	{ DBSC_DBCAM0CNF1, 0x00043218U },
+	{ DBSC_DBCAM0CNF2, 0x000000F4U },
+	{ DBSC_DBSCHCNT0, 0x000F0037U },
+	{ DBSC_DBSCHSZ0, 0x00000001U },
+	{ DBSC_DBSCHRW0, 0x22421111U },
+
+	/* DDR3 */
+	{ DBSC_SCFCTST2, 0x012F1123U },
+
+	/* QoS Settings */
+	{ DBSC_DBSCHQOS00, 0x00000F00U },
+	{ DBSC_DBSCHQOS01, 0x00000B00U },
+	{ DBSC_DBSCHQOS02, 0x00000000U },
+	{ DBSC_DBSCHQOS03, 0x00000000U },
+	{ DBSC_DBSCHQOS40, 0x00000300U },
+	{ DBSC_DBSCHQOS41, 0x000002F0U },
+	{ DBSC_DBSCHQOS42, 0x00000200U },
+	{ DBSC_DBSCHQOS43, 0x00000100U },
+	{ DBSC_DBSCHQOS90, 0x00000100U },
+	{ DBSC_DBSCHQOS91, 0x000000F0U },
+	{ DBSC_DBSCHQOS92, 0x000000A0U },
+	{ DBSC_DBSCHQOS93, 0x00000040U },
+	{ DBSC_DBSCHQOS130, 0x00000100U },
+	{ DBSC_DBSCHQOS131, 0x000000F0U },
+	{ DBSC_DBSCHQOS132, 0x000000A0U },
+	{ DBSC_DBSCHQOS133, 0x00000040U },
+	{ DBSC_DBSCHQOS140, 0x000000C0U },
+	{ DBSC_DBSCHQOS141, 0x000000B0U },
+	{ DBSC_DBSCHQOS142, 0x00000080U },
+	{ DBSC_DBSCHQOS143, 0x00000040U },
+	{ DBSC_DBSCHQOS150, 0x00000040U },
+	{ DBSC_DBSCHQOS151, 0x00000030U },
+	{ DBSC_DBSCHQOS152, 0x00000020U },
+	{ DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2n_v10(void)
+{
+	rzg_qos_dbsc_setting(g2n_v10_qos, ARRAY_SIZE(g2n_v10_qos), true);
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RZ_G2N
+#error "Don't set DRAM Split 4ch(G2N)"
+#else
+	ERROR("DRAM Split 4ch not supported.(G2N)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RZ_G2N
+#error "Don't set DRAM Split 2ch(G2N)"
+#else
+	ERROR("DRAM Split 2ch not supported.(G2N)");
+	panic();
+#endif
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	mmio_write_32(QOSCTRL_RAS, 0x00000028U);
+	mmio_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
+	mmio_write_32(QOSCTRL_DANT, 0x00100804U);
+	mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+	mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+	mmio_write_32(QOSCTRL_EARLYR, 0x00000001U);
+	mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+		      SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2N);
+	mmio_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_G2N);
+
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+		mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+		mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+	}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+		mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]);
+		mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+		mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]);
+		mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]);
+	}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	/* RT bus Leaf setting */
+	mmio_write_32(RT_ACT0, 0x00000000U);
+	mmio_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	mmio_write_32(CPU_ACT0, 0x00000003U);
+	mmio_write_32(CPU_ACT1, 0x00000003U);
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	mmio_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	mmio_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_G2N << 16) |
+		      (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	mmio_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_G2N << 16) |
+		      (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h
new file mode 100644
index 0000000..c7f02d9
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_V10_H
+#define QOS_INIT_G2N_V10_H
+
+void qos_init_g2n_v10(void);
+
+#endif /* QOS_INIT_G2N_V10_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h
new file mode 100644
index 0000000..6e304b0
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_MSTAT195_H
+#define QOS_INIT_G2N_MSTAT195_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004320000FFFFUL,
+	/* 0x0038, */ 0x001004320000FFFFUL,
+	/* 0x0040, */ 0x00140C5D0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404040000FFFFUL,
+	/* 0x0058, */ 0x00140C940000FFFFUL,
+	/* 0x0060, */ 0x00140C940000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404040000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014041F0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C041D0000FFFFUL,
+	/* 0x00a8, */ 0x000C04090000FFFFUL,
+	/* 0x00b0, */ 0x000C040B0000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C041D0000FFFFUL,
+	/* 0x00c8, */ 0x000C04090000FFFFUL,
+	/* 0x00d0, */ 0x000C040B0000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x000C084F0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x000C21E60000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100CA50000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x001010C90000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x00100CA50000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008530000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00101D9D0000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x00100CA50000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x001408020000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408020000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04050000FFFFUL,
+	/* 0x02a8, */ 0x000C04050000FFFFUL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04050000FFFFUL,
+	/* 0x02d8, */ 0x000C04050000FFFFUL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x000C04050000FFFFUL,
+	/* 0x0388, */ 0x000C04050000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002106000BDFFC01UL,
+	/* 0x01c8, */ 0x002106000BDFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x001101000BDF2401UL,
+	/* 0x0220, */ 0x001101000BDF2401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001101000BDF2401UL,
+	/* 0x0238, */ 0x001101000BDF2401UL,
+	/* 0x0240, */ 0x001201000BDF2401UL,
+	/* 0x0248, */ 0x001101000BDF2401UL,
+	/* 0x0250, */ 0x001201000BDF2401UL,
+	/* 0x0258, */ 0x001101000BDF2401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001106000BDFFC01UL,
+	/* 0x02f8, */ 0x001106000BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x001206000BDFFC01UL,
+	/* 0x0360, */ 0x001206000BDFFC01UL,
+	/* 0x0368, */ 0x001200100BD03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x001200100BD03401UL,
+};
+#endif /* QOS_INIT_G2N_MSTAT195_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h
new file mode 100644
index 0000000..4632413
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_MSTAT390_H
+#define QOS_INIT_G2N_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008630000FFFFUL,
+	/* 0x0038, */ 0x001008630000FFFFUL,
+	/* 0x0040, */ 0x001418BA0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404070000FFFFUL,
+	/* 0x0058, */ 0x001415270000FFFFUL,
+	/* 0x0060, */ 0x001415270000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404070000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014083E0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08390000FFFFUL,
+	/* 0x00a8, */ 0x000C04110000FFFFUL,
+	/* 0x00b0, */ 0x000C04150000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08390000FFFFUL,
+	/* 0x00c8, */ 0x000C04110000FFFFUL,
+	/* 0x00d0, */ 0x000C04150000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001045080000FFFFUL,
+	/* 0x00f8, */ 0x000C0C9E0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001015080000FFFFUL,
+	/* 0x0118, */ 0x000C43CB0000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0010194A0000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101D910000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0010194A0000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100CA50000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001037390000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0010194A0000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04020000FFFFUL,
+	/* 0x01f0, */ 0x000C04090000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04090000FFFFUL,
+	/* 0x0210, */ 0x000C04090000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C2A0000FFFFUL,
+	/* 0x0268, */ 0x001410040000FFFFUL,
+	/* 0x0270, */ 0x001404020000FFFFUL,
+	/* 0x0278, */ 0x000C08110000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFFFUL,
+	/* 0x0298, */ 0x001404020000FFFFUL,
+	/* 0x02a0, */ 0x000C04090000FFFFUL,
+	/* 0x02a8, */ 0x000C04090000FFFFUL,
+	/* 0x02b0, */ 0x00140C090000FFFFUL,
+	/* 0x02b8, */ 0x000C04020000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04090000FFFFUL,
+	/* 0x02d8, */ 0x000C04090000FFFFUL,
+	/* 0x02e0, */ 0x00140C090000FFFFUL,
+	/* 0x02e8, */ 0x000C04020000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04020000FFFFUL,
+	/* 0x0378, */ 0x000C04020000FFFFUL,
+	/* 0x0380, */ 0x000C04090000FFFFUL,
+	/* 0x0388, */ 0x000C04090000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060005EFFC01UL,
+	/* 0x01c8, */ 0x0021060005EFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021010005E79401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021010005E79401UL,
+	/* 0x0218, */ 0x0011010005E79401UL,
+	/* 0x0220, */ 0x0011010005E79401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010005E79401UL,
+	/* 0x0238, */ 0x0011010005E79401UL,
+	/* 0x0240, */ 0x0012010005E79401UL,
+	/* 0x0248, */ 0x0011010005E79401UL,
+	/* 0x0250, */ 0x0012010005E79401UL,
+	/* 0x0258, */ 0x0011010005E79401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060005EFFC01UL,
+	/* 0x02f8, */ 0x0011060005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060005EFFC01UL,
+	/* 0x0360, */ 0x0012060005EFFC01UL,
+	/* 0x0368, */ 0x0012001005E03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001005E03401UL,
+};
+#endif /* QOS_INIT_G2N_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h
new file mode 100644
index 0000000..eea1fce
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_QOSWT195_H
+#define QOS_INIT_G2N_QOSWT195_H
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004320000C010UL,
+	/* 0x0038, */ 0x001004320000C010UL,
+	/* 0x0040, */ 0x00140C5D0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00140C940000C010UL,
+	/* 0x0060, */ 0x00140C940000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014041F0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08150000FFF0UL,
+	/* 0x0268, */ 0x001408020000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04090000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408020000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+#endif /* QOS_INIT_G2N_QOSWT195_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h
new file mode 100644
index 0000000..7043303
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_QOSWT390_H
+#define QOS_INIT_G2N_QOSWT390_H
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008630000C010UL,
+	/* 0x0038, */ 0x001008630000C010UL,
+	/* 0x0040, */ 0x001418BA0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x001415270000C010UL,
+	/* 0x0060, */ 0x001415270000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014083E0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C2A0000FFF0UL,
+	/* 0x0268, */ 0x001410040000FFF0UL,
+	/* 0x0270, */ 0x001404020000FFF0UL,
+	/* 0x0278, */ 0x000C08110000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFF0UL,
+	/* 0x0298, */ 0x001404020000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+#endif /* QOS_INIT_G2N_QOSWT390_H */
diff --git a/drivers/renesas/rzg/qos/qos.mk b/drivers/renesas/rzg/qos/qos.mk
index f06c685..f05d126 100644
--- a/drivers/renesas/rzg/qos/qos.mk
+++ b/drivers/renesas/rzg/qos/qos.mk
@@ -1,19 +1,31 @@
 #
-# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 ifeq (${RCAR_LSI},${RCAR_AUTO})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
 else ifeq (${RCAR_LSI_CUT_COMPAT},1)
   ifeq (${RCAR_LSI},${RZ_G2M})
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c
     BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
   endif
+  ifeq (${RCAR_LSI},${RZ_G2H})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2N})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2E})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+  endif
 else
   ifeq (${RCAR_LSI},${RZ_G2M})
     ifeq (${LSI_CUT},10)
@@ -29,6 +41,20 @@
      BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
     endif
   endif
+  ifeq (${RCAR_LSI},${RZ_G2H})
+     BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2N})
+    ifeq (${LSI_CUT},10)
+     BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+    else
+#    LSI_CUT 10 or later
+     BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+    endif
+  endif
+  ifeq (${RCAR_LSI},${RZ_G2E})
+    BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+  endif
 endif
 
 BL2_SOURCES += drivers/renesas/rzg/qos/qos_init.c
diff --git a/drivers/renesas/rzg/qos/qos_common.h b/drivers/renesas/rzg/qos/qos_common.h
index 6e0cf0e..535bf4c 100644
--- a/drivers/renesas/rzg/qos/qos_common.h
+++ b/drivers/renesas/rzg/qos/qos_common.h
@@ -37,6 +37,44 @@
 	((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
 #endif
 
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+/* define used for G2N */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
+#define SUB_SLOT_CYCLE_G2N		0x7EU	/* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2N		0xFCU	/* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_G2N		(SUB_SLOT_CYCLE_G2N - 1U)
+#define QOSWT_WTSET0_CYCLE_G2N		/* unit:ns */	\
+	((SUB_SLOT_CYCLE_G2N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#endif /* (RCAR_LSI == RZ_G2N) */
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+/* define used for G2H */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
+#define SUB_SLOT_CYCLE_G2H		0x7EU	/* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2H		0xFCU	/* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_G2H		(SUB_SLOT_CYCLE_G2H - 1U)
+#define QOSWT_WTSET0_CYCLE_G2H		/* unit:ns */	\
+	((SUB_SLOT_CYCLE_G2H * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E)
+/* define used for G2E */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2E		0xAFU	/* 175 */
+#else /* REF 7.8usec */
+#define SUB_SLOT_CYCLE_G2E		0x15EU	/* 350 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define OPERATING_FREQ_G2E		266U	/* MHz */
+#define SL_INIT_SSLOTCLK_G2E		(SUB_SLOT_CYCLE_G2E - 1U)
+#endif
+
 #define OPERATING_FREQ			400U	/* MHz */
 #define BASE_SUB_SLOT_NUM		0x6U
 #define SUB_SLOT_CYCLE			0x7EU	/* 126 */
diff --git a/drivers/renesas/rzg/qos/qos_init.c b/drivers/renesas/rzg/qos/qos_init.c
index 2d5aece..e527a61 100644
--- a/drivers/renesas/rzg/qos/qos_init.c
+++ b/drivers/renesas/rzg/qos/qos_init.c
@@ -10,23 +10,37 @@
 #include <lib/mmio.h>
 
 #if RCAR_LSI == RCAR_AUTO
+#include "G2E/qos_init_g2e_v10.h"
+#include "G2H/qos_init_g2h_v30.h"
 #include "G2M/qos_init_g2m_v10.h"
 #include "G2M/qos_init_g2m_v11.h"
 #include "G2M/qos_init_g2m_v30.h"
+#include "G2N/qos_init_g2n_v10.h"
 #endif /* RCAR_LSI == RCAR_AUTO */
 #if (RCAR_LSI == RZ_G2M)
 #include "G2M/qos_init_g2m_v10.h"
 #include "G2M/qos_init_g2m_v11.h"
 #include "G2M/qos_init_g2m_v30.h"
 #endif /* RCAR_LSI == RZ_G2M */
+#if RCAR_LSI == RZ_G2H
+#include "G2H/qos_init_g2h_v30.h"
+#endif /* RCAR_LSI == RZ_G2H */
+#if RCAR_LSI == RZ_G2N
+#include "G2N/qos_init_g2n_v10.h"
+#endif /* RCAR_LSI == RZ_G2N */
+#if RCAR_LSI == RZ_G2E
+#include "G2E/qos_init_g2e_v10.h"
+#endif /* RCAR_LSI == RZ_G2E */
 #include "qos_common.h"
 #include "qos_init.h"
 #include "qos_reg.h"
 #include "rcar_def.h"
 
+#if (RCAR_LSI != RZ_G2E)
 #define DRAM_CH_CNT	0x04U
 uint32_t qos_init_ddr_ch;
 uint8_t qos_init_ddr_phyvalid;
+#endif /* RCAR_LSI != RZ_G2E */
 
 #define PRR_PRODUCT_ERR(reg)				\
 	{						\
@@ -45,15 +59,17 @@
 void rzg_qos_init(void)
 {
 	uint32_t reg;
+#if (RCAR_LSI != RZ_G2E)
 	uint32_t i;
 
 	qos_init_ddr_ch = 0U;
-	qos_init_ddr_phyvalid = rzg_get_boardcnf_phyvalid();
+	qos_init_ddr_phyvalid = get_boardcnf_phyvalid();
 	for (i = 0U; i < DRAM_CH_CNT; i++) {
 		if ((qos_init_ddr_phyvalid & (1U << i))) {
 			qos_init_ddr_ch++;
 		}
 	}
+#endif /* RCAR_LSI != RZ_G2E */
 
 	reg = mmio_read_32(PRR);
 #if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
@@ -76,6 +92,42 @@
 		PRR_PRODUCT_ERR(reg);
 #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
 		break;
+	case PRR_PRODUCT_H3:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_30:
+		default:
+			qos_init_g2h_v30();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) */
+		break;
+	case PRR_PRODUCT_M3N:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		default:
+			qos_init_g2n_v10();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N) */
+		break;
+	case PRR_PRODUCT_E3:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		default:
+			qos_init_g2e_v10();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E) */
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -111,12 +163,31 @@
 	}
 	qos_init_g2m_v30();
 #endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
+#elif (RCAR_LSI == RZ_G2H)
+	/* G2H Cut 30 or later */
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_H3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_g2h_v30();
+#elif (RCAR_LSI == RZ_G2N)
+	/* G2N Cut 10 or later */
+	if ((reg & (PRR_PRODUCT_MASK)) != PRR_PRODUCT_M3N) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_g2n_v10();
+#elif RCAR_LSI == RZ_G2E
+	/* G2E Cut 10 or later */
+	if ((reg & (PRR_PRODUCT_MASK)) != PRR_PRODUCT_E3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_g2e_v10();
 #else /* (RCAR_LSI == RZ_G2M) */
 #error "Don't have QoS initialize routine(Unknown chip)."
 #endif /* (RCAR_LSI == RZ_G2M) */
 #endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
 }
 
+#if (RCAR_LSI != RZ_G2E)
 uint32_t get_refperiod(void)
 {
 	uint32_t refperiod = QOSWT_WTSET0_CYCLE;
@@ -140,6 +211,21 @@
 		}
 		break;
 #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+	case PRR_PRODUCT_H3:
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_30:
+		default:
+			refperiod = REFPERIOD_CYCLE;
+			break;
+		}
+		break;
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) */
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+	case PRR_PRODUCT_M3N:
+		refperiod = REFPERIOD_CYCLE;
+		break;
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N) */
 	default:
 		break;
 	}
@@ -150,9 +236,15 @@
 	/* G2M Cut 11|13|30 or later */
 	refperiod = REFPERIOD_CYCLE;
 #endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
+#elif RCAR_LSI == RZ_G2N
+	refperiod = REFPERIOD_CYCLE;
+#elif RCAR_LSI == RZ_G2H
+	/* G2H Cut 30 or later */
+	refperiod = REFPERIOD_CYCLE;
 #endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
 	return refperiod;
 }
+#endif /* RCAR_LSI != RZ_G2E */
 
 void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos,
 			  unsigned int qos_size, bool dbsc_wren)
diff --git a/drivers/renesas/rzg/qos/qos_init.h b/drivers/renesas/rzg/qos/qos_init.h
index 10f60e7..3d62744 100644
--- a/drivers/renesas/rzg/qos/qos_init.h
+++ b/drivers/renesas/rzg/qos/qos_init.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,6 @@
 #define RZG_QOS_INIT_H
 
 void rzg_qos_init(void);
-uint8_t rzg_get_boardcnf_phyvalid(void);
+uint8_t get_boardcnf_phyvalid(void);
 
 #endif /* RZG_QOS_INIT_H */
diff --git a/drivers/scmi-msg/common.h b/drivers/scmi-msg/common.h
index ef5953b..62f3087 100644
--- a/drivers/scmi-msg/common.h
+++ b/drivers/scmi-msg/common.h
@@ -13,6 +13,7 @@
 
 #include "base.h"
 #include "clock.h"
+#include "power_domain.h"
 #include "reset_domain.h"
 
 #define SCMI_VERSION			0x20000U
@@ -111,6 +112,13 @@
 scmi_msg_handler_t scmi_msg_get_rstd_handler(struct scmi_msg *msg);
 
 /*
+ * scmi_msg_get_pd_handler - Return a handler for a power domain message
+ * @msg - message to process
+ * Return a function handler for the message or NULL
+ */
+scmi_msg_handler_t scmi_msg_get_pd_handler(struct scmi_msg *msg);
+
+/*
  * Process Read, process and write response for input SCMI message
  *
  * @msg: SCMI message context
diff --git a/drivers/scmi-msg/entry.c b/drivers/scmi-msg/entry.c
index ea3efa2..3537fbe 100644
--- a/drivers/scmi-msg/entry.c
+++ b/drivers/scmi-msg/entry.c
@@ -11,6 +11,31 @@
 
 #include "common.h"
 
+#pragma weak scmi_msg_get_clock_handler
+#pragma weak scmi_msg_get_rstd_handler
+#pragma weak scmi_msg_get_pd_handler
+#pragma weak scmi_msg_get_voltage_handler
+
+scmi_msg_handler_t scmi_msg_get_clock_handler(struct scmi_msg *msg __unused)
+{
+	return NULL;
+}
+
+scmi_msg_handler_t scmi_msg_get_rstd_handler(struct scmi_msg *msg __unused)
+{
+	return NULL;
+}
+
+scmi_msg_handler_t scmi_msg_get_pd_handler(struct scmi_msg *msg __unused)
+{
+	return NULL;
+}
+
+scmi_msg_handler_t scmi_msg_get_voltage_handler(struct scmi_msg *msg __unused)
+{
+	return NULL;
+}
+
 void scmi_status_response(struct scmi_msg *msg, int32_t status)
 {
 	assert(msg->out && msg->out_size >= sizeof(int32_t));
@@ -47,6 +72,9 @@
 	case SCMI_PROTOCOL_ID_RESET_DOMAIN:
 		handler = scmi_msg_get_rstd_handler(msg);
 		break;
+	case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+		handler = scmi_msg_get_pd_handler(msg);
+		break;
 	default:
 		break;
 	}
diff --git a/drivers/scmi-msg/power_domain.c b/drivers/scmi-msg/power_domain.c
new file mode 100644
index 0000000..c4e1289
--- /dev/null
+++ b/drivers/scmi-msg/power_domain.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2020, Linaro Limited
+ */
+#include <cdefs.h>
+#include <string.h>
+
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
+#include <lib/utils_def.h>
+
+#include "common.h"
+
+#pragma weak plat_scmi_pd_count
+#pragma weak plat_scmi_pd_get_name
+#pragma weak plat_scmi_pd_get_state
+#pragma weak plat_scmi_pd_set_state
+#pragma weak plat_scmi_pd_statistics
+#pragma weak plat_scmi_pd_get_attributes
+
+static bool message_id_is_supported(size_t message_id);
+
+size_t plat_scmi_pd_count(unsigned int agent_id __unused)
+{
+	return 0U;
+}
+
+const char *plat_scmi_pd_get_name(unsigned int agent_id __unused,
+				  unsigned int pd_id __unused)
+{
+	return NULL;
+}
+
+unsigned int plat_scmi_pd_statistics(unsigned int agent_id __unused,
+				     unsigned long *pd_id __unused)
+{
+	return 0U;
+}
+
+unsigned int plat_scmi_pd_get_attributes(unsigned int agent_id __unused,
+					 unsigned int pd_id __unused)
+{
+	return 0U;
+}
+
+unsigned int plat_scmi_pd_get_state(unsigned int agent_id __unused,
+				    unsigned int pd_id __unused)
+{
+	return 0U;
+}
+
+int32_t plat_scmi_pd_set_state(unsigned int agent_id __unused,
+			       unsigned int flags __unused,
+			       unsigned int pd_id __unused,
+			       unsigned int state __unused)
+{
+	return SCMI_NOT_SUPPORTED;
+}
+
+static void report_version(struct scmi_msg *msg)
+{
+	struct scmi_protocol_version_p2a return_values = {
+		.status = SCMI_SUCCESS,
+		.version = SCMI_PROTOCOL_VERSION_PD,
+	};
+
+	if (msg->in_size != 0) {
+		scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+		return;
+	}
+
+	scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void report_attributes(struct scmi_msg *msg)
+{
+	unsigned long addr = 0UL;
+	unsigned int len;
+
+	struct scmi_protocol_attributes_p2a_pd return_values = {
+		.status = SCMI_SUCCESS,
+	};
+
+	if (msg->in_size != 0) {
+		scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+		return;
+	}
+
+	return_values.attributes = plat_scmi_pd_count(msg->agent_id);
+	len = plat_scmi_pd_statistics(msg->agent_id, &addr);
+	if (len != 0U) {
+		return_values.statistics_addr_low = (unsigned int)addr;
+		return_values.statistics_addr_high = (uint32_t)(addr >> 32);
+		return_values.statistics_len = len;
+	}
+
+	scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void report_message_attributes(struct scmi_msg *msg)
+{
+	struct scmi_protocol_message_attributes_a2p *in_args = (void *)msg->in;
+	struct scmi_protocol_message_attributes_p2a return_values = {
+		.status = SCMI_SUCCESS,
+		/* For this protocol, attributes shall be zero */
+		.attributes = 0U,
+	};
+
+	if (msg->in_size != sizeof(*in_args)) {
+		scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+		return;
+	}
+
+	if (!message_id_is_supported(in_args->message_id)) {
+		scmi_status_response(msg, SCMI_NOT_FOUND);
+		return;
+	}
+
+	scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void scmi_pd_attributes(struct scmi_msg *msg)
+{
+	const struct scmi_pd_attributes_a2p *in_args = (void *)msg->in;
+	struct scmi_pd_attributes_p2a return_values = {
+		.status = SCMI_SUCCESS,
+	};
+	const char *name = NULL;
+	unsigned int pd_id = 0U;
+
+	if (msg->in_size != sizeof(*in_args)) {
+		scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+		return;
+	}
+
+	pd_id = SPECULATION_SAFE_VALUE(in_args->pd_id);
+
+	if (pd_id >= plat_scmi_pd_count(msg->agent_id)) {
+		scmi_status_response(msg, SCMI_INVALID_PARAMETERS);
+		return;
+	}
+
+	name = plat_scmi_pd_get_name(msg->agent_id, pd_id);
+	if (name == NULL) {
+		scmi_status_response(msg, SCMI_NOT_FOUND);
+		return;
+	}
+
+	COPY_NAME_IDENTIFIER(return_values.pd_name, name);
+
+	return_values.attributes = plat_scmi_pd_get_attributes(msg->agent_id, pd_id);
+
+	scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void scmi_pd_state_get(struct scmi_msg *msg)
+{
+	const struct scmi_pd_state_get_a2p *in_args = (void *)msg->in;
+	unsigned int state = 0U;
+	struct scmi_pd_state_get_p2a return_values = {
+		.status = SCMI_SUCCESS,
+	};
+	unsigned int pd_id = 0U;
+
+	if (msg->in_size != sizeof(*in_args)) {
+		scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+		return;
+	}
+
+	pd_id = SPECULATION_SAFE_VALUE(in_args->pd_id);
+
+	if (pd_id >= plat_scmi_pd_count(msg->agent_id)) {
+		scmi_status_response(msg, SCMI_INVALID_PARAMETERS);
+		return;
+	}
+
+	state = plat_scmi_pd_get_state(msg->agent_id, pd_id);
+
+	return_values.power_state = state;
+
+	scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void scmi_pd_state_set(struct scmi_msg *msg)
+{
+	const struct scmi_pd_state_set_a2p *in_args = (void *)msg->in;
+	unsigned int flags = 0U;
+	int32_t status = 0;
+	unsigned int pd_id = 0U;
+	unsigned int state = 0U;
+
+	if (msg->in_size != sizeof(*in_args)) {
+		scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+		return;
+	}
+
+	pd_id = SPECULATION_SAFE_VALUE(in_args->pd_id);
+
+	if (pd_id >= plat_scmi_pd_count(msg->agent_id)) {
+		scmi_status_response(msg, SCMI_INVALID_PARAMETERS);
+		return;
+	}
+
+	flags = SPECULATION_SAFE_VALUE(in_args->flags);
+	state = SPECULATION_SAFE_VALUE(in_args->power_state);
+
+	status = plat_scmi_pd_set_state(msg->agent_id, flags, pd_id, state);
+
+	scmi_status_response(msg, status);
+}
+
+static const scmi_msg_handler_t scmi_pd_handler_table[] = {
+	[SCMI_PROTOCOL_VERSION] = report_version,
+	[SCMI_PROTOCOL_ATTRIBUTES] = report_attributes,
+	[SCMI_PROTOCOL_MESSAGE_ATTRIBUTES] = report_message_attributes,
+	[SCMI_PD_ATTRIBUTES] = scmi_pd_attributes,
+	[SCMI_PD_STATE_SET] = scmi_pd_state_set,
+	[SCMI_PD_STATE_GET] = scmi_pd_state_get,
+};
+
+static bool message_id_is_supported(size_t message_id)
+{
+	return (message_id < ARRAY_SIZE(scmi_pd_handler_table)) &&
+	       (scmi_pd_handler_table[message_id] != NULL);
+}
+
+scmi_msg_handler_t scmi_msg_get_pd_handler(struct scmi_msg *msg)
+{
+	const size_t array_size = ARRAY_SIZE(scmi_pd_handler_table);
+	unsigned int message_id = SPECULATION_SAFE_VALUE(msg->message_id);
+
+	if (message_id >= array_size) {
+		VERBOSE("pd handle not found %u", msg->message_id);
+		return NULL;
+	}
+
+	return scmi_pd_handler_table[message_id];
+}
diff --git a/drivers/scmi-msg/power_domain.h b/drivers/scmi-msg/power_domain.h
new file mode 100644
index 0000000..48551fd
--- /dev/null
+++ b/drivers/scmi-msg/power_domain.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef SCMI_MSG_PD_H
+#define SCMI_MSG_PD_H
+
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+#define SCMI_PROTOCOL_VERSION_PD	0x21000U
+
+/*
+ * Identifiers of the SCMI POWER DOMAIN Protocol commands
+ */
+enum scmi_pd_command_id {
+	SCMI_PD_ATTRIBUTES = 0x003,
+	SCMI_PD_STATE_SET = 0x004,
+	SCMI_PD_STATE_GET = 0x005,
+};
+
+/* Protocol attributes */
+struct scmi_pd_attributes_a2p {
+	uint32_t pd_id;
+};
+
+struct scmi_protocol_attributes_p2a_pd {
+	int32_t status;
+	uint32_t attributes;
+	uint32_t statistics_addr_low;
+	uint32_t statistics_addr_high;
+	uint32_t statistics_len;
+};
+
+#define SCMI_PD_NAME_LENGTH_MAX	16U
+
+struct scmi_pd_attributes_p2a {
+	int32_t status;
+	uint32_t attributes;
+	char pd_name[SCMI_PD_NAME_LENGTH_MAX];
+};
+
+/*
+ * Power Domain State Get
+ */
+
+struct scmi_pd_state_get_a2p {
+	uint32_t pd_id;
+};
+
+struct scmi_pd_state_get_p2a {
+	int32_t status;
+	uint32_t power_state;
+};
+
+/*
+ * Power domain State Set
+ */
+
+struct scmi_pd_state_set_a2p {
+	uint32_t flags;
+	uint32_t pd_id;
+	uint32_t power_state;
+};
+
+struct scmi_pd_state_set_p2a {
+	int32_t status;
+};
+
+#endif /* SCMI_MSG_PD_H */
diff --git a/drivers/scmi-msg/smt.c b/drivers/scmi-msg/smt.c
index b08ee06..9b079c7 100644
--- a/drivers/scmi-msg/smt.c
+++ b/drivers/scmi-msg/smt.c
@@ -44,12 +44,12 @@
 	assert_scmi_message_max_length_fits_in_smt_buffer_slot);
 
 /* Flag set in smt_header::status when SMT does not contain pending message */
-#define SMT_STATUS_FREE			BIT(0)
+#define SMT_STATUS_FREE			BIT_32(0)
 /* Flag set in smt_header::status when SMT reports an error */
-#define SMT_STATUS_ERROR		BIT(1)
+#define SMT_STATUS_ERROR		BIT_32(1)
 
 /* Flag set in smt_header::flags when SMT uses interrupts */
-#define SMT_FLAG_INTR_ENABLED		BIT(1)
+#define SMT_FLAG_INTR_ENABLED		BIT_32(1)
 
 /* Bit fields packed in smt_header::message_header */
 #define SMT_MSG_ID_MASK			GENMASK_32(7, 0)
@@ -133,7 +133,7 @@
 			  sizeof(smt_hdr->message_header);
 
 	if (in_payload_size > SCMI_PLAYLOAD_MAX) {
-		VERBOSE("SCMI payload too big %u", in_payload_size);
+		VERBOSE("SCMI payload too big %zu", in_payload_size);
 		goto out;
 	}
 
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 564bd87..6ada96a 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -1737,7 +1737,7 @@
 	void *fdt;
 
 	if (fdt_get_address(&fdt) == 0) {
-		return false;
+		return -FDT_ERR_NOTFOUND;
 	}
 
 	/* Check status field to disable security */
diff --git a/drivers/st/io/io_mmc.c b/drivers/st/io/io_mmc.c
index 0ed7154..2bf88e6 100644
--- a/drivers/st/io/io_mmc.c
+++ b/drivers/st/io/io_mmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,6 +29,7 @@
 static io_type_t device_type_mmc(void);
 
 static signed long long seek_offset;
+static size_t (*_read_blocks)(int lba, uintptr_t buf, size_t size);
 
 static const io_dev_connector_t mmc_dev_connector = {
 	.dev_open = mmc_dev_open
@@ -60,9 +61,15 @@
 /* Open a connection to the mmc device */
 static int mmc_dev_open(const uintptr_t init_params, io_dev_info_t **dev_info)
 {
+	struct io_mmc_dev_spec *device_spec =
+		(struct io_mmc_dev_spec *)init_params;
+
 	assert(dev_info != NULL);
 	*dev_info = (io_dev_info_t *)&mmc_dev_info;
 
+	_read_blocks = !device_spec->use_boot_part ?
+		mmc_read_blocks : mmc_boot_part_read_blocks;
+
 	return 0;
 }
 
@@ -100,8 +107,8 @@
 	uint8_t retries;
 
 	for (retries = 0U; retries < 3U; retries++) {
-		*length_read = mmc_read_blocks(seek_offset / MMC_BLOCK_SIZE,
-					       buffer, length);
+		*length_read = _read_blocks(seek_offset / MMC_BLOCK_SIZE,
+					    buffer, length);
 
 		if (*length_read == length) {
 			return 0;
diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c
index 3e377cd..9fa0c50 100644
--- a/drivers/st/io/io_stm32image.c
+++ b/drivers/st/io/io_stm32image.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -246,10 +246,11 @@
 static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
 				     size_t length, size_t *length_read)
 {
-	int result;
+	int result = -EINVAL;
 	uint8_t *local_buffer;
 	boot_api_image_header_t *header =
 		(boot_api_image_header_t *)first_lba_buffer;
+	size_t hdr_sz = sizeof(boot_api_image_header_t);
 
 	assert(entity != NULL);
 	assert(buffer != 0U);
@@ -286,16 +287,13 @@
 		}
 
 		/* Part of image already loaded with the header */
-		memcpy(local_buffer, (uint8_t *)first_lba_buffer +
-		       sizeof(boot_api_image_header_t),
-		       MAX_LBA_SIZE - sizeof(boot_api_image_header_t));
-		local_buffer += MAX_LBA_SIZE - sizeof(boot_api_image_header_t);
+		memcpy(local_buffer, (uint8_t *)first_lba_buffer + hdr_sz,
+		       MAX_LBA_SIZE - hdr_sz);
+		local_buffer += MAX_LBA_SIZE - hdr_sz;
 		offset = MAX_LBA_SIZE;
 
 		/* New image length to be read */
-		local_length = round_up(length -
-					((MAX_LBA_SIZE) -
-					 sizeof(boot_api_image_header_t)),
+		local_length = round_up(length - ((MAX_LBA_SIZE) - hdr_sz),
 					stm32image_dev.lba_size);
 
 		if ((header->load_address != 0U) &&
@@ -326,7 +324,7 @@
 				 local_length, length_read);
 
 		/* Adding part of size already read from header */
-		*length_read += MAX_LBA_SIZE - sizeof(boot_api_image_header_t);
+		*length_read += MAX_LBA_SIZE - hdr_sz;
 
 		if (result != 0) {
 			ERROR("%s: io_read (%i)\n", __func__, result);
@@ -348,6 +346,9 @@
 			return result;
 		}
 
+		inv_dcache_range(round_up((uintptr_t)(local_buffer + length - hdr_sz),
+					  CACHE_WRITEBACK_GRANULE), *length_read - length + hdr_sz);
+
 		io_close(backend_handle);
 	}
 
diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index b2bb482..be410a1 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -121,6 +121,9 @@
 	}
 
 	regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators");
+	if (regulators_node < 0) {
+		return -ENOENT;
+	}
 
 	fdt_for_each_subnode(regulator_node, fdt, regulators_node) {
 		const fdt32_t *cuint;
@@ -204,6 +207,7 @@
 	i2c->i2c_base_addr		= i2c_info.base;
 	i2c->dt_status			= i2c_info.status;
 	i2c->clock			= i2c_info.clock;
+	i2c->i2c_state			= I2C_STATE_RESET;
 	i2c_init.own_address1		= pmic_i2c_addr;
 	i2c_init.addressing_mode	= I2C_ADDRESSINGMODE_7BIT;
 	i2c_init.dual_address_mode	= I2C_DUALADDRESS_DISABLE;
diff --git a/fdts/arm_fpga.dts b/fdts/arm_fpga.dts
index 6a966fd..b7b4f0e 100644
--- a/fdts/arm_fpga.dts
+++ b/fdts/arm_fpga.dts
@@ -28,7 +28,7 @@
 		bootargs = "console=ttyAMA0,38400n8 earlycon";
 		/* Allow to upload a generous 100MB initrd payload. */
 		linux,initrd-start = <0x0 0x84000000>;
-		linux,initrd-end = <0x0 0x85400000>;
+		linux,initrd-end = <0x0 0x8a400000>;
 	};
 
 	/* /cpus node will be added by BL31 at runtime. */
diff --git a/fdts/fvp-base-gicv2-psci-aarch32.dts b/fdts/fvp-base-gicv2-psci-aarch32.dts
index 591ec58..3a921f4 100644
--- a/fdts/fvp-base-gicv2-psci-aarch32.dts
+++ b/fdts/fvp-base-gicv2-psci-aarch32.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #define	AFF
 #define	REG_32
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fvp-defs.dtsi"
 
 /memreserve/ 0x80000000 0x00010000;
@@ -100,10 +101,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts
index 4b3942e..e99719e 100644
--- a/fdts/fvp-base-gicv2-psci.dts
+++ b/fdts/fvp-base-gicv2-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 
 #define	AFF
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fvp-defs.dtsi"
 
 /memreserve/ 0x80000000 0x00010000;
@@ -99,10 +100,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
index 1a1bd12..85988e9 100644
--- a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
@@ -1,9 +1,11 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /memreserve/ 0x80000000 0x00010000;
 
 / {
@@ -100,10 +102,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi
index 192f574..b6753de 100644
--- a/fdts/fvp-base-gicv3-psci-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-common.dtsi
@@ -1,9 +1,10 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <services/sdei_flags.h>
 
 #define LEVEL	0
@@ -161,10 +162,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-foundation-gicv2-psci.dts b/fdts/fvp-foundation-gicv2-psci.dts
index 95a800e..5a82c46 100644
--- a/fdts/fvp-foundation-gicv2-psci.dts
+++ b/fdts/fvp-foundation-gicv2-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #define	AFF
 #define	CLUSTER_COUNT	1
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fvp-defs.dtsi"
 
 /memreserve/ 0x80000000 0x00010000;
@@ -100,10 +101,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts
index c295dc1..e1249d4 100644
--- a/fdts/fvp-foundation-gicv3-psci.dts
+++ b/fdts/fvp-foundation-gicv3-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #define	AFF
 #define	CLUSTER_COUNT	1
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fvp-defs.dtsi"
 
 /memreserve/ 0x80000000 0x00010000;
@@ -109,10 +110,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <100000000>;
 	};
 
diff --git a/fdts/juno-ethosn.dtsi b/fdts/juno-ethosn.dtsi
new file mode 100644
index 0000000..87ab378
--- /dev/null
+++ b/fdts/juno-ethosn.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	ethosn: ethosn@6f300000 {
+		compatible = "ethosn";
+		reg = <0 0x6f300000 0 0x00100000>;
+		status = "okay";
+
+		/*
+		 * Single-core NPU. For multi-core NPU, additional core nodes
+		 * and reg values must be added.
+		 */
+		core0 {
+			compatible = "ethosn-core";
+			status = "okay";
+		};
+	};
+};
diff --git a/fdts/juno.dts b/fdts/juno.dts
new file mode 100644
index 0000000..56fe167
--- /dev/null
+++ b/fdts/juno.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+
+};
+
+#if ARM_ETHOSN_NPU_DRIVER
+	#include "juno-ethosn.dtsi"
+#endif
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index 4f6c8a7..55c87bf 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -27,33 +27,52 @@
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
-		cpu0@0 {
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+			cluster1 {
+				core0 {
+					cpu = <&CPU2>;
+				};
+				core1 {
+					cpu = <&CPU3>;
+				};
+			};
+		};
+		CPU0: cpu0@0 {
 			compatible = "arm,armv8";
 			reg = <0x0 0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 0>;
 		};
-		cpu1@100 {
+		CPU1: cpu1@100 {
 			compatible = "arm,armv8";
 			reg = <0x0 0x100>;
 			device_type = "cpu";
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 0>;
 		};
-		cpu2@10000 {
+		CPU2: cpu2@10000 {
 			compatible = "arm,armv8";
 			reg = <0x0 0x10000>;
 			device_type = "cpu";
 			enable-method = "psci";
-			clocks = <&scmi_dvfs 0>;
+			clocks = <&scmi_dvfs 1>;
 		};
-		cpu3@10100 {
+		CPU3: cpu3@10100 {
 			compatible = "arm,armv8";
 			reg = <0x0 0x10100>;
 			device_type = "cpu";
 			enable-method = "psci";
-			clocks = <&scmi_dvfs 0>;
+			clocks = <&scmi_dvfs 1>;
 		};
 	};
 
diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi
index d3d1744..058cde2 100644
--- a/fdts/stm32mp15-pinctrl.dtsi
+++ b/fdts/stm32mp15-pinctrl.dtsi
@@ -31,6 +31,16 @@
 		};
 	};
 
+	i2c2_pins_a: i2c2-0 {
+		pins {
+			pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
+				 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+			bias-disable;
+			drive-open-drain;
+			slew-rate = <0>;
+		};
+	};
+
 	qspi_clk_pins_a: qspi-clk-0 {
 		pins {
 			pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
@@ -166,6 +176,15 @@
 		};
 	};
 
+	sdmmc2_d47_pins_d: sdmmc2-d47-3 {
+		pins {
+			pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+				 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+				 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+				 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+		};
+	};
+
 	uart4_pins_a: uart4-0 {
 		pins1 {
 			pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index 8f175a6..c350c66 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -121,6 +121,21 @@
 			status = "disabled";
 		};
 
+		i2c2: i2c@40013000 {
+			compatible = "st,stm32mp15-i2c";
+			reg = <0x40013000 0x400>;
+			interrupt-names = "event", "error";
+			interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+				     <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc I2C2_K>;
+			resets = <&rcc I2C2_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			st,syscfg-fmp = <&syscfg 0x4 0x2>;
+			wakeup-source;
+			status = "disabled";
+		};
+
 		uart7: serial@40018000 {
 			compatible = "st,stm32h7-uart";
 			reg = <0x40018000 0x400>;
diff --git a/fdts/stm32mp157c-odyssey-som.dtsi b/fdts/stm32mp157c-odyssey-som.dtsi
new file mode 100644
index 0000000..6bed339
--- /dev/null
+++ b/fdts/stm32mp157c-odyssey-som.dtsi
@@ -0,0 +1,325 @@
+/*
+ * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
+ * Copyright (C) 2021, Grzegorz Szymaszek.
+ *
+ * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+ */
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
+
+/ {
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0xc0000000 0x20000000>;
+	};
+
+	vin: vin {
+		compatible = "regulator-fixed";
+		regulator-name = "vin";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+};
+
+&bsec {
+	board_id: board_id@ec {
+		reg = <0xec 0x4>;
+		st,non-secure-otp;
+	};
+};
+
+&clk_hse {
+	st,digbypass;
+};
+
+&cpu0 {
+	cpu-supply = <&vddcore>;
+};
+
+&cpu1 {
+	cpu-supply = <&vddcore>;
+};
+
+&cryp1 {
+	status = "okay";
+};
+
+&hash1 {
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins_a>;
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <185>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+
+	pmic: stpmic@33 {
+		compatible = "st,stpmic1";
+		reg = <0x33>;
+		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		status = "okay";
+
+		regulators {
+			compatible = "st,stpmic1-regulators";
+			buck1-supply = <&vin>;
+			buck2-supply = <&vin>;
+			buck3-supply = <&vin>;
+			buck4-supply = <&vin>;
+			ldo1-supply = <&v3v3>;
+			ldo2-supply = <&vin>;
+			ldo3-supply = <&vdd_ddr>;
+			ldo4-supply = <&vin>;
+			ldo5-supply = <&vin>;
+			ldo6-supply = <&v3v3>;
+			vref_ddr-supply = <&vin>;
+			boost-supply = <&vin>;
+			pwr_sw1-supply = <&bst_out>;
+			pwr_sw2-supply = <&bst_out>;
+
+			vddcore: buck1 {
+				regulator-name = "vddcore";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+				regulator-initial-mode = <0>;
+				regulator-over-current-protection;
+			};
+
+			vdd_ddr: buck2 {
+				regulator-name = "vdd_ddr";
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+				regulator-initial-mode = <0>;
+				regulator-over-current-protection;
+			};
+
+			vdd: buck3 {
+				regulator-name = "vdd";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				st,mask-reset;
+				regulator-initial-mode = <0>;
+				regulator-over-current-protection;
+			};
+
+			v3v3: buck4 {
+				regulator-name = "v3v3";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-over-current-protection;
+				regulator-initial-mode = <0>;
+			};
+
+			v1v8_audio: ldo1 {
+				regulator-name = "v1v8_audio";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			v3v3_hdmi: ldo2 {
+				regulator-name = "v3v3_hdmi";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vtt_ddr: ldo3 {
+				regulator-name = "vtt_ddr";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <750000>;
+				regulator-always-on;
+				regulator-over-current-protection;
+			};
+
+			vdd_usb: ldo4 {
+				regulator-name = "vdd_usb";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdda: ldo5 {
+				regulator-name = "vdda";
+				regulator-min-microvolt = <2900000>;
+				regulator-max-microvolt = <2900000>;
+				regulator-boot-on;
+			};
+
+			v1v2_hdmi: ldo6 {
+				regulator-name = "v1v2_hdmi";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
+
+			vref_ddr: vref_ddr {
+				regulator-name = "vref_ddr";
+				regulator-always-on;
+				regulator-over-current-protection;
+			};
+
+			bst_out: boost {
+				regulator-name = "bst_out";
+			};
+
+			vbus_otg: pwr_sw1 {
+				regulator-name = "vbus_otg";
+			};
+
+			vbus_sw: pwr_sw2 {
+				regulator-name = "vbus_sw";
+				regulator-active-discharge = <1>;
+			};
+		};
+
+		pmic_watchdog: watchdog {
+			compatible = "st,stpmic1-wdt";
+			status = "disabled";
+		};
+	};
+};
+
+&iwdg2 {
+	timeout-sec = <32>;
+	status = "okay";
+};
+
+&pwr_regulators {
+	vdd-supply = <&vdd>;
+	vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rcc {
+	secure-status = "disabled";
+	st,clksrc = <
+		CLK_MPU_PLL1P
+		CLK_AXI_PLL2P
+		CLK_MCU_PLL3P
+		CLK_PLL12_HSE
+		CLK_PLL3_HSE
+		CLK_PLL4_HSE
+		CLK_RTC_LSE
+		CLK_MCO1_DISABLED
+		CLK_MCO2_DISABLED
+	>;
+
+	st,clkdiv = <
+		1 /*MPU*/
+		0 /*AXI*/
+		0 /*MCU*/
+		1 /*APB1*/
+		1 /*APB2*/
+		1 /*APB3*/
+		1 /*APB4*/
+		2 /*APB5*/
+		23 /*RTC*/
+		0 /*MCO1*/
+		0 /*MCO2*/
+	>;
+
+	st,pkcs = <
+		CLK_CKPER_HSE
+		CLK_FMC_ACLK
+		CLK_QSPI_ACLK
+		CLK_ETH_PLL4P
+		CLK_SDMMC12_PLL4P
+		CLK_DSI_DSIPLL
+		CLK_STGEN_HSE
+		CLK_USBPHY_HSE
+		CLK_SPI2S1_PLL3Q
+		CLK_SPI2S23_PLL3Q
+		CLK_SPI45_HSI
+		CLK_SPI6_HSI
+		CLK_I2C46_HSI
+		CLK_SDMMC3_PLL4P
+		CLK_USBO_USBPHY
+		CLK_ADC_CKPER
+		CLK_CEC_LSE
+		CLK_I2C12_HSI
+		CLK_I2C35_HSI
+		CLK_UART1_HSI
+		CLK_UART24_HSI
+		CLK_UART35_HSI
+		CLK_UART6_HSI
+		CLK_UART78_HSI
+		CLK_SPDIF_PLL4P
+		CLK_FDCAN_PLL4R
+		CLK_SAI1_PLL3Q
+		CLK_SAI2_PLL3Q
+		CLK_SAI3_PLL3Q
+		CLK_SAI4_PLL3Q
+		CLK_RNG1_LSI
+		CLK_RNG2_LSI
+		CLK_LPTIM1_PCLK1
+		CLK_LPTIM23_PCLK3
+		CLK_LPTIM45_LSE
+	>;
+
+	/* VCO = 1300.0 MHz => P = 650 (CPU) */
+	pll1: st,pll@0 {
+		compatible = "st,stm32mp1-pll";
+		reg = <0>;
+		cfg = <2 80 0 0 0 PQR(1,0,0)>;
+		frac = <0x800>;
+	};
+
+	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+	pll2: st,pll@1 {
+		compatible = "st,stm32mp1-pll";
+		reg = <1>;
+		cfg = <2 65 1 0 0 PQR(1,1,1)>;
+		frac = <0x1400>;
+	};
+
+	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+	pll3: st,pll@2 {
+		compatible = "st,stm32mp1-pll";
+		reg = <2>;
+		cfg = <1 33 1 16 36 PQR(1,1,1)>;
+		frac = <0x1a04>;
+	};
+
+	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+	pll4: st,pll@3 {
+		compatible = "st,stm32mp1-pll";
+		reg = <3>;
+		cfg = <3 98 5 7 7 PQR(1,1,1)>;
+	};
+};
+
+&rng1 {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sdmmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	st,neg-edge;
+	bus-width = <8>;
+	vmmc-supply = <&v3v3>;
+	vqmmc-supply = <&vdd>;
+	mmc-ddr-3_3v;
+	status = "okay";
+};
diff --git a/fdts/stm32mp157c-odyssey.dts b/fdts/stm32mp157c-odyssey.dts
new file mode 100644
index 0000000..03800f9
--- /dev/null
+++ b/fdts/stm32mp157c-odyssey.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
+ * Copyright (C) 2021, Grzegorz Szymaszek.
+ *
+ * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-odyssey-som.dtsi"
+
+/ {
+	model = "Seeed Studio Odyssey-STM32MP157C Board";
+	compatible = "seeed,stm32mp157c-odyssey",
+		     "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
+
+	aliases {
+		serial0 = &uart4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&sdmmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_b4_pins_a>;
+	disable-wp;
+	st,neg-edge;
+	bus-width = <4>;
+	vmmc-supply = <&v3v3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pins_a>;
+	status = "okay";
+};
diff --git a/fdts/tc0.dts b/fdts/tc0.dts
index 2d7611c..9051b7b 100644
--- a/fdts/tc0.dts
+++ b/fdts/tc0.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,6 +17,7 @@
 	};
 
 	chosen {
+		bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -85,6 +86,7 @@
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 0>;
 			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+			capacity-dmips-mhz = <406>;
 		};
 
 		CPU1:cpu@100 {
@@ -94,6 +96,7 @@
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 0>;
 			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+			capacity-dmips-mhz = <406>;
 		};
 
 		CPU2:cpu@200 {
@@ -103,6 +106,7 @@
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 0>;
 			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+			capacity-dmips-mhz = <406>;
 		};
 
 		CPU3:cpu@300 {
@@ -112,6 +116,7 @@
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 0>;
 			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+			capacity-dmips-mhz = <406>;
 		};
 
 		CPU4:cpu@400 {
@@ -121,6 +126,7 @@
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 1>;
 			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+			capacity-dmips-mhz = <912>;
 		};
 
 		CPU5:cpu@500 {
@@ -130,6 +136,7 @@
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 1>;
 			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+			capacity-dmips-mhz = <912>;
 		};
 
 		CPU6:cpu@600 {
@@ -139,6 +146,7 @@
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 1>;
 			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+			capacity-dmips-mhz = <912>;
 		};
 
 		CPU7:cpu@700 {
@@ -146,8 +154,9 @@
 			compatible = "arm,armv8";
 			reg = <0x700>;
 			enable-method = "psci";
-			clocks = <&scmi_dvfs 1>;
+			clocks = <&scmi_dvfs 2>;
 			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
 		};
 
 	};
@@ -169,7 +178,7 @@
 	};
 
 	psci {
-		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
 		method = "smc";
 	};
 
@@ -188,31 +197,32 @@
 	};
 
 	mbox_db_rx: mhu@45010000 {
-		compatible = "arm,mhuv2","arm,primecell";
+		compatible = "arm,mhuv2-rx","arm,primecell";
 		reg = <0x0 0x45010000 0x0 0x1000>;
 		clocks = <&soc_refclk100mhz>;
 		clock-names = "apb_pclk";
-		#mbox-cells = <1>;
+		#mbox-cells = <2>;
 		interrupts = <0 317 4>;
 		interrupt-names = "mhu_rx";
 		mhu-protocol = "doorbell";
+		arm,mhuv2-protocols = <0 1>;
 	};
 
 	mbox_db_tx: mhu@45000000 {
-		compatible = "arm,mhuv2","arm,primecell";
+		compatible = "arm,mhuv2-tx","arm,primecell";
 		reg = <0x0 0x45000000 0x0 0x1000>;
 		clocks = <&soc_refclk100mhz>;
 		clock-names = "apb_pclk";
-		#mbox-cells = <1>;
+		#mbox-cells = <2>;
 		interrupt-names = "mhu_tx";
 		mhu-protocol = "doorbell";
+		arm,mhuv2-protocols = <0 1>;
 	};
 
 	scmi {
 		compatible = "arm,scmi";
-		method = "mailbox-doorbell";
 		mbox-names = "tx", "rx";
-		mboxes = <&mbox_db_tx 0 &mbox_db_rx 0>;
+		mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
 		shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -236,7 +246,7 @@
 		ranges;
 		interrupt-controller;
 		reg = <0x0 0x30000000 0 0x10000>, /* GICD */
-		      <0x0 0x30140000 0 0x200000>; /* GICR */
+		      <0x0 0x30080000 0 0x200000>; /* GICR */
 		interrupts = <0x1 0x9 0x4>;
 	};
 
@@ -430,16 +440,4 @@
 		};
 	};
 
-	ffa {
-		compatible = "arm,ffa";
-		conduit = "smc";
-		mem_share_buffer = "tx";
-	};
-
-	firmware {
-		optee {
-		      compatible = "linaro,optee-tz";
-		      method = "ffa";
-		};
-	};
 };
diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S
index f75da0c..483f9fe 100644
--- a/include/arch/aarch32/asm_macros.S
+++ b/include/arch/aarch32/asm_macros.S
@@ -107,12 +107,12 @@
 
 #else
 	/*
-	 * Macro for mitigating against speculative execution beyond ERET.
-	 * If possible use Speculation Barrier instruction defined in ARMv8.5
+	 * Macro for mitigating against speculative execution beyond ERET. Uses the
+	 * speculation barrier instruction introduced by FEAT_SB, if it's enabled.
 	 */
 	.macro exception_return
 	eret
-#if ARM_ARCH_AT_LEAST(8, 5)
+#if ENABLE_FEAT_SB
 	sb
 #else
 	dsb	nsh
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 580dd95..7fff4c7 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,9 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <assert_macros.S>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+
+#define PAGE_START_MASK		~(PAGE_SIZE_MASK)
 
 	/*
 	 * Helper macro to initialise EL3 registers we care about.
@@ -199,11 +202,18 @@
  *
  * _exception_vectors:
  *	Address of the exception vectors to program in the VBAR_EL3 register.
+ *
+ * _pie_fixup_size:
+ *	Size of memory region to fixup Global Descriptor Table (GDT).
+ *
+ *	A non-zero value is expected when firmware needs GDT to be fixed-up.
+ *
  * -----------------------------------------------------------------------------
  */
 	.macro el3_entrypoint_common					\
 		_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot,	\
-		_init_memory, _init_c_runtime, _exception_vectors
+		_init_memory, _init_c_runtime, _exception_vectors,	\
+		_pie_fixup_size
 
 	/* Make sure we are in Secure Mode */
 #if ENABLE_ASSERTIONS
@@ -259,6 +269,27 @@
 		bxne	r0
 	.endif /* _warm_boot_mailbox */
 
+	.if \_pie_fixup_size
+#if ENABLE_PIE
+		/*
+		 * ------------------------------------------------------------
+		 * If PIE is enabled fixup the Global descriptor Table only
+		 * once during primary core cold boot path.
+		 *
+		 * Compile time base address, required for fixup, is calculated
+		 * using "pie_fixup" label present within first page.
+		 * ------------------------------------------------------------
+		 */
+	pie_fixup:
+		ldr	r0, =pie_fixup
+		ldr	r1, =PAGE_START_MASK
+		and	r0, r0, r1
+		mov_imm	r1, \_pie_fixup_size
+		add	r1, r1, r0
+		bl	fixup_gdt_reloc
+#endif /* ENABLE_PIE */
+	.endif /* _pie_fixup_size */
+
 	/* ---------------------------------------------------------------------
 	 * Set the exception vectors (VBAR/MVBAR).
 	 * ---------------------------------------------------------------------
@@ -339,12 +370,14 @@
 		 */
 		mov	r7, r12
 		ldr	r0, =__BSS_START__
-		ldr	r1, =__BSS_SIZE__
+		ldr	r1, =__BSS_END__
+		sub 	r1, r1, r0
 		bl	zeromem
 
 #if USE_COHERENT_MEM
 		ldr	r0, =__COHERENT_RAM_START__
-		ldr	r1, =__COHERENT_RAM_UNALIGNED_SIZE__
+		ldr	r1, =__COHERENT_RAM_END_UNALIGNED__
+		sub 	r1, r1, r0
 		bl	zeromem
 #endif
 
@@ -358,7 +391,8 @@
 		 */
 		ldr	r0, =__DATA_RAM_START__
 		ldr	r1, =__DATA_ROM_START__
-		ldr	r2, =__DATA_SIZE__
+		ldr	r2, =__DATA_RAM_END__
+		sub 	r2, r2, r0
 		bl	memcpy4
 #endif
 	.endif /* _init_c_runtime */
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index b86a13e..c12dbc4 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -170,6 +170,7 @@
 #define ID_AA64PFR0_GIC_MASK	ULL(0xf)
 #define ID_AA64PFR0_SVE_SHIFT	U(32)
 #define ID_AA64PFR0_SVE_MASK	ULL(0xf)
+#define ID_AA64PFR0_SVE_LENGTH	U(4)
 #define ID_AA64PFR0_SEL2_SHIFT	U(36)
 #define ID_AA64PFR0_SEL2_MASK	ULL(0xf)
 #define ID_AA64PFR0_MPAM_SHIFT	U(40)
@@ -262,6 +263,9 @@
 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED		ULL(0x2)
 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED		ULL(0x3)
 
+#define ID_AA64MMFR1_EL1_VHE_SHIFT		U(8)
+#define ID_AA64MMFR1_EL1_VHE_MASK		ULL(0xf)
+
 /* ID_AA64MMFR2_EL1 definitions */
 #define ID_AA64MMFR2_EL1		S3_0_C0_C7_2
 
@@ -389,7 +393,8 @@
 
 #define SCTLR_ATA0_BIT		(ULL(1) << 42)
 #define SCTLR_ATA_BIT		(ULL(1) << 43)
-#define SCTLR_DSSBS_BIT		(ULL(1) << 44)
+#define SCTLR_DSSBS_SHIFT	U(44)
+#define SCTLR_DSSBS_BIT		(ULL(1) << SCTLR_DSSBS_SHIFT)
 #define SCTLR_TWEDEn_BIT	(ULL(1) << 45)
 #define SCTLR_TWEDEL_SHIFT	U(46)
 #define SCTLR_TWEDEL_MASK	ULL(0xf)
@@ -434,8 +439,16 @@
 #define SCR_RESET_VAL		SCR_RES1_BITS
 
 /* MDCR_EL3 definitions */
+#define MDCR_EnPMSN_BIT		(ULL(1) << 36)
+#define MDCR_MPMX_BIT		(ULL(1) << 35)
+#define MDCR_MCCD_BIT		(ULL(1) << 34)
 #define MDCR_MTPME_BIT		(ULL(1) << 28)
+#define MDCR_TDCC_BIT		(ULL(1) << 27)
 #define MDCR_SCCD_BIT		(ULL(1) << 23)
+#define MDCR_EPMAD_BIT		(ULL(1) << 21)
+#define MDCR_EDAD_BIT		(ULL(1) << 20)
+#define MDCR_TTRF_BIT		(ULL(1) << 19)
+#define MDCR_STE_BIT		(ULL(1) << 18)
 #define MDCR_SPME_BIT		(ULL(1) << 17)
 #define MDCR_SDD_BIT		(ULL(1) << 16)
 #define MDCR_SPD32(x)		((x) << 14)
@@ -521,7 +534,7 @@
 #define TTA_BIT			(U(1) << 20)
 #define TFP_BIT			(U(1) << 10)
 #define CPTR_EZ_BIT		(U(1) << 8)
-#define CPTR_EL3_RESET_VAL	U(0x0)
+#define CPTR_EL3_RESET_VAL	(TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT & ~(CPTR_EZ_BIT))
 
 /* CPTR_EL2 definitions */
 #define CPTR_EL2_RES1		((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
@@ -561,8 +574,16 @@
 #define SPSR_EL_SHIFT		U(2)
 #define SPSR_EL_WIDTH		U(2)
 
+#define SPSR_SSBS_SHIFT_AARCH64 U(12)
+#define SPSR_SSBS_BIT_AARCH64	(ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
+#define SPSR_SSBS_SHIFT_AARCH32 U(23)
+#define SPSR_SSBS_BIT_AARCH32	(ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
+
+#define SPSR_PAN_BIT		BIT_64(22)
+
+#define SPSR_DIT_BIT		BIT(24)
+
-#define SPSR_SSBS_BIT_AARCH64	BIT_64(12)
-#define SPSR_SSBS_BIT_AARCH32	BIT_64(23)
+#define SPSR_TCO_BIT_AARCH64	BIT_64(25)
 
 #define DISABLE_ALL_EXCEPTIONS \
 		(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 47a797a..dc0b7f3 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -17,6 +17,18 @@
 	return true;
 }
 
+static inline bool is_armv8_1_pan_present(void)
+{
+	return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_PAN_SHIFT) &
+		ID_AA64MMFR1_EL1_PAN_MASK) != 0U;
+}
+
+static inline bool is_armv8_1_vhe_present(void)
+{
+	return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_VHE_SHIFT) &
+		ID_AA64MMFR1_EL1_VHE_MASK) != 0U;
+}
+
 static inline bool is_armv8_2_ttcnp_present(void)
 {
 	return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 8c3400a..a41b325 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -260,6 +260,9 @@
 DEFINE_SYSREG_RW_FUNCS(elr_el1)
 DEFINE_SYSREG_RW_FUNCS(elr_el2)
 DEFINE_SYSREG_RW_FUNCS(elr_el3)
+DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
+DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
+DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
 
 DEFINE_SYSOP_FUNC(wfi)
 DEFINE_SYSOP_FUNC(wfe)
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index cbb9f0b..7706cd8 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -10,10 +10,6 @@
 #include <common/asm_macros_common.S>
 #include <lib/spinlock.h>
 
-#if ENABLE_BTI && !ARM_ARCH_AT_LEAST(8, 5)
-#error Branch Target Identification requires ARM_ARCH_MINOR >= 5
-#endif
-
 /*
  * TLBI instruction with type specifier that implements the workaround for
  * errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76.
@@ -219,12 +215,12 @@
 	.endm
 
 	/*
-	 * Macro for mitigating against speculative execution beyond ERET.
-	 * If possible use Speculation Barrier instruction defined in ARMv8.5
+	 * Macro for mitigating against speculative execution beyond ERET. Uses the
+	 * speculation barrier instruction introduced by FEAT_SB, if it's enabled.
 	 */
 	.macro exception_return
 	eret
-#if ARM_ARCH_AT_LEAST(8, 5)
+#if ENABLE_FEAT_SB
 	sb
 #else
 	dsb	nsh
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index f759983..9734335 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -113,8 +113,13 @@
 	 *
 	 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
 	 *  prohibited in Secure state. This bit is RES0 in versions of the
-	 *  architecture earlier than ARMv8.5, setting it to 1 doesn't have any
-	 *  effect on them.
+	 *  architecture with FEAT_PMUv3p5 not implemented, setting it to 1
+	 *  doesn't have any effect on them.
+	 *
+	 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
+	 *  prohibited in EL3. This bit is RES0 in versions of the
+	 *  architecture with FEAT_PMUv3p7 not implemented, setting it to 1
+	 *  doesn't have any effect on them.
 	 *
 	 * MDCR_EL3.SPME: Set to zero so that event counting by the programmable
 	 *  counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2
@@ -124,9 +129,9 @@
 	 * ---------------------------------------------------------------------
 	 */
 	mov_imm	x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
-		      MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \
-		    ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \
-		      MDCR_TPM_BIT))
+		      MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \
+		      MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \
+		      MDCR_TDA_BIT | MDCR_TPM_BIT))
 
 	msr	mdcr_el3, x0
 
@@ -180,7 +185,14 @@
 	 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
 	 *  by Advanced SIMD, floating-point or SVE instructions (if implemented)
 	 *  do not trap to EL3.
+	 *
+	 * CPTR_EL3.TAM: Set to one so that Activity Monitor access is
+	 *  trapped to EL3 by default.
+	 *
+	 * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped
+	 *  to EL3 by default.
 	 */
+
 	mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
 	msr	cptr_el3, x0
 
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 77fb1f6..e33840c 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -106,6 +106,10 @@
 IMPORT_SYM(uintptr_t, __RO_START__,		BL_CODE_BASE);
 IMPORT_SYM(uintptr_t, __RO_END__,		BL_CODE_END);
 #endif
+#if SEPARATE_NOBITS_REGION
+IMPORT_SYM(uintptr_t, __NOBITS_START__,		BL_NOBITS_BASE);
+IMPORT_SYM(uintptr_t, __NOBITS_END__,		BL_NOBITS_END);
+#endif
 IMPORT_SYM(uintptr_t, __RW_END__,		BL_END);
 
 #if defined(IMAGE_BL1)
diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h
index ab3391a..5147e37 100644
--- a/include/common/bl_common.ld.h
+++ b/include/common/bl_common.ld.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -105,10 +105,18 @@
  * .rela.dyn needs to come after .data for the read-elf utility to parse
  * this section correctly.
  */
+#if __aarch64__
+#define RELA_DYN_NAME		.rela.dyn
+#define RELOC_SECTIONS_PATTERN	*(.rela*)
+#else
+#define RELA_DYN_NAME		.rel.dyn
+#define RELOC_SECTIONS_PATTERN	*(.rel*)
+#endif
+
 #define RELA_SECTION					\
-	.rela.dyn : ALIGN(STRUCT_ALIGN) {		\
+	RELA_DYN_NAME : ALIGN(STRUCT_ALIGN) {		\
 		__RELA_START__ = .;			\
-		*(.rela*)				\
+		RELOC_SECTIONS_PATTERN			\
 		__RELA_END__ = .;			\
 	}
 
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index a571092..e8b3933 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,6 +24,8 @@
 			  unsigned int cells, uint32_t *value);
 int fdtw_read_string(const void *dtb, int node, const char *prop,
 		char *str, size_t size);
+int fdtw_read_uuid(const void *dtb, int node, const char *prop,
+		   unsigned int length, uint8_t *uuid);
 int fdtw_write_inplace_cells(void *dtb, int node, const char *prop,
 		unsigned int cells, void *value);
 int fdtw_read_bytes(const void *dtb, int node, const char *prop,
diff --git a/include/common/hw_crc32.h b/include/common/hw_crc32.h
new file mode 100644
index 0000000..0d14d57
--- /dev/null
+++ b/include/common/hw_crc32.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef HW_CRC32_H
+#define HW_CRC32_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* compute CRC using Arm intrinsic function */
+uint32_t hw_crc32(uint32_t crc, const unsigned char *buf, size_t size);
+
+#endif /* HW_CRC32_H */
diff --git a/include/common/uuid.h b/include/common/uuid.h
new file mode 100644
index 0000000..5651d0d
--- /dev/null
+++ b/include/common/uuid.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UUID_H
+#define UUID_H
+
+#define UUID_BYTES_LENGTH	16
+#define UUID_STRING_LENGTH	36
+
+int read_uuid(uint8_t *dest, char *uuid);
+
+#endif /* UUID_H */
diff --git a/include/drivers/arm/css/scmi.h b/include/drivers/arm/css/scmi.h
index e8a2863..adce7a6 100644
--- a/include/drivers/arm/css/scmi.h
+++ b/include/drivers/arm/css/scmi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,7 @@
 
 /* Supported SCMI Protocol Versions */
 #define SCMI_AP_CORE_PROTO_VER			MAKE_SCMI_VERSION(1, 0)
-#define SCMI_PWR_DMN_PROTO_VER			MAKE_SCMI_VERSION(1, 0)
+#define SCMI_PWR_DMN_PROTO_VER			MAKE_SCMI_VERSION(2, 0)
 #define SCMI_SYS_PWR_PROTO_VER			MAKE_SCMI_VERSION(1, 0)
 
 #define GET_SCMI_MAJOR_VER(ver)			(((ver) >> 16) & 0xffff)
diff --git a/include/drivers/arm/dcc.h b/include/drivers/arm/dcc.h
new file mode 100644
index 0000000..1f1fd03
--- /dev/null
+++ b/include/drivers/arm/dcc.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2021,  Xilinx Inc.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DCC_H
+#define DCC_H
+
+#include <stdint.h>
+#include <drivers/console.h>
+
+/*
+ * Initialize a new dcc console instance and register it with the console
+ * framework.
+ */
+int console_dcc_register(void);
+
+#endif /* DCC */
diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h
new file mode 100644
index 0000000..6de2abb
--- /dev/null
+++ b/include/drivers/arm/ethosn.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ETHOSN_H
+#define ETHOSN_H
+
+#include <lib/smccc.h>
+
+/* Function numbers */
+#define ETHOSN_FNUM_VERSION		U(0x50)
+#define ETHOSN_FNUM_IS_SEC		U(0x51)
+#define ETHOSN_FNUM_HARD_RESET		U(0x52)
+#define ETHOSN_FNUM_SOFT_RESET		U(0x53)
+/* 0x54-0x5F reserved for future use */
+
+/* SMC64 function IDs */
+#define ETHOSN_FID_64(func_num)		U(0xC2000000 | func_num)
+#define ETHOSN_FID_VERSION_64		ETHOSN_FID_64(ETHOSN_FNUM_VERSION)
+#define ETHOSN_FID_IS_SEC_64		ETHOSN_FID_64(ETHOSN_FNUM_IS_SEC)
+#define ETHOSN_FID_HARD_RESET_64	ETHOSN_FID_64(ETHOSN_FNUM_HARD_RESET)
+#define ETHOSN_FID_SOFT_RESET_64	ETHOSN_FID_64(ETHOSN_FNUM_SOFT_RESET)
+
+/* SMC32 function IDs */
+#define ETHOSN_FID_32(func_num)		U(0x82000000 | func_num)
+#define ETHOSN_FID_VERSION_32		ETHOSN_FID_32(ETHOSN_FNUM_VERSION)
+#define ETHOSN_FID_IS_SEC_32		ETHOSN_FID_32(ETHOSN_FNUM_IS_SEC)
+#define ETHOSN_FID_HARD_RESET_32	ETHOSN_FID_32(ETHOSN_FNUM_HARD_RESET)
+#define ETHOSN_FID_SOFT_RESET_32	ETHOSN_FID_32(ETHOSN_FNUM_SOFT_RESET)
+
+#define ETHOSN_NUM_SMC_CALLS	8
+
+/* Macro to identify function calls */
+#define ETHOSN_FID_MASK		U(0xFFF0)
+#define ETHOSN_FID_VALUE	U(0x50)
+#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
+
+/* Service version  */
+#define ETHOSN_VERSION_MAJOR U(0)
+#define ETHOSN_VERSION_MINOR U(1)
+
+/* Return codes for function calls */
+#define ETHOSN_SUCCESS			 0
+#define ETHOSN_NOT_SUPPORTED		-1
+/* -2 Reserved for NOT_REQUIRED */
+/* -3 Reserved for INVALID_PARAMETER */
+#define ETHOSN_FAILURE			-4
+#define ETHOSN_CORE_IDX_OUT_OF_RANGE	-5
+
+uintptr_t ethosn_smc_handler(uint32_t smc_fid,
+			     u_register_t core_idx,
+			     u_register_t x2,
+			     u_register_t x3,
+			     u_register_t x4,
+			     void *cookie,
+			     void *handle,
+			     u_register_t flags);
+
+#endif  /* ETHOSN_H */
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index aacd5df..5f8a48f 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -90,6 +90,8 @@
 #define TZC_400_REGION_SIZE			U(0x20)
 #define TZC_400_ACTION_OFF			U(0x4)
 
+#define FILTER_OFFSET				U(0x10)
+
 #ifndef __ASSEMBLER__
 
 #include <cdefs.h>
@@ -110,6 +112,7 @@
 void tzc400_set_action(unsigned int action);
 void tzc400_enable_filters(void);
 void tzc400_disable_filters(void);
+int tzc400_it_handler(void);
 
 static inline void tzc_init(uintptr_t base)
 {
diff --git a/include/drivers/brcm/mdio/mdio.h b/include/drivers/brcm/mdio/mdio.h
new file mode 100644
index 0000000..b27c7b3
--- /dev/null
+++ b/include/drivers/brcm/mdio/mdio.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MDIO_H
+#define MDIO_H
+
+#define CMIC_MIIM_PARAM		(PLAT_CMIC_MIIM_BASE + 0x23cU)
+#define MDIO_PARAM_MIIM_CYCLE	29U
+#define MDIO_PARAM_INTERNAL_SEL	25U
+#define MDIO_PARAM_BUSID	22U
+#define MDIO_PARAM_BUSID_MASK	0x7U
+#define MDIO_PARAM_C45_SEL	21U
+#define MDIO_PARAM_PHYID	16U
+#define MDIO_PARAM_PHYID_MASK	0x1FU
+#define MDIO_PARAM_DATA		0U
+#define MDIO_PARAM_DATA_MASK	0xFFFFU
+#define CMIC_MIIM_READ_DATA	(PLAT_CMIC_MIIM_BASE + 0x240U)
+#define MDIO_READ_DATA_MASK	0xffffU
+#define CMIC_MIIM_ADDRESS	(PLAT_CMIC_MIIM_BASE + 0x244U)
+#define CMIC_MIIM_CTRL		(PLAT_CMIC_MIIM_BASE + 0x248U)
+#define MDIO_CTRL_WRITE_OP	0x1U
+#define MDIO_CTRL_READ_OP	0x2U
+#define CMIC_MIIM_STAT		(PLAT_CMIC_MIIM_BASE + 0x24cU)
+#define MDIO_STAT_DONE		1U
+
+int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val);
+int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg);
+#endif /* MDIO_H */
diff --git a/include/drivers/brcm/usbh_xhci_regs.h b/include/drivers/brcm/usbh_xhci_regs.h
new file mode 100644
index 0000000..93dec7b
--- /dev/null
+++ b/include/drivers/brcm/usbh_xhci_regs.h
@@ -0,0 +1,4809 @@
+/*
+ * Copyright (c) 2017 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef USBH_XHCI_REGS_H
+#define USBH_XHCI_REGS_H
+
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define XHCI_LEN (8096U)
+
+#define XHC_CPLIVER_OFFSET			0x000U
+#define XHC_SPARAMS1_OFFSET			0x004U
+#define XHC_SPARAMS2_OFFSET			0x008U
+#define XHC_SPARAMS3_OFFSET			0x00cU
+#define XHC_CPARAMS1_OFFSET			0x010U
+#define XHC_DBOFF_OFFSET			0x014U
+#define XHC_RTOFF_OFFSET			0x018U
+#define XHC_CPARAMS2_OFFSET			0x01cU
+#define XHC_USBCMD_OFFSET			0x020U
+#define XHC_USBSTS_OFFSET			0x024U
+#define XHC_PAGESIZE_OFFSET			0x028U
+#define XHC_DNCTRL_OFFSET			0x034U
+#define XHC_CRCRL_OFFSET			0x038U
+#define XHC_CRCRH_OFFSET			0x03cU
+#define XHC_DCBAAPL_OFFSET			0x050U
+#define XHC_DCBAAPH_OFFSET			0x054U
+#define XHC_CONFIG_OFFSET			0x058U
+#define XHC_PORTSC1_OFFSET			0x420U
+#define XHC_PORTPM1_OFFSET			0x424U
+#define XHC_PORTLC1_OFFSET			0x428U
+#define XHC_PORTSC2_OFFSET			0x430U
+#define XHC_PORTPM2_OFFSET			0x434U
+#define XHC_PORTLC2_OFFSET			0x43cU
+#define XHC_PORTSC3_OFFSET			0x440U
+#define XHC_PORTPM3_OFFSET			0x444U
+#define XHC_PORTLI3_OFFSET			0x44cU
+#define XHC_MFINDEX_OFFSET			0x4a0U
+#define XHC_IMAN0_OFFSET			0x4c0U
+#define XHC_IMOD0_OFFSET			0x4c4U
+#define XHC_ERSTSZ0_OFFSET			0x4c8U
+#define XHC_ERSTBAL0_OFFSET			0x4d0U
+#define XHC_ERSTBAH0_OFFSET			0x4d4U
+#define XHC_ERDPL0_OFFSET			0x4d8U
+#define XHC_ERDPH0_OFFSET			0x4dcU
+#define XHC_IMAN1_OFFSET			0x4e0U
+#define XHC_IMOD1_OFFSET			0x4e4U
+#define XHC_ERSTSZ1_OFFSET			0x4e8U
+#define XHC_ERSTBAL1_OFFSET			0x4f0U
+#define XHC_ERSTBAH1_OFFSET			0x4f4U
+#define XHC_ERDPL1_OFFSET			0x4f8U
+#define XHC_ERDPH1_OFFSET			0x4fcU
+#define XHC_DBLCMD_OFFSET			0x8c0U
+#define XHC_DBLDVX1_OFFSET			0x8c4U
+#define XHC_DBLDVX2_OFFSET			0x8c8U
+#define XHC_DBLDVX3_OFFSET			0x8ccU
+#define XHC_DBLDVX4_OFFSET			0x8d0U
+#define XHC_DBLDVX5_OFFSET			0x8d4U
+#define XHC_DBLDVX6_OFFSET			0x8d8U
+#define XHC_DBLDVX7_OFFSET			0x8dcU
+#define XHC_DBLDVX8_OFFSET			0x8e0U
+#define XHC_DBLDVX9_OFFSET			0x8e4U
+#define XHC_DBLDVX10_OFFSET			0x8e8U
+#define XHC_DBLDVX11_OFFSET			0x8ecU
+#define XHC_DBLDVX12_OFFSET			0x8f0U
+#define XHC_DBLDVX13_OFFSET			0x8f4U
+#define XHC_DBLDVX14_OFFSET			0x8f8U
+#define XHC_DBLDVX15_OFFSET			0x8fcU
+#define XHC_DBLDVX16_OFFSET			0x900U
+#define XHC_ECHSPT3_OFFSET			0x940U
+#define XHC_PNSTR3_OFFSET			0x944U
+#define XHC_PSUM3_OFFSET			0x948U
+#define XHC_PTSLTYP3_OFFSET			0x94cU
+#define XHC_ECHSPT2_OFFSET			0x950U
+#define XHC_PNSTR2_OFFSET			0x954U
+#define XHC_PSUM2_OFFSET			0x958U
+#define XHC_PTSLTYP2_OFFSET			0x95cU
+#define XHC_ECHRSVP_OFFSET			0x960U
+#define XHC_ECHRSVI_OFFSET			0x968U
+#define XHC_ECHRSVM_OFFSET			0xae8U
+#define XHC_ECHRSVD_OFFSET			0xaf8U
+#define XHC_ECHRSVO_OFFSET			0xb38U
+#define XHC_ECHCTT_OFFSET			0xbf0U
+#define XHC_CTTMTS0_OFFSET			0xbf8U
+#define XHC_CTTMTS1_OFFSET			0xbfcU
+#define XHC_ECHBIU_OFFSET			0xc00U
+#define XHC_BIUSPC_OFFSET			0xc04U
+#define XHC_AXIWRA_OFFSET			0xc08U
+#define XHC_AXIRDA_OFFSET			0xc0cU
+#define XHC_AXILPM_OFFSET			0xc10U
+#define XHC_AXIQOS_OFFSET			0xc14U
+#define XHC_ECHCSR_OFFSET			0xc20U
+#define XHC_CSRSPC_OFFSET			0xc24U
+#define XHC_ECHAIU_OFFSET			0xc30U
+#define XHC_AIUDMA_OFFSET			0xc34U
+#define XHC_AIUFLA_OFFSET			0xc38U
+#define XHC_AIUCFG_OFFSET			0xc3cU
+#define XHC_ECHFSC_OFFSET			0xc40U
+#define XHC_FSCPOC_OFFSET			0xc54U
+#define XHC_FSCGOC_OFFSET			0xc58U
+#define XHC_FSCNOC_OFFSET			0xc5cU
+#define XHC_FSCAIC_OFFSET			0xc60U
+#define XHC_FSCPIC_OFFSET			0xc64U
+#define XHC_FSCGIC_OFFSET			0xc68U
+#define XHC_FSCNIC_OFFSET			0xc6cU
+#define XHC_ECHPRT_OFFSET			0xc70U
+#define XHC_PRTHSC_OFFSET			0xc78U
+#define XHC_PRTHSR_OFFSET			0xc7cU
+#define XHC_ECHRHS_OFFSET			0xc80U
+#define XHC_RHSDES_OFFSET			0xc84U
+#define XHC_RHSHSC0_OFFSET			0xc90U
+#define XHC_RHSHSR0_OFFSET			0xc94U
+#define XHC_RHSHSC1_OFFSET			0xc98U
+#define XHC_RHSHSR1_OFFSET			0xc9cU
+#define XHC_RHSHSC2_OFFSET			0xca0U
+#define XHC_RHSHSR2_OFFSET			0xca4U
+#define XHC_RHSHSC3_OFFSET			0xca8U
+#define XHC_RHSHSR3_OFFSET			0xcacU
+#define XHC_ECHSSP_OFFSET			0xcb0U
+#define XHC_SSPVER_OFFSET			0xcb4U
+#define XHC_SSPMGN_OFFSET			0xcb8U
+#define XHC_ECHFSC2_OFFSET			0xcc0U
+#define XHC_FSC2POC_OFFSET			0xcd4U
+#define XHC_FSC2GOC_OFFSET			0xcd8U
+#define XHC_FSC2NOC_OFFSET			0xcdcU
+#define XHC_FSC2AIC_OFFSET			0xce0U
+#define XHC_FSC2PIC_OFFSET			0xce4U
+#define XHC_FSC2GIC_OFFSET			0xce8U
+#define XHC_FSC2NIC_OFFSET			0xcecU
+#define XHC_ECHPRT2_OFFSET			0xcf0U
+#define XHC_PRT2HSC_OFFSET			0xcf8U
+#define XHC_PRT2HSR_OFFSET			0xcfcU
+#define XHC_ECHRH2_OFFSET			0xd00U
+#define XHC_RH2DES_OFFSET			0xd04U
+#define XHC_RH2HSC0_OFFSET			0xd10U
+#define XHC_RH2HSR0_OFFSET			0xd14U
+#define XHC_RH2HSC1_OFFSET			0xd18U
+#define XHC_RH2HSR1_OFFSET			0xd1cU
+#define XHC_RH2HSC2_OFFSET			0xd20U
+#define XHC_RH2HSR2_OFFSET			0xd24U
+#define XHC_RH2HSC3_OFFSET			0xd28U
+#define XHC_RH2HSR3_OFFSET			0xd2cU
+#define XHC_ECHU2P_OFFSET			0xd30U
+#define XHC_U2PVER_OFFSET			0xd34U
+#define XHC_U2PMGN_OFFSET			0xd38U
+#define XHC_ECHRSV2_OFFSET			0xd40U
+#define XHC_ECHIRA_OFFSET			0xf90U
+#define XHC_IRAADR_OFFSET			0xf98U
+#define XHC_IRADAT_OFFSET			0xf9cU
+#define XHC_ECHHST_OFFSET			0xfa0U
+#define XHC_HSTDBG_OFFSET			0xfa4U
+#define XHC_HSTNPL_OFFSET			0xfa8U
+#define XHC_HSTNPH_OFFSET			0xfacU
+#define XHC_ECHRBV_OFFSET			0xfb0U
+#define XHC_RBVPDT_OFFSET			0xfb4U
+#define XHC_RBVMGN_OFFSET			0xfbcU
+
+#define XHC_CPLIVER_BASE			0x000U
+#define XHC_CPLIVER__IVH_L			31U
+#define XHC_CPLIVER__IVH_R			24U
+#define XHC_CPLIVER__IVH_WIDTH			8U
+#define XHC_CPLIVER__IVH_RESETVALUE		0x01U
+#define XHC_CPLIVER__IVL_L			23U
+#define XHC_CPLIVER__IVL_R			16U
+#define XHC_CPLIVER__IVL_WIDTH			8U
+#define XHC_CPLIVER__IVL_RESETVALUE		0x10U
+#define XHC_CPLIVER__reserved_L			15U
+#define XHC_CPLIVER__reserved_R			8U
+#define XHC_CPLIVER__reserved_WIDTH		8U
+#define XHC_CPLIVER__reserved_RESETVALUE	0x00U
+#define XHC_CPLIVER__CPL_L			7U
+#define XHC_CPLIVER__CPL_R			0U
+#define XHC_CPLIVER__CPL_WIDTH			8U
+#define XHC_CPLIVER__CPL_RESETVALUE		0x00U
+#define XHC_CPLIVER_WIDTH			32U
+#define XHC_CPLIVER__WIDTH			32U
+#define XHC_CPLIVER_ALL_L			31U
+#define XHC_CPLIVER_ALL_R			0U
+#define XHC_CPLIVER__ALL_L			31U
+#define XHC_CPLIVER__ALL_R			0U
+#define XHC_CPLIVER_DATAMASK			0xffffffffU
+#define XHC_CPLIVER_RDWRMASK			0x00000000U
+#define XHC_CPLIVER_RESETVALUE			0x01100000U
+
+#define XHC_SPARAMS1_OFFSET			0x004U
+#define XHC_SPARAMS1_BASE			0x004U
+#define XHC_SPARAMS1__NPTS_L			31U
+#define XHC_SPARAMS1__NPTS_R			24U
+#define XHC_SPARAMS1__NPTS_WIDTH		8U
+#define XHC_SPARAMS1__NPTS_RESETVALUE		0x00U
+#define XHC_SPARAMS1__reserved_L		23U
+#define XHC_SPARAMS1__reserved_R		19U
+#define XHC_SPARAMS1__reserved_WIDTH		5U
+#define XHC_SPARAMS1__reserved_RESETVALUE	0x0U
+#define XHC_SPARAMS1__MITS_L			18U
+#define XHC_SPARAMS1__MITS_R			8U
+#define XHC_SPARAMS1__MITS_WIDTH		11U
+#define XHC_SPARAMS1__MITS_RESETVALUE		0x1U
+#define XHC_SPARAMS1__MSLS_L			7U
+#define XHC_SPARAMS1__MSLS_R			0U
+#define XHC_SPARAMS1__MSLS_WIDTH		8U
+#define XHC_SPARAMS1__MSLS_RESETVALUE		0x00U
+#define XHC_SPARAMS1_WIDTH			32U
+#define XHC_SPARAMS1__WIDTH			32U
+#define XHC_SPARAMS1_ALL_L			31U
+#define XHC_SPARAMS1_ALL_R			0U
+#define XHC_SPARAMS1__ALL_L			31U
+#define XHC_SPARAMS1__ALL_R			0U
+#define XHC_SPARAMS1_DATAMASK			0xffffffffU
+#define XHC_SPARAMS1_RDWRMASK			0x00000000U
+#define XHC_SPARAMS1_RESETVALUE			0x00000100U
+
+#define XHC_SPARAMS2_OFFSET			0x008U
+#define XHC_SPARAMS2_BASE			0x008U
+#define XHC_SPARAMS2__MSPBSL_L			31U
+#define XHC_SPARAMS2__MSPBSL_R			27U
+#define XHC_SPARAMS2__MSPBSL_WIDTH		5U
+#define XHC_SPARAMS2__MSPBSL_RESETVALUE		0x0U
+#define XHC_SPARAMS2__SPR			26U
+#define XHC_SPARAMS2__SPR_L			26U
+#define XHC_SPARAMS2__SPR_R			26U
+#define XHC_SPARAMS2__SPR_WIDTH			1U
+#define XHC_SPARAMS2__SPR_RESETVALUE		0x1U
+#define XHC_SPARAMS2__MSPBSH_L			25U
+#define XHC_SPARAMS2__MSPBSH_R			21U
+#define XHC_SPARAMS2__MSPBSH_WIDTH		5U
+#define XHC_SPARAMS2__MSPBSH_RESETVALUE		0x0U
+#define XHC_SPARAMS2__reserved_L		20U
+#define XHC_SPARAMS2__reserved_R		8U
+#define XHC_SPARAMS2__reserved_WIDTH		13U
+#define XHC_SPARAMS2__reserved_RESETVALUE	0x0U
+#define XHC_SPARAMS2__MERST_L			7U
+#define XHC_SPARAMS2__MERST_R			4U
+#define XHC_SPARAMS2__MERST_WIDTH		4U
+#define XHC_SPARAMS2__MERST_RESETVALUE		0x0U
+#define XHC_SPARAMS2__IST_L			3U
+#define XHC_SPARAMS2__IST_R			0U
+#define XHC_SPARAMS2__IST_WIDTH			4U
+#define XHC_SPARAMS2__IST_RESETVALUE		0x0U
+#define XHC_SPARAMS2_WIDTH			32U
+#define XHC_SPARAMS2__WIDTH			32U
+#define XHC_SPARAMS2_ALL_L			31U
+#define XHC_SPARAMS2_ALL_R			0U
+#define XHC_SPARAMS2__ALL_L			31U
+#define XHC_SPARAMS2__ALL_R			0U
+#define XHC_SPARAMS2_DATAMASK			0xffffffffU
+#define XHC_SPARAMS2_RDWRMASK			0x00000000U
+#define XHC_SPARAMS2_RESETVALUE			0x04000000U
+
+#define XHC_SPARAMS3_OFFSET			0x00cU
+#define XHC_SPARAMS3_BASE			0x00cU
+#define XHC_SPARAMS3__U2L_L			31U
+#define XHC_SPARAMS3__U2L_R			16U
+#define XHC_SPARAMS3__U2L_WIDTH			16U
+#define XHC_SPARAMS3__U2L_RESETVALUE		0x0000U
+#define XHC_SPARAMS3__reserved_L		15U
+#define XHC_SPARAMS3__reserved_R		8U
+#define XHC_SPARAMS3__reserved_WIDTH		8U
+#define XHC_SPARAMS3__reserved_RESETVALUE	0x00U
+#define XHC_SPARAMS3__U1L_L			7U
+#define XHC_SPARAMS3__U1L_R			0U
+#define XHC_SPARAMS3__U1L_WIDTH			8U
+#define XHC_SPARAMS3__U1L_RESETVALUE		0x00U
+#define XHC_SPARAMS3_WIDTH			32U
+#define XHC_SPARAMS3__WIDTH			32U
+#define XHC_SPARAMS3_ALL_L			31U
+#define XHC_SPARAMS3_ALL_R			0U
+#define XHC_SPARAMS3__ALL_L			31U
+#define XHC_SPARAMS3__ALL_R			0U
+#define XHC_SPARAMS3_DATAMASK			0xffffffffU
+#define XHC_SPARAMS3_RDWRMASK			0x00000000U
+#define XHC_SPARAMS3_RESETVALUE			0x00000000U
+
+#define XHC_CPARAMS1_OFFSET			0x010U
+#define XHC_CPARAMS1_BASE			0x010U
+#define XHC_CPARAMS1__XECP_L			31U
+#define XHC_CPARAMS1__XECP_R			16U
+#define XHC_CPARAMS1__XECP_WIDTH		16U
+#define XHC_CPARAMS1__XECP_RESETVALUE		0x0000U
+#define XHC_CPARAMS1__MPSA_L			15U
+#define XHC_CPARAMS1__MPSA_R			12U
+#define XHC_CPARAMS1__MPSA_WIDTH		4U
+#define XHC_CPARAMS1__MPSA_RESETVALUE		0x0U
+#define XHC_CPARAMS1__CFC			11U
+#define XHC_CPARAMS1__CFC_L			11U
+#define XHC_CPARAMS1__CFC_R			11U
+#define XHC_CPARAMS1__CFC_WIDTH			1U
+#define XHC_CPARAMS1__CFC_RESETVALUE		0x0U
+#define XHC_CPARAMS1__SEC			10U
+#define XHC_CPARAMS1__SEC_L			10U
+#define XHC_CPARAMS1__SEC_R			10U
+#define XHC_CPARAMS1__SEC_WIDTH			1U
+#define XHC_CPARAMS1__SEC_RESETVALUE		0x0U
+#define XHC_CPARAMS1__SPC			9U
+#define XHC_CPARAMS1__SPC_L			9U
+#define XHC_CPARAMS1__SPC_R			9U
+#define XHC_CPARAMS1__SPC_WIDTH			1U
+#define XHC_CPARAMS1__SPC_RESETVALUE		0x0U
+#define XHC_CPARAMS1__PAE			8U
+#define XHC_CPARAMS1__PAE_L			8U
+#define XHC_CPARAMS1__PAE_R			8U
+#define XHC_CPARAMS1__PAE_WIDTH			1U
+#define XHC_CPARAMS1__PAE_RESETVALUE		0x1U
+#define XHC_CPARAMS1__NSS			7U
+#define XHC_CPARAMS1__NSS_L			7U
+#define XHC_CPARAMS1__NSS_R			7U
+#define XHC_CPARAMS1__NSS_WIDTH			1U
+#define XHC_CPARAMS1__NSS_RESETVALUE		0x0U
+#define XHC_CPARAMS1__LTC			6U
+#define XHC_CPARAMS1__LTC_L			6U
+#define XHC_CPARAMS1__LTC_R			6U
+#define XHC_CPARAMS1__LTC_WIDTH			1U
+#define XHC_CPARAMS1__LTC_RESETVALUE		0x1U
+#define XHC_CPARAMS1__LRC			5U
+#define XHC_CPARAMS1__LRC_L			5U
+#define XHC_CPARAMS1__LRC_R			5U
+#define XHC_CPARAMS1__LRC_WIDTH			1U
+#define XHC_CPARAMS1__LRC_RESETVALUE		0x0U
+#define XHC_CPARAMS1__PIND			4U
+#define XHC_CPARAMS1__PIND_L			4U
+#define XHC_CPARAMS1__PIND_R			4U
+#define XHC_CPARAMS1__PIND_WIDTH		1U
+#define XHC_CPARAMS1__PIND_RESETVALUE		0x0U
+
+#define XHC_CPARAMS1__PPC_L			3U
+#define XHC_CPARAMS1__PPC_R			3U
+#define XHC_CPARAMS1__PPC_WIDTH			1U
+#define XHC_CPARAMS1__PPC_RESETVALUE		0x0U
+#define XHC_CPARAMS1__CSZ			2U
+#define XHC_CPARAMS1__CSZ_L			2U
+#define XHC_CPARAMS1__CSZ_R			2U
+#define XHC_CPARAMS1__CSZ_WIDTH			1U
+#define XHC_CPARAMS1__CSZ_RESETVALUE		0x1U
+#define XHC_CPARAMS1__BNC			1U
+#define XHC_CPARAMS1__BNC_L			1U
+#define XHC_CPARAMS1__BNC_R			1U
+#define XHC_CPARAMS1__BNC_WIDTH			1U
+#define XHC_CPARAMS1__BNC_RESETVALUE		0x0U
+#define XHC_CPARAMS1__AC64			0U
+#define XHC_CPARAMS1__AC64_L			0U
+#define XHC_CPARAMS1__AC64_R			0U
+#define XHC_CPARAMS1__AC64_WIDTH		1U
+#define XHC_CPARAMS1__AC64_RESETVALUE		0x0U
+#define XHC_CPARAMS1_WIDTH			32U
+#define XHC_CPARAMS1__WIDTH			32U
+#define XHC_CPARAMS1_ALL_L			31U
+#define XHC_CPARAMS1_ALL_R			0U
+#define XHC_CPARAMS1__ALL_L			31U
+#define XHC_CPARAMS1__ALL_R			0U
+#define XHC_CPARAMS1_DATAMASK			0xffffffffU
+#define XHC_CPARAMS1_RDWRMASK			0x00000000U
+#define XHC_CPARAMS1_RESETVALUE			0x00000144U
+
+#define XHC_DBOFF_OFFSET			0x014U
+#define XHC_DBOFF_BASE				0x014U
+#define XHC_DBOFF__DBO_L			15U
+#define XHC_DBOFF__DBO_R			2U
+#define XHC_DBOFF__DBO_WIDTH			14U
+#define XHC_DBOFF__DBO_RESETVALUE		0x0U
+#define XHC_DBOFF__reserved_L			1U
+#define XHC_DBOFF__reserved_R			0U
+#define XHC_DBOFF__reserved_WIDTH		2U
+#define XHC_DBOFF__reserved_RESETVALUE		0x0U
+#define XHC_DBOFF__RESERVED_L			31U
+#define XHC_DBOFF__RESERVED_R			16U
+#define XHC_DBOFF_WIDTH				16U
+#define XHC_DBOFF__WIDTH			16U
+#define XHC_DBOFF_ALL_L				15U
+#define XHC_DBOFF_ALL_R				0U
+#define XHC_DBOFF__ALL_L			15U
+#define XHC_DBOFF__ALL_R			0U
+#define XHC_DBOFF_DATAMASK			0x0000ffffU
+#define XHC_DBOFF_RDWRMASK			0xffff0000U
+#define XHC_DBOFF_RESETVALUE			0x0000U
+
+#define XHC_RTOFF_OFFSET			0x018U
+#define XHC_RTOFF_BASE				0x018U
+#define XHC_RTOFF__RTO_L			15U
+#define XHC_RTOFF__RTO_R			5U
+#define XHC_RTOFF__RTO_WIDTH			11U
+#define XHC_RTOFF__RTO_RESETVALUE		0x0U
+#define XHC_RTOFF__reserved_L			4U
+#define XHC_RTOFF__reserved_R			0U
+#define XHC_RTOFF__reserved_WIDTH		5U
+#define XHC_RTOFF__reserved_RESETVALUE		0x0U
+#define XHC_RTOFF__RESERVED_L			31U
+#define XHC_RTOFF__RESERVED_R			16U
+#define XHC_RTOFF_WIDTH				16U
+#define XHC_RTOFF__WIDTH			16U
+#define XHC_RTOFF_ALL_L				15U
+#define XHC_RTOFF_ALL_R				0U
+#define XHC_RTOFF__ALL_L			15U
+#define XHC_RTOFF__ALL_R			0U
+#define XHC_RTOFF_DATAMASK			0x0000ffffU
+#define XHC_RTOFF_RDWRMASK			0xffff0000U
+#define XHC_RTOFF_RESETVALUE			0x0000U
+
+#define XHC_CPARAMS2_OFFSET			0x01cU
+#define XHC_CPARAMS2_BASE			0x01cU
+#define XHC_CPARAMS2__reserved_L		31U
+#define XHC_CPARAMS2__reserved_R		6U
+#define XHC_CPARAMS2__reserved_WIDTH		26U
+#define XHC_CPARAMS2__reserved_RESETVALUE	0x0U
+#define XHC_CPARAMS2__CIC			5U
+#define XHC_CPARAMS2__CIC_L			5U
+#define XHC_CPARAMS2__CIC_R			5U
+#define XHC_CPARAMS2__CIC_WIDTH			1U
+#define XHC_CPARAMS2__CIC_RESETVALUE		0x0U
+#define XHC_CPARAMS2__LEC			4U
+#define XHC_CPARAMS2__LEC_L			4U
+#define XHC_CPARAMS2__LEC_R			4U
+#define XHC_CPARAMS2__LEC_WIDTH			1U
+#define XHC_CPARAMS2__LEC_RESETVALUE		0x0U
+#define XHC_CPARAMS2__CTC			3U
+#define XHC_CPARAMS2__CTC_L			3U
+#define XHC_CPARAMS2__CTC_R			3U
+#define XHC_CPARAMS2__CTC_WIDTH			1U
+#define XHC_CPARAMS2__CTC_RESETVALUE		0x0U
+#define XHC_CPARAMS2__FSC			2U
+#define XHC_CPARAMS2__FSC_L			2U
+#define XHC_CPARAMS2__FSC_R			2U
+#define XHC_CPARAMS2__FSC_WIDTH			1U
+#define XHC_CPARAMS2__FSC_RESETVALUE		0x0U
+#define XHC_CPARAMS2__CMC			1U
+#define XHC_CPARAMS2__CMC_L			1U
+#define XHC_CPARAMS2__CMC_R			1U
+#define XHC_CPARAMS2__CMC_WIDTH			1U
+#define XHC_CPARAMS2__CMC_RESETVALUE		0x0U
+#define XHC_CPARAMS2__U3C			0U
+#define XHC_CPARAMS2__U3C_L			0U
+#define XHC_CPARAMS2__U3C_R			0U
+#define XHC_CPARAMS2__U3C_WIDTH			1U
+#define XHC_CPARAMS2__U3C_RESETVALUE		0x0U
+#define XHC_CPARAMS2_WIDTH			32U
+#define XHC_CPARAMS2__WIDTH			32U
+#define XHC_CPARAMS2_ALL_L			31U
+#define XHC_CPARAMS2_ALL_R			0U
+#define XHC_CPARAMS2__ALL_L			31U
+#define XHC_CPARAMS2__ALL_R			0U
+#define XHC_CPARAMS2_DATAMASK			0xffffffffU
+#define XHC_CPARAMS2_RDWRMASK			0x00000000U
+#define XHC_CPARAMS2_RESETVALUE			0x00000000U
+
+#define XHC_USBCMD_OFFSET			0x020U
+#define XHC_USBCMD_BASE				0x020U
+#define XHC_USBCMD__CME				13U
+#define XHC_USBCMD__CME_L			13U
+#define XHC_USBCMD__CME_R			13U
+#define XHC_USBCMD__CME_WIDTH			1U
+#define XHC_USBCMD__CME_RESETVALUE		0x0U
+#define XHC_USBCMD__SPE				12U
+#define XHC_USBCMD__SPE_L			12U
+#define XHC_USBCMD__SPE_R			12U
+#define XHC_USBCMD__SPE_WIDTH			1U
+#define XHC_USBCMD__SPE_RESETVALUE		0x0U
+#define XHC_USBCMD__EU3S			11U
+#define XHC_USBCMD__EU3S_L			11U
+#define XHC_USBCMD__EU3S_R			11U
+#define XHC_USBCMD__EU3S_WIDTH			1U
+#define XHC_USBCMD__EU3S_RESETVALUE		0x0U
+#define XHC_USBCMD__EWE				10U
+#define XHC_USBCMD__EWE_L			10U
+#define XHC_USBCMD__EWE_R			10U
+#define XHC_USBCMD__EWE_WIDTH			1U
+#define XHC_USBCMD__EWE_RESETVALUE		0x0U
+#define XHC_USBCMD__CRS				9U
+#define XHC_USBCMD__CRS_L			9U
+#define XHC_USBCMD__CRS_R			9U
+#define XHC_USBCMD__CRS_WIDTH			1U
+#define XHC_USBCMD__CRS_RESETVALUE		0x0U
+#define XHC_USBCMD__CSS				8U
+#define XHC_USBCMD__CSS_L			8U
+#define XHC_USBCMD__CSS_R			8U
+#define XHC_USBCMD__CSS_WIDTH			1U
+#define XHC_USBCMD__CSS_RESETVALUE		0x0U
+#define XHC_USBCMD__LRST			7U
+#define XHC_USBCMD__LRST_L			7U
+#define XHC_USBCMD__LRST_R			7U
+#define XHC_USBCMD__LRST_WIDTH			1U
+#define XHC_USBCMD__LRST_RESETVALUE		0x0U
+#define XHC_USBCMD__reserved_L			6U
+#define XHC_USBCMD__reserved_R			4U
+#define XHC_USBCMD__reserved_WIDTH		3U
+#define XHC_USBCMD__reserved_RESETVALUE		0x0U
+#define XHC_USBCMD__HSEE			3U
+#define XHC_USBCMD__HSEE_L			3U
+#define XHC_USBCMD__HSEE_R			3U
+#define XHC_USBCMD__HSEE_WIDTH			1U
+#define XHC_USBCMD__HSEE_RESETVALUE		0x0U
+#define XHC_USBCMD__INTE			2U
+#define XHC_USBCMD__INTE_L			2U
+#define XHC_USBCMD__INTE_R			2U
+#define XHC_USBCMD__INTE_WIDTH			1U
+#define XHC_USBCMD__INTE_RESETVALUE		0x0U
+#define XHC_USBCMD__RST				1U
+#define XHC_USBCMD__RST_L			1U
+#define XHC_USBCMD__RST_R			1U
+#define XHC_USBCMD__RST_WIDTH			1U
+#define XHC_USBCMD__RST_RESETVALUE		0x0U
+#define XHC_USBCMD__RS				0U
+#define XHC_USBCMD__RS_L			0U
+#define XHC_USBCMD__RS_R			0U
+#define XHC_USBCMD__RS_WIDTH			1U
+#define XHC_USBCMD__RS_RESETVALUE		0x0U
+#define XHC_USBCMD__RESERVED_L			31U
+#define XHC_USBCMD__RESERVED_R			14U
+#define XHC_USBCMD_WIDTH			14U
+#define XHC_USBCMD__WIDTH			14U
+#define XHC_USBCMD_ALL_L			13U
+#define XHC_USBCMD_ALL_R			0U
+#define XHC_USBCMD__ALL_L			13U
+#define XHC_USBCMD__ALL_R			0U
+#define XHC_USBCMD_DATAMASK			0x00003fffU
+#define XHC_USBCMD_RDWRMASK			0xffffc000U
+#define XHC_USBCMD_RESETVALUE			0x0000U
+
+#define XHC_USBSTS_OFFSET			0x024U
+#define XHC_USBSTS_BASE				0x024U
+#define XHC_USBSTS__CE				12U
+#define XHC_USBSTS__CE_L			12U
+#define XHC_USBSTS__CE_R			12U
+#define XHC_USBSTS__CE_WIDTH			1U
+#define XHC_USBSTS__CE_RESETVALUE		0x0U
+#define XHC_USBSTS__CNR				11U
+#define XHC_USBSTS__CNR_L			11U
+#define XHC_USBSTS__CNR_R			11U
+#define XHC_USBSTS__CNR_WIDTH			1U
+#define XHC_USBSTS__CNR_RESETVALUE		0x1U
+
+#define XHC_USBSTS__SRE				10U
+#define XHC_USBSTS__SRE_L			10U
+#define XHC_USBSTS__SRE_R			10U
+#define XHC_USBSTS__SRE_WIDTH			1U
+#define XHC_USBSTS__SRE_RESETVALUE		0x0U
+#define XHC_USBSTS__RSS				9U
+#define XHC_USBSTS__RSS_L			9U
+#define XHC_USBSTS__RSS_R			9U
+#define XHC_USBSTS__RSS_WIDTH			1U
+#define XHC_USBSTS__RSS_RESETVALUE		0x0U
+#define XHC_USBSTS__SSS				8U
+#define XHC_USBSTS__SSS_L			8U
+#define XHC_USBSTS__SSS_R			8U
+#define XHC_USBSTS__SSS_WIDTH			1U
+#define XHC_USBSTS__SSS_RESETVALUE		0x0U
+#define XHC_USBSTS__PCD				4U
+#define XHC_USBSTS__PCD_L			4U
+#define XHC_USBSTS__PCD_R			4U
+#define XHC_USBSTS__PCD_WIDTH			1U
+#define XHC_USBSTS__PCD_RESETVALUE		0x0U
+#define XHC_USBSTS__EINT			3U
+#define XHC_USBSTS__EINT_L			3U
+#define XHC_USBSTS__EINT_R			3U
+#define XHC_USBSTS__EINT_WIDTH			1U
+#define XHC_USBSTS__EINT_RESETVALUE		0x0U
+#define XHC_USBSTS__HSE				2U
+#define XHC_USBSTS__HSE_L			2U
+#define XHC_USBSTS__HSE_R			2U
+#define XHC_USBSTS__HSE_WIDTH			1U
+#define XHC_USBSTS__HSE_RESETVALUE		0x0U
+#define XHC_USBSTS__reserved			1U
+#define XHC_USBSTS__reserved_L			1U
+#define XHC_USBSTS__reserved_R			1U
+#define XHC_USBSTS__reserved_WIDTH		1U
+#define XHC_USBSTS__reserved_RESETVALUE		0x0U
+
+#define XHC_USBSTS__CH_L			0U
+#define XHC_USBSTS__CH_R			0U
+#define XHC_USBSTS__CH_WIDTH			1U
+#define XHC_USBSTS__CH_RESETVALUE		0x1U
+#define XHC_USBSTS__RESERVED_L			31U
+#define XHC_USBSTS__RESERVED_R			13U
+#define XHC_USBSTS_WIDTH			13U
+#define XHC_USBSTS__WIDTH			13U
+#define XHC_USBSTS_ALL_L			12U
+#define XHC_USBSTS_ALL_R			0U
+#define XHC_USBSTS__ALL_L			12U
+#define XHC_USBSTS__ALL_R			0U
+#define XHC_USBSTS_DATAMASK			0x00001f1fU
+#define XHC_USBSTS_RDWRMASK			0xffffe0e0U
+#define XHC_USBSTS_RESETVALUE			0x0801U
+
+#define XHC_PAGESIZE_OFFSET			0x028U
+#define XHC_PAGESIZE_BASE			0x028U
+#define XHC_PAGESIZE__reserved_L		31U
+#define XHC_PAGESIZE__reserved_R		16U
+#define XHC_PAGESIZE__reserved_WIDTH		16U
+#define XHC_PAGESIZE__reserved_RESETVALUE	0x0000U
+#define XHC_PAGESIZE__PS_L			15U
+#define XHC_PAGESIZE__PS_R			0U
+#define XHC_PAGESIZE__PS_WIDTH			16U
+#define XHC_PAGESIZE__PS_RESETVALUE		0x0000U
+#define XHC_PAGESIZE_WIDTH			32U
+#define XHC_PAGESIZE__WIDTH			32U
+#define XHC_PAGESIZE_ALL_L			31U
+#define XHC_PAGESIZE_ALL_R			0U
+#define XHC_PAGESIZE__ALL_L			31U
+#define XHC_PAGESIZE__ALL_R			0U
+#define XHC_PAGESIZE_DATAMASK			0xffffffffU
+#define XHC_PAGESIZE_RDWRMASK			0x00000000U
+#define XHC_PAGESIZE_RESETVALUE			0x00000000U
+
+#define XHC_DNCTRL_OFFSET			0x034U
+#define XHC_DNCTRL_BASE				0x034U
+#define XHC_DNCTRL__reserved_L			31U
+#define XHC_DNCTRL__reserved_R			16U
+#define XHC_DNCTRL__reserved_WIDTH		16U
+#define XHC_DNCTRL__reserved_RESETVALUE		0x0000U
+#define XHC_DNCTRL__DNE_L			15U
+#define XHC_DNCTRL__DNE_R			0U
+#define XHC_DNCTRL__DNE_WIDTH			16U
+#define XHC_DNCTRL__DNE_RESETVALUE		0x0000U
+#define XHC_DNCTRL_WIDTH			32U
+#define XHC_DNCTRL__WIDTH			32U
+#define XHC_DNCTRL_ALL_L			31U
+#define XHC_DNCTRL_ALL_R			0U
+#define XHC_DNCTRL__ALL_L			31U
+#define XHC_DNCTRL__ALL_R			0U
+#define XHC_DNCTRL_DATAMASK			0xffffffffU
+#define XHC_DNCTRL_RDWRMASK			0x00000000U
+#define XHC_DNCTRL_RESETVALUE			0x00000000U
+
+#define XHC_CRCRL_OFFSET			0x038U
+#define XHC_CRCRL_BASE				0x038U
+#define XHC_CRCRL__CRPL_L			31U
+#define XHC_CRCRL__CRPL_R			6U
+#define XHC_CRCRL__CRPL_WIDTH			26U
+#define XHC_CRCRL__CRPL_RESETVALUE		0x0U
+#define XHC_CRCRL__reserved_L			5U
+#define XHC_CRCRL__reserved_R			4U
+#define XHC_CRCRL__reserved_WIDTH		2U
+#define XHC_CRCRL__reserved_RESETVALUE		0x0U
+#define XHC_CRCRL__CRR				3U
+#define XHC_CRCRL__CRR_L			3U
+#define XHC_CRCRL__CRR_R			3U
+#define XHC_CRCRL__CRR_WIDTH			1U
+#define XHC_CRCRL__CRR_RESETVALUE		0x0U
+#define XHC_CRCRL__CA				2U
+#define XHC_CRCRL__CA_L				2U
+#define XHC_CRCRL__CA_R				2U
+#define XHC_CRCRL__CA_WIDTH			1U
+#define XHC_CRCRL__CA_RESETVALUE		0x0U
+#define XHC_CRCRL__CS				1U
+#define XHC_CRCRL__CS_L				1U
+#define XHC_CRCRL__CS_R				1U
+#define XHC_CRCRL__CS_WIDTH			1U
+#define XHC_CRCRL__CS_RESETVALUE		0x0U
+#define XHC_CRCRL__RCS				0U
+#define XHC_CRCRL__RCS_L			0U
+#define XHC_CRCRL__RCS_R			0U
+#define XHC_CRCRL__RCS_WIDTH			1U
+#define XHC_CRCRL__RCS_RESETVALUE		0x0U
+#define XHC_CRCRL_WIDTH				32U
+#define XHC_CRCRL__WIDTH			32U
+#define XHC_CRCRL_ALL_L				31U
+#define XHC_CRCRL_ALL_R				0U
+#define XHC_CRCRL__ALL_L			31U
+#define XHC_CRCRL__ALL_R			0U
+#define XHC_CRCRL_DATAMASK			0xffffffffU
+#define XHC_CRCRL_RDWRMASK			0x00000000U
+#define XHC_CRCRL_RESETVALUE			0x00000000U
+
+#define XHC_CRCRH_OFFSET			0x03cU
+#define XHC_CRCRH_BASE				0x03cU
+#define XHC_CRCRH__CRPH_L			31U
+#define XHC_CRCRH__CRPH_R			0U
+#define XHC_CRCRH__CRPH_WIDTH			32U
+#define XHC_CRCRH__CRPH_RESETVALUE		0x00000000U
+#define XHC_CRCRH_WIDTH				32U
+#define XHC_CRCRH__WIDTH			32U
+#define XHC_CRCRH_ALL_L				31U
+#define XHC_CRCRH_ALL_R				0U
+#define XHC_CRCRH__ALL_L			31U
+#define XHC_CRCRH__ALL_R			0U
+#define XHC_CRCRH_DATAMASK			0xffffffffU
+#define XHC_CRCRH_RDWRMASK			0x00000000U
+#define XHC_CRCRH_RESETVALUE			0x00000000U
+
+#define XHC_DCBAAPL_OFFSET			0x050U
+#define XHC_DCBAAPL_BASE			0x050U
+#define XHC_DCBAAPL__DCAL_L			31U
+#define XHC_DCBAAPL__DCAL_R			6U
+#define XHC_DCBAAPL__DCAL_WIDTH			26U
+#define XHC_DCBAAPL__DCAL_RESETVALUE		0x0U
+
+#define XHC_DCBAAPL__reserved_L			5U
+#define XHC_DCBAAPL__reserved_R			0U
+#define XHC_DCBAAPL__reserved_WIDTH		6U
+#define XHC_DCBAAPL__reserved_RESETVALUE	0x0U
+#define XHC_DCBAAPL_WIDTH			32U
+#define XHC_DCBAAPL__WIDTH			32U
+#define XHC_DCBAAPL_ALL_L			31U
+#define XHC_DCBAAPL_ALL_R			0U
+#define XHC_DCBAAPL__ALL_L			31U
+#define XHC_DCBAAPL__ALL_R			0U
+#define XHC_DCBAAPL_DATAMASK			0xffffffffU
+#define XHC_DCBAAPL_RDWRMASK			0x00000000U
+#define XHC_DCBAAPL_RESETVALUE			0x00000000U
+
+#define XHC_DCBAAPH_OFFSET			0x054U
+#define XHC_DCBAAPH_BASE			0x054U
+#define XHC_DCBAAPH__DCAH_L			31U
+#define XHC_DCBAAPH__DCAH_R			0U
+#define XHC_DCBAAPH__DCAH_WIDTH			32U
+#define XHC_DCBAAPH__DCAH_RESETVALUE		0x00000000U
+#define XHC_DCBAAPH_WIDTH			32U
+#define XHC_DCBAAPH__WIDTH			32U
+#define XHC_DCBAAPH_ALL_L			31U
+#define XHC_DCBAAPH_ALL_R			0U
+#define XHC_DCBAAPH__ALL_L			31U
+#define XHC_DCBAAPH__ALL_R			0U
+#define XHC_DCBAAPH_DATAMASK			0xffffffffU
+#define XHC_DCBAAPH_RDWRMASK			0x00000000U
+#define XHC_DCBAAPH_RESETVALUE			0x00000000U
+
+#define XHC_CONFIG_OFFSET			0x058U
+#define XHC_CONFIG_BASE				0x058U
+#define XHC_CONFIG__reserved_L			31U
+#define XHC_CONFIG__reserved_R			10U
+#define XHC_CONFIG__reserved_WIDTH		22U
+#define XHC_CONFIG__reserved_RESETVALUE		0x0U
+#define XHC_CONFIG__CIE				9U
+#define XHC_CONFIG__CIE_L			9U
+#define XHC_CONFIG__CIE_R			9U
+#define XHC_CONFIG__CIE_WIDTH			1U
+#define XHC_CONFIG__CIE_RESETVALUE		0x0U
+#define XHC_CONFIG__U3E				8U
+#define XHC_CONFIG__U3E_L			8U
+#define XHC_CONFIG__U3E_R			8U
+#define XHC_CONFIG__U3E_WIDTH			1U
+#define XHC_CONFIG__U3E_RESETVALUE		0x0U
+#define XHC_CONFIG__MSE_L			7U
+#define XHC_CONFIG__MSE_R			0U
+#define XHC_CONFIG__MSE_WIDTH			8U
+#define XHC_CONFIG__MSE_RESETVALUE		0x00U
+#define XHC_CONFIG_WIDTH			32U
+#define XHC_CONFIG__WIDTH			32U
+#define XHC_CONFIG_ALL_L			31U
+#define XHC_CONFIG_ALL_R			0U
+#define XHC_CONFIG__ALL_L			31U
+#define XHC_CONFIG__ALL_R			0U
+#define XHC_CONFIG_DATAMASK			0xffffffffU
+#define XHC_CONFIG_RDWRMASK			0x00000000U
+#define XHC_CONFIG_RESETVALUE			0x00000000U
+
+#define XHC_PORTSC1_OFFSET			0x420U
+#define XHC_PORTSC1_BASE			0x420U
+
+#define XHC_PORTSC1__WPR_L			31U
+#define XHC_PORTSC1__WPR_R			31U
+#define XHC_PORTSC1__WPR_WIDTH			1U
+#define XHC_PORTSC1__WPR_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__DNR_L			30U
+#define XHC_PORTSC1__DNR_R			30U
+#define XHC_PORTSC1__DNR_WIDTH			1U
+#define XHC_PORTSC1__DNR_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__WOE_L			27U
+#define XHC_PORTSC1__WOE_R			27U
+#define XHC_PORTSC1__WOE_WIDTH			1U
+#define XHC_PORTSC1__WOE_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__WDE_L			26U
+#define XHC_PORTSC1__WDE_R			26U
+#define XHC_PORTSC1__WDE_WIDTH			1U
+#define XHC_PORTSC1__WDE_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__WCE_L			25U
+#define XHC_PORTSC1__WCE_R			25U
+#define XHC_PORTSC1__WCE_WIDTH			1U
+#define XHC_PORTSC1__WCE_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__CAS_L			24U
+#define XHC_PORTSC1__CAS_R			24U
+#define XHC_PORTSC1__CAS_WIDTH			1U
+#define XHC_PORTSC1__CAS_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__CEC_L			23U
+#define XHC_PORTSC1__CEC_R			23U
+#define XHC_PORTSC1__CEC_WIDTH			1U
+#define XHC_PORTSC1__CEC_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__PLC_L			22U
+#define XHC_PORTSC1__PLC_R			22U
+#define XHC_PORTSC1__PLC_WIDTH			1U
+#define XHC_PORTSC1__PLC_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__PRC_L			21U
+#define XHC_PORTSC1__PRC_R			21U
+#define XHC_PORTSC1__PRC_WIDTH			1U
+#define XHC_PORTSC1__PRC_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__OCC_L			20U
+#define XHC_PORTSC1__OCC_R			20U
+#define XHC_PORTSC1__OCC_WIDTH			1U
+#define XHC_PORTSC1__OCC_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__WRC_L			19U
+#define XHC_PORTSC1__WRC_R			19U
+#define XHC_PORTSC1__WRC_WIDTH			1U
+#define XHC_PORTSC1__WRC_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__PEC_L			18U
+#define XHC_PORTSC1__PEC_R			18U
+#define XHC_PORTSC1__PEC_WIDTH			1U
+#define XHC_PORTSC1__PEC_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__CSC_L			17U
+#define XHC_PORTSC1__CSC_R			17U
+#define XHC_PORTSC1__CSC_WIDTH			1U
+#define XHC_PORTSC1__CSC_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__LWS_L			16U
+#define XHC_PORTSC1__LWS_R			16U
+#define XHC_PORTSC1__LWS_WIDTH			1U
+#define XHC_PORTSC1__LWS_RESETVALUE		0x0U
+#define XHC_PORTSC1__PIC_L			15U
+#define XHC_PORTSC1__PIC_R			14U
+#define XHC_PORTSC1__PIC_WIDTH			2U
+#define XHC_PORTSC1__PIC_RESETVALUE		0x0U
+#define XHC_PORTSC1__PS_L			13U
+#define XHC_PORTSC1__PS_R			10U
+#define XHC_PORTSC1__PS_WIDTH			4U
+#define XHC_PORTSC1__PS_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__PP_L			9U
+#define XHC_PORTSC1__PP_R			9U
+#define XHC_PORTSC1__PP_WIDTH			1U
+#define XHC_PORTSC1__PP_RESETVALUE		0x0U
+#define XHC_PORTSC1__PLS_L			8U
+#define XHC_PORTSC1__PLS_R			5U
+#define XHC_PORTSC1__PLS_WIDTH			4U
+#define XHC_PORTSC1__PLS_RESETVALUE		0x5U
+
+#define XHC_PORTSC1__PRST_L			4U
+#define XHC_PORTSC1__PRST_R			4U
+#define XHC_PORTSC1__PRST_WIDTH			1U
+#define XHC_PORTSC1__PRST_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__OCA_L			3U
+#define XHC_PORTSC1__OCA_R			3U
+#define XHC_PORTSC1__OCA_WIDTH			1U
+#define XHC_PORTSC1__OCA_RESETVALUE		0x0U
+#define XHC_PORTSC1__reserved			2U
+#define XHC_PORTSC1__reserved_L			2U
+#define XHC_PORTSC1__reserved_R			2U
+#define XHC_PORTSC1__reserved_WIDTH		1U
+#define XHC_PORTSC1__reserved_RESETVALUE	0x0U
+
+#define XHC_PORTSC1__PED_L			1U
+#define XHC_PORTSC1__PED_R			1U
+#define XHC_PORTSC1__PED_WIDTH			1U
+#define XHC_PORTSC1__PED_RESETVALUE		0x0U
+
+#define XHC_PORTSC1__CCS_L			0U
+#define XHC_PORTSC1__CCS_R			0U
+#define XHC_PORTSC1__CCS_WIDTH			1U
+#define XHC_PORTSC1__CCS_RESETVALUE		0x0U
+#define XHC_PORTSC1__RESERVED_L			29U
+#define XHC_PORTSC1__RESERVED_R			28U
+#define XHC_PORTSC1_WIDTH			32U
+#define XHC_PORTSC1__WIDTH			32U
+#define XHC_PORTSC1_ALL_L			31U
+#define XHC_PORTSC1_ALL_R			0U
+#define XHC_PORTSC1__ALL_L			31U
+#define XHC_PORTSC1__ALL_R			0U
+#define XHC_PORTSC1_DATAMASK			0xcfffffffU
+#define XHC_PORTSC1_RDWRMASK			0x30000000U
+#define XHC_PORTSC1_RESETVALUE			0x000000a0U
+
+#define XHC_PORTPM1_OFFSET			0x424U
+#define XHC_PORTPM1_BASE			0x424U
+#define XHC_PORTPM1__reserved_L			31U
+#define XHC_PORTPM1__reserved_R			17U
+#define XHC_PORTPM1__reserved_WIDTH		15U
+#define XHC_PORTPM1__reserved_RESETVALUE	0x0U
+#define XHC_PORTPM1__FLA			16U
+#define XHC_PORTPM1__FLA_L			16U
+#define XHC_PORTPM1__FLA_R			16U
+#define XHC_PORTPM1__FLA_WIDTH			1U
+#define XHC_PORTPM1__FLA_RESETVALUE		0x0U
+#define XHC_PORTPM1__U2T_L			15U
+#define XHC_PORTPM1__U2T_R			8U
+#define XHC_PORTPM1__U2T_WIDTH			8U
+#define XHC_PORTPM1__U2T_RESETVALUE		0x00U
+#define XHC_PORTPM1__U1T_L			7U
+#define XHC_PORTPM1__U1T_R			0U
+#define XHC_PORTPM1__U1T_WIDTH			8U
+#define XHC_PORTPM1__U1T_RESETVALUE		0x00U
+#define XHC_PORTPM1_WIDTH			32U
+#define XHC_PORTPM1__WIDTH			32U
+#define XHC_PORTPM1_ALL_L			31U
+#define XHC_PORTPM1_ALL_R			0U
+#define XHC_PORTPM1__ALL_L			31U
+#define XHC_PORTPM1__ALL_R			0U
+#define XHC_PORTPM1_DATAMASK			0xffffffffU
+#define XHC_PORTPM1_RDWRMASK			0x00000000U
+#define XHC_PORTPM1_RESETVALUE			0x00000000U
+
+#define XHC_PORTLC1_OFFSET			0x428U
+#define XHC_PORTLC1_BASE			0x428U
+#define XHC_PORTLC1__reserved_L			31U
+#define XHC_PORTLC1__reserved_R			0U
+#define XHC_PORTLC1__reserved_WIDTH		32U
+#define XHC_PORTLC1__reserved_RESETVALUE	0x00000000U
+#define XHC_PORTLC1_WIDTH			32U
+#define XHC_PORTLC1__WIDTH			32U
+#define XHC_PORTLC1_ALL_L			31U
+#define XHC_PORTLC1_ALL_R			0U
+#define XHC_PORTLC1__ALL_L			31U
+#define XHC_PORTLC1__ALL_R			0U
+#define XHC_PORTLC1_DATAMASK			0xffffffffU
+#define XHC_PORTLC1_RDWRMASK			0x00000000U
+#define XHC_PORTLC1_RESETVALUE			0x00000000U
+
+#define XHC_PORTSC2_OFFSET			0x430U
+#define XHC_PORTSC2_BASE			0x430U
+#define XHC_PORTSC2__WPR			31U
+#define XHC_PORTSC2__WPR_L			31U
+#define XHC_PORTSC2__WPR_R			31U
+#define XHC_PORTSC2__WPR_WIDTH			1U
+#define XHC_PORTSC2__WPR_RESETVALUE		0x0U
+#define XHC_PORTSC2__DNR			30U
+#define XHC_PORTSC2__DNR_L			30U
+#define XHC_PORTSC2__DNR_R			30U
+#define XHC_PORTSC2__DNR_WIDTH			1U
+#define XHC_PORTSC2__DNR_RESETVALUE		0x0U
+#define XHC_PORTSC2__WOE			27U
+#define XHC_PORTSC2__WOE_L			27U
+#define XHC_PORTSC2__WOE_R			27U
+#define XHC_PORTSC2__WOE_WIDTH			1U
+#define XHC_PORTSC2__WOE_RESETVALUE		0x0U
+#define XHC_PORTSC2__WDE			26U
+#define XHC_PORTSC2__WDE_L			26U
+#define XHC_PORTSC2__WDE_R			26U
+#define XHC_PORTSC2__WDE_WIDTH			1U
+#define XHC_PORTSC2__WDE_RESETVALUE		0x0U
+#define XHC_PORTSC2__WCE			25U
+#define XHC_PORTSC2__WCE_L			25U
+#define XHC_PORTSC2__WCE_R			25U
+#define XHC_PORTSC2__WCE_WIDTH			1U
+#define XHC_PORTSC2__WCE_RESETVALUE		0x0U
+#define XHC_PORTSC2__CAS			24U
+#define XHC_PORTSC2__CAS_L			24U
+#define XHC_PORTSC2__CAS_R			24U
+#define XHC_PORTSC2__CAS_WIDTH			1U
+#define XHC_PORTSC2__CAS_RESETVALUE		0x0U
+#define XHC_PORTSC2__CEC			23U
+#define XHC_PORTSC2__CEC_L			23U
+#define XHC_PORTSC2__CEC_R			23U
+#define XHC_PORTSC2__CEC_WIDTH			1U
+#define XHC_PORTSC2__CEC_RESETVALUE		0x0U
+#define XHC_PORTSC2__PLC			22U
+#define XHC_PORTSC2__PLC_L			22U
+#define XHC_PORTSC2__PLC_R			22U
+#define XHC_PORTSC2__PLC_WIDTH			1U
+#define XHC_PORTSC2__PLC_RESETVALUE		0x0U
+#define XHC_PORTSC2__PRC			21U
+#define XHC_PORTSC2__PRC_L			21U
+#define XHC_PORTSC2__PRC_R			21U
+#define XHC_PORTSC2__PRC_WIDTH			1U
+#define XHC_PORTSC2__PRC_RESETVALUE		0x0U
+#define XHC_PORTSC2__OCC			20U
+#define XHC_PORTSC2__OCC_L			20U
+#define XHC_PORTSC2__OCC_R			20U
+#define XHC_PORTSC2__OCC_WIDTH			1U
+#define XHC_PORTSC2__OCC_RESETVALUE		0x0U
+#define XHC_PORTSC2__WRC			19U
+#define XHC_PORTSC2__WRC_L			19U
+#define XHC_PORTSC2__WRC_R			19U
+#define XHC_PORTSC2__WRC_WIDTH			1U
+#define XHC_PORTSC2__WRC_RESETVALUE		0x0U
+#define XHC_PORTSC2__PEC			18U
+#define XHC_PORTSC2__PEC_L			18U
+#define XHC_PORTSC2__PEC_R			18U
+#define XHC_PORTSC2__PEC_WIDTH			1U
+#define XHC_PORTSC2__PEC_RESETVALUE		0x0U
+#define XHC_PORTSC2__CSC			17U
+#define XHC_PORTSC2__CSC_L			17U
+#define XHC_PORTSC2__CSC_R			17U
+#define XHC_PORTSC2__CSC_WIDTH			1U
+#define XHC_PORTSC2__CSC_RESETVALUE		0x0U
+#define XHC_PORTSC2__LWS			16U
+#define XHC_PORTSC2__LWS_L			16U
+#define XHC_PORTSC2__LWS_R			16U
+#define XHC_PORTSC2__LWS_WIDTH			1U
+#define XHC_PORTSC2__LWS_RESETVALUE		0x0U
+#define XHC_PORTSC2__PIC_L			15U
+#define XHC_PORTSC2__PIC_R			14U
+#define XHC_PORTSC2__PIC_WIDTH			2U
+#define XHC_PORTSC2__PIC_RESETVALUE		0x0U
+#define XHC_PORTSC2__PS_L			13U
+#define XHC_PORTSC2__PS_R			10U
+#define XHC_PORTSC2__PS_WIDTH			4U
+#define XHC_PORTSC2__PS_RESETVALUE		0x0U
+#define XHC_PORTSC2__PP				9U
+#define XHC_PORTSC2__PP_L			9U
+#define XHC_PORTSC2__PP_R			9U
+#define XHC_PORTSC2__PP_WIDTH			1U
+#define XHC_PORTSC2__PP_RESETVALUE		0x0U
+#define XHC_PORTSC2__PLS_L			8U
+#define XHC_PORTSC2__PLS_R			5U
+#define XHC_PORTSC2__PLS_WIDTH			4U
+#define XHC_PORTSC2__PLS_RESETVALUE		0x5U
+
+#define XHC_PORTSC2__PRST_L			4U
+#define XHC_PORTSC2__PRST_R			4U
+#define XHC_PORTSC2__PRST_WIDTH			1U
+#define XHC_PORTSC2__PRST_RESETVALUE		0x0U
+#define XHC_PORTSC2__OCA			3U
+#define XHC_PORTSC2__OCA_L			3U
+#define XHC_PORTSC2__OCA_R			3U
+#define XHC_PORTSC2__OCA_WIDTH			1U
+#define XHC_PORTSC2__OCA_RESETVALUE		0x0U
+#define XHC_PORTSC2__reserved			2U
+#define XHC_PORTSC2__reserved_L			2U
+#define XHC_PORTSC2__reserved_R			2U
+#define XHC_PORTSC2__reserved_WIDTH		1U
+#define XHC_PORTSC2__reserved_RESETVALUE	0x0U
+#define XHC_PORTSC2__PED			1U
+#define XHC_PORTSC2__PED_L			1U
+#define XHC_PORTSC2__PED_R			1U
+#define XHC_PORTSC2__PED_WIDTH			1U
+#define XHC_PORTSC2__PED_RESETVALUE		0x0U
+#define XHC_PORTSC2__CCS			0U
+#define XHC_PORTSC2__CCS_L			0U
+#define XHC_PORTSC2__CCS_R			0U
+#define XHC_PORTSC2__CCS_WIDTH			1U
+#define XHC_PORTSC2__CCS_RESETVALUE		0x0U
+#define XHC_PORTSC2__RESERVED_L			29U
+#define XHC_PORTSC2__RESERVED_R			28U
+#define XHC_PORTSC2_WIDTH			32U
+#define XHC_PORTSC2__WIDTH			32U
+#define XHC_PORTSC2_ALL_L			31U
+#define XHC_PORTSC2_ALL_R			0U
+#define XHC_PORTSC2__ALL_L			31U
+#define XHC_PORTSC2__ALL_R			0U
+#define XHC_PORTSC2_DATAMASK			0xcfffffffU
+#define XHC_PORTSC2_RDWRMASK			0x30000000U
+#define XHC_PORTSC2_RESETVALUE			0x000000a0U
+
+#define XHC_PORTPM2_OFFSET			0x434U
+#define XHC_PORTPM2_BASE			0x434U
+#define XHC_PORTPM2__PTC_L			31U
+#define XHC_PORTPM2__PTC_R			28U
+#define XHC_PORTPM2__PTC_WIDTH			4U
+#define XHC_PORTPM2__PTC_RESETVALUE		0x0U
+#define XHC_PORTPM2__reserved_L			27U
+#define XHC_PORTPM2__reserved_R			17U
+#define XHC_PORTPM2__reserved_WIDTH		11U
+#define XHC_PORTPM2__reserved_RESETVALUE	0x0U
+#define XHC_PORTPM2__HLE			16U
+#define XHC_PORTPM2__HLE_L			16U
+#define XHC_PORTPM2__HLE_R			16U
+#define XHC_PORTPM2__HLE_WIDTH			1U
+#define XHC_PORTPM2__HLE_RESETVALUE		0x0U
+#define XHC_PORTPM2__L1DS_L			15U
+#define XHC_PORTPM2__L1DS_R			8U
+#define XHC_PORTPM2__L1DS_WIDTH			8U
+#define XHC_PORTPM2__L1DS_RESETVALUE		0x00U
+#define XHC_PORTPM2__BESL_L			7U
+#define XHC_PORTPM2__BESL_R			4U
+#define XHC_PORTPM2__BESL_WIDTH			4U
+#define XHC_PORTPM2__BESL_RESETVALUE		0x0U
+#define XHC_PORTPM2__RWE			3U
+#define XHC_PORTPM2__RWE_L			3U
+#define XHC_PORTPM2__RWE_R			3U
+#define XHC_PORTPM2__RWE_WIDTH			1U
+#define XHC_PORTPM2__RWE_RESETVALUE		0x0U
+#define XHC_PORTPM2__L1S_L			2U
+#define XHC_PORTPM2__L1S_R			0U
+#define XHC_PORTPM2__L1S_WIDTH			3U
+#define XHC_PORTPM2__L1S_RESETVALUE		0x0U
+#define XHC_PORTPM2_WIDTH			32U
+#define XHC_PORTPM2__WIDTH			32U
+#define XHC_PORTPM2_ALL_L			31U
+#define XHC_PORTPM2_ALL_R			0U
+#define XHC_PORTPM2__ALL_L			31U
+#define XHC_PORTPM2__ALL_R			0U
+#define XHC_PORTPM2_DATAMASK			0xffffffffU
+#define XHC_PORTPM2_RDWRMASK			0x00000000U
+#define XHC_PORTPM2_RESETVALUE			0x00000000U
+
+#define XHC_PORTLC2_OFFSET			0x43cU
+#define XHC_PORTLC2_BASE			0x43cU
+#define XHC_PORTLC2__reserved_L			31U
+#define XHC_PORTLC2__reserved_R			14U
+#define XHC_PORTLC2__reserved_WIDTH		18U
+#define XHC_PORTLC2__reserved_RESETVALUE	0x0U
+#define XHC_PORTLC2__BESLD_L			13U
+#define XHC_PORTLC2__BESLD_R			10U
+#define XHC_PORTLC2__BESLD_WIDTH		4U
+#define XHC_PORTLC2__BESLD_RESETVALUE		0x0U
+#define XHC_PORTLC2__L1T_L			9U
+#define XHC_PORTLC2__L1T_R			2U
+#define XHC_PORTLC2__L1T_WIDTH			8U
+#define XHC_PORTLC2__L1T_RESETVALUE		0x00U
+#define XHC_PORTLC2__HIRDM_L			1U
+#define XHC_PORTLC2__HIRDM_R			0U
+#define XHC_PORTLC2__HIRDM_WIDTH		2U
+#define XHC_PORTLC2__HIRDM_RESETVALUE		0x0U
+#define XHC_PORTLC2_WIDTH			32U
+#define XHC_PORTLC2__WIDTH			32U
+#define XHC_PORTLC2_ALL_L			31U
+#define XHC_PORTLC2_ALL_R			0U
+#define XHC_PORTLC2__ALL_L			31U
+#define XHC_PORTLC2__ALL_R			0U
+#define XHC_PORTLC2_DATAMASK			0xffffffffU
+#define XHC_PORTLC2_RDWRMASK			0x00000000U
+#define XHC_PORTLC2_RESETVALUE			0x00000000U
+
+#define XHC_PORTSC3_OFFSET			0x440U
+#define XHC_PORTSC3_BASE			0x440U
+#define XHC_PORTSC3__WPR			31U
+#define XHC_PORTSC3__WPR_L			31U
+#define XHC_PORTSC3__WPR_R			31U
+#define XHC_PORTSC3__WPR_WIDTH			1U
+#define XHC_PORTSC3__WPR_RESETVALUE		0x0U
+#define XHC_PORTSC3__DNR			30U
+#define XHC_PORTSC3__DNR_L			30U
+#define XHC_PORTSC3__DNR_R			30U
+#define XHC_PORTSC3__DNR_WIDTH			1U
+#define XHC_PORTSC3__DNR_RESETVALUE		0x0U
+#define XHC_PORTSC3__WOE			27U
+#define XHC_PORTSC3__WOE_L			27U
+#define XHC_PORTSC3__WOE_R			27U
+#define XHC_PORTSC3__WOE_WIDTH			1U
+#define XHC_PORTSC3__WOE_RESETVALUE		0x0U
+#define XHC_PORTSC3__WDE			26U
+#define XHC_PORTSC3__WDE_L			26U
+#define XHC_PORTSC3__WDE_R			26U
+#define XHC_PORTSC3__WDE_WIDTH			1U
+#define XHC_PORTSC3__WDE_RESETVALUE		0x0U
+#define XHC_PORTSC3__WCE			25U
+#define XHC_PORTSC3__WCE_L			25U
+#define XHC_PORTSC3__WCE_R			25U
+#define XHC_PORTSC3__WCE_WIDTH			1U
+#define XHC_PORTSC3__WCE_RESETVALUE		0x0U
+#define XHC_PORTSC3__CAS			24U
+#define XHC_PORTSC3__CAS_L			24U
+#define XHC_PORTSC3__CAS_R			24U
+#define XHC_PORTSC3__CAS_WIDTH			1U
+#define XHC_PORTSC3__CAS_RESETVALUE		0x0U
+#define XHC_PORTSC3__CEC			23U
+#define XHC_PORTSC3__CEC_L			23U
+#define XHC_PORTSC3__CEC_R			23U
+#define XHC_PORTSC3__CEC_WIDTH			1U
+#define XHC_PORTSC3__CEC_RESETVALUE		0x0U
+#define XHC_PORTSC3__PLC			22U
+#define XHC_PORTSC3__PLC_L			22U
+#define XHC_PORTSC3__PLC_R			22U
+#define XHC_PORTSC3__PLC_WIDTH			1U
+#define XHC_PORTSC3__PLC_RESETVALUE		0x0U
+#define XHC_PORTSC3__PRC			21U
+#define XHC_PORTSC3__PRC_L			21U
+#define XHC_PORTSC3__PRC_R			21U
+#define XHC_PORTSC3__PRC_WIDTH			1U
+#define XHC_PORTSC3__PRC_RESETVALUE		0x0U
+#define XHC_PORTSC3__OCC			20U
+#define XHC_PORTSC3__OCC_L			20U
+#define XHC_PORTSC3__OCC_R			20U
+#define XHC_PORTSC3__OCC_WIDTH			1U
+#define XHC_PORTSC3__OCC_RESETVALUE		0x0U
+#define XHC_PORTSC3__WRC			19U
+#define XHC_PORTSC3__WRC_L			19U
+#define XHC_PORTSC3__WRC_R			19U
+#define XHC_PORTSC3__WRC_WIDTH			1U
+#define XHC_PORTSC3__WRC_RESETVALUE		0x0U
+#define XHC_PORTSC3__PEC			18U
+#define XHC_PORTSC3__PEC_L			18U
+#define XHC_PORTSC3__PEC_R			18U
+#define XHC_PORTSC3__PEC_WIDTH			1U
+#define XHC_PORTSC3__PEC_RESETVALUE		0x0U
+#define XHC_PORTSC3__CSC			17U
+#define XHC_PORTSC3__CSC_L			17U
+#define XHC_PORTSC3__CSC_R			17U
+#define XHC_PORTSC3__CSC_WIDTH			1U
+#define XHC_PORTSC3__CSC_RESETVALUE		0x0U
+#define XHC_PORTSC3__LWS			16U
+#define XHC_PORTSC3__LWS_L			16U
+#define XHC_PORTSC3__LWS_R			16U
+#define XHC_PORTSC3__LWS_WIDTH			1U
+#define XHC_PORTSC3__LWS_RESETVALUE		0x0U
+#define XHC_PORTSC3__PIC_L			15U
+#define XHC_PORTSC3__PIC_R			14U
+#define XHC_PORTSC3__PIC_WIDTH			2U
+#define XHC_PORTSC3__PIC_RESETVALUE		0x0U
+#define XHC_PORTSC3__PS_L			13U
+#define XHC_PORTSC3__PS_R			10U
+#define XHC_PORTSC3__PS_WIDTH			4U
+#define XHC_PORTSC3__PS_RESETVALUE		0x0U
+#define XHC_PORTSC3__PP				9U
+#define XHC_PORTSC3__PP_L			9U
+#define XHC_PORTSC3__PP_R			9U
+#define XHC_PORTSC3__PP_WIDTH			1U
+#define XHC_PORTSC3__PP_RESETVALUE		0x0U
+#define XHC_PORTSC3__PLS_L			8U
+#define XHC_PORTSC3__PLS_R			5U
+#define XHC_PORTSC3__PLS_WIDTH			4U
+#define XHC_PORTSC3__PLS_RESETVALUE		0x5U
+#define XHC_PORTSC3__PR				4U
+#define XHC_PORTSC3__PR_L			4U
+#define XHC_PORTSC3__PR_R			4U
+#define XHC_PORTSC3__PR_WIDTH			1U
+#define XHC_PORTSC3__PR_RESETVALUE		0x0U
+#define XHC_PORTSC3__OCA			3U
+#define XHC_PORTSC3__OCA_L			3U
+#define XHC_PORTSC3__OCA_R			3U
+#define XHC_PORTSC3__OCA_WIDTH			1U
+#define XHC_PORTSC3__OCA_RESETVALUE		0x0U
+#define XHC_PORTSC3__reserved			2U
+#define XHC_PORTSC3__reserved_L			2U
+#define XHC_PORTSC3__reserved_R			2U
+#define XHC_PORTSC3__reserved_WIDTH		1U
+#define XHC_PORTSC3__reserved_RESETVALUE	0x0U
+#define XHC_PORTSC3__PED			1U
+#define XHC_PORTSC3__PED_L			1U
+#define XHC_PORTSC3__PED_R			1U
+#define XHC_PORTSC3__PED_WIDTH			1U
+#define XHC_PORTSC3__PED_RESETVALUE		0x0U
+#define XHC_PORTSC3__CCS			0U
+#define XHC_PORTSC3__CCS_L			0U
+#define XHC_PORTSC3__CCS_R			0U
+#define XHC_PORTSC3__CCS_WIDTH			1U
+#define XHC_PORTSC3__CCS_RESETVALUE		0x0U
+#define XHC_PORTSC3__RESERVED_L			29U
+#define XHC_PORTSC3__RESERVED_R			28U
+#define XHC_PORTSC3_WIDTH			32U
+#define XHC_PORTSC3__WIDTH			32U
+#define XHC_PORTSC3_ALL_L			31U
+#define XHC_PORTSC3_ALL_R			0U
+#define XHC_PORTSC3__ALL_L			31U
+#define XHC_PORTSC3__ALL_R			0U
+#define XHC_PORTSC3_DATAMASK			0xcfffffffU
+#define XHC_PORTSC3_RDWRMASK			0x30000000U
+#define XHC_PORTSC3_RESETVALUE			0x000000a0U
+
+#define XHC_PORTPM3_OFFSET			0x444U
+#define XHC_PORTPM3_BASE			0x444U
+#define XHC_PORTPM3__PTC_L			31U
+#define XHC_PORTPM3__PTC_R			28U
+#define XHC_PORTPM3__PTC_WIDTH			4U
+#define XHC_PORTPM3__PTC_RESETVALUE		0x0U
+#define XHC_PORTPM3__reserved_L			27U
+#define XHC_PORTPM3__reserved_R			17U
+#define XHC_PORTPM3__reserved_WIDTH		11U
+#define XHC_PORTPM3__reserved_RESETVALUE	0x0U
+#define XHC_PORTPM3__HLE			16U
+#define XHC_PORTPM3__HLE_L			16U
+#define XHC_PORTPM3__HLE_R			16U
+#define XHC_PORTPM3__HLE_WIDTH			1U
+#define XHC_PORTPM3__HLE_RESETVALUE		0x0U
+#define XHC_PORTPM3__L1DS_L			15U
+#define XHC_PORTPM3__L1DS_R			8U
+#define XHC_PORTPM3__L1DS_WIDTH			8U
+#define XHC_PORTPM3__L1DS_RESETVALUE		0x00U
+#define XHC_PORTPM3__BESL_L			7U
+#define XHC_PORTPM3__BESL_R			4U
+#define XHC_PORTPM3__BESL_WIDTH			4U
+#define XHC_PORTPM3__BESL_RESETVALUE		0x0U
+#define XHC_PORTPM3__RWE			3U
+#define XHC_PORTPM3__RWE_L			3U
+#define XHC_PORTPM3__RWE_R			3U
+#define XHC_PORTPM3__RWE_WIDTH			1U
+#define XHC_PORTPM3__RWE_RESETVALUE		0x0U
+#define XHC_PORTPM3__L1S_L			2U
+#define XHC_PORTPM3__L1S_R			0U
+#define XHC_PORTPM3__L1S_WIDTH			3U
+#define XHC_PORTPM3__L1S_RESETVALUE		0x0U
+#define XHC_PORTPM3_WIDTH			32U
+#define XHC_PORTPM3__WIDTH			32U
+#define XHC_PORTPM3_ALL_L			31U
+#define XHC_PORTPM3_ALL_R			0U
+#define XHC_PORTPM3__ALL_L			31U
+#define XHC_PORTPM3__ALL_R			0U
+#define XHC_PORTPM3_DATAMASK			0xffffffffU
+#define XHC_PORTPM3_RDWRMASK			0x00000000U
+#define XHC_PORTPM3_RESETVALUE			0x00000000U
+
+#define XHC_PORTLI3_OFFSET			0x44cU
+#define XHC_PORTLI3_BASE			0x44cU
+#define XHC_PORTLI3__reserved_L			31U
+#define XHC_PORTLI3__reserved_R			0U
+#define XHC_PORTLI3__reserved_WIDTH		32U
+#define XHC_PORTLI3__reserved_RESETVALUE	0x00000000U
+#define XHC_PORTLI3_WIDTH			32U
+#define XHC_PORTLI3__WIDTH			32U
+#define XHC_PORTLI3_ALL_L			31U
+#define XHC_PORTLI3_ALL_R			0U
+#define XHC_PORTLI3__ALL_L			31U
+#define XHC_PORTLI3__ALL_R			0U
+#define XHC_PORTLI3_DATAMASK			0xffffffffU
+#define XHC_PORTLI3_RDWRMASK			0x00000000U
+#define XHC_PORTLI3_RESETVALUE			0x00000000U
+
+#define XHC_MFINDEX_OFFSET			0x4a0U
+#define XHC_MFINDEX_BASE			0x4a0U
+#define XHC_MFINDEX__reserved_L			31U
+#define XHC_MFINDEX__reserved_R			14U
+#define XHC_MFINDEX__reserved_WIDTH		18U
+#define XHC_MFINDEX__reserved_RESETVALUE	0x0U
+#define XHC_MFINDEX__MFI_L			13U
+#define XHC_MFINDEX__MFI_R			0U
+#define XHC_MFINDEX__MFI_WIDTH			14U
+#define XHC_MFINDEX__MFI_RESETVALUE		0x0U
+#define XHC_MFINDEX_WIDTH			32U
+#define XHC_MFINDEX__WIDTH			32U
+#define XHC_MFINDEX_ALL_L			31U
+#define XHC_MFINDEX_ALL_R			0U
+#define XHC_MFINDEX__ALL_L			31U
+#define XHC_MFINDEX__ALL_R			0U
+#define XHC_MFINDEX_DATAMASK			0xffffffffU
+#define XHC_MFINDEX_RDWRMASK			0x00000000U
+#define XHC_MFINDEX_RESETVALUE			0x00000000U
+
+#define XHC_IMAN0_OFFSET			0x4c0U
+#define XHC_IMAN0_BASE				0x4c0U
+#define XHC_IMAN0__reserved_L			31U
+#define XHC_IMAN0__reserved_R			2U
+#define XHC_IMAN0__reserved_WIDTH		30U
+#define XHC_IMAN0__reserved_RESETVALUE		0x0U
+#define XHC_IMAN0__IE				1U
+#define XHC_IMAN0__IE_L				1U
+#define XHC_IMAN0__IE_R				1U
+#define XHC_IMAN0__IE_WIDTH			1U
+#define XHC_IMAN0__IE_RESETVALUE		0x0U
+#define XHC_IMAN0__IP				0U
+#define XHC_IMAN0__IP_L				0U
+#define XHC_IMAN0__IP_R				0U
+#define XHC_IMAN0__IP_WIDTH			1U
+#define XHC_IMAN0__IP_RESETVALUE		0x0U
+#define XHC_IMAN0_WIDTH				32U
+#define XHC_IMAN0__WIDTH			32U
+#define XHC_IMAN0_ALL_L				31U
+#define XHC_IMAN0_ALL_R				0U
+#define XHC_IMAN0__ALL_L			31U
+#define XHC_IMAN0__ALL_R			0U
+#define XHC_IMAN0_DATAMASK			0xffffffffU
+#define XHC_IMAN0_RDWRMASK			0x00000000U
+#define XHC_IMAN0_RESETVALUE			0x00000000U
+
+#define XHC_IMOD0_OFFSET			0x4c4U
+#define XHC_IMOD0_BASE				0x4c4U
+#define XHC_IMOD0__IMODC_L			31U
+#define XHC_IMOD0__IMODC_R			16U
+#define XHC_IMOD0__IMODC_WIDTH			16U
+#define XHC_IMOD0__IMODC_RESETVALUE		0x0000U
+#define XHC_IMOD0__IMODI_L			15U
+#define XHC_IMOD0__IMODI_R			0U
+#define XHC_IMOD0__IMODI_WIDTH			16U
+#define XHC_IMOD0__IMODI_RESETVALUE		0x4000U
+#define XHC_IMOD0_WIDTH				32U
+#define XHC_IMOD0__WIDTH			32U
+#define XHC_IMOD0_ALL_L				31U
+#define XHC_IMOD0_ALL_R				0U
+#define XHC_IMOD0__ALL_L			31U
+#define XHC_IMOD0__ALL_R			0U
+#define XHC_IMOD0_DATAMASK			0xffffffffU
+#define XHC_IMOD0_RDWRMASK			0x00000000U
+#define XHC_IMOD0_RESETVALUE			0x00004000U
+
+#define XHC_ERSTSZ0_OFFSET			0x4c8U
+#define XHC_ERSTSZ0_BASE			0x4c8U
+#define XHC_ERSTSZ0__reserved_L			31U
+#define XHC_ERSTSZ0__reserved_R			16U
+#define XHC_ERSTSZ0__reserved_WIDTH		16U
+#define XHC_ERSTSZ0__reserved_RESETVALUE	0x0000U
+#define XHC_ERSTSZ0__TSZ_L			15U
+#define XHC_ERSTSZ0__TSZ_R			0U
+#define XHC_ERSTSZ0__TSZ_WIDTH			16U
+#define XHC_ERSTSZ0__TSZ_RESETVALUE		0x0000U
+#define XHC_ERSTSZ0_WIDTH			32U
+#define XHC_ERSTSZ0__WIDTH			32U
+#define XHC_ERSTSZ0_ALL_L			31U
+#define XHC_ERSTSZ0_ALL_R			0U
+#define XHC_ERSTSZ0__ALL_L			31U
+#define XHC_ERSTSZ0__ALL_R			0U
+#define XHC_ERSTSZ0_DATAMASK			0xffffffffU
+#define XHC_ERSTSZ0_RDWRMASK			0x00000000U
+#define XHC_ERSTSZ0_RESETVALUE			0x00000000U
+
+#define XHC_ERSTBAL0_OFFSET			0x4d0U
+#define XHC_ERSTBAL0_BASE			0x4d0U
+#define XHC_ERSTBAL0__BAL_L			31U
+#define XHC_ERSTBAL0__BAL_R			4U
+#define XHC_ERSTBAL0__BAL_WIDTH			28U
+#define XHC_ERSTBAL0__BAL_RESETVALUE		0x0000000U
+#define XHC_ERSTBAL0__reserved_L		3U
+#define XHC_ERSTBAL0__reserved_R		0U
+#define XHC_ERSTBAL0__reserved_WIDTH		4U
+#define XHC_ERSTBAL0__reserved_RESETVALUE	0x0U
+#define XHC_ERSTBAL0_WIDTH			32U
+#define XHC_ERSTBAL0__WIDTH			32U
+#define XHC_ERSTBAL0_ALL_L			31U
+#define XHC_ERSTBAL0_ALL_R			0U
+#define XHC_ERSTBAL0__ALL_L			31U
+#define XHC_ERSTBAL0__ALL_R			0U
+#define XHC_ERSTBAL0_DATAMASK			0xffffffffU
+#define XHC_ERSTBAL0_RDWRMASK			0x00000000U
+#define XHC_ERSTBAL0_RESETVALUE			0x00000000U
+
+#define XHC_ERSTBAH0_OFFSET			0x4d4U
+#define XHC_ERSTBAH0_BASE			0x4d4U
+#define XHC_ERSTBAH0__BAH_L			31U
+#define XHC_ERSTBAH0__BAH_R			0U
+#define XHC_ERSTBAH0__BAH_WIDTH			32U
+#define XHC_ERSTBAH0__BAH_RESETVALUE		0x00000000U
+#define XHC_ERSTBAH0_WIDTH			32U
+#define XHC_ERSTBAH0__WIDTH			32U
+#define XHC_ERSTBAH0_ALL_L			31U
+#define XHC_ERSTBAH0_ALL_R			0U
+#define XHC_ERSTBAH0__ALL_L			31U
+#define XHC_ERSTBAH0__ALL_R			0U
+#define XHC_ERSTBAH0_DATAMASK			0xffffffffU
+#define XHC_ERSTBAH0_RDWRMASK			0x00000000U
+#define XHC_ERSTBAH0_RESETVALUE			0x00000000U
+
+#define XHC_ERDPL0_OFFSET			0x4d8U
+#define XHC_ERDPL0_BASE				0x4d8U
+#define XHC_ERDPL0__DPL_L			31U
+#define XHC_ERDPL0__DPL_R			4U
+#define XHC_ERDPL0__DPL_WIDTH			28U
+#define XHC_ERDPL0__DPL_RESETVALUE		0x0000000U
+#define XHC_ERDPL0__EHB				3U
+#define XHC_ERDPL0__EHB_L			3U
+#define XHC_ERDPL0__EHB_R			3U
+#define XHC_ERDPL0__EHB_WIDTH			1U
+#define XHC_ERDPL0__EHB_RESETVALUE		0x0U
+#define XHC_ERDPL0__DESI_L			2U
+#define XHC_ERDPL0__DESI_R			0U
+#define XHC_ERDPL0__DESI_WIDTH			3U
+#define XHC_ERDPL0__DESI_RESETVALUE		0x0U
+#define XHC_ERDPL0_WIDTH			32U
+#define XHC_ERDPL0__WIDTH			32U
+#define XHC_ERDPL0_ALL_L			31U
+#define XHC_ERDPL0_ALL_R			0U
+#define XHC_ERDPL0__ALL_L			31U
+#define XHC_ERDPL0__ALL_R			0U
+#define XHC_ERDPL0_DATAMASK			0xffffffffU
+#define XHC_ERDPL0_RDWRMASK			0x00000000U
+#define XHC_ERDPL0_RESETVALUE			0x00000000U
+
+#define XHC_ERDPH0_OFFSET			0x4dcU
+#define XHC_ERDPH0_BASE				0x4dcU
+#define XHC_ERDPH0__DPH_L			31U
+#define XHC_ERDPH0__DPH_R			0U
+#define XHC_ERDPH0__DPH_WIDTH			32U
+#define XHC_ERDPH0__DPH_RESETVALUE		0x00000000U
+#define XHC_ERDPH0_WIDTH			32U
+#define XHC_ERDPH0__WIDTH			32U
+#define XHC_ERDPH0_ALL_L			31U
+#define XHC_ERDPH0_ALL_R			0U
+#define XHC_ERDPH0__ALL_L			31U
+#define XHC_ERDPH0__ALL_R			0U
+#define XHC_ERDPH0_DATAMASK			0xffffffffU
+#define XHC_ERDPH0_RDWRMASK			0x00000000U
+#define XHC_ERDPH0_RESETVALUE			0x00000000U
+
+#define XHC_IMAN1_OFFSET			0x4e0U
+#define XHC_IMAN1_BASE				0x4e0U
+#define XHC_IMAN1__reserved_L			31U
+#define XHC_IMAN1__reserved_R			2U
+#define XHC_IMAN1__reserved_WIDTH		30U
+#define XHC_IMAN1__reserved_RESETVALUE		0x0U
+#define XHC_IMAN1__IE				1U
+#define XHC_IMAN1__IE_L				1U
+#define XHC_IMAN1__IE_R				1U
+#define XHC_IMAN1__IE_WIDTH			1U
+#define XHC_IMAN1__IE_RESETVALUE		0x0U
+#define XHC_IMAN1__IP				0U
+#define XHC_IMAN1__IP_L				0U
+#define XHC_IMAN1__IP_R				0U
+#define XHC_IMAN1__IP_WIDTH			1U
+#define XHC_IMAN1__IP_RESETVALUE		0x0U
+#define XHC_IMAN1_WIDTH				32U
+#define XHC_IMAN1__WIDTH			32U
+#define XHC_IMAN1_ALL_L				31U
+#define XHC_IMAN1_ALL_R				0U
+#define XHC_IMAN1__ALL_L			31U
+#define XHC_IMAN1__ALL_R			0U
+#define XHC_IMAN1_DATAMASK			0xffffffffU
+#define XHC_IMAN1_RDWRMASK			0x00000000U
+#define XHC_IMAN1_RESETVALUE			0x00000000U
+
+#define XHC_IMOD1_OFFSET			0x4e4U
+#define XHC_IMOD1_BASE				0x4e4U
+#define XHC_IMOD1__IMODC_L			31U
+#define XHC_IMOD1__IMODC_R			16U
+#define XHC_IMOD1__IMODC_WIDTH			16U
+#define XHC_IMOD1__IMODC_RESETVALUE		0x0000U
+#define XHC_IMOD1__IMODI_L			15U
+#define XHC_IMOD1__IMODI_R			0U
+#define XHC_IMOD1__IMODI_WIDTH			16U
+#define XHC_IMOD1__IMODI_RESETVALUE		0x4000U
+#define XHC_IMOD1_WIDTH				32U
+#define XHC_IMOD1__WIDTH			32U
+#define XHC_IMOD1_ALL_L				31U
+#define XHC_IMOD1_ALL_R				0U
+#define XHC_IMOD1__ALL_L			31U
+#define XHC_IMOD1__ALL_R			0U
+#define XHC_IMOD1_DATAMASK			0xffffffffU
+#define XHC_IMOD1_RDWRMASK			0x00000000U
+#define XHC_IMOD1_RESETVALUE			0x00004000U
+
+#define XHC_ERSTSZ1_OFFSET			0x4e8U
+#define XHC_ERSTSZ1_BASE			0x4e8U
+#define XHC_ERSTSZ1__reserved_L			31U
+#define XHC_ERSTSZ1__reserved_R			16U
+#define XHC_ERSTSZ1__reserved_WIDTH		16U
+#define XHC_ERSTSZ1__reserved_RESETVALUE	0x0000U
+#define XHC_ERSTSZ1__TSZ_L			15U
+#define XHC_ERSTSZ1__TSZ_R			0U
+#define XHC_ERSTSZ1__TSZ_WIDTH			16U
+#define XHC_ERSTSZ1__TSZ_RESETVALUE		0x0000U
+#define XHC_ERSTSZ1_WIDTH			32U
+#define XHC_ERSTSZ1__WIDTH			32U
+#define XHC_ERSTSZ1_ALL_L			31U
+#define XHC_ERSTSZ1_ALL_R			0U
+#define XHC_ERSTSZ1__ALL_L			31U
+#define XHC_ERSTSZ1__ALL_R			0U
+#define XHC_ERSTSZ1_DATAMASK			0xffffffffU
+#define XHC_ERSTSZ1_RDWRMASK			0x00000000U
+#define XHC_ERSTSZ1_RESETVALUE			0x00000000U
+
+#define XHC_ERSTBAL1_OFFSET			0x4f0U
+#define XHC_ERSTBAL1_BASE			0x4f0U
+#define XHC_ERSTBAL1__BAL_L			31U
+#define XHC_ERSTBAL1__BAL_R			4U
+#define XHC_ERSTBAL1__BAL_WIDTH			28U
+#define XHC_ERSTBAL1__BAL_RESETVALUE		0x0000000U
+#define XHC_ERSTBAL1__reserved_L		3U
+#define XHC_ERSTBAL1__reserved_R		0U
+#define XHC_ERSTBAL1__reserved_WIDTH		4U
+#define XHC_ERSTBAL1__reserved_RESETVALUE	0x0U
+#define XHC_ERSTBAL1_WIDTH			32U
+#define XHC_ERSTBAL1__WIDTH			32U
+#define XHC_ERSTBAL1_ALL_L			31U
+#define XHC_ERSTBAL1_ALL_R			0U
+#define XHC_ERSTBAL1__ALL_L			31U
+#define XHC_ERSTBAL1__ALL_R			0U
+#define XHC_ERSTBAL1_DATAMASK			0xffffffffU
+#define XHC_ERSTBAL1_RDWRMASK			0x00000000U
+#define XHC_ERSTBAL1_RESETVALUE			0x00000000U
+
+#define XHC_ERSTBAH1_OFFSET			0x4f4U
+#define XHC_ERSTBAH1_BASE			0x4f4U
+#define XHC_ERSTBAH1__BAH_L			31U
+#define XHC_ERSTBAH1__BAH_R			0U
+#define XHC_ERSTBAH1__BAH_WIDTH			32U
+#define XHC_ERSTBAH1__BAH_RESETVALUE		0x00000000U
+#define XHC_ERSTBAH1_WIDTH			32U
+#define XHC_ERSTBAH1__WIDTH			32U
+#define XHC_ERSTBAH1_ALL_L			31U
+#define XHC_ERSTBAH1_ALL_R			0U
+#define XHC_ERSTBAH1__ALL_L			31U
+#define XHC_ERSTBAH1__ALL_R			0U
+#define XHC_ERSTBAH1_DATAMASK			0xffffffffU
+#define XHC_ERSTBAH1_RDWRMASK			0x00000000U
+#define XHC_ERSTBAH1_RESETVALUE			0x00000000U
+
+#define XHC_ERDPL1_OFFSET			0x4f8U
+#define XHC_ERDPL1_BASE				0x4f8U
+#define XHC_ERDPL1__DPL_L			31U
+#define XHC_ERDPL1__DPL_R			4U
+#define XHC_ERDPL1__DPL_WIDTH			28U
+#define XHC_ERDPL1__DPL_RESETVALUE		0x0000000U
+#define XHC_ERDPL1__EHB				3U
+#define XHC_ERDPL1__EHB_L			3U
+#define XHC_ERDPL1__EHB_R			3U
+#define XHC_ERDPL1__EHB_WIDTH			1U
+#define XHC_ERDPL1__EHB_RESETVALUE		0x0U
+#define XHC_ERDPL1__DESI_L			2U
+#define XHC_ERDPL1__DESI_R			0U
+#define XHC_ERDPL1__DESI_WIDTH			3U
+#define XHC_ERDPL1__DESI_RESETVALUE		0x0U
+#define XHC_ERDPL1_WIDTH			32U
+#define XHC_ERDPL1__WIDTH			32U
+#define XHC_ERDPL1_ALL_L			31U
+#define XHC_ERDPL1_ALL_R			0U
+#define XHC_ERDPL1__ALL_L			31U
+#define XHC_ERDPL1__ALL_R			0U
+#define XHC_ERDPL1_DATAMASK			0xffffffffU
+#define XHC_ERDPL1_RDWRMASK			0x00000000U
+#define XHC_ERDPL1_RESETVALUE			0x00000000U
+
+#define XHC_ERDPH1_OFFSET			0x4fcU
+#define XHC_ERDPH1_BASE				0x4fcU
+#define XHC_ERDPH1__DPH_L			31U
+#define XHC_ERDPH1__DPH_R			0U
+#define XHC_ERDPH1__DPH_WIDTH			32U
+#define XHC_ERDPH1__DPH_RESETVALUE		0x00000000U
+#define XHC_ERDPH1_WIDTH			32U
+#define XHC_ERDPH1__WIDTH			32U
+#define XHC_ERDPH1_ALL_L			31U
+#define XHC_ERDPH1_ALL_R			0U
+#define XHC_ERDPH1__ALL_L			31U
+#define XHC_ERDPH1__ALL_R			0U
+#define XHC_ERDPH1_DATAMASK			0xffffffffU
+#define XHC_ERDPH1_RDWRMASK			0x00000000U
+#define XHC_ERDPH1_RESETVALUE			0x00000000U
+
+#define XHC_DBLCMD_OFFSET			0x8c0U
+#define XHC_DBLCMD_BASE				0x8c0U
+#define XHC_DBLCMD__SID_L			31U
+#define XHC_DBLCMD__SID_R			16U
+#define XHC_DBLCMD__SID_WIDTH			16U
+#define XHC_DBLCMD__SID_RESETVALUE		0x0000U
+#define XHC_DBLCMD__reserved_L			15U
+#define XHC_DBLCMD__reserved_R			8U
+#define XHC_DBLCMD__reserved_WIDTH		8U
+#define XHC_DBLCMD__reserved_RESETVALUE		0x00U
+#define XHC_DBLCMD__TGT_L			7U
+#define XHC_DBLCMD__TGT_R			0U
+#define XHC_DBLCMD__TGT_WIDTH			8U
+#define XHC_DBLCMD__TGT_RESETVALUE		0x00U
+#define XHC_DBLCMD_WIDTH			32U
+#define XHC_DBLCMD__WIDTH			32U
+#define XHC_DBLCMD_ALL_L			31U
+#define XHC_DBLCMD_ALL_R			0U
+#define XHC_DBLCMD__ALL_L			31U
+#define XHC_DBLCMD__ALL_R			0U
+#define XHC_DBLCMD_DATAMASK			0xffffffffU
+#define XHC_DBLCMD_RDWRMASK			0x00000000U
+#define XHC_DBLCMD_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX1_OFFSET			0x8c4U
+#define XHC_DBLDVX1_BASE			0x8c4U
+#define XHC_DBLDVX1__SID_L			31U
+#define XHC_DBLDVX1__SID_R			16U
+#define XHC_DBLDVX1__SID_WIDTH			16U
+#define XHC_DBLDVX1__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX1__reserved_L			15U
+#define XHC_DBLDVX1__reserved_R			8U
+#define XHC_DBLDVX1__reserved_WIDTH		8U
+#define XHC_DBLDVX1__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX1__TGT_L			7U
+#define XHC_DBLDVX1__TGT_R			0U
+#define XHC_DBLDVX1__TGT_WIDTH			8U
+#define XHC_DBLDVX1__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX1_WIDTH			32U
+#define XHC_DBLDVX1__WIDTH			32U
+#define XHC_DBLDVX1_ALL_L			31U
+#define XHC_DBLDVX1_ALL_R			0U
+#define XHC_DBLDVX1__ALL_L			31U
+#define XHC_DBLDVX1__ALL_R			0U
+#define XHC_DBLDVX1_DATAMASK			0xffffffffU
+#define XHC_DBLDVX1_RDWRMASK			0x00000000U
+#define XHC_DBLDVX1_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX2_OFFSET			0x8c8U
+#define XHC_DBLDVX2_BASE			0x8c8U
+#define XHC_DBLDVX2__SID_L			31U
+#define XHC_DBLDVX2__SID_R			16U
+#define XHC_DBLDVX2__SID_WIDTH			16U
+#define XHC_DBLDVX2__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX2__reserved_L			15U
+#define XHC_DBLDVX2__reserved_R			8U
+#define XHC_DBLDVX2__reserved_WIDTH		8U
+#define XHC_DBLDVX2__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX2__TGT_L			7U
+#define XHC_DBLDVX2__TGT_R			0U
+#define XHC_DBLDVX2__TGT_WIDTH			8U
+#define XHC_DBLDVX2__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX2_WIDTH			32U
+#define XHC_DBLDVX2__WIDTH			32U
+#define XHC_DBLDVX2_ALL_L			31U
+#define XHC_DBLDVX2_ALL_R			0U
+#define XHC_DBLDVX2__ALL_L			31U
+#define XHC_DBLDVX2__ALL_R			0U
+#define XHC_DBLDVX2_DATAMASK			0xffffffffU
+#define XHC_DBLDVX2_RDWRMASK			0x00000000U
+#define XHC_DBLDVX2_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX3_OFFSET			0x8ccU
+#define XHC_DBLDVX3_BASE			0x8ccU
+#define XHC_DBLDVX3__SID_L			31U
+#define XHC_DBLDVX3__SID_R			16U
+#define XHC_DBLDVX3__SID_WIDTH			16U
+#define XHC_DBLDVX3__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX3__reserved_L			15U
+#define XHC_DBLDVX3__reserved_R			8U
+#define XHC_DBLDVX3__reserved_WIDTH		8U
+#define XHC_DBLDVX3__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX3__TGT_L			7U
+#define XHC_DBLDVX3__TGT_R			0U
+#define XHC_DBLDVX3__TGT_WIDTH			8U
+#define XHC_DBLDVX3__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX3_WIDTH			32U
+#define XHC_DBLDVX3__WIDTH			32U
+#define XHC_DBLDVX3_ALL_L			31U
+#define XHC_DBLDVX3_ALL_R			0U
+#define XHC_DBLDVX3__ALL_L			31U
+#define XHC_DBLDVX3__ALL_R			0U
+#define XHC_DBLDVX3_DATAMASK			0xffffffffU
+#define XHC_DBLDVX3_RDWRMASK			0x00000000U
+#define XHC_DBLDVX3_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX4_OFFSET			0x8d0U
+#define XHC_DBLDVX4_BASE			0x8d0U
+#define XHC_DBLDVX4__SID_L			31U
+#define XHC_DBLDVX4__SID_R			16U
+#define XHC_DBLDVX4__SID_WIDTH			16U
+#define XHC_DBLDVX4__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX4__reserved_L			15U
+#define XHC_DBLDVX4__reserved_R			8U
+#define XHC_DBLDVX4__reserved_WIDTH		8U
+#define XHC_DBLDVX4__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX4__TGT_L			7U
+#define XHC_DBLDVX4__TGT_R			0U
+#define XHC_DBLDVX4__TGT_WIDTH			8U
+#define XHC_DBLDVX4__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX4_WIDTH			32U
+#define XHC_DBLDVX4__WIDTH			32U
+#define XHC_DBLDVX4_ALL_L			31U
+#define XHC_DBLDVX4_ALL_R			0U
+#define XHC_DBLDVX4__ALL_L			31U
+#define XHC_DBLDVX4__ALL_R			0U
+#define XHC_DBLDVX4_DATAMASK			0xffffffffU
+#define XHC_DBLDVX4_RDWRMASK			0x00000000U
+#define XHC_DBLDVX4_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX5_OFFSET			0x8d4U
+#define XHC_DBLDVX5_BASE			0x8d4U
+#define XHC_DBLDVX5__SID_L			31U
+#define XHC_DBLDVX5__SID_R			16U
+#define XHC_DBLDVX5__SID_WIDTH			16U
+#define XHC_DBLDVX5__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX5__reserved_L			15U
+#define XHC_DBLDVX5__reserved_R			8U
+#define XHC_DBLDVX5__reserved_WIDTH		8U
+#define XHC_DBLDVX5__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX5__TGT_L			7U
+#define XHC_DBLDVX5__TGT_R			0U
+#define XHC_DBLDVX5__TGT_WIDTH			8U
+#define XHC_DBLDVX5__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX5_WIDTH			32U
+#define XHC_DBLDVX5__WIDTH			32U
+#define XHC_DBLDVX5_ALL_L			31U
+#define XHC_DBLDVX5_ALL_R			0U
+#define XHC_DBLDVX5__ALL_L			31U
+#define XHC_DBLDVX5__ALL_R			0U
+#define XHC_DBLDVX5_DATAMASK			0xffffffffU
+#define XHC_DBLDVX5_RDWRMASK			0x00000000U
+#define XHC_DBLDVX5_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX6_OFFSET			0x8d8U
+#define XHC_DBLDVX6_BASE			0x8d8U
+#define XHC_DBLDVX6__SID_L			31U
+#define XHC_DBLDVX6__SID_R			16U
+#define XHC_DBLDVX6__SID_WIDTH			16U
+#define XHC_DBLDVX6__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX6__reserved_L			15U
+#define XHC_DBLDVX6__reserved_R			8U
+#define XHC_DBLDVX6__reserved_WIDTH		8U
+#define XHC_DBLDVX6__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX6__TGT_L			7U
+#define XHC_DBLDVX6__TGT_R			0U
+#define XHC_DBLDVX6__TGT_WIDTH			8U
+#define XHC_DBLDVX6__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX6_WIDTH			32U
+#define XHC_DBLDVX6__WIDTH			32U
+#define XHC_DBLDVX6_ALL_L			31U
+#define XHC_DBLDVX6_ALL_R			0U
+#define XHC_DBLDVX6__ALL_L			31U
+#define XHC_DBLDVX6__ALL_R			0U
+#define XHC_DBLDVX6_DATAMASK			0xffffffffU
+#define XHC_DBLDVX6_RDWRMASK			0x00000000U
+#define XHC_DBLDVX6_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX7_OFFSET			0x8dcU
+#define XHC_DBLDVX7_BASE			0x8dcU
+#define XHC_DBLDVX7__SID_L			31U
+#define XHC_DBLDVX7__SID_R			16U
+#define XHC_DBLDVX7__SID_WIDTH			16U
+#define XHC_DBLDVX7__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX7__reserved_L			15U
+#define XHC_DBLDVX7__reserved_R			8U
+#define XHC_DBLDVX7__reserved_WIDTH		8U
+#define XHC_DBLDVX7__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX7__TGT_L			7U
+#define XHC_DBLDVX7__TGT_R			0U
+#define XHC_DBLDVX7__TGT_WIDTH			8U
+#define XHC_DBLDVX7__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX7_WIDTH			32U
+#define XHC_DBLDVX7__WIDTH			32U
+#define XHC_DBLDVX7_ALL_L			31U
+#define XHC_DBLDVX7_ALL_R			0U
+#define XHC_DBLDVX7__ALL_L			31U
+#define XHC_DBLDVX7__ALL_R			0U
+#define XHC_DBLDVX7_DATAMASK			0xffffffffU
+#define XHC_DBLDVX7_RDWRMASK			0x00000000U
+#define XHC_DBLDVX7_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX8_OFFSET			0x8e0U
+#define XHC_DBLDVX8_BASE			0x8e0U
+#define XHC_DBLDVX8__SID_L			31U
+#define XHC_DBLDVX8__SID_R			16U
+#define XHC_DBLDVX8__SID_WIDTH			16U
+#define XHC_DBLDVX8__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX8__reserved_L			15U
+#define XHC_DBLDVX8__reserved_R			8U
+#define XHC_DBLDVX8__reserved_WIDTH		8U
+#define XHC_DBLDVX8__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX8__TGT_L			7U
+#define XHC_DBLDVX8__TGT_R			0U
+#define XHC_DBLDVX8__TGT_WIDTH			8U
+#define XHC_DBLDVX8__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX8_WIDTH			32U
+#define XHC_DBLDVX8__WIDTH			32U
+#define XHC_DBLDVX8_ALL_L			31U
+#define XHC_DBLDVX8_ALL_R			0U
+#define XHC_DBLDVX8__ALL_L			31U
+#define XHC_DBLDVX8__ALL_R			0U
+#define XHC_DBLDVX8_DATAMASK			0xffffffffU
+#define XHC_DBLDVX8_RDWRMASK			0x00000000U
+#define XHC_DBLDVX8_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX9_OFFSET			0x8e4U
+#define XHC_DBLDVX9_BASE			0x8e4U
+#define XHC_DBLDVX9__SID_L			31U
+#define XHC_DBLDVX9__SID_R			16U
+#define XHC_DBLDVX9__SID_WIDTH			16U
+#define XHC_DBLDVX9__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX9__reserved_L			15U
+#define XHC_DBLDVX9__reserved_R			8U
+#define XHC_DBLDVX9__reserved_WIDTH		8U
+#define XHC_DBLDVX9__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX9__TGT_L			7U
+#define XHC_DBLDVX9__TGT_R			0U
+#define XHC_DBLDVX9__TGT_WIDTH			8U
+#define XHC_DBLDVX9__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX9_WIDTH			32U
+#define XHC_DBLDVX9__WIDTH			32U
+#define XHC_DBLDVX9_ALL_L			31U
+#define XHC_DBLDVX9_ALL_R			0U
+#define XHC_DBLDVX9__ALL_L			31U
+#define XHC_DBLDVX9__ALL_R			0U
+#define XHC_DBLDVX9_DATAMASK			0xffffffffU
+#define XHC_DBLDVX9_RDWRMASK			0x00000000U
+#define XHC_DBLDVX9_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX10_OFFSET			0x8e8U
+#define XHC_DBLDVX10_BASE			0x8e8U
+#define XHC_DBLDVX10__SID_L			31U
+#define XHC_DBLDVX10__SID_R			16U
+#define XHC_DBLDVX10__SID_WIDTH			16U
+#define XHC_DBLDVX10__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX10__reserved_L		15U
+#define XHC_DBLDVX10__reserved_R		8U
+#define XHC_DBLDVX10__reserved_WIDTH		8U
+#define XHC_DBLDVX10__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX10__TGT_L			7U
+#define XHC_DBLDVX10__TGT_R			0U
+#define XHC_DBLDVX10__TGT_WIDTH			8U
+#define XHC_DBLDVX10__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX10_WIDTH			32U
+#define XHC_DBLDVX10__WIDTH			32U
+#define XHC_DBLDVX10_ALL_L			31U
+#define XHC_DBLDVX10_ALL_R			0U
+#define XHC_DBLDVX10__ALL_L			31U
+#define XHC_DBLDVX10__ALL_R			0U
+#define XHC_DBLDVX10_DATAMASK			0xffffffffU
+#define XHC_DBLDVX10_RDWRMASK			0x00000000U
+#define XHC_DBLDVX10_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX11_OFFSET			0x8ecU
+#define XHC_DBLDVX11_BASE			0x8ecU
+#define XHC_DBLDVX11__SID_L			31U
+#define XHC_DBLDVX11__SID_R			16U
+#define XHC_DBLDVX11__SID_WIDTH			16U
+#define XHC_DBLDVX11__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX11__reserved_L		15U
+#define XHC_DBLDVX11__reserved_R		8U
+#define XHC_DBLDVX11__reserved_WIDTH		8U
+#define XHC_DBLDVX11__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX11__TGT_L			7U
+#define XHC_DBLDVX11__TGT_R			0U
+#define XHC_DBLDVX11__TGT_WIDTH			8U
+#define XHC_DBLDVX11__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX11_WIDTH			32U
+#define XHC_DBLDVX11__WIDTH			32U
+#define XHC_DBLDVX11_ALL_L			31U
+#define XHC_DBLDVX11_ALL_R			0U
+#define XHC_DBLDVX11__ALL_L			31U
+#define XHC_DBLDVX11__ALL_R			0U
+#define XHC_DBLDVX11_DATAMASK			0xffffffffU
+#define XHC_DBLDVX11_RDWRMASK			0x00000000U
+#define XHC_DBLDVX11_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX12_OFFSET			0x8f0U
+#define XHC_DBLDVX12_BASE			0x8f0U
+#define XHC_DBLDVX12__SID_L			31U
+#define XHC_DBLDVX12__SID_R			16U
+#define XHC_DBLDVX12__SID_WIDTH			16U
+#define XHC_DBLDVX12__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX12__reserved_L		15U
+#define XHC_DBLDVX12__reserved_R		8U
+#define XHC_DBLDVX12__reserved_WIDTH		8U
+#define XHC_DBLDVX12__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX12__TGT_L			7U
+#define XHC_DBLDVX12__TGT_R			0U
+#define XHC_DBLDVX12__TGT_WIDTH			8U
+#define XHC_DBLDVX12__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX12_WIDTH			32U
+#define XHC_DBLDVX12__WIDTH			32U
+#define XHC_DBLDVX12_ALL_L			31U
+#define XHC_DBLDVX12_ALL_R			0U
+#define XHC_DBLDVX12__ALL_L			31U
+#define XHC_DBLDVX12__ALL_R			0U
+#define XHC_DBLDVX12_DATAMASK			0xffffffffU
+#define XHC_DBLDVX12_RDWRMASK			0x00000000U
+#define XHC_DBLDVX12_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX13_OFFSET			0x8f4U
+#define XHC_DBLDVX13_BASE			0x8f4U
+#define XHC_DBLDVX13__SID_L			31U
+#define XHC_DBLDVX13__SID_R			16U
+#define XHC_DBLDVX13__SID_WIDTH			16U
+#define XHC_DBLDVX13__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX13__reserved_L		15U
+#define XHC_DBLDVX13__reserved_R		8U
+#define XHC_DBLDVX13__reserved_WIDTH		8U
+#define XHC_DBLDVX13__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX13__TGT_L			7U
+#define XHC_DBLDVX13__TGT_R			0U
+#define XHC_DBLDVX13__TGT_WIDTH			8U
+#define XHC_DBLDVX13__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX13_WIDTH			32U
+#define XHC_DBLDVX13__WIDTH			32U
+#define XHC_DBLDVX13_ALL_L			31U
+#define XHC_DBLDVX13_ALL_R			0U
+#define XHC_DBLDVX13__ALL_L			31U
+#define XHC_DBLDVX13__ALL_R			0U
+#define XHC_DBLDVX13_DATAMASK			0xffffffffU
+#define XHC_DBLDVX13_RDWRMASK			0x00000000U
+#define XHC_DBLDVX13_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX14_OFFSET			0x8f8U
+#define XHC_DBLDVX14_BASE			0x8f8U
+#define XHC_DBLDVX14__SID_L			31U
+#define XHC_DBLDVX14__SID_R			16U
+#define XHC_DBLDVX14__SID_WIDTH			16U
+#define XHC_DBLDVX14__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX14__reserved_L		15U
+#define XHC_DBLDVX14__reserved_R		8U
+#define XHC_DBLDVX14__reserved_WIDTH		8U
+#define XHC_DBLDVX14__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX14__TGT_L			7U
+#define XHC_DBLDVX14__TGT_R			0U
+#define XHC_DBLDVX14__TGT_WIDTH			8U
+#define XHC_DBLDVX14__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX14_WIDTH			32U
+#define XHC_DBLDVX14__WIDTH			32U
+#define XHC_DBLDVX14_ALL_L			31U
+#define XHC_DBLDVX14_ALL_R			0U
+#define XHC_DBLDVX14__ALL_L			31U
+#define XHC_DBLDVX14__ALL_R			0U
+#define XHC_DBLDVX14_DATAMASK			0xffffffffU
+#define XHC_DBLDVX14_RDWRMASK			0x00000000U
+#define XHC_DBLDVX14_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX15_OFFSET			0x8fcU
+#define XHC_DBLDVX15_BASE			0x8fcU
+#define XHC_DBLDVX15__SID_L			31U
+#define XHC_DBLDVX15__SID_R			16U
+#define XHC_DBLDVX15__SID_WIDTH			16U
+#define XHC_DBLDVX15__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX15__reserved_L		15U
+#define XHC_DBLDVX15__reserved_R		8U
+#define XHC_DBLDVX15__reserved_WIDTH		8U
+#define XHC_DBLDVX15__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX15__TGT_L			7U
+#define XHC_DBLDVX15__TGT_R			0U
+#define XHC_DBLDVX15__TGT_WIDTH			8U
+#define XHC_DBLDVX15__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX15_WIDTH			32U
+#define XHC_DBLDVX15__WIDTH			32U
+#define XHC_DBLDVX15_ALL_L			31U
+#define XHC_DBLDVX15_ALL_R			0U
+#define XHC_DBLDVX15__ALL_L			31U
+#define XHC_DBLDVX15__ALL_R			0U
+#define XHC_DBLDVX15_DATAMASK			0xffffffffU
+#define XHC_DBLDVX15_RDWRMASK			0x00000000U
+#define XHC_DBLDVX15_RESETVALUE			0x00000000U
+
+#define XHC_DBLDVX16_OFFSET			0x900U
+#define XHC_DBLDVX16_BASE			0x900U
+#define XHC_DBLDVX16__SID_L			31U
+#define XHC_DBLDVX16__SID_R			16U
+#define XHC_DBLDVX16__SID_WIDTH			16U
+#define XHC_DBLDVX16__SID_RESETVALUE		0x0000U
+#define XHC_DBLDVX16__reserved_L		15U
+#define XHC_DBLDVX16__reserved_R		8U
+#define XHC_DBLDVX16__reserved_WIDTH		8U
+#define XHC_DBLDVX16__reserved_RESETVALUE	0x00U
+#define XHC_DBLDVX16__TGT_L			7U
+#define XHC_DBLDVX16__TGT_R			0U
+#define XHC_DBLDVX16__TGT_WIDTH			8U
+#define XHC_DBLDVX16__TGT_RESETVALUE		0x00U
+#define XHC_DBLDVX16_WIDTH			32U
+#define XHC_DBLDVX16__WIDTH			32U
+#define XHC_DBLDVX16_ALL_L			31U
+#define XHC_DBLDVX16_ALL_R			0U
+#define XHC_DBLDVX16__ALL_L			31U
+#define XHC_DBLDVX16__ALL_R			0U
+#define XHC_DBLDVX16_DATAMASK			0xffffffffU
+#define XHC_DBLDVX16_RDWRMASK			0x00000000U
+#define XHC_DBLDVX16_RESETVALUE			0x00000000U
+
+#define XHC_ECHSPT3_OFFSET			0x940U
+#define XHC_ECHSPT3_BASE			0x940U
+#define XHC_ECHSPT3__RMAJ_L			31U
+#define XHC_ECHSPT3__RMAJ_R			24U
+#define XHC_ECHSPT3__RMAJ_WIDTH			8U
+#define XHC_ECHSPT3__RMAJ_RESETVALUE		0x00U
+#define XHC_ECHSPT3__RMIN_L			23U
+#define XHC_ECHSPT3__RMIN_R			16U
+#define XHC_ECHSPT3__RMIN_WIDTH			8U
+#define XHC_ECHSPT3__RMIN_RESETVALUE		0x00U
+#define XHC_ECHSPT3__NCP_L			15U
+#define XHC_ECHSPT3__NCP_R			8U
+#define XHC_ECHSPT3__NCP_WIDTH			8U
+#define XHC_ECHSPT3__NCP_RESETVALUE		0x00U
+#define XHC_ECHSPT3__CID_L			7U
+#define XHC_ECHSPT3__CID_R			0U
+#define XHC_ECHSPT3__CID_WIDTH			8U
+#define XHC_ECHSPT3__CID_RESETVALUE		0x02U
+#define XHC_ECHSPT3_WIDTH			32U
+#define XHC_ECHSPT3__WIDTH			32U
+#define XHC_ECHSPT3_ALL_L			31U
+#define XHC_ECHSPT3_ALL_R			0U
+#define XHC_ECHSPT3__ALL_L			31U
+#define XHC_ECHSPT3__ALL_R			0U
+#define XHC_ECHSPT3_DATAMASK			0xffffffffU
+#define XHC_ECHSPT3_RDWRMASK			0x00000000U
+#define XHC_ECHSPT3_RESETVALUE			0x00000002U
+
+#define XHC_PNSTR3_OFFSET			0x944U
+#define XHC_PNSTR3_BASE				0x944U
+#define XHC_PNSTR3__STR_L			31U
+#define XHC_PNSTR3__STR_R			0U
+#define XHC_PNSTR3__STR_WIDTH			32U
+#define XHC_PNSTR3__STR_RESETVALUE		0x20425355U
+#define XHC_PNSTR3_WIDTH			32U
+#define XHC_PNSTR3__WIDTH			32U
+#define XHC_PNSTR3_ALL_L			31U
+#define XHC_PNSTR3_ALL_R			0U
+#define XHC_PNSTR3__ALL_L			31U
+#define XHC_PNSTR3__ALL_R			0U
+#define XHC_PNSTR3_DATAMASK			0xffffffffU
+#define XHC_PNSTR3_RDWRMASK			0x00000000U
+#define XHC_PNSTR3_RESETVALUE			0x20425355U
+
+#define XHC_PSUM3_OFFSET			0x948U
+#define XHC_PSUM3_BASE				0x948U
+#define XHC_PSUM3__PSIC_L			31U
+#define XHC_PSUM3__PSIC_R			28U
+#define XHC_PSUM3__PSIC_WIDTH			4U
+#define XHC_PSUM3__PSIC_RESETVALUE		0x0U
+#define XHC_PSUM3__MHD_L			27U
+#define XHC_PSUM3__MHD_R			25U
+#define XHC_PSUM3__MHD_WIDTH			3U
+#define XHC_PSUM3__MHD_RESETVALUE		0x0U
+#define XHC_PSUM3__BLC				20U
+#define XHC_PSUM3__BLC_L			20U
+#define XHC_PSUM3__BLC_R			20U
+#define XHC_PSUM3__BLC_WIDTH			1U
+#define XHC_PSUM3__BLC_RESETVALUE		0x0U
+#define XHC_PSUM3__HLC				19U
+#define XHC_PSUM3__HLC_L			19U
+#define XHC_PSUM3__HLC_R			19U
+#define XHC_PSUM3__HLC_WIDTH			1U
+#define XHC_PSUM3__HLC_RESETVALUE		0x1U
+#define XHC_PSUM3__IHI				18U
+#define XHC_PSUM3__IHI_L			18U
+#define XHC_PSUM3__IHI_R			18U
+#define XHC_PSUM3__IHI_WIDTH			1U
+#define XHC_PSUM3__IHI_RESETVALUE		0x0U
+#define XHC_PSUM3__HSO				17U
+#define XHC_PSUM3__HSO_L			17U
+#define XHC_PSUM3__HSO_R			17U
+#define XHC_PSUM3__HSO_WIDTH			1U
+#define XHC_PSUM3__HSO_RESETVALUE		0x0U
+#define XHC_PSUM3__reserved			16U
+#define XHC_PSUM3__reserved_L			16U
+#define XHC_PSUM3__reserved_R			16U
+#define XHC_PSUM3__reserved_WIDTH		1U
+#define XHC_PSUM3__reserved_RESETVALUE		0x0U
+#define XHC_PSUM3__CPC_L			15U
+#define XHC_PSUM3__CPC_R			8U
+#define XHC_PSUM3__CPC_WIDTH			8U
+#define XHC_PSUM3__CPC_RESETVALUE		0x00U
+#define XHC_PSUM3__CPO_L			7U
+#define XHC_PSUM3__CPO_R			0U
+#define XHC_PSUM3__CPO_WIDTH			8U
+#define XHC_PSUM3__CPO_RESETVALUE		0x00U
+#define XHC_PSUM3__RESERVED_L			24U
+#define XHC_PSUM3__RESERVED_R			21U
+#define XHC_PSUM3_WIDTH				32U
+#define XHC_PSUM3__WIDTH			32U
+#define XHC_PSUM3_ALL_L				31U
+#define XHC_PSUM3_ALL_R				0U
+#define XHC_PSUM3__ALL_L			31U
+#define XHC_PSUM3__ALL_R			0U
+#define XHC_PSUM3_DATAMASK			0xfe1fffffU
+#define XHC_PSUM3_RDWRMASK			0x01e00000U
+#define XHC_PSUM3_RESETVALUE			0x00080000U
+
+#define XHC_PTSLTYP3_OFFSET			0x94cU
+#define XHC_PTSLTYP3_BASE			0x94cU
+#define XHC_PTSLTYP3__reserved_L		31U
+#define XHC_PTSLTYP3__reserved_R		5U
+#define XHC_PTSLTYP3__reserved_WIDTH		27U
+#define XHC_PTSLTYP3__reserved_RESETVALUE	0x0U
+#define XHC_PTSLTYP3__PST_L			4U
+#define XHC_PTSLTYP3__PST_R			0U
+#define XHC_PTSLTYP3__PST_WIDTH			5U
+#define XHC_PTSLTYP3__PST_RESETVALUE		0x0U
+#define XHC_PTSLTYP3_WIDTH			32U
+#define XHC_PTSLTYP3__WIDTH			32U
+#define XHC_PTSLTYP3_ALL_L			31U
+#define XHC_PTSLTYP3_ALL_R			0U
+#define XHC_PTSLTYP3__ALL_L			31U
+#define XHC_PTSLTYP3__ALL_R			0U
+#define XHC_PTSLTYP3_DATAMASK			0xffffffffU
+#define XHC_PTSLTYP3_RDWRMASK			0x00000000U
+#define XHC_PTSLTYP3_RESETVALUE			0x00000000U
+
+#define XHC_ECHSPT2_OFFSET			0x950U
+#define XHC_ECHSPT2_BASE			0x950U
+#define XHC_ECHSPT2__RMAJ_L			31U
+#define XHC_ECHSPT2__RMAJ_R			24U
+#define XHC_ECHSPT2__RMAJ_WIDTH			8U
+#define XHC_ECHSPT2__RMAJ_RESETVALUE		0x00U
+#define XHC_ECHSPT2__RMIN_L			23U
+#define XHC_ECHSPT2__RMIN_R			16U
+#define XHC_ECHSPT2__RMIN_WIDTH			8U
+#define XHC_ECHSPT2__RMIN_RESETVALUE		0x00U
+#define XHC_ECHSPT2__NCP_L			15U
+#define XHC_ECHSPT2__NCP_R			8U
+#define XHC_ECHSPT2__NCP_WIDTH			8U
+#define XHC_ECHSPT2__NCP_RESETVALUE		0x00U
+#define XHC_ECHSPT2__CID_L			7U
+#define XHC_ECHSPT2__CID_R			0U
+#define XHC_ECHSPT2__CID_WIDTH			8U
+#define XHC_ECHSPT2__CID_RESETVALUE		0x02U
+#define XHC_ECHSPT2_WIDTH			32U
+#define XHC_ECHSPT2__WIDTH			32U
+#define XHC_ECHSPT2_ALL_L			31U
+#define XHC_ECHSPT2_ALL_R			0U
+#define XHC_ECHSPT2__ALL_L			31U
+#define XHC_ECHSPT2__ALL_R			0U
+#define XHC_ECHSPT2_DATAMASK			0xffffffffU
+#define XHC_ECHSPT2_RDWRMASK			0x00000000U
+#define XHC_ECHSPT2_RESETVALUE			0x00000002U
+
+#define XHC_PNSTR2_OFFSET			0x954U
+#define XHC_PNSTR2_BASE				0x954U
+#define XHC_PNSTR2__STR_L			31U
+#define XHC_PNSTR2__STR_R			0U
+#define XHC_PNSTR2__STR_WIDTH			32U
+#define XHC_PNSTR2__STR_RESETVALUE		0x20425355U
+#define XHC_PNSTR2_WIDTH			32U
+#define XHC_PNSTR2__WIDTH			32U
+#define XHC_PNSTR2_ALL_L			31U
+#define XHC_PNSTR2_ALL_R			0U
+#define XHC_PNSTR2__ALL_L			31U
+#define XHC_PNSTR2__ALL_R			0U
+#define XHC_PNSTR2_DATAMASK			0xffffffffU
+#define XHC_PNSTR2_RDWRMASK			0x00000000U
+#define XHC_PNSTR2_RESETVALUE			0x20425355U
+
+#define XHC_PSUM2_OFFSET			0x958U
+#define XHC_PSUM2_BASE				0x958U
+#define XHC_PSUM2__PSIC_L			31U
+#define XHC_PSUM2__PSIC_R			28U
+#define XHC_PSUM2__PSIC_WIDTH			4U
+#define XHC_PSUM2__PSIC_RESETVALUE		0x0U
+#define XHC_PSUM2__MHD_L			27U
+#define XHC_PSUM2__MHD_R			25U
+#define XHC_PSUM2__MHD_WIDTH			3U
+#define XHC_PSUM2__MHD_RESETVALUE		0x0U
+#define XHC_PSUM2__BLC				20U
+#define XHC_PSUM2__BLC_L			20U
+#define XHC_PSUM2__BLC_R			20U
+#define XHC_PSUM2__BLC_WIDTH			1U
+#define XHC_PSUM2__BLC_RESETVALUE		0x0U
+#define XHC_PSUM2__HLC				19U
+#define XHC_PSUM2__HLC_L			19U
+#define XHC_PSUM2__HLC_R			19U
+#define XHC_PSUM2__HLC_WIDTH			1U
+#define XHC_PSUM2__HLC_RESETVALUE		0x1U
+#define XHC_PSUM2__IHI				18U
+#define XHC_PSUM2__IHI_L			18U
+#define XHC_PSUM2__IHI_R			18U
+#define XHC_PSUM2__IHI_WIDTH			1U
+#define XHC_PSUM2__IHI_RESETVALUE		0x0U
+#define XHC_PSUM2__HSO				17U
+#define XHC_PSUM2__HSO_L			17U
+#define XHC_PSUM2__HSO_R			17U
+#define XHC_PSUM2__HSO_WIDTH			1U
+#define XHC_PSUM2__HSO_RESETVALUE		0x0U
+#define XHC_PSUM2__reserved			16U
+#define XHC_PSUM2__reserved_L			16U
+#define XHC_PSUM2__reserved_R			16U
+#define XHC_PSUM2__reserved_WIDTH		1U
+#define XHC_PSUM2__reserved_RESETVALUE		0x0U
+#define XHC_PSUM2__CPC_L			15U
+#define XHC_PSUM2__CPC_R			8U
+#define XHC_PSUM2__CPC_WIDTH			8U
+#define XHC_PSUM2__CPC_RESETVALUE		0x00U
+#define XHC_PSUM2__CPO_L			7U
+#define XHC_PSUM2__CPO_R			0U
+#define XHC_PSUM2__CPO_WIDTH			8U
+#define XHC_PSUM2__CPO_RESETVALUE		0x00U
+#define XHC_PSUM2__RESERVED_L			24U
+#define XHC_PSUM2__RESERVED_R			21U
+#define XHC_PSUM2_WIDTH				32U
+#define XHC_PSUM2__WIDTH			32U
+#define XHC_PSUM2_ALL_L				31U
+#define XHC_PSUM2_ALL_R				0U
+#define XHC_PSUM2__ALL_L			31U
+#define XHC_PSUM2__ALL_R			0U
+#define XHC_PSUM2_DATAMASK			0xfe1fffffU
+#define XHC_PSUM2_RDWRMASK			0x01e00000U
+#define XHC_PSUM2_RESETVALUE			0x00080000U
+
+#define XHC_PTSLTYP2_OFFSET			0x95cU
+#define XHC_PTSLTYP2_BASE			0x95cU
+#define XHC_PTSLTYP2__reserved_L		31U
+#define XHC_PTSLTYP2__reserved_R		5U
+#define XHC_PTSLTYP2__reserved_WIDTH		27U
+#define XHC_PTSLTYP2__reserved_RESETVALUE	0x0U
+#define XHC_PTSLTYP2__PST_L			4U
+#define XHC_PTSLTYP2__PST_R			0U
+#define XHC_PTSLTYP2__PST_WIDTH			5U
+#define XHC_PTSLTYP2__PST_RESETVALUE		0x0U
+#define XHC_PTSLTYP2_WIDTH			32U
+#define XHC_PTSLTYP2__WIDTH			32U
+#define XHC_PTSLTYP2_ALL_L			31U
+#define XHC_PTSLTYP2_ALL_R			0U
+#define XHC_PTSLTYP2__ALL_L			31U
+#define XHC_PTSLTYP2__ALL_R			0U
+#define XHC_PTSLTYP2_DATAMASK			0xffffffffU
+#define XHC_PTSLTYP2_RDWRMASK			0x00000000U
+#define XHC_PTSLTYP2_RESETVALUE			0x00000000U
+
+#define XHC_ECHRSVP_OFFSET			0x960U
+#define XHC_ECHRSVP_BASE			0x960U
+#define XHC_ECHRSVP__reserved_L			31U
+#define XHC_ECHRSVP__reserved_R			16U
+#define XHC_ECHRSVP__reserved_WIDTH		16U
+#define XHC_ECHRSVP__reserved_RESETVALUE	0x0000U
+#define XHC_ECHRSVP__NCP_L			15U
+#define XHC_ECHRSVP__NCP_R			8U
+#define XHC_ECHRSVP__NCP_WIDTH			8U
+#define XHC_ECHRSVP__NCP_RESETVALUE		0x00U
+#define XHC_ECHRSVP__CID_L			7U
+#define XHC_ECHRSVP__CID_R			0U
+#define XHC_ECHRSVP__CID_WIDTH			8U
+#define XHC_ECHRSVP__CID_RESETVALUE		0xffU
+#define XHC_ECHRSVP_WIDTH			32U
+#define XHC_ECHRSVP__WIDTH			32U
+#define XHC_ECHRSVP_ALL_L			31U
+#define XHC_ECHRSVP_ALL_R			0U
+#define XHC_ECHRSVP__ALL_L			31U
+#define XHC_ECHRSVP__ALL_R			0U
+#define XHC_ECHRSVP_DATAMASK			0xffffffffU
+#define XHC_ECHRSVP_RDWRMASK			0x00000000U
+#define XHC_ECHRSVP_RESETVALUE			0x000000ffU
+
+#define XHC_ECHRSVI_OFFSET			0x968U
+#define XHC_ECHRSVI_BASE			0x968U
+#define XHC_ECHRSVI__reserved_L			31U
+#define XHC_ECHRSVI__reserved_R			16U
+#define XHC_ECHRSVI__reserved_WIDTH		16U
+#define XHC_ECHRSVI__reserved_RESETVALUE	0x0000U
+#define XHC_ECHRSVI__NCP_L			15U
+#define XHC_ECHRSVI__NCP_R			8U
+#define XHC_ECHRSVI__NCP_WIDTH			8U
+#define XHC_ECHRSVI__NCP_RESETVALUE		0x00U
+#define XHC_ECHRSVI__CID_L			7U
+#define XHC_ECHRSVI__CID_R			0U
+#define XHC_ECHRSVI__CID_WIDTH			8U
+#define XHC_ECHRSVI__CID_RESETVALUE		0xffU
+#define XHC_ECHRSVI_WIDTH			32U
+#define XHC_ECHRSVI__WIDTH			32U
+#define XHC_ECHRSVI_ALL_L			31U
+#define XHC_ECHRSVI_ALL_R			0U
+#define XHC_ECHRSVI__ALL_L			31U
+#define XHC_ECHRSVI__ALL_R			0U
+#define XHC_ECHRSVI_DATAMASK			0xffffffffU
+#define XHC_ECHRSVI_RDWRMASK			0x00000000U
+#define XHC_ECHRSVI_RESETVALUE			0x000000ffU
+
+#define XHC_ECHRSVM_OFFSET			0xae8U
+#define XHC_ECHRSVM_BASE			0xae8U
+#define XHC_ECHRSVM__reserved_L			31U
+#define XHC_ECHRSVM__reserved_R			16U
+#define XHC_ECHRSVM__reserved_WIDTH		16U
+#define XHC_ECHRSVM__reserved_RESETVALUE	0x0000U
+#define XHC_ECHRSVM__NCP_L			15U
+#define XHC_ECHRSVM__NCP_R			8U
+#define XHC_ECHRSVM__NCP_WIDTH			8U
+#define XHC_ECHRSVM__NCP_RESETVALUE		0x00U
+#define XHC_ECHRSVM__CID_L			7U
+#define XHC_ECHRSVM__CID_R			0U
+#define XHC_ECHRSVM__CID_WIDTH			8U
+#define XHC_ECHRSVM__CID_RESETVALUE		0xffU
+#define XHC_ECHRSVM_WIDTH			32U
+#define XHC_ECHRSVM__WIDTH			32U
+#define XHC_ECHRSVM_ALL_L			31U
+#define XHC_ECHRSVM_ALL_R			0U
+#define XHC_ECHRSVM__ALL_L			31U
+#define XHC_ECHRSVM__ALL_R			0U
+#define XHC_ECHRSVM_DATAMASK			0xffffffffU
+#define XHC_ECHRSVM_RDWRMASK			0x00000000U
+#define XHC_ECHRSVM_RESETVALUE			0x000000ffU
+
+#define XHC_ECHRSVD_OFFSET			0xaf8U
+#define XHC_ECHRSVD_BASE			0xaf8U
+#define XHC_ECHRSVD__reserved_L			31U
+#define XHC_ECHRSVD__reserved_R			16U
+#define XHC_ECHRSVD__reserved_WIDTH		16U
+#define XHC_ECHRSVD__reserved_RESETVALUE	0x0000U
+#define XHC_ECHRSVD__NCP_L			15U
+#define XHC_ECHRSVD__NCP_R			8U
+#define XHC_ECHRSVD__NCP_WIDTH			8U
+#define XHC_ECHRSVD__NCP_RESETVALUE		0x00U
+#define XHC_ECHRSVD__CID_L			7U
+#define XHC_ECHRSVD__CID_R			0U
+#define XHC_ECHRSVD__CID_WIDTH			8U
+#define XHC_ECHRSVD__CID_RESETVALUE		0xffU
+#define XHC_ECHRSVD_WIDTH			32U
+#define XHC_ECHRSVD__WIDTH			32U
+#define XHC_ECHRSVD_ALL_L			31U
+#define XHC_ECHRSVD_ALL_R			0U
+#define XHC_ECHRSVD__ALL_L			31U
+#define XHC_ECHRSVD__ALL_R			0U
+#define XHC_ECHRSVD_DATAMASK			0xffffffffU
+#define XHC_ECHRSVD_RDWRMASK			0x00000000U
+#define XHC_ECHRSVD_RESETVALUE			0x000000ffU
+
+#define XHC_ECHRSVO_OFFSET			0xb38U
+#define XHC_ECHRSVO_BASE			0xb38U
+#define XHC_ECHRSVO__reserved_L			31U
+#define XHC_ECHRSVO__reserved_R			16U
+#define XHC_ECHRSVO__reserved_WIDTH		16U
+#define XHC_ECHRSVO__reserved_RESETVALUE	0x0000U
+#define XHC_ECHRSVO__NCP_L			15U
+#define XHC_ECHRSVO__NCP_R			8U
+#define XHC_ECHRSVO__NCP_WIDTH			8U
+#define XHC_ECHRSVO__NCP_RESETVALUE		0x00U
+#define XHC_ECHRSVO__CID_L			7U
+#define XHC_ECHRSVO__CID_R			0U
+#define XHC_ECHRSVO__CID_WIDTH			8U
+#define XHC_ECHRSVO__CID_RESETVALUE		0xffU
+#define XHC_ECHRSVO_WIDTH			32U
+#define XHC_ECHRSVO__WIDTH			32U
+#define XHC_ECHRSVO_ALL_L			31U
+#define XHC_ECHRSVO_ALL_R			0U
+#define XHC_ECHRSVO__ALL_L			31U
+#define XHC_ECHRSVO__ALL_R			0U
+#define XHC_ECHRSVO_DATAMASK			0xffffffffU
+#define XHC_ECHRSVO_RDWRMASK			0x00000000U
+#define XHC_ECHRSVO_RESETVALUE			0x000000ffU
+
+#define XHC_ECHCTT_OFFSET			0xbf0U
+#define XHC_ECHCTT_BASE				0xbf0U
+#define XHC_ECHCTT__reserved_L			31U
+#define XHC_ECHCTT__reserved_R			16U
+#define XHC_ECHCTT__reserved_WIDTH		16U
+#define XHC_ECHCTT__reserved_RESETVALUE		0x0000U
+#define XHC_ECHCTT__NCP_L			15U
+#define XHC_ECHCTT__NCP_R			8U
+#define XHC_ECHCTT__NCP_WIDTH			8U
+#define XHC_ECHCTT__NCP_RESETVALUE		0x04U
+#define XHC_ECHCTT__CID_L			7U
+#define XHC_ECHCTT__CID_R			0U
+#define XHC_ECHCTT__CID_WIDTH			8U
+#define XHC_ECHCTT__CID_RESETVALUE		0xe0U
+#define XHC_ECHCTT_WIDTH			32U
+#define XHC_ECHCTT__WIDTH			32U
+#define XHC_ECHCTT_ALL_L			31U
+#define XHC_ECHCTT_ALL_R			0U
+#define XHC_ECHCTT__ALL_L			31U
+#define XHC_ECHCTT__ALL_R			0U
+#define XHC_ECHCTT_DATAMASK			0xffffffffU
+#define XHC_ECHCTT_RDWRMASK			0x00000000U
+#define XHC_ECHCTT_RESETVALUE			0x000004e0U
+
+#define XHC_CTTMTS0_OFFSET			0xbf8U
+#define XHC_CTTMTS0_BASE			0xbf8U
+#define XHC_CTTMTS0__DCM			31U
+#define XHC_CTTMTS0__DCM_L			31U
+#define XHC_CTTMTS0__DCM_R			31U
+#define XHC_CTTMTS0__DCM_WIDTH			1U
+#define XHC_CTTMTS0__DCM_RESETVALUE		0x0U
+#define XHC_CTTMTS0__reserved_L			30U
+#define XHC_CTTMTS0__reserved_R			10U
+#define XHC_CTTMTS0__reserved_WIDTH		21U
+#define XHC_CTTMTS0__reserved_RESETVALUE	0x0U
+#define XHC_CTTMTS0__SLA_L			9U
+#define XHC_CTTMTS0__SLA_R			0U
+#define XHC_CTTMTS0__SLA_WIDTH			10U
+#define XHC_CTTMTS0__SLA_RESETVALUE		0x0U
+#define XHC_CTTMTS0_WIDTH			32U
+#define XHC_CTTMTS0__WIDTH			32U
+#define XHC_CTTMTS0_ALL_L			31U
+#define XHC_CTTMTS0_ALL_R			0U
+#define XHC_CTTMTS0__ALL_L			31U
+#define XHC_CTTMTS0__ALL_R			0U
+#define XHC_CTTMTS0_DATAMASK			0xffffffffU
+#define XHC_CTTMTS0_RDWRMASK			0x00000000U
+#define XHC_CTTMTS0_RESETVALUE			0x00000000U
+
+#define XHC_CTTMTS1_OFFSET			0xbfcU
+#define XHC_CTTMTS1_BASE			0xbfcU
+#define XHC_CTTMTS1__TXF_L			25U
+#define XHC_CTTMTS1__TXF_R			16U
+#define XHC_CTTMTS1__TXF_WIDTH			10U
+#define XHC_CTTMTS1__TXF_RESETVALUE		0x0U
+#define XHC_CTTMTS1__reserved_L			15U
+#define XHC_CTTMTS1__reserved_R			10U
+#define XHC_CTTMTS1__reserved_WIDTH		6U
+#define XHC_CTTMTS1__reserved_RESETVALUE	0x0U
+#define XHC_CTTMTS1__RXF_L			9U
+#define XHC_CTTMTS1__RXF_R			0U
+#define XHC_CTTMTS1__RXF_WIDTH			10U
+#define XHC_CTTMTS1__RXF_RESETVALUE		0x0U
+#define XHC_CTTMTS1__RESERVED_L			31U
+#define XHC_CTTMTS1__RESERVED_R			26U
+#define XHC_CTTMTS1_WIDTH			26U
+#define XHC_CTTMTS1__WIDTH			26U
+#define XHC_CTTMTS1_ALL_L			25U
+#define XHC_CTTMTS1_ALL_R			0U
+#define XHC_CTTMTS1__ALL_L			25U
+#define XHC_CTTMTS1__ALL_R			0U
+#define XHC_CTTMTS1_DATAMASK			0x03ffffffU
+#define XHC_CTTMTS1_RDWRMASK			0xfc000000U
+#define XHC_CTTMTS1_RESETVALUE			0x0000000U
+
+#define XHC_ECHBIU_OFFSET			0xc00U
+#define XHC_ECHBIU_BASE				0xc00U
+#define XHC_ECHBIU__CLK_L			31U
+#define XHC_ECHBIU__CLK_R			21U
+#define XHC_ECHBIU__CLK_WIDTH			11U
+#define XHC_ECHBIU__CLK_RESETVALUE		0x0U
+#define XHC_ECHBIU__reserved_L			20U
+#define XHC_ECHBIU__reserved_R			19U
+#define XHC_ECHBIU__reserved_WIDTH		2U
+#define XHC_ECHBIU__reserved_RESETVALUE		0x0U
+#define XHC_ECHBIU__WID_L			18U
+#define XHC_ECHBIU__WID_R			16U
+#define XHC_ECHBIU__WID_WIDTH			3U
+#define XHC_ECHBIU__WID_RESETVALUE		0x0U
+#define XHC_ECHBIU__NCP_L			15U
+#define XHC_ECHBIU__NCP_R			8U
+#define XHC_ECHBIU__NCP_WIDTH			8U
+#define XHC_ECHBIU__NCP_RESETVALUE		0x08U
+#define XHC_ECHBIU__CID_L			7U
+#define XHC_ECHBIU__CID_R			0U
+#define XHC_ECHBIU__CID_WIDTH			8U
+#define XHC_ECHBIU__CID_RESETVALUE		0xc0U
+#define XHC_ECHBIU_WIDTH			32U
+#define XHC_ECHBIU__WIDTH			32U
+#define XHC_ECHBIU_ALL_L			31U
+#define XHC_ECHBIU_ALL_R			0U
+#define XHC_ECHBIU__ALL_L			31U
+#define XHC_ECHBIU__ALL_R			0U
+#define XHC_ECHBIU_DATAMASK			0xffffffffU
+#define XHC_ECHBIU_RDWRMASK			0x00000000U
+#define XHC_ECHBIU_RESETVALUE			0x000008c0U
+
+#define XHC_BIUSPC_OFFSET			0xc04U
+#define XHC_BIUSPC_BASE				0xc04U
+#define XHC_BIUSPC__MAJ_L			31U
+#define XHC_BIUSPC__MAJ_R			28U
+#define XHC_BIUSPC__MAJ_WIDTH			4U
+#define XHC_BIUSPC__MAJ_RESETVALUE		0x0U
+#define XHC_BIUSPC__MIN_L			27U
+#define XHC_BIUSPC__MIN_R			24U
+#define XHC_BIUSPC__MIN_WIDTH			4U
+#define XHC_BIUSPC__MIN_RESETVALUE		0x0U
+#define XHC_BIUSPC__RLS_L			23U
+#define XHC_BIUSPC__RLS_R			20U
+#define XHC_BIUSPC__RLS_WIDTH			4U
+#define XHC_BIUSPC__RLS_RESETVALUE		0x0U
+#define XHC_BIUSPC__reserved_L			19U
+#define XHC_BIUSPC__reserved_R			4U
+#define XHC_BIUSPC__reserved_WIDTH		16U
+#define XHC_BIUSPC__reserved_RESETVALUE		0x0000U
+#define XHC_BIUSPC__SPI_L			3U
+#define XHC_BIUSPC__SPI_R			2U
+#define XHC_BIUSPC__SPI_WIDTH			2U
+#define XHC_BIUSPC__SPI_RESETVALUE		0x3U
+#define XHC_BIUSPC__TYP_L			1U
+#define XHC_BIUSPC__TYP_R			0U
+#define XHC_BIUSPC__TYP_WIDTH			2U
+#define XHC_BIUSPC__TYP_RESETVALUE		0x0U
+#define XHC_BIUSPC_WIDTH			32U
+#define XHC_BIUSPC__WIDTH			32U
+#define XHC_BIUSPC_ALL_L			31U
+#define XHC_BIUSPC_ALL_R			0U
+#define XHC_BIUSPC__ALL_L			31U
+#define XHC_BIUSPC__ALL_R			0U
+#define XHC_BIUSPC_DATAMASK			0xffffffffU
+#define XHC_BIUSPC_RDWRMASK			0x00000000U
+#define XHC_BIUSPC_RESETVALUE			0x0000000cU
+
+#define XHC_AXIWRA_OFFSET			0xc08U
+#define XHC_AXIWRA_BASE				0xc08U
+#define XHC_AXIWRA__WTS_L			31U
+#define XHC_AXIWRA__WTS_R			28U
+#define XHC_AXIWRA__WTS_WIDTH			4U
+#define XHC_AXIWRA__WTS_RESETVALUE		0x2U
+#define XHC_AXIWRA__WUA_L			24U
+#define XHC_AXIWRA__WUA_R			16U
+#define XHC_AXIWRA__WUA_WIDTH			9U
+#define XHC_AXIWRA__WUA_RESETVALUE		0x0U
+#define XHC_AXIWRA__reserved_L			15U
+#define XHC_AXIWRA__reserved_R			10U
+#define XHC_AXIWRA__reserved_WIDTH		6U
+#define XHC_AXIWRA__reserved_RESETVALUE		0x0U
+#define XHC_AXIWRA__BYP				9U
+#define XHC_AXIWRA__BYP_L			9U
+#define XHC_AXIWRA__BYP_R			9U
+#define XHC_AXIWRA__BYP_WIDTH			1U
+#define XHC_AXIWRA__BYP_RESETVALUE		0x0U
+#define XHC_AXIWRA__WSA_L			8U
+#define XHC_AXIWRA__WSA_R			0U
+#define XHC_AXIWRA__WSA_WIDTH			9U
+#define XHC_AXIWRA__WSA_RESETVALUE		0x0U
+#define XHC_AXIWRA__RESERVED_L			27U
+#define XHC_AXIWRA__RESERVED_R			25U
+#define XHC_AXIWRA_WIDTH			32U
+#define XHC_AXIWRA__WIDTH			32U
+#define XHC_AXIWRA_ALL_L			31U
+#define XHC_AXIWRA_ALL_R			0U
+#define XHC_AXIWRA__ALL_L			31U
+#define XHC_AXIWRA__ALL_R			0U
+#define XHC_AXIWRA_DATAMASK			0xf1ffffffU
+#define XHC_AXIWRA_RDWRMASK			0x0e000000U
+#define XHC_AXIWRA_RESETVALUE			0x20000000U
+
+#define XHC_AXIRDA_OFFSET			0xc0cU
+#define XHC_AXIRDA_BASE				0xc0cU
+#define XHC_AXIRDA__RTS_L			31U
+#define XHC_AXIRDA__RTS_R			28U
+#define XHC_AXIRDA__RTS_WIDTH			4U
+#define XHC_AXIRDA__RTS_RESETVALUE		0x2U
+#define XHC_AXIRDA__RFPC			27U
+#define XHC_AXIRDA__RFPC_L			27U
+#define XHC_AXIRDA__RFPC_R			27U
+#define XHC_AXIRDA__RFPC_WIDTH			1U
+#define XHC_AXIRDA__RFPC_RESETVALUE		0x0U
+#define XHC_AXIRDA__RUA_L			24U
+#define XHC_AXIRDA__RUA_R			16U
+#define XHC_AXIRDA__RUA_WIDTH			9U
+#define XHC_AXIRDA__RUA_RESETVALUE		0x0U
+#define XHC_AXIRDA__reserved_L			15U
+#define XHC_AXIRDA__reserved_R			9U
+#define XHC_AXIRDA__reserved_WIDTH		7U
+#define XHC_AXIRDA__reserved_RESETVALUE		0x0U
+#define XHC_AXIRDA__RSA_L			8U
+#define XHC_AXIRDA__RSA_R			0U
+#define XHC_AXIRDA__RSA_WIDTH			9U
+#define XHC_AXIRDA__RSA_RESETVALUE		0x0U
+#define XHC_AXIRDA__RESERVED_L			26U
+#define XHC_AXIRDA__RESERVED_R			25U
+#define XHC_AXIRDA_WIDTH			32U
+#define XHC_AXIRDA__WIDTH			32U
+#define XHC_AXIRDA_ALL_L			31U
+#define XHC_AXIRDA_ALL_R			0U
+#define XHC_AXIRDA__ALL_L			31U
+#define XHC_AXIRDA__ALL_R			0U
+#define XHC_AXIRDA_DATAMASK			0xf9ffffffU
+#define XHC_AXIRDA_RDWRMASK			0x06000000U
+#define XHC_AXIRDA_RESETVALUE			0x20000000U
+
+#define XHC_AXILPM_OFFSET			0xc10U
+#define XHC_AXILPM_BASE				0xc10U
+#define XHC_AXILPM__ENB				31U
+#define XHC_AXILPM__ENB_L			31U
+#define XHC_AXILPM__ENB_R			31U
+#define XHC_AXILPM__ENB_WIDTH			1U
+#define XHC_AXILPM__ENB_RESETVALUE		0x0U
+#define XHC_AXILPM__reserved_L			30U
+#define XHC_AXILPM__reserved_R			3U
+#define XHC_AXILPM__reserved_WIDTH		28U
+#define XHC_AXILPM__reserved_RESETVALUE		0x0000000U
+#define XHC_AXILPM__ITT_L			2U
+#define XHC_AXILPM__ITT_R			0U
+#define XHC_AXILPM__ITT_WIDTH			3U
+#define XHC_AXILPM__ITT_RESETVALUE		0x0U
+#define XHC_AXILPM_WIDTH			32U
+#define XHC_AXILPM__WIDTH			32U
+#define XHC_AXILPM_ALL_L			31U
+#define XHC_AXILPM_ALL_R			0U
+#define XHC_AXILPM__ALL_L			31U
+#define XHC_AXILPM__ALL_R			0U
+#define XHC_AXILPM_DATAMASK			0xffffffffU
+#define XHC_AXILPM_RDWRMASK			0x00000000U
+#define XHC_AXILPM_RESETVALUE			0x00000000U
+
+#define XHC_AXIQOS_OFFSET			0xc14U
+#define XHC_AXIQOS_BASE				0xc14U
+#define XHC_AXIQOS__WQOS3_L			31U
+#define XHC_AXIQOS__WQOS3_R			28U
+#define XHC_AXIQOS__WQOS3_WIDTH			4U
+#define XHC_AXIQOS__WQOS3_RESETVALUE		0x0U
+#define XHC_AXIQOS__WQOS2_L			27U
+#define XHC_AXIQOS__WQOS2_R			24U
+#define XHC_AXIQOS__WQOS2_WIDTH			4U
+#define XHC_AXIQOS__WQOS2_RESETVALUE		0x0U
+#define XHC_AXIQOS__WQOS1_L			23U
+#define XHC_AXIQOS__WQOS1_R			20U
+#define XHC_AXIQOS__WQOS1_WIDTH			4U
+#define XHC_AXIQOS__WQOS1_RESETVALUE		0x0U
+#define XHC_AXIQOS__WQOS0_L			19U
+#define XHC_AXIQOS__WQOS0_R			16U
+#define XHC_AXIQOS__WQOS0_WIDTH			4U
+#define XHC_AXIQOS__WQOS0_RESETVALUE		0x0U
+#define XHC_AXIQOS__RQOS3_L			15U
+#define XHC_AXIQOS__RQOS3_R			12U
+#define XHC_AXIQOS__RQOS3_WIDTH			4U
+#define XHC_AXIQOS__RQOS3_RESETVALUE		0x0U
+#define XHC_AXIQOS__RQOS2_L			11U
+#define XHC_AXIQOS__RQOS2_R			8U
+#define XHC_AXIQOS__RQOS2_WIDTH			4U
+#define XHC_AXIQOS__RQOS2_RESETVALUE		0x0U
+#define XHC_AXIQOS__RQOS1_L			7U
+#define XHC_AXIQOS__RQOS1_R			4U
+#define XHC_AXIQOS__RQOS1_WIDTH			4U
+#define XHC_AXIQOS__RQOS1_RESETVALUE		0x0U
+#define XHC_AXIQOS__RQOS0_L			3U
+#define XHC_AXIQOS__RQOS0_R			0U
+#define XHC_AXIQOS__RQOS0_WIDTH			4U
+#define XHC_AXIQOS__RQOS0_RESETVALUE		0x0U
+#define XHC_AXIQOS_WIDTH			32U
+#define XHC_AXIQOS__WIDTH			32U
+#define XHC_AXIQOS_ALL_L			31U
+#define XHC_AXIQOS_ALL_R			0U
+#define XHC_AXIQOS__ALL_L			31U
+#define XHC_AXIQOS__ALL_R			0U
+#define XHC_AXIQOS_DATAMASK			0xffffffffU
+#define XHC_AXIQOS_RDWRMASK			0x00000000U
+#define XHC_AXIQOS_RESETVALUE			0x00000000U
+
+#define XHC_ECHCSR_OFFSET			0xc20U
+#define XHC_ECHCSR_BASE				0xc20U
+#define XHC_ECHCSR__CLK_L			31U
+#define XHC_ECHCSR__CLK_R			21U
+#define XHC_ECHCSR__CLK_WIDTH			11U
+#define XHC_ECHCSR__CLK_RESETVALUE		0x0U
+#define XHC_ECHCSR__reserved_L			20U
+#define XHC_ECHCSR__reserved_R			19U
+#define XHC_ECHCSR__reserved_WIDTH		2U
+#define XHC_ECHCSR__reserved_RESETVALUE		0x0U
+#define XHC_ECHCSR__WID_L			18U
+#define XHC_ECHCSR__WID_R			16U
+#define XHC_ECHCSR__WID_WIDTH			3U
+#define XHC_ECHCSR__WID_RESETVALUE		0x0U
+#define XHC_ECHCSR__NCP_L			15U
+#define XHC_ECHCSR__NCP_R			8U
+#define XHC_ECHCSR__NCP_WIDTH			8U
+#define XHC_ECHCSR__NCP_RESETVALUE		0x04U
+#define XHC_ECHCSR__CID_L			7U
+#define XHC_ECHCSR__CID_R			0U
+#define XHC_ECHCSR__CID_WIDTH			8U
+#define XHC_ECHCSR__CID_RESETVALUE		0xc1U
+#define XHC_ECHCSR_WIDTH			32U
+#define XHC_ECHCSR__WIDTH			32U
+#define XHC_ECHCSR_ALL_L			31U
+#define XHC_ECHCSR_ALL_R			0U
+#define XHC_ECHCSR__ALL_L			31U
+#define XHC_ECHCSR__ALL_R			0U
+#define XHC_ECHCSR_DATAMASK			0xffffffffU
+#define XHC_ECHCSR_RDWRMASK			0x00000000U
+#define XHC_ECHCSR_RESETVALUE			0x000004c1U
+
+#define XHC_CSRSPC_OFFSET			0xc24U
+#define XHC_CSRSPC_BASE				0xc24U
+#define XHC_CSRSPC__MAJ_L			31U
+#define XHC_CSRSPC__MAJ_R			28U
+#define XHC_CSRSPC__MAJ_WIDTH			4U
+#define XHC_CSRSPC__MAJ_RESETVALUE		0x0U
+#define XHC_CSRSPC__MIN_L			27U
+#define XHC_CSRSPC__MIN_R			24U
+#define XHC_CSRSPC__MIN_WIDTH			4U
+#define XHC_CSRSPC__MIN_RESETVALUE		0x0U
+#define XHC_CSRSPC__RLS_L			23U
+#define XHC_CSRSPC__RLS_R			20U
+#define XHC_CSRSPC__RLS_WIDTH			4U
+#define XHC_CSRSPC__RLS_RESETVALUE		0x0U
+#define XHC_CSRSPC__reserved_L			19U
+#define XHC_CSRSPC__reserved_R			3U
+#define XHC_CSRSPC__reserved_WIDTH		17U
+#define XHC_CSRSPC__reserved_RESETVALUE		0x0U
+#define XHC_CSRSPC__ASP				2U
+#define XHC_CSRSPC__ASP_L			2U
+#define XHC_CSRSPC__ASP_R			2U
+#define XHC_CSRSPC__ASP_WIDTH			1U
+#define XHC_CSRSPC__ASP_RESETVALUE		0x0U
+#define XHC_CSRSPC__TYP_L			1U
+#define XHC_CSRSPC__TYP_R			0U
+#define XHC_CSRSPC__TYP_WIDTH			2U
+#define XHC_CSRSPC__TYP_RESETVALUE		0x0U
+#define XHC_CSRSPC_WIDTH			32U
+#define XHC_CSRSPC__WIDTH			32U
+#define XHC_CSRSPC_ALL_L			31U
+#define XHC_CSRSPC_ALL_R			0U
+#define XHC_CSRSPC__ALL_L			31U
+#define XHC_CSRSPC__ALL_R			0U
+#define XHC_CSRSPC_DATAMASK			0xffffffffU
+#define XHC_CSRSPC_RDWRMASK			0x00000000U
+#define XHC_CSRSPC_RESETVALUE			0x00000000U
+
+#define XHC_ECHAIU_OFFSET			0xc30U
+#define XHC_ECHAIU_BASE				0xc30U
+#define XHC_ECHAIU__DMA_L			31U
+#define XHC_ECHAIU__DMA_R			30U
+#define XHC_ECHAIU__DMA_WIDTH			2U
+#define XHC_ECHAIU__DMA_RESETVALUE		0x1U
+#define XHC_ECHAIU__PBRS_L			29U
+#define XHC_ECHAIU__PBRS_R			28U
+#define XHC_ECHAIU__PBRS_WIDTH			2U
+#define XHC_ECHAIU__PBRS_RESETVALUE		0x0U
+#define XHC_ECHAIU__PBR2_L			27U
+#define XHC_ECHAIU__PBR2_R			26U
+#define XHC_ECHAIU__PBR2_WIDTH			2U
+#define XHC_ECHAIU__PBR2_RESETVALUE		0x0U
+#define XHC_ECHAIU__SCHS_L			25U
+#define XHC_ECHAIU__SCHS_R			24U
+#define XHC_ECHAIU__SCHS_WIDTH			2U
+#define XHC_ECHAIU__SCHS_RESETVALUE		0x0U
+#define XHC_ECHAIU__SCH2_L			23U
+#define XHC_ECHAIU__SCH2_R			22U
+#define XHC_ECHAIU__SCH2_WIDTH			2U
+#define XHC_ECHAIU__SCH2_RESETVALUE		0x0U
+#define XHC_ECHAIU__CHMS_L			21U
+#define XHC_ECHAIU__CHMS_R			20U
+#define XHC_ECHAIU__CHMS_WIDTH			2U
+#define XHC_ECHAIU__CHMS_RESETVALUE		0x3U
+#define XHC_ECHAIU__CHM2_L			19U
+#define XHC_ECHAIU__CHM2_R			18U
+#define XHC_ECHAIU__CHM2_WIDTH			2U
+#define XHC_ECHAIU__CHM2_RESETVALUE		0x0U
+#define XHC_ECHAIU__reserved_L			17U
+#define XHC_ECHAIU__reserved_R			16U
+#define XHC_ECHAIU__reserved_WIDTH		2U
+#define XHC_ECHAIU__reserved_RESETVALUE		0x0U
+#define XHC_ECHAIU__NCP_L			15U
+#define XHC_ECHAIU__NCP_R			8U
+#define XHC_ECHAIU__NCP_WIDTH			8U
+#define XHC_ECHAIU__NCP_RESETVALUE		0x04U
+#define XHC_ECHAIU__CID_L			7U
+#define XHC_ECHAIU__CID_R			0U
+#define XHC_ECHAIU__CID_WIDTH			8U
+#define XHC_ECHAIU__CID_RESETVALUE		0xc2U
+#define XHC_ECHAIU_WIDTH			32U
+#define XHC_ECHAIU__WIDTH			32U
+#define XHC_ECHAIU_ALL_L			31U
+#define XHC_ECHAIU_ALL_R			0U
+#define XHC_ECHAIU__ALL_L			31U
+#define XHC_ECHAIU__ALL_R			0U
+#define XHC_ECHAIU_DATAMASK			0xffffffffU
+#define XHC_ECHAIU_RDWRMASK			0x00000000U
+#define XHC_ECHAIU_RESETVALUE			0x403004c2U
+
+#define XHC_AIUDMA_OFFSET			0xc34U
+#define XHC_AIUDMA_BASE				0xc34U
+#define XHC_AIUDMA__WRMB_L			31U
+#define XHC_AIUDMA__WRMB_R			28U
+#define XHC_AIUDMA__WRMB_WIDTH			4U
+#define XHC_AIUDMA__WRMB_RESETVALUE		0x0U
+#define XHC_AIUDMA__WRD_L			27U
+#define XHC_AIUDMA__WRD_R			26U
+#define XHC_AIUDMA__WRD_WIDTH			2U
+#define XHC_AIUDMA__WRD_RESETVALUE		0x0U
+#define XHC_AIUDMA__WED_L			25U
+#define XHC_AIUDMA__WED_R			24U
+#define XHC_AIUDMA__WED_WIDTH			2U
+#define XHC_AIUDMA__WED_RESETVALUE		0x0U
+#define XHC_AIUDMA__WMS_L			23U
+#define XHC_AIUDMA__WMS_R			22U
+#define XHC_AIUDMA__WMS_WIDTH			2U
+#define XHC_AIUDMA__WMS_RESETVALUE		0x0U
+#define XHC_AIUDMA__WMI_L			21U
+#define XHC_AIUDMA__WMI_R			20U
+#define XHC_AIUDMA__WMI_WIDTH			2U
+#define XHC_AIUDMA__WMI_RESETVALUE		0x0U
+#define XHC_AIUDMA__WPF_L			19U
+#define XHC_AIUDMA__WPF_R			16U
+#define XHC_AIUDMA__WPF_WIDTH			4U
+#define XHC_AIUDMA__WPF_RESETVALUE		0x6U
+#define XHC_AIUDMA__RRMB_L			15U
+#define XHC_AIUDMA__RRMB_R			12U
+#define XHC_AIUDMA__RRMB_WIDTH			4U
+#define XHC_AIUDMA__RRMB_RESETVALUE		0x0U
+#define XHC_AIUDMA__RTD_L			11U
+#define XHC_AIUDMA__RTD_R			10U
+#define XHC_AIUDMA__RTD_WIDTH			2U
+#define XHC_AIUDMA__RTD_RESETVALUE		0x0U
+#define XHC_AIUDMA__RTF_L			9U
+#define XHC_AIUDMA__RTF_R			8U
+#define XHC_AIUDMA__RTF_WIDTH			2U
+#define XHC_AIUDMA__RTF_RESETVALUE		0x0U
+#define XHC_AIUDMA__RM_S_L			7U
+#define XHC_AIUDMA__RM_S_R			6U
+#define XHC_AIUDMA__RM_S_WIDTH			2U
+#define XHC_AIUDMA__RM_S_RESETVALUE		0x0U
+#define XHC_AIUDMA__TFBS_L			5U
+#define XHC_AIUDMA__TFBS_R			3U
+#define XHC_AIUDMA__TFBS_WIDTH			3U
+#define XHC_AIUDMA__TFBS_RESETVALUE		0x0U
+#define XHC_AIUDMA__reserved_L			2U
+#define XHC_AIUDMA__reserved_R			0U
+#define XHC_AIUDMA__reserved_WIDTH		3U
+#define XHC_AIUDMA__reserved_RESETVALUE		0x0U
+#define XHC_AIUDMA_WIDTH			32U
+#define XHC_AIUDMA__WIDTH			32U
+#define XHC_AIUDMA_ALL_L			31U
+#define XHC_AIUDMA_ALL_R			0U
+#define XHC_AIUDMA__ALL_L			31U
+#define XHC_AIUDMA__ALL_R			0U
+#define XHC_AIUDMA_DATAMASK			0xffffffffU
+#define XHC_AIUDMA_RDWRMASK			0x00000000U
+#define XHC_AIUDMA_RESETVALUE			0x00060000U
+
+#define XHC_AIUFLA_OFFSET			0xc38U
+#define XHC_AIUFLA_BASE				0xc38U
+#define XHC_AIUFLA__ACLK_L			31U
+#define XHC_AIUFLA__ACLK_R			23U
+#define XHC_AIUFLA__ACLK_WIDTH			9U
+#define XHC_AIUFLA__ACLK_RESETVALUE		0x0U
+#define XHC_AIUFLA__MFLV_L			22U
+#define XHC_AIUFLA__MFLV_R			7U
+#define XHC_AIUFLA__MFLV_WIDTH			16U
+#define XHC_AIUFLA__MFLV_RESETVALUE		0x0000U
+#define XHC_AIUFLA__NFC				6U
+#define XHC_AIUFLA__NFC_L			6U
+#define XHC_AIUFLA__NFC_R			6U
+#define XHC_AIUFLA__NFC_WIDTH			1U
+#define XHC_AIUFLA__NFC_RESETVALUE		0x1U
+#define XHC_AIUFLA__FLADJ_L			5U
+#define XHC_AIUFLA__FLADJ_R			0U
+#define XHC_AIUFLA__FLADJ_WIDTH			6U
+#define XHC_AIUFLA__FLADJ_RESETVALUE		0x20U
+#define XHC_AIUFLA_WIDTH			32U
+#define XHC_AIUFLA__WIDTH			32U
+#define XHC_AIUFLA_ALL_L			31U
+#define XHC_AIUFLA_ALL_R			0U
+#define XHC_AIUFLA__ALL_L			31U
+#define XHC_AIUFLA__ALL_R			0U
+#define XHC_AIUFLA_DATAMASK			0xffffffffU
+#define XHC_AIUFLA_RDWRMASK			0x00000000U
+#define XHC_AIUFLA_RESETVALUE			0x00000060U
+
+#define XHC_AIUCFG_OFFSET			0xc3cU
+#define XHC_AIUCFG_BASE				0xc3cU
+#define XHC_AIUCFG__ISO_L			30U
+#define XHC_AIUCFG__ISO_R			28U
+#define XHC_AIUCFG__ISO_WIDTH			3U
+#define XHC_AIUCFG__ISO_RESETVALUE		0x0U
+#define XHC_AIUCFG__EPC_L			26U
+#define XHC_AIUCFG__EPC_R			24U
+#define XHC_AIUCFG__EPC_WIDTH			3U
+#define XHC_AIUCFG__EPC_RESETVALUE		0x5U
+#define XHC_AIUCFG__PTQ_L			22U
+#define XHC_AIUCFG__PTQ_R			20U
+#define XHC_AIUCFG__PTQ_WIDTH			3U
+#define XHC_AIUCFG__PTQ_RESETVALUE		0x3U
+#define XHC_AIUCFG__NTQ_L			18U
+#define XHC_AIUCFG__NTQ_R			16U
+#define XHC_AIUCFG__NTQ_WIDTH			3U
+#define XHC_AIUCFG__NTQ_RESETVALUE		0x3U
+#define XHC_AIUCFG__HID				15U
+#define XHC_AIUCFG__HID_L			15U
+#define XHC_AIUCFG__HID_R			15U
+#define XHC_AIUCFG__HID_WIDTH			1U
+#define XHC_AIUCFG__HID_RESETVALUE		0x0U
+#define XHC_AIUCFG__EPS_L			14U
+#define XHC_AIUCFG__EPS_R			12U
+#define XHC_AIUCFG__EPS_WIDTH			3U
+#define XHC_AIUCFG__EPS_RESETVALUE		0x0U
+#define XHC_AIUCFG__reserved_L			11U
+#define XHC_AIUCFG__reserved_R			9U
+#define XHC_AIUCFG__reserved_WIDTH		3U
+#define XHC_AIUCFG__reserved_RESETVALUE		0x0U
+#define XHC_AIUCFG__PEP2_L			8U
+#define XHC_AIUCFG__PEP2_R			6U
+#define XHC_AIUCFG__PEP2_WIDTH			3U
+#define XHC_AIUCFG__PEP2_RESETVALUE		0x4U
+#define XHC_AIUCFG__MELADJ_L			5U
+#define XHC_AIUCFG__MELADJ_R			0U
+#define XHC_AIUCFG__MELADJ_WIDTH		6U
+#define XHC_AIUCFG__MELADJ_RESETVALUE		0x0U
+#define XHC_AIUCFG__RESERVED_0			31U
+#define XHC_AIUCFG__RESERVED_0_L		31U
+#define XHC_AIUCFG__RESERVED_0_R		31U
+#define XHC_AIUCFG__RESERVED_1			27U
+#define XHC_AIUCFG__RESERVED_1_L		27U
+#define XHC_AIUCFG__RESERVED_1_R		27U
+#define XHC_AIUCFG__RESERVED_2			23U
+#define XHC_AIUCFG__RESERVED_2_L		23U
+#define XHC_AIUCFG__RESERVED_2_R		23U
+#define XHC_AIUCFG__RESERVED_3			19U
+#define XHC_AIUCFG__RESERVED_3_L		19U
+#define XHC_AIUCFG__RESERVED_3_R		19U
+#define XHC_AIUCFG_WIDTH			31U
+#define XHC_AIUCFG__WIDTH			31U
+#define XHC_AIUCFG_ALL_L			30U
+#define XHC_AIUCFG_ALL_R			0U
+#define XHC_AIUCFG__ALL_L			30U
+#define XHC_AIUCFG__ALL_R			0U
+#define XHC_AIUCFG_DATAMASK			0x7777ffffU
+#define XHC_AIUCFG_RDWRMASK			0x88880000U
+#define XHC_AIUCFG_RESETVALUE			0x05330100U
+
+#define XHC_ECHFSC_OFFSET			0xc40U
+#define XHC_ECHFSC_BASE				0xc40U
+#define XHC_ECHFSC__reserved_L			31U
+#define XHC_ECHFSC__reserved_R			24U
+#define XHC_ECHFSC__reserved_WIDTH		8U
+#define XHC_ECHFSC__reserved_RESETVALUE		0x00U
+#define XHC_ECHFSC__WRMB_L			23U
+#define XHC_ECHFSC__WRMB_R			20U
+#define XHC_ECHFSC__WRMB_WIDTH			4U
+#define XHC_ECHFSC__WRMB_RESETVALUE		0x0U
+#define XHC_ECHFSC__RRMB_L			19U
+#define XHC_ECHFSC__RRMB_R			16U
+#define XHC_ECHFSC__RRMB_WIDTH			4U
+#define XHC_ECHFSC__RRMB_RESETVALUE		0x0U
+#define XHC_ECHFSC__NCP_L			15U
+#define XHC_ECHFSC__NCP_R			8U
+#define XHC_ECHFSC__NCP_WIDTH			8U
+#define XHC_ECHFSC__NCP_RESETVALUE		0x50U
+#define XHC_ECHFSC__CID_L			7U
+#define XHC_ECHFSC__CID_R			0U
+#define XHC_ECHFSC__CID_WIDTH			8U
+#define XHC_ECHFSC__CID_RESETVALUE		0xc3U
+#define XHC_ECHFSC_WIDTH			32U
+#define XHC_ECHFSC__WIDTH			32U
+#define XHC_ECHFSC_ALL_L			31U
+#define XHC_ECHFSC_ALL_R			0U
+#define XHC_ECHFSC__ALL_L			31U
+#define XHC_ECHFSC__ALL_R			0U
+#define XHC_ECHFSC_DATAMASK			0xffffffffU
+#define XHC_ECHFSC_RDWRMASK			0x00000000U
+#define XHC_ECHFSC_RESETVALUE			0x000050c3U
+
+#define XHC_FSCPOC_OFFSET			0xc54U
+#define XHC_FSCPOC_BASE				0xc54U
+#define XHC_FSCPOC__NCS_L			31U
+#define XHC_FSCPOC__NCS_R			28U
+#define XHC_FSCPOC__NCS_WIDTH			4U
+#define XHC_FSCPOC__NCS_RESETVALUE		0x0U
+#define XHC_FSCPOC__FSIZ_L			22U
+#define XHC_FSCPOC__FSIZ_R			18U
+#define XHC_FSCPOC__FSIZ_WIDTH			5U
+#define XHC_FSCPOC__FSIZ_RESETVALUE		0x0U
+#define XHC_FSCPOC__PSIZ_L			16U
+#define XHC_FSCPOC__PSIZ_R			12U
+#define XHC_FSCPOC__PSIZ_WIDTH			5U
+#define XHC_FSCPOC__PSIZ_RESETVALUE		0x0U
+#define XHC_FSCPOC__reserved_L			11U
+#define XHC_FSCPOC__reserved_R			5U
+#define XHC_FSCPOC__reserved_WIDTH		7U
+#define XHC_FSCPOC__reserved_RESETVALUE		0x0U
+#define XHC_FSCPOC__TSIZ_L			4U
+#define XHC_FSCPOC__TSIZ_R			0U
+#define XHC_FSCPOC__TSIZ_WIDTH			5U
+#define XHC_FSCPOC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSCPOC__RESERVED_L			27U
+#define XHC_FSCPOC__RESERVED_R			23U
+#define XHC_FSCPOC_WIDTH			32U
+#define XHC_FSCPOC__WIDTH			32U
+#define XHC_FSCPOC_ALL_L			31U
+#define XHC_FSCPOC_ALL_R			0U
+#define XHC_FSCPOC__ALL_L			31U
+#define XHC_FSCPOC__ALL_R			0U
+#define XHC_FSCPOC_DATAMASK			0xf07dffffU
+#define XHC_FSCPOC_RDWRMASK			0x0f820000U
+#define XHC_FSCPOC_RESETVALUE			0x00000000U
+
+#define XHC_FSCGOC_OFFSET			0xc58U
+#define XHC_FSCGOC_BASE				0xc58U
+#define XHC_FSCGOC__NCS_L			31U
+#define XHC_FSCGOC__NCS_R			28U
+#define XHC_FSCGOC__NCS_WIDTH			4U
+#define XHC_FSCGOC__NCS_RESETVALUE		0x0U
+#define XHC_FSCGOC__FSIZ_L			22U
+#define XHC_FSCGOC__FSIZ_R			18U
+#define XHC_FSCGOC__FSIZ_WIDTH			5U
+#define XHC_FSCGOC__FSIZ_RESETVALUE		0x0U
+#define XHC_FSCGOC__PSIZ_L			16U
+#define XHC_FSCGOC__PSIZ_R			12U
+#define XHC_FSCGOC__PSIZ_WIDTH			5U
+#define XHC_FSCGOC__PSIZ_RESETVALUE		0x0U
+#define XHC_FSCGOC__reserved_L			11U
+#define XHC_FSCGOC__reserved_R			5U
+#define XHC_FSCGOC__reserved_WIDTH		7U
+#define XHC_FSCGOC__reserved_RESETVALUE		0x0U
+#define XHC_FSCGOC__TSIZ_L			4U
+#define XHC_FSCGOC__TSIZ_R			0U
+#define XHC_FSCGOC__TSIZ_WIDTH			5U
+#define XHC_FSCGOC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSCGOC__RESERVED_L			27U
+#define XHC_FSCGOC__RESERVED_R			23U
+#define XHC_FSCGOC_WIDTH			32U
+#define XHC_FSCGOC__WIDTH			32U
+#define XHC_FSCGOC_ALL_L			31U
+#define XHC_FSCGOC_ALL_R			0U
+#define XHC_FSCGOC__ALL_L			31U
+#define XHC_FSCGOC__ALL_R			0U
+#define XHC_FSCGOC_DATAMASK			0xf07dffffU
+#define XHC_FSCGOC_RDWRMASK			0x0f820000U
+#define XHC_FSCGOC_RESETVALUE			0x00000000U
+
+#define XHC_FSCNOC_OFFSET			0xc5cU
+#define XHC_FSCNOC_BASE				0xc5cU
+#define XHC_FSCNOC__NCS_L			31U
+#define XHC_FSCNOC__NCS_R			28U
+#define XHC_FSCNOC__NCS_WIDTH			4U
+#define XHC_FSCNOC__NCS_RESETVALUE		0x0U
+#define XHC_FSCNOC__FSIZ_L			22U
+#define XHC_FSCNOC__FSIZ_R			18U
+#define XHC_FSCNOC__FSIZ_WIDTH			5U
+#define XHC_FSCNOC__FSIZ_RESETVALUE		0x0U
+#define XHC_FSCNOC__PSIZ_L			16U
+#define XHC_FSCNOC__PSIZ_R			12U
+#define XHC_FSCNOC__PSIZ_WIDTH			5U
+#define XHC_FSCNOC__PSIZ_RESETVALUE		0x0U
+#define XHC_FSCNOC__reserved_L			11U
+#define XHC_FSCNOC__reserved_R			5U
+#define XHC_FSCNOC__reserved_WIDTH		7U
+#define XHC_FSCNOC__reserved_RESETVALUE		0x0U
+#define XHC_FSCNOC__TSIZ_L			4U
+#define XHC_FSCNOC__TSIZ_R			0U
+#define XHC_FSCNOC__TSIZ_WIDTH			5U
+#define XHC_FSCNOC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSCNOC__RESERVED_L			27U
+#define XHC_FSCNOC__RESERVED_R			23U
+#define XHC_FSCNOC_WIDTH			32U
+#define XHC_FSCNOC__WIDTH			32U
+#define XHC_FSCNOC_ALL_L			31U
+#define XHC_FSCNOC_ALL_R			0U
+#define XHC_FSCNOC__ALL_L			31U
+#define XHC_FSCNOC__ALL_R			0U
+#define XHC_FSCNOC_DATAMASK			0xf07dffffU
+#define XHC_FSCNOC_RDWRMASK			0x0f820000U
+#define XHC_FSCNOC_RESETVALUE			0x00000000U
+
+#define XHC_FSCAIC_OFFSET			0xc60U
+#define XHC_FSCAIC_BASE				0xc60U
+#define XHC_FSCAIC__FSIZ_L			22U
+#define XHC_FSCAIC__FSIZ_R			18U
+#define XHC_FSCAIC__FSIZ_WIDTH			5U
+#define XHC_FSCAIC__FSIZ_RESETVALUE		0x0U
+#define XHC_FSCAIC__PSIZ_L			16U
+#define XHC_FSCAIC__PSIZ_R			12U
+#define XHC_FSCAIC__PSIZ_WIDTH			5U
+#define XHC_FSCAIC__PSIZ_RESETVALUE		0x0U
+#define XHC_FSCAIC__reserved_L			11U
+#define XHC_FSCAIC__reserved_R			0U
+#define XHC_FSCAIC__reserved_WIDTH		12U
+#define XHC_FSCAIC__reserved_RESETVALUE		0x000U
+#define XHC_FSCAIC__RESERVED_L			31U
+#define XHC_FSCAIC__RESERVED_R			23U
+#define XHC_FSCAIC_WIDTH			23U
+#define XHC_FSCAIC__WIDTH			23U
+#define XHC_FSCAIC_ALL_L			22U
+#define XHC_FSCAIC_ALL_R			0U
+#define XHC_FSCAIC__ALL_L			22U
+#define XHC_FSCAIC__ALL_R			0U
+#define XHC_FSCAIC_DATAMASK			0x007dffffU
+#define XHC_FSCAIC_RDWRMASK			0xff820000U
+#define XHC_FSCAIC_RESETVALUE			0x000000U
+
+#define XHC_FSCPIC_OFFSET			0xc64U
+#define XHC_FSCPIC_BASE				0xc64U
+#define XHC_FSCPIC__NCS_L			31U
+#define XHC_FSCPIC__NCS_R			28U
+#define XHC_FSCPIC__NCS_WIDTH			4U
+#define XHC_FSCPIC__NCS_RESETVALUE		0x0U
+#define XHC_FSCPIC__reserved_L			27U
+#define XHC_FSCPIC__reserved_R			5U
+#define XHC_FSCPIC__reserved_WIDTH		23U
+#define XHC_FSCPIC__reserved_RESETVALUE		0x0U
+#define XHC_FSCPIC__TSIZ_L			4U
+#define XHC_FSCPIC__TSIZ_R			0U
+#define XHC_FSCPIC__TSIZ_WIDTH			5U
+#define XHC_FSCPIC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSCPIC_WIDTH			32U
+#define XHC_FSCPIC__WIDTH			32U
+#define XHC_FSCPIC_ALL_L			31U
+#define XHC_FSCPIC_ALL_R			0U
+#define XHC_FSCPIC__ALL_L			31U
+#define XHC_FSCPIC__ALL_R			0U
+#define XHC_FSCPIC_DATAMASK			0xffffffffU
+#define XHC_FSCPIC_RDWRMASK			0x00000000U
+#define XHC_FSCPIC_RESETVALUE			0x00000000U
+
+#define XHC_FSCGIC_OFFSET			0xc68U
+#define XHC_FSCGIC_BASE				0xc68U
+#define XHC_FSCGIC__NCS_L			31U
+#define XHC_FSCGIC__NCS_R			28U
+#define XHC_FSCGIC__NCS_WIDTH			4U
+#define XHC_FSCGIC__NCS_RESETVALUE		0x0U
+#define XHC_FSCGIC__reserved_L			27U
+#define XHC_FSCGIC__reserved_R			5U
+#define XHC_FSCGIC__reserved_WIDTH		23U
+#define XHC_FSCGIC__reserved_RESETVALUE		0x0U
+#define XHC_FSCGIC__TSIZ_L			4U
+#define XHC_FSCGIC__TSIZ_R			0U
+#define XHC_FSCGIC__TSIZ_WIDTH			5U
+#define XHC_FSCGIC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSCGIC_WIDTH			32U
+#define XHC_FSCGIC__WIDTH			32U
+#define XHC_FSCGIC_ALL_L			31U
+#define XHC_FSCGIC_ALL_R			0U
+#define XHC_FSCGIC__ALL_L			31U
+#define XHC_FSCGIC__ALL_R			0U
+#define XHC_FSCGIC_DATAMASK			0xffffffffU
+#define XHC_FSCGIC_RDWRMASK			0x00000000U
+#define XHC_FSCGIC_RESETVALUE			0x00000000U
+
+#define XHC_FSCNIC_OFFSET			0xc6cU
+#define XHC_FSCNIC_BASE				0xc6cU
+#define XHC_FSCNIC__NCS_L			31U
+#define XHC_FSCNIC__NCS_R			28U
+#define XHC_FSCNIC__NCS_WIDTH			4U
+#define XHC_FSCNIC__NCS_RESETVALUE		0x0U
+#define XHC_FSCNIC__reserved_L			27U
+#define XHC_FSCNIC__reserved_R			5U
+#define XHC_FSCNIC__reserved_WIDTH		23U
+#define XHC_FSCNIC__reserved_RESETVALUE		0x0U
+#define XHC_FSCNIC__TSIZ_L			4U
+#define XHC_FSCNIC__TSIZ_R			0U
+#define XHC_FSCNIC__TSIZ_WIDTH			5U
+#define XHC_FSCNIC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSCNIC_WIDTH			32U
+#define XHC_FSCNIC__WIDTH			32U
+#define XHC_FSCNIC_ALL_L			31U
+#define XHC_FSCNIC_ALL_R			0U
+#define XHC_FSCNIC__ALL_L			31U
+#define XHC_FSCNIC__ALL_R			0U
+#define XHC_FSCNIC_DATAMASK			0xffffffffU
+#define XHC_FSCNIC_RDWRMASK			0x00000000U
+#define XHC_FSCNIC_RESETVALUE			0x00000000U
+
+#define XHC_ECHPRT_OFFSET			0xc70U
+#define XHC_ECHPRT_BASE				0xc70U
+#define XHC_ECHPRT__TDP				31U
+#define XHC_ECHPRT__TDP_L			31U
+#define XHC_ECHPRT__TDP_R			31U
+#define XHC_ECHPRT__TDP_WIDTH			1U
+#define XHC_ECHPRT__TDP_RESETVALUE		0x0U
+#define XHC_ECHPRT__RDP				30U
+#define XHC_ECHPRT__RDP_L			30U
+#define XHC_ECHPRT__RDP_R			30U
+#define XHC_ECHPRT__RDP_WIDTH			1U
+#define XHC_ECHPRT__RDP_RESETVALUE		0x0U
+#define XHC_ECHPRT__reserved_L			29U
+#define XHC_ECHPRT__reserved_R			25U
+#define XHC_ECHPRT__reserved_WIDTH		5U
+#define XHC_ECHPRT__reserved_RESETVALUE		0x0U
+#define XHC_ECHPRT__MFT_L			24U
+#define XHC_ECHPRT__MFT_R			17U
+#define XHC_ECHPRT__MFT_WIDTH			8U
+#define XHC_ECHPRT__MFT_RESETVALUE		0x7dU
+#define XHC_ECHPRT__HST				16U
+#define XHC_ECHPRT__HST_L			16U
+#define XHC_ECHPRT__HST_R			16U
+#define XHC_ECHPRT__HST_WIDTH			1U
+#define XHC_ECHPRT__HST_RESETVALUE		0x0U
+#define XHC_ECHPRT__NCP_L			15U
+#define XHC_ECHPRT__NCP_R			8U
+#define XHC_ECHPRT__NCP_WIDTH			8U
+#define XHC_ECHPRT__NCP_RESETVALUE		0x04U
+#define XHC_ECHPRT__CID_L			7U
+#define XHC_ECHPRT__CID_R			0U
+#define XHC_ECHPRT__CID_WIDTH			8U
+#define XHC_ECHPRT__CID_RESETVALUE		0xc4U
+#define XHC_ECHPRT_WIDTH			32U
+#define XHC_ECHPRT__WIDTH			32U
+#define XHC_ECHPRT_ALL_L			31U
+#define XHC_ECHPRT_ALL_R			0U
+#define XHC_ECHPRT__ALL_L			31U
+#define XHC_ECHPRT__ALL_R			0U
+#define XHC_ECHPRT_DATAMASK			0xffffffffU
+#define XHC_ECHPRT_RDWRMASK			0x00000000U
+#define XHC_ECHPRT_RESETVALUE			0x00fa04c4U
+
+#define XHC_PRTHSC_OFFSET			0xc78U
+#define XHC_PRTHSC_BASE				0xc78U
+#define XHC_PRTHSC__TMR_L			31U
+#define XHC_PRTHSC__TMR_R			16U
+#define XHC_PRTHSC__TMR_WIDTH			16U
+#define XHC_PRTHSC__TMR_RESETVALUE		0x0000U
+#define XHC_PRTHSC__RSL_L			7U
+#define XHC_PRTHSC__RSL_R			6U
+#define XHC_PRTHSC__RSL_WIDTH			2U
+#define XHC_PRTHSC__RSL_RESETVALUE		0x0U
+#define XHC_PRTHSC__AS_M_L			5U
+#define XHC_PRTHSC__AS_M_R			4U
+#define XHC_PRTHSC__AS_M_WIDTH			2U
+#define XHC_PRTHSC__AS_M_RESETVALUE		0x0U
+#define XHC_PRTHSC__CMD_L			3U
+#define XHC_PRTHSC__CMD_R			2U
+#define XHC_PRTHSC__CMD_WIDTH			2U
+#define XHC_PRTHSC__CMD_RESETVALUE		0x0U
+#define XHC_PRTHSC__reserved			1U
+#define XHC_PRTHSC__reserved_L			1U
+#define XHC_PRTHSC__reserved_R			1U
+#define XHC_PRTHSC__reserved_WIDTH		1U
+#define XHC_PRTHSC__reserved_RESETVALUE		0x0U
+#define XHC_PRTHSC__STB				0U
+#define XHC_PRTHSC__STB_L			0U
+#define XHC_PRTHSC__STB_R			0U
+#define XHC_PRTHSC__STB_WIDTH			1U
+#define XHC_PRTHSC__STB_RESETVALUE		0x0U
+#define XHC_PRTHSC__RESERVED_L			15U
+#define XHC_PRTHSC__RESERVED_R			8U
+#define XHC_PRTHSC_WIDTH			32U
+#define XHC_PRTHSC__WIDTH			32U
+#define XHC_PRTHSC_ALL_L			31U
+#define XHC_PRTHSC_ALL_R			0U
+#define XHC_PRTHSC__ALL_L			31U
+#define XHC_PRTHSC__ALL_R			0U
+#define XHC_PRTHSC_DATAMASK			0xffff00ffU
+#define XHC_PRTHSC_RDWRMASK			0x0000ff00U
+#define XHC_PRTHSC_RESETVALUE			0x00000000U
+
+#define XHC_PRTHSR_OFFSET			0xc7cU
+#define XHC_PRTHSR_BASE				0xc7cU
+#define XHC_PRTHSR__RDLY_L			31U
+#define XHC_PRTHSR__RDLY_R			24U
+#define XHC_PRTHSR__RDLY_WIDTH			8U
+#define XHC_PRTHSR__RDLY_RESETVALUE		0x00U
+#define XHC_PRTHSR__TDPP_L			23U
+#define XHC_PRTHSR__TDPP_R			16U
+#define XHC_PRTHSR__TDPP_WIDTH			8U
+#define XHC_PRTHSR__TDPP_RESETVALUE		0x00U
+#define XHC_PRTHSR__RDPP_L			15U
+#define XHC_PRTHSR__RDPP_R			8U
+#define XHC_PRTHSR__RDPP_WIDTH			8U
+#define XHC_PRTHSR__RDPP_RESETVALUE		0x00U
+#define XHC_PRTHSR__TRTY_L			7U
+#define XHC_PRTHSR__TRTY_R			0U
+#define XHC_PRTHSR__TRTY_WIDTH			8U
+#define XHC_PRTHSR__TRTY_RESETVALUE		0x00U
+#define XHC_PRTHSR_WIDTH			32U
+#define XHC_PRTHSR__WIDTH			32U
+#define XHC_PRTHSR_ALL_L			31U
+#define XHC_PRTHSR_ALL_R			0U
+#define XHC_PRTHSR__ALL_L			31U
+#define XHC_PRTHSR__ALL_R			0U
+#define XHC_PRTHSR_DATAMASK			0xffffffffU
+#define XHC_PRTHSR_RDWRMASK			0x00000000U
+#define XHC_PRTHSR_RESETVALUE			0x00000000U
+
+#define XHC_ECHRHS_OFFSET			0xc80U
+#define XHC_ECHRHS_BASE				0xc80U
+#define XHC_ECHRHS__RPO_L			30U
+#define XHC_ECHRHS__RPO_R			24U
+#define XHC_ECHRHS__RPO_WIDTH			7U
+#define XHC_ECHRHS__RPO_RESETVALUE		0x0U
+#define XHC_ECHRHS__reserved_L			23U
+#define XHC_ECHRHS__reserved_R			22U
+#define XHC_ECHRHS__reserved_WIDTH		2U
+#define XHC_ECHRHS__reserved_RESETVALUE		0x0U
+#define XHC_ECHRHS__RPN_L			21U
+#define XHC_ECHRHS__RPN_R			20U
+#define XHC_ECHRHS__RPN_WIDTH			2U
+#define XHC_ECHRHS__RPN_RESETVALUE		0x0U
+#define XHC_ECHRHS__DNR_L			19U
+#define XHC_ECHRHS__DNR_R			16U
+#define XHC_ECHRHS__DNR_WIDTH			4U
+#define XHC_ECHRHS__DNR_RESETVALUE		0x0U
+#define XHC_ECHRHS__NCP_L			15U
+#define XHC_ECHRHS__NCP_R			8U
+#define XHC_ECHRHS__NCP_WIDTH			8U
+#define XHC_ECHRHS__NCP_RESETVALUE		0x0cU
+#define XHC_ECHRHS__CID_L			7U
+#define XHC_ECHRHS__CID_R			0U
+#define XHC_ECHRHS__CID_WIDTH			8U
+#define XHC_ECHRHS__CID_RESETVALUE		0xc8U
+#define XHC_ECHRHS__RESERVED			31U
+#define XHC_ECHRHS__RESERVED_L			31U
+#define XHC_ECHRHS__RESERVED_R			31U
+#define XHC_ECHRHS_WIDTH			31U
+#define XHC_ECHRHS__WIDTH			31U
+#define XHC_ECHRHS_ALL_L			30U
+#define XHC_ECHRHS_ALL_R			0U
+#define XHC_ECHRHS__ALL_L			30U
+#define XHC_ECHRHS__ALL_R			0U
+#define XHC_ECHRHS_DATAMASK			0x7fffffffU
+#define XHC_ECHRHS_RDWRMASK			0x80000000U
+#define XHC_ECHRHS_RESETVALUE			0x00000cc8U
+
+#define XHC_RHSDES_OFFSET			0xc84U
+#define XHC_RHSDES_BASE				0xc84U
+#define XHC_RHSDES__PIS3_L			31U
+#define XHC_RHSDES__PIS3_R			30U
+#define XHC_RHSDES__PIS3_WIDTH			2U
+#define XHC_RHSDES__PIS3_RESETVALUE		0x0U
+#define XHC_RHSDES__HIST3			24U
+#define XHC_RHSDES__HIST3_L			24U
+#define XHC_RHSDES__HIST3_R			24U
+#define XHC_RHSDES__HIST3_WIDTH			1U
+#define XHC_RHSDES__HIST3_RESETVALUE		0x0U
+#define XHC_RHSDES__PIS2_L			23U
+#define XHC_RHSDES__PIS2_R			22U
+#define XHC_RHSDES__PIS2_WIDTH			2U
+#define XHC_RHSDES__PIS2_RESETVALUE		0x0U
+#define XHC_RHSDES__HIST2			16U
+#define XHC_RHSDES__HIST2_L			16U
+#define XHC_RHSDES__HIST2_R			16U
+#define XHC_RHSDES__HIST2_WIDTH			1U
+#define XHC_RHSDES__HIST2_RESETVALUE		0x0U
+#define XHC_RHSDES__PIS1_L			15U
+#define XHC_RHSDES__PIS1_R			14U
+#define XHC_RHSDES__PIS1_WIDTH			2U
+#define XHC_RHSDES__PIS1_RESETVALUE		0x0U
+#define XHC_RHSDES__HIST1			8U
+#define XHC_RHSDES__HIST1_L			8U
+#define XHC_RHSDES__HIST1_R			8U
+#define XHC_RHSDES__HIST1_WIDTH			1U
+#define XHC_RHSDES__HIST1_RESETVALUE		0x0U
+#define XHC_RHSDES__PIS0_L			7U
+#define XHC_RHSDES__PIS0_R			6U
+#define XHC_RHSDES__PIS0_WIDTH			2U
+#define XHC_RHSDES__PIS0_RESETVALUE		0x0U
+#define XHC_RHSDES__reserved_L			5U
+#define XHC_RHSDES__reserved_R			1U
+#define XHC_RHSDES__reserved_WIDTH		5U
+#define XHC_RHSDES__reserved_RESETVALUE		0x0U
+#define XHC_RHSDES__HIST0			0U
+#define XHC_RHSDES__HIST0_L			0U
+#define XHC_RHSDES__HIST0_R			0U
+#define XHC_RHSDES__HIST0_WIDTH			1U
+#define XHC_RHSDES__HIST0_RESETVALUE		0x0U
+#define XHC_RHSDES__RESERVED_0_L		29U
+#define XHC_RHSDES__RESERVED_0_R		25U
+#define XHC_RHSDES__RESERVED_1_L		21U
+#define XHC_RHSDES__RESERVED_1_R		17U
+#define XHC_RHSDES__RESERVED_2_L		13U
+#define XHC_RHSDES__RESERVED_2_R		9U
+#define XHC_RHSDES__RESERVED_L			29U
+#define XHC_RHSDES__RESERVED_R			25U
+#define XHC_RHSDES_WIDTH			32U
+#define XHC_RHSDES__WIDTH			32U
+#define XHC_RHSDES_ALL_L			31U
+#define XHC_RHSDES_ALL_R			0U
+#define XHC_RHSDES__ALL_L			31U
+#define XHC_RHSDES__ALL_R			0U
+#define XHC_RHSDES_DATAMASK			0xc1c1c1ffU
+#define XHC_RHSDES_RDWRMASK			0x3e3e3e00U
+#define XHC_RHSDES_RESETVALUE			0x00000000U
+
+#define XHC_RHSHSC0_OFFSET			0xc90U
+#define XHC_RHSHSC0_BASE			0xc90U
+#define XHC_RHSHSC0__TMR_L			31U
+#define XHC_RHSHSC0__TMR_R			16U
+#define XHC_RHSHSC0__TMR_WIDTH			16U
+#define XHC_RHSHSC0__TMR_RESETVALUE		0x0000U
+#define XHC_RHSHSC0__RSL_L			7U
+#define XHC_RHSHSC0__RSL_R			6U
+#define XHC_RHSHSC0__RSL_WIDTH			2U
+#define XHC_RHSHSC0__RSL_RESETVALUE		0x0U
+#define XHC_RHSHSC0__AS_M_L			5U
+#define XHC_RHSHSC0__AS_M_R			4U
+#define XHC_RHSHSC0__AS_M_WIDTH			2U
+#define XHC_RHSHSC0__AS_M_RESETVALUE		0x0U
+#define XHC_RHSHSC0__CMD_L			3U
+#define XHC_RHSHSC0__CMD_R			2U
+#define XHC_RHSHSC0__CMD_WIDTH			2U
+#define XHC_RHSHSC0__CMD_RESETVALUE		0x0U
+#define XHC_RHSHSC0__reserved			1U
+#define XHC_RHSHSC0__reserved_L			1U
+#define XHC_RHSHSC0__reserved_R			1U
+#define XHC_RHSHSC0__reserved_WIDTH		1U
+#define XHC_RHSHSC0__reserved_RESETVALUE	0x0U
+#define XHC_RHSHSC0__STB			0U
+#define XHC_RHSHSC0__STB_L			0U
+#define XHC_RHSHSC0__STB_R			0U
+#define XHC_RHSHSC0__STB_WIDTH			1U
+#define XHC_RHSHSC0__STB_RESETVALUE		0x0U
+#define XHC_RHSHSC0__RESERVED_L			15U
+#define XHC_RHSHSC0__RESERVED_R			8U
+#define XHC_RHSHSC0_WIDTH			32U
+#define XHC_RHSHSC0__WIDTH			32U
+#define XHC_RHSHSC0_ALL_L			31U
+#define XHC_RHSHSC0_ALL_R			0U
+#define XHC_RHSHSC0__ALL_L			31U
+#define XHC_RHSHSC0__ALL_R			0U
+#define XHC_RHSHSC0_DATAMASK			0xffff00ffU
+#define XHC_RHSHSC0_RDWRMASK			0x0000ff00U
+#define XHC_RHSHSC0_RESETVALUE			0x00000000U
+
+#define XHC_RHSHSR0_OFFSET			0xc94U
+#define XHC_RHSHSR0_BASE			0xc94U
+#define XHC_RHSHSR0__C2U_L			31U
+#define XHC_RHSHSR0__C2U_R			24U
+#define XHC_RHSHSR0__C2U_WIDTH			8U
+#define XHC_RHSHSR0__C2U_RESETVALUE		0x00U
+#define XHC_RHSHSR0__C1U_L			23U
+#define XHC_RHSHSR0__C1U_R			16U
+#define XHC_RHSHSR0__C1U_WIDTH			8U
+#define XHC_RHSHSR0__C1U_RESETVALUE		0x00U
+#define XHC_RHSHSR0__RCV_L			15U
+#define XHC_RHSHSR0__RCV_R			8U
+#define XHC_RHSHSR0__RCV_WIDTH			8U
+#define XHC_RHSHSR0__RCV_RESETVALUE		0x00U
+#define XHC_RHSHSR0__RTY_L			7U
+#define XHC_RHSHSR0__RTY_R			0U
+#define XHC_RHSHSR0__RTY_WIDTH			8U
+#define XHC_RHSHSR0__RTY_RESETVALUE		0x00U
+#define XHC_RHSHSR0_WIDTH			32U
+#define XHC_RHSHSR0__WIDTH			32U
+#define XHC_RHSHSR0_ALL_L			31U
+#define XHC_RHSHSR0_ALL_R			0U
+#define XHC_RHSHSR0__ALL_L			31U
+#define XHC_RHSHSR0__ALL_R			0U
+#define XHC_RHSHSR0_DATAMASK			0xffffffffU
+#define XHC_RHSHSR0_RDWRMASK			0x00000000U
+#define XHC_RHSHSR0_RESETVALUE			0x00000000U
+
+#define XHC_RHSHSC1_OFFSET			0xc98U
+#define XHC_RHSHSC1_BASE			0xc98U
+#define XHC_RHSHSC1__TMR_L			31U
+#define XHC_RHSHSC1__TMR_R			16U
+#define XHC_RHSHSC1__TMR_WIDTH			16U
+#define XHC_RHSHSC1__TMR_RESETVALUE		0x0000U
+#define XHC_RHSHSC1__RSL_L			7U
+#define XHC_RHSHSC1__RSL_R			6U
+#define XHC_RHSHSC1__RSL_WIDTH			2U
+#define XHC_RHSHSC1__RSL_RESETVALUE		0x0U
+#define XHC_RHSHSC1__AS_M_L			5U
+#define XHC_RHSHSC1__AS_M_R			4U
+#define XHC_RHSHSC1__AS_M_WIDTH			2U
+#define XHC_RHSHSC1__AS_M_RESETVALUE		0x0U
+#define XHC_RHSHSC1__CMD_L			3U
+#define XHC_RHSHSC1__CMD_R			2U
+#define XHC_RHSHSC1__CMD_WIDTH			2U
+#define XHC_RHSHSC1__CMD_RESETVALUE		0x0U
+#define XHC_RHSHSC1__reserved			1U
+#define XHC_RHSHSC1__reserved_L			1U
+#define XHC_RHSHSC1__reserved_R			1U
+#define XHC_RHSHSC1__reserved_WIDTH		1U
+#define XHC_RHSHSC1__reserved_RESETVALUE	0x0U
+#define XHC_RHSHSC1__STB			0U
+#define XHC_RHSHSC1__STB_L			0U
+#define XHC_RHSHSC1__STB_R			0U
+#define XHC_RHSHSC1__STB_WIDTH			1U
+#define XHC_RHSHSC1__STB_RESETVALUE		0x0U
+#define XHC_RHSHSC1__RESERVED_L			15U
+#define XHC_RHSHSC1__RESERVED_R			8U
+#define XHC_RHSHSC1_WIDTH			32U
+#define XHC_RHSHSC1__WIDTH			32U
+#define XHC_RHSHSC1_ALL_L			31U
+#define XHC_RHSHSC1_ALL_R			0U
+#define XHC_RHSHSC1__ALL_L			31U
+#define XHC_RHSHSC1__ALL_R			0U
+#define XHC_RHSHSC1_DATAMASK			0xffff00ffU
+#define XHC_RHSHSC1_RDWRMASK			0x0000ff00U
+#define XHC_RHSHSC1_RESETVALUE			0x00000000U
+
+#define XHC_RHSHSR1_OFFSET			0xc9cU
+#define XHC_RHSHSR1_BASE			0xc9cU
+#define XHC_RHSHSR1__C2U_L			31U
+#define XHC_RHSHSR1__C2U_R			24U
+#define XHC_RHSHSR1__C2U_WIDTH			8U
+#define XHC_RHSHSR1__C2U_RESETVALUE		0x00U
+#define XHC_RHSHSR1__C1U_L			23U
+#define XHC_RHSHSR1__C1U_R			16U
+#define XHC_RHSHSR1__C1U_WIDTH			8U
+#define XHC_RHSHSR1__C1U_RESETVALUE		0x00U
+#define XHC_RHSHSR1__RCV_L			15U
+#define XHC_RHSHSR1__RCV_R			8U
+#define XHC_RHSHSR1__RCV_WIDTH			8U
+#define XHC_RHSHSR1__RCV_RESETVALUE		0x00U
+#define XHC_RHSHSR1__RTY_L			7U
+#define XHC_RHSHSR1__RTY_R			0U
+#define XHC_RHSHSR1__RTY_WIDTH			8U
+#define XHC_RHSHSR1__RTY_RESETVALUE		0x00U
+#define XHC_RHSHSR1_WIDTH			32U
+#define XHC_RHSHSR1__WIDTH			32U
+#define XHC_RHSHSR1_ALL_L			31U
+#define XHC_RHSHSR1_ALL_R			0U
+#define XHC_RHSHSR1__ALL_L			31U
+#define XHC_RHSHSR1__ALL_R			0U
+#define XHC_RHSHSR1_DATAMASK			0xffffffffU
+#define XHC_RHSHSR1_RDWRMASK			0x00000000U
+#define XHC_RHSHSR1_RESETVALUE			0x00000000U
+
+#define XHC_RHSHSC2_OFFSET			0xca0U
+#define XHC_RHSHSC2_BASE			0xca0U
+#define XHC_RHSHSC2__TMR_L			31U
+#define XHC_RHSHSC2__TMR_R			16U
+#define XHC_RHSHSC2__TMR_WIDTH			16U
+#define XHC_RHSHSC2__TMR_RESETVALUE		0x0000U
+#define XHC_RHSHSC2__RSL_L			7U
+#define XHC_RHSHSC2__RSL_R			6U
+#define XHC_RHSHSC2__RSL_WIDTH			2U
+#define XHC_RHSHSC2__RSL_RESETVALUE		0x0U
+#define XHC_RHSHSC2__AS_M_L			5U
+#define XHC_RHSHSC2__AS_M_R			4U
+#define XHC_RHSHSC2__AS_M_WIDTH			2U
+#define XHC_RHSHSC2__AS_M_RESETVALUE		0x0U
+#define XHC_RHSHSC2__CMD_L			3U
+#define XHC_RHSHSC2__CMD_R			2U
+#define XHC_RHSHSC2__CMD_WIDTH			2U
+#define XHC_RHSHSC2__CMD_RESETVALUE		0x0U
+#define XHC_RHSHSC2__reserved			1U
+#define XHC_RHSHSC2__reserved_L			1U
+#define XHC_RHSHSC2__reserved_R			1U
+#define XHC_RHSHSC2__reserved_WIDTH		1U
+#define XHC_RHSHSC2__reserved_RESETVALUE	0x0U
+#define XHC_RHSHSC2__STB			0U
+#define XHC_RHSHSC2__STB_L			0U
+#define XHC_RHSHSC2__STB_R			0U
+#define XHC_RHSHSC2__STB_WIDTH			1U
+#define XHC_RHSHSC2__STB_RESETVALUE		0x0U
+#define XHC_RHSHSC2__RESERVED_L			15U
+#define XHC_RHSHSC2__RESERVED_R			8U
+#define XHC_RHSHSC2_WIDTH			32U
+#define XHC_RHSHSC2__WIDTH			32U
+#define XHC_RHSHSC2_ALL_L			31U
+#define XHC_RHSHSC2_ALL_R			0U
+#define XHC_RHSHSC2__ALL_L			31U
+#define XHC_RHSHSC2__ALL_R			0U
+#define XHC_RHSHSC2_DATAMASK			0xffff00ffU
+#define XHC_RHSHSC2_RDWRMASK			0x0000ff00U
+#define XHC_RHSHSC2_RESETVALUE			0x00000000U
+
+#define XHC_RHSHSR2_OFFSET			0xca4U
+#define XHC_RHSHSR2_BASE			0xca4U
+#define XHC_RHSHSR2__C2U_L			31U
+#define XHC_RHSHSR2__C2U_R			24U
+#define XHC_RHSHSR2__C2U_WIDTH			8U
+#define XHC_RHSHSR2__C2U_RESETVALUE		0x00U
+#define XHC_RHSHSR2__C1U_L			23U
+#define XHC_RHSHSR2__C1U_R			16U
+#define XHC_RHSHSR2__C1U_WIDTH			8U
+#define XHC_RHSHSR2__C1U_RESETVALUE		0x00U
+#define XHC_RHSHSR2__RCV_L			15U
+#define XHC_RHSHSR2__RCV_R			8U
+#define XHC_RHSHSR2__RCV_WIDTH			8U
+#define XHC_RHSHSR2__RCV_RESETVALUE		0x00U
+#define XHC_RHSHSR2__RTY_L			7U
+#define XHC_RHSHSR2__RTY_R			0U
+#define XHC_RHSHSR2__RTY_WIDTH			8U
+#define XHC_RHSHSR2__RTY_RESETVALUE		0x00U
+#define XHC_RHSHSR2_WIDTH			32U
+#define XHC_RHSHSR2__WIDTH			32U
+#define XHC_RHSHSR2_ALL_L			31U
+#define XHC_RHSHSR2_ALL_R			0U
+#define XHC_RHSHSR2__ALL_L			31U
+#define XHC_RHSHSR2__ALL_R			0U
+#define XHC_RHSHSR2_DATAMASK			0xffffffffU
+#define XHC_RHSHSR2_RDWRMASK			0x00000000U
+#define XHC_RHSHSR2_RESETVALUE			0x00000000U
+
+#define XHC_RHSHSC3_OFFSET			0xca8U
+#define XHC_RHSHSC3_BASE			0xca8U
+#define XHC_RHSHSC3__TMR_L			31U
+#define XHC_RHSHSC3__TMR_R			16U
+#define XHC_RHSHSC3__TMR_WIDTH			16U
+#define XHC_RHSHSC3__TMR_RESETVALUE		0x0000U
+#define XHC_RHSHSC3__RSL_L			7U
+#define XHC_RHSHSC3__RSL_R			6U
+#define XHC_RHSHSC3__RSL_WIDTH			2U
+#define XHC_RHSHSC3__RSL_RESETVALUE		0x0U
+#define XHC_RHSHSC3__AS_M_L			5U
+#define XHC_RHSHSC3__AS_M_R			4U
+#define XHC_RHSHSC3__AS_M_WIDTH			2U
+#define XHC_RHSHSC3__AS_M_RESETVALUE		0x0U
+#define XHC_RHSHSC3__CMD_L			3U
+#define XHC_RHSHSC3__CMD_R			2U
+#define XHC_RHSHSC3__CMD_WIDTH			2U
+#define XHC_RHSHSC3__CMD_RESETVALUE		0x0U
+#define XHC_RHSHSC3__reserved			1U
+#define XHC_RHSHSC3__reserved_L			1U
+#define XHC_RHSHSC3__reserved_R			1U
+#define XHC_RHSHSC3__reserved_WIDTH		1U
+#define XHC_RHSHSC3__reserved_RESETVALUE	0x0U
+#define XHC_RHSHSC3__STB			0U
+#define XHC_RHSHSC3__STB_L			0U
+#define XHC_RHSHSC3__STB_R			0U
+#define XHC_RHSHSC3__STB_WIDTH			1U
+#define XHC_RHSHSC3__STB_RESETVALUE		0x0U
+#define XHC_RHSHSC3__RESERVED_L			15U
+#define XHC_RHSHSC3__RESERVED_R			8U
+#define XHC_RHSHSC3_WIDTH			32U
+#define XHC_RHSHSC3__WIDTH			32U
+#define XHC_RHSHSC3_ALL_L			31U
+#define XHC_RHSHSC3_ALL_R			0U
+#define XHC_RHSHSC3__ALL_L			31U
+#define XHC_RHSHSC3__ALL_R			0U
+#define XHC_RHSHSC3_DATAMASK			0xffff00ffU
+#define XHC_RHSHSC3_RDWRMASK			0x0000ff00U
+#define XHC_RHSHSC3_RESETVALUE			0x00000000U
+
+#define XHC_RHSHSR3_OFFSET			0xcacU
+#define XHC_RHSHSR3_BASE			0xcacU
+#define XHC_RHSHSR3__C2U_L			31U
+#define XHC_RHSHSR3__C2U_R			24U
+#define XHC_RHSHSR3__C2U_WIDTH			8U
+#define XHC_RHSHSR3__C2U_RESETVALUE		0x00U
+#define XHC_RHSHSR3__C1U_L			23U
+#define XHC_RHSHSR3__C1U_R			16U
+#define XHC_RHSHSR3__C1U_WIDTH			8U
+#define XHC_RHSHSR3__C1U_RESETVALUE		0x00U
+#define XHC_RHSHSR3__RCV_L			15U
+#define XHC_RHSHSR3__RCV_R			8U
+#define XHC_RHSHSR3__RCV_WIDTH			8U
+#define XHC_RHSHSR3__RCV_RESETVALUE		0x00U
+#define XHC_RHSHSR3__RTY_L			7U
+#define XHC_RHSHSR3__RTY_R			0U
+#define XHC_RHSHSR3__RTY_WIDTH			8U
+#define XHC_RHSHSR3__RTY_RESETVALUE		0x00U
+#define XHC_RHSHSR3_WIDTH			32U
+#define XHC_RHSHSR3__WIDTH			32U
+#define XHC_RHSHSR3_ALL_L			31U
+#define XHC_RHSHSR3_ALL_R			0U
+#define XHC_RHSHSR3__ALL_L			31U
+#define XHC_RHSHSR3__ALL_R			0U
+#define XHC_RHSHSR3_DATAMASK			0xffffffffU
+#define XHC_RHSHSR3_RDWRMASK			0x00000000U
+#define XHC_RHSHSR3_RESETVALUE			0x00000000U
+
+#define XHC_ECHSSP_OFFSET			0xcb0U
+#define XHC_ECHSSP_BASE				0xcb0U
+#define XHC_ECHSSP__reserved_L			31U
+#define XHC_ECHSSP__reserved_R			16U
+#define XHC_ECHSSP__reserved_WIDTH		16U
+#define XHC_ECHSSP__reserved_RESETVALUE		0x0000U
+#define XHC_ECHSSP__NCP_L			15U
+#define XHC_ECHSSP__NCP_R			8U
+#define XHC_ECHSSP__NCP_WIDTH			8U
+#define XHC_ECHSSP__NCP_RESETVALUE		0x04U
+#define XHC_ECHSSP__CID_L			7U
+#define XHC_ECHSSP__CID_R			0U
+#define XHC_ECHSSP__CID_WIDTH			8U
+#define XHC_ECHSSP__CID_RESETVALUE		0xc6U
+#define XHC_ECHSSP_WIDTH			32U
+#define XHC_ECHSSP__WIDTH			32U
+#define XHC_ECHSSP_ALL_L			31U
+#define XHC_ECHSSP_ALL_R			0U
+#define XHC_ECHSSP__ALL_L			31U
+#define XHC_ECHSSP__ALL_R			0U
+#define XHC_ECHSSP_DATAMASK			0xffffffffU
+#define XHC_ECHSSP_RDWRMASK			0x00000000U
+#define XHC_ECHSSP_RESETVALUE			0x000004c6U
+
+#define XHC_SSPVER_OFFSET			0xcb4U
+#define XHC_SSPVER_BASE				0xcb4U
+#define XHC_SSPVER__MAJ_L			31U
+#define XHC_SSPVER__MAJ_R			28U
+#define XHC_SSPVER__MAJ_WIDTH			4U
+#define XHC_SSPVER__MAJ_RESETVALUE		0x0U
+#define XHC_SSPVER__MIN_L			27U
+#define XHC_SSPVER__MIN_R			24U
+#define XHC_SSPVER__MIN_WIDTH			4U
+#define XHC_SSPVER__MIN_RESETVALUE		0x0U
+#define XHC_SSPVER__RLS_L			23U
+#define XHC_SSPVER__RLS_R			20U
+#define XHC_SSPVER__RLS_WIDTH			4U
+#define XHC_SSPVER__RLS_RESETVALUE		0x0U
+#define XHC_SSPVER__reserved_L			19U
+#define XHC_SSPVER__reserved_R			0U
+#define XHC_SSPVER__reserved_WIDTH		20U
+#define XHC_SSPVER__reserved_RESETVALUE		0x00000U
+#define XHC_SSPVER_WIDTH			32U
+#define XHC_SSPVER__WIDTH			32U
+#define XHC_SSPVER_ALL_L			31U
+#define XHC_SSPVER_ALL_R			0U
+#define XHC_SSPVER__ALL_L			31U
+#define XHC_SSPVER__ALL_R			0U
+#define XHC_SSPVER_DATAMASK			0xffffffffU
+#define XHC_SSPVER_RDWRMASK			0x00000000U
+#define XHC_SSPVER_RESETVALUE			0x00000000U
+
+#define XHC_SSPMGN_OFFSET			0xcb8U
+#define XHC_SSPMGN_BASE				0xcb8U
+#define XHC_SSPMGN__MGN_L			31U
+#define XHC_SSPMGN__MGN_R			0U
+#define XHC_SSPMGN__MGN_WIDTH			32U
+#define XHC_SSPMGN__MGN_RESETVALUE		0x4b535040U
+#define XHC_SSPMGN_WIDTH			32U
+#define XHC_SSPMGN__WIDTH			32U
+#define XHC_SSPMGN_ALL_L			31U
+#define XHC_SSPMGN_ALL_R			0U
+#define XHC_SSPMGN__ALL_L			31U
+#define XHC_SSPMGN__ALL_R			0U
+#define XHC_SSPMGN_DATAMASK			0xffffffffU
+#define XHC_SSPMGN_RDWRMASK			0x00000000U
+#define XHC_SSPMGN_RESETVALUE			0x4b535040U
+
+#define XHC_ECHFSC2_OFFSET			0xcc0U
+#define XHC_ECHFSC2_BASE			0xcc0U
+#define XHC_ECHFSC2__reserved_L			31U
+#define XHC_ECHFSC2__reserved_R			16U
+#define XHC_ECHFSC2__reserved_WIDTH		16U
+#define XHC_ECHFSC2__reserved_RESETVALUE	0x0000U
+#define XHC_ECHFSC2__NCP_L			15U
+#define XHC_ECHFSC2__NCP_R			8U
+#define XHC_ECHFSC2__NCP_WIDTH			8U
+#define XHC_ECHFSC2__NCP_RESETVALUE		0x50U
+#define XHC_ECHFSC2__CID_L			7U
+#define XHC_ECHFSC2__CID_R			0U
+#define XHC_ECHFSC2__CID_WIDTH			8U
+#define XHC_ECHFSC2__CID_RESETVALUE		0xc7U
+#define XHC_ECHFSC2_WIDTH			32U
+#define XHC_ECHFSC2__WIDTH			32U
+#define XHC_ECHFSC2_ALL_L			31U
+#define XHC_ECHFSC2_ALL_R			0U
+#define XHC_ECHFSC2__ALL_L			31U
+#define XHC_ECHFSC2__ALL_R			0U
+#define XHC_ECHFSC2_DATAMASK			0xffffffffU
+#define XHC_ECHFSC2_RDWRMASK			0x00000000U
+#define XHC_ECHFSC2_RESETVALUE			0x000050c7U
+
+#define XHC_FSC2POC_OFFSET			0xcd4U
+#define XHC_FSC2POC_BASE			0xcd4U
+#define XHC_FSC2POC__NCS_L			31U
+#define XHC_FSC2POC__NCS_R			28U
+#define XHC_FSC2POC__NCS_WIDTH			4U
+#define XHC_FSC2POC__NCS_RESETVALUE		0x0U
+#define XHC_FSC2POC__FSIZ_L			22U
+#define XHC_FSC2POC__FSIZ_R			18U
+#define XHC_FSC2POC__FSIZ_WIDTH			5U
+#define XHC_FSC2POC__FSIZ_RESETVALUE		0x0U
+#define XHC_FSC2POC__PSIZ_L			16U
+#define XHC_FSC2POC__PSIZ_R			12U
+#define XHC_FSC2POC__PSIZ_WIDTH			5U
+#define XHC_FSC2POC__PSIZ_RESETVALUE		0x0U
+#define XHC_FSC2POC__reserved_L			11U
+#define XHC_FSC2POC__reserved_R			5U
+#define XHC_FSC2POC__reserved_WIDTH		7U
+#define XHC_FSC2POC__reserved_RESETVALUE	0x0U
+#define XHC_FSC2POC__TSIZ_L			4U
+#define XHC_FSC2POC__TSIZ_R			0U
+#define XHC_FSC2POC__TSIZ_WIDTH			5U
+#define XHC_FSC2POC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSC2POC__RESERVED_L			27U
+#define XHC_FSC2POC__RESERVED_R			23U
+#define XHC_FSC2POC_WIDTH			32U
+#define XHC_FSC2POC__WIDTH			32U
+#define XHC_FSC2POC_ALL_L			31U
+#define XHC_FSC2POC_ALL_R			0U
+#define XHC_FSC2POC__ALL_L			31U
+#define XHC_FSC2POC__ALL_R			0U
+#define XHC_FSC2POC_DATAMASK			0xf07dffffU
+#define XHC_FSC2POC_RDWRMASK			0x0f820000U
+#define XHC_FSC2POC_RESETVALUE			0x00000000U
+
+#define XHC_FSC2GOC_OFFSET			0xcd8U
+#define XHC_FSC2GOC_BASE			0xcd8U
+#define XHC_FSC2GOC__NCS_L			31U
+#define XHC_FSC2GOC__NCS_R			28U
+#define XHC_FSC2GOC__NCS_WIDTH			4U
+#define XHC_FSC2GOC__NCS_RESETVALUE		0x0U
+#define XHC_FSC2GOC__FSIZ_L			22U
+#define XHC_FSC2GOC__FSIZ_R			18U
+#define XHC_FSC2GOC__FSIZ_WIDTH			5U
+#define XHC_FSC2GOC__FSIZ_RESETVALUE		0x0U
+#define XHC_FSC2GOC__PSIZ_L			16U
+#define XHC_FSC2GOC__PSIZ_R			12U
+#define XHC_FSC2GOC__PSIZ_WIDTH			5U
+#define XHC_FSC2GOC__PSIZ_RESETVALUE		0x0U
+#define XHC_FSC2GOC__reserved_L			11U
+#define XHC_FSC2GOC__reserved_R			5U
+#define XHC_FSC2GOC__reserved_WIDTH		7U
+#define XHC_FSC2GOC__reserved_RESETVALUE	0x0U
+#define XHC_FSC2GOC__TSIZ_L			4U
+#define XHC_FSC2GOC__TSIZ_R			0U
+#define XHC_FSC2GOC__TSIZ_WIDTH			5U
+#define XHC_FSC2GOC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSC2GOC__RESERVED_L			27U
+#define XHC_FSC2GOC__RESERVED_R			23U
+#define XHC_FSC2GOC_WIDTH			32U
+#define XHC_FSC2GOC__WIDTH			32U
+#define XHC_FSC2GOC_ALL_L			31U
+#define XHC_FSC2GOC_ALL_R			0U
+#define XHC_FSC2GOC__ALL_L			31U
+#define XHC_FSC2GOC__ALL_R			0U
+#define XHC_FSC2GOC_DATAMASK			0xf07dffffU
+#define XHC_FSC2GOC_RDWRMASK			0x0f820000U
+#define XHC_FSC2GOC_RESETVALUE			0x00000000U
+
+#define XHC_FSC2NOC_OFFSET			0xcdcU
+#define XHC_FSC2NOC_BASE			0xcdcU
+#define XHC_FSC2NOC__NCS_L			31U
+#define XHC_FSC2NOC__NCS_R			28U
+#define XHC_FSC2NOC__NCS_WIDTH			4U
+#define XHC_FSC2NOC__NCS_RESETVALUE		0x0U
+#define XHC_FSC2NOC__FSIZ_L			22U
+#define XHC_FSC2NOC__FSIZ_R			18U
+#define XHC_FSC2NOC__FSIZ_WIDTH			5U
+#define XHC_FSC2NOC__FSIZ_RESETVALUE		0x0U
+#define XHC_FSC2NOC__PSIZ_L			16U
+#define XHC_FSC2NOC__PSIZ_R			12U
+#define XHC_FSC2NOC__PSIZ_WIDTH			5U
+#define XHC_FSC2NOC__PSIZ_RESETVALUE		0x0U
+#define XHC_FSC2NOC__reserved_L			11U
+#define XHC_FSC2NOC__reserved_R			5U
+#define XHC_FSC2NOC__reserved_WIDTH		7U
+#define XHC_FSC2NOC__reserved_RESETVALUE	0x0U
+#define XHC_FSC2NOC__TSIZ_L			4U
+#define XHC_FSC2NOC__TSIZ_R			0U
+#define XHC_FSC2NOC__TSIZ_WIDTH			5U
+#define XHC_FSC2NOC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSC2NOC__RESERVED_L			27U
+#define XHC_FSC2NOC__RESERVED_R			23U
+#define XHC_FSC2NOC_WIDTH			32U
+#define XHC_FSC2NOC__WIDTH			32U
+#define XHC_FSC2NOC_ALL_L			31U
+#define XHC_FSC2NOC_ALL_R			0U
+#define XHC_FSC2NOC__ALL_L			31U
+#define XHC_FSC2NOC__ALL_R			0U
+#define XHC_FSC2NOC_DATAMASK			0xf07dffffU
+#define XHC_FSC2NOC_RDWRMASK			0x0f820000U
+#define XHC_FSC2NOC_RESETVALUE			0x00000000U
+
+#define XHC_FSC2AIC_OFFSET			0xce0U
+#define XHC_FSC2AIC_BASE			0xce0U
+#define XHC_FSC2AIC__FSIZ_L			22U
+#define XHC_FSC2AIC__FSIZ_R			18U
+#define XHC_FSC2AIC__FSIZ_WIDTH			5U
+#define XHC_FSC2AIC__FSIZ_RESETVALUE		0x0U
+#define XHC_FSC2AIC__PSIZ_L			16U
+#define XHC_FSC2AIC__PSIZ_R			12U
+#define XHC_FSC2AIC__PSIZ_WIDTH			5U
+#define XHC_FSC2AIC__PSIZ_RESETVALUE		0x0U
+#define XHC_FSC2AIC__reserved_L			11U
+#define XHC_FSC2AIC__reserved_R			0U
+#define XHC_FSC2AIC__reserved_WIDTH		12U
+#define XHC_FSC2AIC__reserved_RESETVALUE	0x000U
+#define XHC_FSC2AIC__RESERVED_L			31U
+#define XHC_FSC2AIC__RESERVED_R			23U
+#define XHC_FSC2AIC_WIDTH			23U
+#define XHC_FSC2AIC__WIDTH			23U
+#define XHC_FSC2AIC_ALL_L			22U
+#define XHC_FSC2AIC_ALL_R			0U
+#define XHC_FSC2AIC__ALL_L			22U
+#define XHC_FSC2AIC__ALL_R			0U
+#define XHC_FSC2AIC_DATAMASK			0x007dffffU
+#define XHC_FSC2AIC_RDWRMASK			0xff820000U
+#define XHC_FSC2AIC_RESETVALUE			0x000000U
+
+#define XHC_FSC2PIC_OFFSET			0xce4U
+#define XHC_FSC2PIC_BASE			0xce4U
+#define XHC_FSC2PIC__NCS_L			31U
+#define XHC_FSC2PIC__NCS_R			28U
+#define XHC_FSC2PIC__NCS_WIDTH			4U
+#define XHC_FSC2PIC__NCS_RESETVALUE		0x0U
+#define XHC_FSC2PIC__reserved_L			27U
+#define XHC_FSC2PIC__reserved_R			5U
+#define XHC_FSC2PIC__reserved_WIDTH		23U
+#define XHC_FSC2PIC__reserved_RESETVALUE	0x0U
+#define XHC_FSC2PIC__TSIZ_L			4U
+#define XHC_FSC2PIC__TSIZ_R			0U
+#define XHC_FSC2PIC__TSIZ_WIDTH			5U
+#define XHC_FSC2PIC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSC2PIC_WIDTH			32U
+#define XHC_FSC2PIC__WIDTH			32U
+#define XHC_FSC2PIC_ALL_L			31U
+#define XHC_FSC2PIC_ALL_R			0U
+#define XHC_FSC2PIC__ALL_L			31U
+#define XHC_FSC2PIC__ALL_R			0U
+#define XHC_FSC2PIC_DATAMASK			0xffffffffU
+#define XHC_FSC2PIC_RDWRMASK			0x00000000U
+#define XHC_FSC2PIC_RESETVALUE			0x00000000U
+
+#define XHC_FSC2GIC_OFFSET			0xce8U
+#define XHC_FSC2GIC_BASE			0xce8U
+#define XHC_FSC2GIC__NCS_L			31U
+#define XHC_FSC2GIC__NCS_R			28U
+#define XHC_FSC2GIC__NCS_WIDTH			4U
+#define XHC_FSC2GIC__NCS_RESETVALUE		0x0U
+#define XHC_FSC2GIC__reserved_L			27U
+#define XHC_FSC2GIC__reserved_R			5U
+#define XHC_FSC2GIC__reserved_WIDTH		23U
+#define XHC_FSC2GIC__reserved_RESETVALUE	0x0U
+#define XHC_FSC2GIC__TSIZ_L			4U
+#define XHC_FSC2GIC__TSIZ_R			0U
+#define XHC_FSC2GIC__TSIZ_WIDTH			5U
+#define XHC_FSC2GIC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSC2GIC_WIDTH			32U
+#define XHC_FSC2GIC__WIDTH			32U
+#define XHC_FSC2GIC_ALL_L			31U
+#define XHC_FSC2GIC_ALL_R			0U
+#define XHC_FSC2GIC__ALL_L			31U
+#define XHC_FSC2GIC__ALL_R			0U
+#define XHC_FSC2GIC_DATAMASK			0xffffffffU
+#define XHC_FSC2GIC_RDWRMASK			0x00000000U
+#define XHC_FSC2GIC_RESETVALUE			0x00000000U
+
+#define XHC_FSC2NIC_OFFSET			0xcecU
+#define XHC_FSC2NIC_BASE			0xcecU
+#define XHC_FSC2NIC__NCS_L			31U
+#define XHC_FSC2NIC__NCS_R			28U
+#define XHC_FSC2NIC__NCS_WIDTH			4U
+#define XHC_FSC2NIC__NCS_RESETVALUE		0x0U
+#define XHC_FSC2NIC__reserved_L			27U
+#define XHC_FSC2NIC__reserved_R			5U
+#define XHC_FSC2NIC__reserved_WIDTH		23U
+#define XHC_FSC2NIC__reserved_RESETVALUE	0x0U
+#define XHC_FSC2NIC__TSIZ_L			4U
+#define XHC_FSC2NIC__TSIZ_R			0U
+#define XHC_FSC2NIC__TSIZ_WIDTH			5U
+#define XHC_FSC2NIC__TSIZ_RESETVALUE		0x0U
+#define XHC_FSC2NIC_WIDTH			32U
+#define XHC_FSC2NIC__WIDTH			32U
+#define XHC_FSC2NIC_ALL_L			31U
+#define XHC_FSC2NIC_ALL_R			0U
+#define XHC_FSC2NIC__ALL_L			31U
+#define XHC_FSC2NIC__ALL_R			0U
+#define XHC_FSC2NIC_DATAMASK			0xffffffffU
+#define XHC_FSC2NIC_RDWRMASK			0x00000000U
+#define XHC_FSC2NIC_RESETVALUE			0x00000000U
+
+#define XHC_ECHPRT2_OFFSET			0xcf0U
+#define XHC_ECHPRT2_BASE			0xcf0U
+#define XHC_ECHPRT2__HDP			31U
+#define XHC_ECHPRT2__HDP_L			31U
+#define XHC_ECHPRT2__HDP_R			31U
+#define XHC_ECHPRT2__HDP_WIDTH			1U
+#define XHC_ECHPRT2__HDP_RESETVALUE		0x0U
+#define XHC_ECHPRT2__FDP			30U
+#define XHC_ECHPRT2__FDP_L			30U
+#define XHC_ECHPRT2__FDP_R			30U
+#define XHC_ECHPRT2__FDP_WIDTH			1U
+#define XHC_ECHPRT2__FDP_RESETVALUE		0x0U
+#define XHC_ECHPRT2__reserved_L			29U
+#define XHC_ECHPRT2__reserved_R			17U
+#define XHC_ECHPRT2__reserved_WIDTH		13U
+#define XHC_ECHPRT2__reserved_RESETVALUE	0x0U
+#define XHC_ECHPRT2__HST			16U
+#define XHC_ECHPRT2__HST_L			16U
+#define XHC_ECHPRT2__HST_R			16U
+#define XHC_ECHPRT2__HST_WIDTH			1U
+#define XHC_ECHPRT2__HST_RESETVALUE		0x0U
+#define XHC_ECHPRT2__NCP_L			15U
+#define XHC_ECHPRT2__NCP_R			8U
+#define XHC_ECHPRT2__NCP_WIDTH			8U
+#define XHC_ECHPRT2__NCP_RESETVALUE		0x04U
+#define XHC_ECHPRT2__CID_L			7U
+#define XHC_ECHPRT2__CID_R			0U
+#define XHC_ECHPRT2__CID_WIDTH			8U
+#define XHC_ECHPRT2__CID_RESETVALUE		0xc8U
+#define XHC_ECHPRT2_WIDTH			32U
+#define XHC_ECHPRT2__WIDTH			32U
+#define XHC_ECHPRT2_ALL_L			31U
+#define XHC_ECHPRT2_ALL_R			0U
+#define XHC_ECHPRT2__ALL_L			31U
+#define XHC_ECHPRT2__ALL_R			0U
+#define XHC_ECHPRT2_DATAMASK			0xffffffffU
+#define XHC_ECHPRT2_RDWRMASK			0x00000000U
+#define XHC_ECHPRT2_RESETVALUE			0x000004c8U
+
+#define XHC_PRT2HSC_OFFSET			0xcf8U
+#define XHC_PRT2HSC_BASE			0xcf8U
+#define XHC_PRT2HSC__TMR_L			31U
+#define XHC_PRT2HSC__TMR_R			16U
+#define XHC_PRT2HSC__TMR_WIDTH			16U
+#define XHC_PRT2HSC__TMR_RESETVALUE		0x0000U
+#define XHC_PRT2HSC__RSL_L			7U
+#define XHC_PRT2HSC__RSL_R			6U
+#define XHC_PRT2HSC__RSL_WIDTH			2U
+#define XHC_PRT2HSC__RSL_RESETVALUE		0x0U
+#define XHC_PRT2HSC__AS_M_L			5U
+#define XHC_PRT2HSC__AS_M_R			4U
+#define XHC_PRT2HSC__AS_M_WIDTH			2U
+#define XHC_PRT2HSC__AS_M_RESETVALUE		0x0U
+#define XHC_PRT2HSC__CMD_L			3U
+#define XHC_PRT2HSC__CMD_R			2U
+#define XHC_PRT2HSC__CMD_WIDTH			2U
+#define XHC_PRT2HSC__CMD_RESETVALUE		0x0U
+#define XHC_PRT2HSC__reserved			1U
+#define XHC_PRT2HSC__reserved_L			1U
+#define XHC_PRT2HSC__reserved_R			1U
+#define XHC_PRT2HSC__reserved_WIDTH		1U
+#define XHC_PRT2HSC__reserved_RESETVALUE	0x0U
+#define XHC_PRT2HSC__STB			0U
+#define XHC_PRT2HSC__STB_L			0U
+#define XHC_PRT2HSC__STB_R			0U
+#define XHC_PRT2HSC__STB_WIDTH			1U
+#define XHC_PRT2HSC__STB_RESETVALUE		0x0U
+#define XHC_PRT2HSC__RESERVED_L			15U
+#define XHC_PRT2HSC__RESERVED_R			8U
+#define XHC_PRT2HSC_WIDTH			32U
+#define XHC_PRT2HSC__WIDTH			32U
+#define XHC_PRT2HSC_ALL_L			31U
+#define XHC_PRT2HSC_ALL_R			0U
+#define XHC_PRT2HSC__ALL_L			31U
+#define XHC_PRT2HSC__ALL_R			0U
+#define XHC_PRT2HSC_DATAMASK			0xffff00ffU
+#define XHC_PRT2HSC_RDWRMASK			0x0000ff00U
+#define XHC_PRT2HSC_RESETVALUE			0x00000000U
+
+#define XHC_PRT2HSR_OFFSET			0xcfcU
+#define XHC_PRT2HSR_BASE			0xcfcU
+#define XHC_PRT2HSR__RNAK_L			31U
+#define XHC_PRT2HSR__RNAK_R			24U
+#define XHC_PRT2HSR__RNAK_WIDTH			8U
+#define XHC_PRT2HSR__RNAK_RESETVALUE		0x00U
+#define XHC_PRT2HSR__HSTX_L			23U
+#define XHC_PRT2HSR__HSTX_R			16U
+#define XHC_PRT2HSR__HSTX_WIDTH			8U
+#define XHC_PRT2HSR__HSTX_RESETVALUE		0x00U
+#define XHC_PRT2HSR__HSRX_L			15U
+#define XHC_PRT2HSR__HSRX_R			8U
+#define XHC_PRT2HSR__HSRX_WIDTH			8U
+#define XHC_PRT2HSR__HSRX_RESETVALUE		0x00U
+#define XHC_PRT2HSR__SPLT_L			7U
+#define XHC_PRT2HSR__SPLT_R			0U
+#define XHC_PRT2HSR__SPLT_WIDTH			8U
+#define XHC_PRT2HSR__SPLT_RESETVALUE		0x00U
+#define XHC_PRT2HSR_WIDTH			32U
+#define XHC_PRT2HSR__WIDTH			32U
+#define XHC_PRT2HSR_ALL_L			31U
+#define XHC_PRT2HSR_ALL_R			0U
+#define XHC_PRT2HSR__ALL_L			31U
+#define XHC_PRT2HSR__ALL_R			0U
+#define XHC_PRT2HSR_DATAMASK			0xffffffffU
+#define XHC_PRT2HSR_RDWRMASK			0x00000000U
+#define XHC_PRT2HSR_RESETVALUE			0x00000000U
+
+#define XHC_ECHRH2_OFFSET			0xd00U
+#define XHC_ECHRH2_BASE				0xd00U
+#define XHC_ECHRH2__MTT				31U
+#define XHC_ECHRH2__MTT_L			31U
+#define XHC_ECHRH2__MTT_R			31U
+#define XHC_ECHRH2__MTT_WIDTH			1U
+#define XHC_ECHRH2__MTT_RESETVALUE		0x0U
+#define XHC_ECHRH2__RPO_L			30U
+#define XHC_ECHRH2__RPO_R			24U
+#define XHC_ECHRH2__RPO_WIDTH			7U
+#define XHC_ECHRH2__RPO_RESETVALUE		0x0U
+#define XHC_ECHRH2__reserved_L			23U
+#define XHC_ECHRH2__reserved_R			22U
+#define XHC_ECHRH2__reserved_WIDTH		2U
+#define XHC_ECHRH2__reserved_RESETVALUE		0x0U
+#define XHC_ECHRH2__RPN_L			21U
+#define XHC_ECHRH2__RPN_R			20U
+#define XHC_ECHRH2__RPN_WIDTH			2U
+#define XHC_ECHRH2__RPN_RESETVALUE		0x0U
+#define XHC_ECHRH2__DNR_L			19U
+#define XHC_ECHRH2__DNR_R			16U
+#define XHC_ECHRH2__DNR_WIDTH			4U
+#define XHC_ECHRH2__DNR_RESETVALUE		0x0U
+#define XHC_ECHRH2__NCP_L			15U
+#define XHC_ECHRH2__NCP_R			8U
+#define XHC_ECHRH2__NCP_WIDTH			8U
+#define XHC_ECHRH2__NCP_RESETVALUE		0x0cU
+#define XHC_ECHRH2__CID_L			7U
+#define XHC_ECHRH2__CID_R			0U
+#define XHC_ECHRH2__CID_WIDTH			8U
+#define XHC_ECHRH2__CID_RESETVALUE		0xc9U
+#define XHC_ECHRH2_WIDTH			32U
+#define XHC_ECHRH2__WIDTH			32U
+#define XHC_ECHRH2_ALL_L			31U
+#define XHC_ECHRH2_ALL_R			0U
+#define XHC_ECHRH2__ALL_L			31U
+#define XHC_ECHRH2__ALL_R			0U
+#define XHC_ECHRH2_DATAMASK			0xffffffffU
+#define XHC_ECHRH2_RDWRMASK			0x00000000U
+#define XHC_ECHRH2_RESETVALUE			0x00000cc9U
+
+#define XHC_RH2DES_OFFSET			0xd04U
+#define XHC_RH2DES_BASE				0xd04U
+#define XHC_RH2DES__PIS3_L			31U
+#define XHC_RH2DES__PIS3_R			30U
+#define XHC_RH2DES__PIS3_WIDTH			2U
+#define XHC_RH2DES__PIS3_RESETVALUE		0x0U
+#define XHC_RH2DES__HIST3			24U
+#define XHC_RH2DES__HIST3_L			24U
+#define XHC_RH2DES__HIST3_R			24U
+#define XHC_RH2DES__HIST3_WIDTH			1U
+#define XHC_RH2DES__HIST3_RESETVALUE		0x0U
+#define XHC_RH2DES__PIS2_L			23U
+#define XHC_RH2DES__PIS2_R			22U
+#define XHC_RH2DES__PIS2_WIDTH			2U
+#define XHC_RH2DES__PIS2_RESETVALUE		0x0U
+#define XHC_RH2DES__HIST2			16U
+#define XHC_RH2DES__HIST2_L			16U
+#define XHC_RH2DES__HIST2_R			16U
+#define XHC_RH2DES__HIST2_WIDTH			1U
+#define XHC_RH2DES__HIST2_RESETVALUE		0x0U
+#define XHC_RH2DES__PIS1_L			15U
+#define XHC_RH2DES__PIS1_R			14U
+#define XHC_RH2DES__PIS1_WIDTH			2U
+#define XHC_RH2DES__PIS1_RESETVALUE		0x0U
+#define XHC_RH2DES__HIST1			8U
+#define XHC_RH2DES__HIST1_L			8U
+#define XHC_RH2DES__HIST1_R			8U
+#define XHC_RH2DES__HIST1_WIDTH			1U
+#define XHC_RH2DES__HIST1_RESETVALUE		0x0U
+#define XHC_RH2DES__PIS0_L			7U
+#define XHC_RH2DES__PIS0_R			6U
+#define XHC_RH2DES__PIS0_WIDTH			2U
+#define XHC_RH2DES__PIS0_RESETVALUE		0x0U
+#define XHC_RH2DES__reserved_L			5U
+#define XHC_RH2DES__reserved_R			1U
+#define XHC_RH2DES__reserved_WIDTH		5U
+#define XHC_RH2DES__reserved_RESETVALUE		0x0U
+#define XHC_RH2DES__HIST0			0U
+#define XHC_RH2DES__HIST0_L			0U
+#define XHC_RH2DES__HIST0_R			0U
+#define XHC_RH2DES__HIST0_WIDTH			1U
+#define XHC_RH2DES__HIST0_RESETVALUE		0x0U
+#define XHC_RH2DES__RESERVED_0_L		29U
+#define XHC_RH2DES__RESERVED_0_R		25U
+#define XHC_RH2DES__RESERVED_1_L		21U
+#define XHC_RH2DES__RESERVED_1_R		17U
+#define XHC_RH2DES__RESERVED_2_L		13U
+#define XHC_RH2DES__RESERVED_2_R		9U
+#define XHC_RH2DES__RESERVED_L			29U
+#define XHC_RH2DES__RESERVED_R			25U
+#define XHC_RH2DES_WIDTH			32U
+#define XHC_RH2DES__WIDTH			32U
+#define XHC_RH2DES_ALL_L			31U
+#define XHC_RH2DES_ALL_R			0U
+#define XHC_RH2DES__ALL_L			31U
+#define XHC_RH2DES__ALL_R			0U
+#define XHC_RH2DES_DATAMASK			0xc1c1c1ffU
+#define XHC_RH2DES_RDWRMASK			0x3e3e3e00U
+#define XHC_RH2DES_RESETVALUE			0x00000000U
+
+#define XHC_RH2HSC0_OFFSET			0xd10U
+#define XHC_RH2HSC0_BASE			0xd10U
+#define XHC_RH2HSC0__TMR_L			31U
+#define XHC_RH2HSC0__TMR_R			16U
+#define XHC_RH2HSC0__TMR_WIDTH			16U
+#define XHC_RH2HSC0__TMR_RESETVALUE		0x0000U
+#define XHC_RH2HSC0__RSL_L			7U
+#define XHC_RH2HSC0__RSL_R			6U
+#define XHC_RH2HSC0__RSL_WIDTH			2U
+#define XHC_RH2HSC0__RSL_RESETVALUE		0x0U
+#define XHC_RH2HSC0__AS_M_L			5U
+#define XHC_RH2HSC0__AS_M_R			4U
+#define XHC_RH2HSC0__AS_M_WIDTH			2U
+#define XHC_RH2HSC0__AS_M_RESETVALUE		0x0U
+#define XHC_RH2HSC0__CMD_L			3U
+#define XHC_RH2HSC0__CMD_R			2U
+#define XHC_RH2HSC0__CMD_WIDTH			2U
+#define XHC_RH2HSC0__CMD_RESETVALUE		0x0U
+#define XHC_RH2HSC0__reserved			1U
+#define XHC_RH2HSC0__reserved_L			1U
+#define XHC_RH2HSC0__reserved_R			1U
+#define XHC_RH2HSC0__reserved_WIDTH		1U
+#define XHC_RH2HSC0__reserved_RESETVALUE	0x0U
+#define XHC_RH2HSC0__STB			0U
+#define XHC_RH2HSC0__STB_L			0U
+#define XHC_RH2HSC0__STB_R			0U
+#define XHC_RH2HSC0__STB_WIDTH			1U
+#define XHC_RH2HSC0__STB_RESETVALUE		0x0U
+#define XHC_RH2HSC0__RESERVED_L			15U
+#define XHC_RH2HSC0__RESERVED_R			8U
+#define XHC_RH2HSC0_WIDTH			32U
+#define XHC_RH2HSC0__WIDTH			32U
+#define XHC_RH2HSC0_ALL_L			31U
+#define XHC_RH2HSC0_ALL_R			0U
+#define XHC_RH2HSC0__ALL_L			31U
+#define XHC_RH2HSC0__ALL_R			0U
+#define XHC_RH2HSC0_DATAMASK			0xffff00ffU
+#define XHC_RH2HSC0_RDWRMASK			0x0000ff00U
+#define XHC_RH2HSC0_RESETVALUE			0x00000000U
+
+#define XHC_RH2HSR0_OFFSET			0xd14U
+#define XHC_RH2HSR0_BASE			0xd14U
+#define XHC_RH2HSR0__C2U_L			31U
+#define XHC_RH2HSR0__C2U_R			24U
+#define XHC_RH2HSR0__C2U_WIDTH			8U
+#define XHC_RH2HSR0__C2U_RESETVALUE		0x00U
+#define XHC_RH2HSR0__C1U_L			23U
+#define XHC_RH2HSR0__C1U_R			16U
+#define XHC_RH2HSR0__C1U_WIDTH			8U
+#define XHC_RH2HSR0__C1U_RESETVALUE		0x00U
+#define XHC_RH2HSR0__reserved_L			15U
+#define XHC_RH2HSR0__reserved_R			8U
+#define XHC_RH2HSR0__reserved_WIDTH		8U
+#define XHC_RH2HSR0__reserved_RESETVALUE	0x00U
+#define XHC_RH2HSR0__RTY_L			7U
+#define XHC_RH2HSR0__RTY_R			0U
+#define XHC_RH2HSR0__RTY_WIDTH			8U
+#define XHC_RH2HSR0__RTY_RESETVALUE		0x00U
+#define XHC_RH2HSR0_WIDTH			32U
+#define XHC_RH2HSR0__WIDTH			32U
+#define XHC_RH2HSR0_ALL_L			31U
+#define XHC_RH2HSR0_ALL_R			0U
+#define XHC_RH2HSR0__ALL_L			31U
+#define XHC_RH2HSR0__ALL_R			0U
+#define XHC_RH2HSR0_DATAMASK			0xffffffffU
+#define XHC_RH2HSR0_RDWRMASK			0x00000000U
+#define XHC_RH2HSR0_RESETVALUE			0x00000000U
+
+#define XHC_RH2HSC1_OFFSET			0xd18U
+#define XHC_RH2HSC1_BASE			0xd18U
+#define XHC_RH2HSC1__TMR_L			31U
+#define XHC_RH2HSC1__TMR_R			16U
+#define XHC_RH2HSC1__TMR_WIDTH			16U
+#define XHC_RH2HSC1__TMR_RESETVALUE		0x0000U
+#define XHC_RH2HSC1__RSL_L			7U
+#define XHC_RH2HSC1__RSL_R			6U
+#define XHC_RH2HSC1__RSL_WIDTH			2U
+#define XHC_RH2HSC1__RSL_RESETVALUE		0x0U
+#define XHC_RH2HSC1__AS_M_L			5U
+#define XHC_RH2HSC1__AS_M_R			4U
+#define XHC_RH2HSC1__AS_M_WIDTH			2U
+#define XHC_RH2HSC1__AS_M_RESETVALUE		0x0U
+#define XHC_RH2HSC1__CMD_L			3U
+#define XHC_RH2HSC1__CMD_R			2U
+#define XHC_RH2HSC1__CMD_WIDTH			2U
+#define XHC_RH2HSC1__CMD_RESETVALUE		0x0U
+#define XHC_RH2HSC1__reserved			1U
+#define XHC_RH2HSC1__reserved_L			1U
+#define XHC_RH2HSC1__reserved_R			1U
+#define XHC_RH2HSC1__reserved_WIDTH		1U
+#define XHC_RH2HSC1__reserved_RESETVALUE	0x0U
+#define XHC_RH2HSC1__STB			0U
+#define XHC_RH2HSC1__STB_L			0U
+#define XHC_RH2HSC1__STB_R			0U
+#define XHC_RH2HSC1__STB_WIDTH			1U
+#define XHC_RH2HSC1__STB_RESETVALUE		0x0U
+#define XHC_RH2HSC1__RESERVED_L			15U
+#define XHC_RH2HSC1__RESERVED_R			8U
+#define XHC_RH2HSC1_WIDTH			32U
+#define XHC_RH2HSC1__WIDTH			32U
+#define XHC_RH2HSC1_ALL_L			31U
+#define XHC_RH2HSC1_ALL_R			0U
+#define XHC_RH2HSC1__ALL_L			31U
+#define XHC_RH2HSC1__ALL_R			0U
+#define XHC_RH2HSC1_DATAMASK			0xffff00ffU
+#define XHC_RH2HSC1_RDWRMASK			0x0000ff00U
+#define XHC_RH2HSC1_RESETVALUE			0x00000000U
+
+#define XHC_RH2HSR1_OFFSET			0xd1cU
+#define XHC_RH2HSR1_BASE			0xd1cU
+#define XHC_RH2HSR1__C2U_L			31U
+#define XHC_RH2HSR1__C2U_R			24U
+#define XHC_RH2HSR1__C2U_WIDTH			8U
+#define XHC_RH2HSR1__C2U_RESETVALUE		0x00U
+#define XHC_RH2HSR1__C1U_L			23U
+#define XHC_RH2HSR1__C1U_R			16U
+#define XHC_RH2HSR1__C1U_WIDTH			8U
+#define XHC_RH2HSR1__C1U_RESETVALUE		0x00U
+#define XHC_RH2HSR1__reserved_L			15U
+#define XHC_RH2HSR1__reserved_R			8U
+#define XHC_RH2HSR1__reserved_WIDTH		8U
+#define XHC_RH2HSR1__reserved_RESETVALUE	0x00U
+#define XHC_RH2HSR1__RTY_L			7U
+#define XHC_RH2HSR1__RTY_R			0U
+#define XHC_RH2HSR1__RTY_WIDTH			8U
+#define XHC_RH2HSR1__RTY_RESETVALUE		0x00U
+#define XHC_RH2HSR1_WIDTH			32U
+#define XHC_RH2HSR1__WIDTH			32U
+#define XHC_RH2HSR1_ALL_L			31U
+#define XHC_RH2HSR1_ALL_R			0U
+#define XHC_RH2HSR1__ALL_L			31U
+#define XHC_RH2HSR1__ALL_R			0U
+#define XHC_RH2HSR1_DATAMASK			0xffffffffU
+#define XHC_RH2HSR1_RDWRMASK			0x00000000U
+#define XHC_RH2HSR1_RESETVALUE			0x00000000U
+
+#define XHC_RH2HSC2_OFFSET			0xd20U
+#define XHC_RH2HSC2_BASE			0xd20U
+#define XHC_RH2HSC2__TMR_L			31U
+#define XHC_RH2HSC2__TMR_R			16U
+#define XHC_RH2HSC2__TMR_WIDTH			16U
+#define XHC_RH2HSC2__TMR_RESETVALUE		0x0000U
+#define XHC_RH2HSC2__RSL_L			7U
+#define XHC_RH2HSC2__RSL_R			6U
+#define XHC_RH2HSC2__RSL_WIDTH			2U
+#define XHC_RH2HSC2__RSL_RESETVALUE		0x0U
+#define XHC_RH2HSC2__AS_M_L			5U
+#define XHC_RH2HSC2__AS_M_R			4U
+#define XHC_RH2HSC2__AS_M_WIDTH			2U
+#define XHC_RH2HSC2__AS_M_RESETVALUE		0x0U
+#define XHC_RH2HSC2__CMD_L			3U
+#define XHC_RH2HSC2__CMD_R			2U
+#define XHC_RH2HSC2__CMD_WIDTH			2U
+#define XHC_RH2HSC2__CMD_RESETVALUE		0x0U
+#define XHC_RH2HSC2__reserved			1U
+#define XHC_RH2HSC2__reserved_L			1U
+#define XHC_RH2HSC2__reserved_R			1U
+#define XHC_RH2HSC2__reserved_WIDTH		1U
+#define XHC_RH2HSC2__reserved_RESETVALUE	0x0U
+#define XHC_RH2HSC2__STB			0U
+#define XHC_RH2HSC2__STB_L			0U
+#define XHC_RH2HSC2__STB_R			0U
+#define XHC_RH2HSC2__STB_WIDTH			1U
+#define XHC_RH2HSC2__STB_RESETVALUE		0x0U
+#define XHC_RH2HSC2__RESERVED_L			15U
+#define XHC_RH2HSC2__RESERVED_R			8U
+#define XHC_RH2HSC2_WIDTH			32U
+#define XHC_RH2HSC2__WIDTH			32U
+#define XHC_RH2HSC2_ALL_L			31U
+#define XHC_RH2HSC2_ALL_R			0U
+#define XHC_RH2HSC2__ALL_L			31U
+#define XHC_RH2HSC2__ALL_R			0U
+#define XHC_RH2HSC2_DATAMASK			0xffff00ffU
+#define XHC_RH2HSC2_RDWRMASK			0x0000ff00U
+#define XHC_RH2HSC2_RESETVALUE			0x00000000U
+
+#define XHC_RH2HSR2_OFFSET			0xd24U
+#define XHC_RH2HSR2_BASE			0xd24U
+#define XHC_RH2HSR2__C2U_L			31U
+#define XHC_RH2HSR2__C2U_R			24U
+#define XHC_RH2HSR2__C2U_WIDTH			8U
+#define XHC_RH2HSR2__C2U_RESETVALUE		0x00U
+#define XHC_RH2HSR2__C1U_L			23U
+#define XHC_RH2HSR2__C1U_R			16U
+#define XHC_RH2HSR2__C1U_WIDTH			8U
+#define XHC_RH2HSR2__C1U_RESETVALUE		0x00U
+#define XHC_RH2HSR2__reserved_L			15U
+#define XHC_RH2HSR2__reserved_R			8U
+#define XHC_RH2HSR2__reserved_WIDTH		8U
+#define XHC_RH2HSR2__reserved_RESETVALUE	0x00U
+#define XHC_RH2HSR2__RTY_L			7U
+#define XHC_RH2HSR2__RTY_R			0U
+#define XHC_RH2HSR2__RTY_WIDTH			8U
+#define XHC_RH2HSR2__RTY_RESETVALUE		0x00U
+#define XHC_RH2HSR2_WIDTH			32U
+#define XHC_RH2HSR2__WIDTH			32U
+#define XHC_RH2HSR2_ALL_L			31U
+#define XHC_RH2HSR2_ALL_R			0U
+#define XHC_RH2HSR2__ALL_L			31U
+#define XHC_RH2HSR2__ALL_R			0U
+#define XHC_RH2HSR2_DATAMASK			0xffffffffU
+#define XHC_RH2HSR2_RDWRMASK			0x00000000U
+#define XHC_RH2HSR2_RESETVALUE			0x00000000U
+
+#define XHC_RH2HSC3_OFFSET			0xd28U
+#define XHC_RH2HSC3_BASE			0xd28U
+#define XHC_RH2HSC3__TMR_L			31U
+#define XHC_RH2HSC3__TMR_R			16U
+#define XHC_RH2HSC3__TMR_WIDTH			16U
+#define XHC_RH2HSC3__TMR_RESETVALUE		0x0000U
+#define XHC_RH2HSC3__RSL_L			7U
+#define XHC_RH2HSC3__RSL_R			6U
+#define XHC_RH2HSC3__RSL_WIDTH			2U
+#define XHC_RH2HSC3__RSL_RESETVALUE		0x0U
+#define XHC_RH2HSC3__AS_M_L			5U
+#define XHC_RH2HSC3__AS_M_R			4U
+#define XHC_RH2HSC3__AS_M_WIDTH			2U
+#define XHC_RH2HSC3__AS_M_RESETVALUE		0x0U
+#define XHC_RH2HSC3__CMD_L			3U
+#define XHC_RH2HSC3__CMD_R			2U
+#define XHC_RH2HSC3__CMD_WIDTH			2U
+#define XHC_RH2HSC3__CMD_RESETVALUE		0x0U
+#define XHC_RH2HSC3__reserved			1U
+#define XHC_RH2HSC3__reserved_L			1U
+#define XHC_RH2HSC3__reserved_R			1U
+#define XHC_RH2HSC3__reserved_WIDTH		1U
+#define XHC_RH2HSC3__reserved_RESETVALUE	0x0U
+#define XHC_RH2HSC3__STB			0U
+#define XHC_RH2HSC3__STB_L			0U
+#define XHC_RH2HSC3__STB_R			0U
+#define XHC_RH2HSC3__STB_WIDTH			1U
+#define XHC_RH2HSC3__STB_RESETVALUE		0x0U
+#define XHC_RH2HSC3__RESERVED_L			15U
+#define XHC_RH2HSC3__RESERVED_R			8U
+#define XHC_RH2HSC3_WIDTH			32U
+#define XHC_RH2HSC3__WIDTH			32U
+#define XHC_RH2HSC3_ALL_L			31U
+#define XHC_RH2HSC3_ALL_R			0U
+#define XHC_RH2HSC3__ALL_L			31U
+#define XHC_RH2HSC3__ALL_R			0U
+#define XHC_RH2HSC3_DATAMASK			0xffff00ffU
+#define XHC_RH2HSC3_RDWRMASK			0x0000ff00U
+#define XHC_RH2HSC3_RESETVALUE			0x00000000U
+
+#define XHC_RH2HSR3_OFFSET			0xd2cU
+#define XHC_RH2HSR3_BASE			0xd2cU
+#define XHC_RH2HSR3__C2U_L			31U
+#define XHC_RH2HSR3__C2U_R			24U
+#define XHC_RH2HSR3__C2U_WIDTH			8U
+#define XHC_RH2HSR3__C2U_RESETVALUE		0x00U
+#define XHC_RH2HSR3__C1U_L			23U
+#define XHC_RH2HSR3__C1U_R			16U
+#define XHC_RH2HSR3__C1U_WIDTH			8U
+#define XHC_RH2HSR3__C1U_RESETVALUE		0x00U
+#define XHC_RH2HSR3__reserved_L			15U
+#define XHC_RH2HSR3__reserved_R			8U
+#define XHC_RH2HSR3__reserved_WIDTH		8U
+#define XHC_RH2HSR3__reserved_RESETVALUE	0x00U
+#define XHC_RH2HSR3__RTY_L			7U
+#define XHC_RH2HSR3__RTY_R			0U
+#define XHC_RH2HSR3__RTY_WIDTH			8U
+#define XHC_RH2HSR3__RTY_RESETVALUE		0x00U
+#define XHC_RH2HSR3_WIDTH			32U
+#define XHC_RH2HSR3__WIDTH			32U
+#define XHC_RH2HSR3_ALL_L			31U
+#define XHC_RH2HSR3_ALL_R			0U
+#define XHC_RH2HSR3__ALL_L			31U
+#define XHC_RH2HSR3__ALL_R			0U
+#define XHC_RH2HSR3_DATAMASK			0xffffffffU
+#define XHC_RH2HSR3_RDWRMASK			0x00000000U
+#define XHC_RH2HSR3_RESETVALUE			0x00000000U
+
+#define XHC_ECHU2P_OFFSET			0xd30U
+#define XHC_ECHU2P_BASE				0xd30U
+#define XHC_ECHU2P__reserved_L			31U
+#define XHC_ECHU2P__reserved_R			16U
+#define XHC_ECHU2P__reserved_WIDTH		16U
+#define XHC_ECHU2P__reserved_RESETVALUE		0x0000U
+#define XHC_ECHU2P__NCP_L			15U
+#define XHC_ECHU2P__NCP_R			8U
+#define XHC_ECHU2P__NCP_WIDTH			8U
+#define XHC_ECHU2P__NCP_RESETVALUE		0x04U
+#define XHC_ECHU2P__CID_L			7U
+#define XHC_ECHU2P__CID_R			0U
+#define XHC_ECHU2P__CID_WIDTH			8U
+#define XHC_ECHU2P__CID_RESETVALUE		0xcaU
+#define XHC_ECHU2P_WIDTH			32U
+#define XHC_ECHU2P__WIDTH			32U
+#define XHC_ECHU2P_ALL_L			31U
+#define XHC_ECHU2P_ALL_R			0U
+#define XHC_ECHU2P__ALL_L			31U
+#define XHC_ECHU2P__ALL_R			0U
+#define XHC_ECHU2P_DATAMASK			0xffffffffU
+#define XHC_ECHU2P_RDWRMASK			0x00000000U
+#define XHC_ECHU2P_RESETVALUE			0x000004caU
+
+#define XHC_U2PVER_OFFSET			0xd34U
+#define XHC_U2PVER_BASE				0xd34U
+#define XHC_U2PVER__MAJ_L			31U
+#define XHC_U2PVER__MAJ_R			28U
+#define XHC_U2PVER__MAJ_WIDTH			4U
+#define XHC_U2PVER__MAJ_RESETVALUE		0x0U
+#define XHC_U2PVER__MIN_L			27U
+#define XHC_U2PVER__MIN_R			24U
+#define XHC_U2PVER__MIN_WIDTH			4U
+#define XHC_U2PVER__MIN_RESETVALUE		0x0U
+#define XHC_U2PVER__RLS_L			23U
+#define XHC_U2PVER__RLS_R			20U
+#define XHC_U2PVER__RLS_WIDTH			4U
+#define XHC_U2PVER__RLS_RESETVALUE		0x0U
+#define XHC_U2PVER__reserved_L			19U
+#define XHC_U2PVER__reserved_R			0U
+#define XHC_U2PVER__reserved_WIDTH		20U
+#define XHC_U2PVER__reserved_RESETVALUE		0x00000U
+#define XHC_U2PVER_WIDTH			32U
+#define XHC_U2PVER__WIDTH			32U
+#define XHC_U2PVER_ALL_L			31U
+#define XHC_U2PVER_ALL_R			0U
+#define XHC_U2PVER__ALL_L			31U
+#define XHC_U2PVER__ALL_R			0U
+#define XHC_U2PVER_DATAMASK			0xffffffffU
+#define XHC_U2PVER_RDWRMASK			0x00000000U
+#define XHC_U2PVER_RESETVALUE			0x00000000U
+
+#define XHC_U2PMGN_OFFSET			0xd38U
+#define XHC_U2PMGN_BASE				0xd38U
+#define XHC_U2PMGN__MGN_L			31U
+#define XHC_U2PMGN__MGN_R			0U
+#define XHC_U2PMGN__MGN_WIDTH			32U
+#define XHC_U2PMGN__MGN_RESETVALUE		0x4b534b4dU
+#define XHC_U2PMGN_WIDTH			32U
+#define XHC_U2PMGN__WIDTH			32U
+#define XHC_U2PMGN_ALL_L			31U
+#define XHC_U2PMGN_ALL_R			0U
+#define XHC_U2PMGN__ALL_L			31U
+#define XHC_U2PMGN__ALL_R			0U
+#define XHC_U2PMGN_DATAMASK			0xffffffffU
+#define XHC_U2PMGN_RDWRMASK			0x00000000U
+#define XHC_U2PMGN_RESETVALUE			0x4b534b4dU
+
+#define XHC_ECHRSV2_OFFSET			0xd40U
+#define XHC_ECHRSV2_BASE			0xd40U
+#define XHC_ECHRSV2__reserved_L			31U
+#define XHC_ECHRSV2__reserved_R			16U
+#define XHC_ECHRSV2__reserved_WIDTH		16U
+#define XHC_ECHRSV2__reserved_RESETVALUE	0x0000U
+#define XHC_ECHRSV2__NCP_L			15U
+#define XHC_ECHRSV2__NCP_R			8U
+#define XHC_ECHRSV2__NCP_WIDTH			8U
+#define XHC_ECHRSV2__NCP_RESETVALUE		0x00U
+#define XHC_ECHRSV2__CID_L			7U
+#define XHC_ECHRSV2__CID_R			0U
+#define XHC_ECHRSV2__CID_WIDTH			8U
+#define XHC_ECHRSV2__CID_RESETVALUE		0xffU
+#define XHC_ECHRSV2_WIDTH			32U
+#define XHC_ECHRSV2__WIDTH			32U
+#define XHC_ECHRSV2_ALL_L			31U
+#define XHC_ECHRSV2_ALL_R			0U
+#define XHC_ECHRSV2__ALL_L			31U
+#define XHC_ECHRSV2__ALL_R			0U
+#define XHC_ECHRSV2_DATAMASK			0xffffffffU
+#define XHC_ECHRSV2_RDWRMASK			0x00000000U
+#define XHC_ECHRSV2_RESETVALUE			0x000000ffU
+
+#define XHC_ECHIRA_OFFSET			0xf90U
+#define XHC_ECHIRA_BASE				0xf90U
+#define XHC_ECHIRA__reserved_L			31U
+#define XHC_ECHIRA__reserved_R			16U
+#define XHC_ECHIRA__reserved_WIDTH		16U
+#define XHC_ECHIRA__reserved_RESETVALUE		0x0000U
+#define XHC_ECHIRA__NCP_L			15U
+#define XHC_ECHIRA__NCP_R			8U
+#define XHC_ECHIRA__NCP_WIDTH			8U
+#define XHC_ECHIRA__NCP_RESETVALUE		0x04U
+#define XHC_ECHIRA__CID_L			7U
+#define XHC_ECHIRA__CID_R			0U
+#define XHC_ECHIRA__CID_WIDTH			8U
+#define XHC_ECHIRA__CID_RESETVALUE		0xfdU
+#define XHC_ECHIRA_WIDTH			32U
+#define XHC_ECHIRA__WIDTH			32U
+#define XHC_ECHIRA_ALL_L			31U
+#define XHC_ECHIRA_ALL_R			0U
+#define XHC_ECHIRA__ALL_L			31U
+#define XHC_ECHIRA__ALL_R			0U
+#define XHC_ECHIRA_DATAMASK			0xffffffffU
+#define XHC_ECHIRA_RDWRMASK			0x00000000U
+#define XHC_ECHIRA_RESETVALUE			0x000004fdU
+
+#define XHC_IRAADR_OFFSET			0xf98U
+#define XHC_IRAADR_BASE				0xf98U
+#define XHC_IRAADR__ADR_L			23U
+#define XHC_IRAADR__ADR_R			2U
+#define XHC_IRAADR__ADR_WIDTH			22U
+#define XHC_IRAADR__ADR_RESETVALUE		0x0U
+#define XHC_IRAADR__reserved			1U
+#define XHC_IRAADR__reserved_L			1U
+#define XHC_IRAADR__reserved_R			1U
+#define XHC_IRAADR__reserved_WIDTH		1U
+#define XHC_IRAADR__reserved_RESETVALUE		0x0U
+#define XHC_IRAADR__MOD				0U
+#define XHC_IRAADR__MOD_L			0U
+#define XHC_IRAADR__MOD_R			0U
+#define XHC_IRAADR__MOD_WIDTH			1U
+#define XHC_IRAADR__MOD_RESETVALUE		0x0U
+#define XHC_IRAADR__RESERVED_L			31U
+#define XHC_IRAADR__RESERVED_R			24U
+#define XHC_IRAADR_WIDTH			24U
+#define XHC_IRAADR__WIDTH			24U
+#define XHC_IRAADR_ALL_L			23U
+#define XHC_IRAADR_ALL_R			0U
+#define XHC_IRAADR__ALL_L			23U
+#define XHC_IRAADR__ALL_R			0U
+#define XHC_IRAADR_DATAMASK			0x00ffffffU
+#define XHC_IRAADR_RDWRMASK			0xff000000U
+#define XHC_IRAADR_RESETVALUE			0x000000U
+
+#define XHC_IRADAT_OFFSET			0xf9cU
+#define XHC_IRADAT_BASE			0xf9cU
+#define XHC_IRADAT__DAT_L			31U
+#define XHC_IRADAT__DAT_R			0U
+#define XHC_IRADAT__DAT_WIDTH			32U
+#define XHC_IRADAT__DAT_RESETVALUE			0x00000000U
+#define XHC_IRADAT_WIDTH			32U
+#define XHC_IRADAT__WIDTH			32U
+#define XHC_IRADAT_ALL_L			31U
+#define XHC_IRADAT_ALL_R			0U
+#define XHC_IRADAT__ALL_L			31U
+#define XHC_IRADAT__ALL_R			0U
+#define XHC_IRADAT_DATAMASK			0xffffffffU
+#define XHC_IRADAT_RDWRMASK			0x00000000U
+#define XHC_IRADAT_RESETVALUE			0x00000000U
+
+
+#define XHC_ECHHST_OFFSET			0xfa0U
+#define XHC_ECHHST_BASE				0xfa0U
+#define XHC_ECHHST__CCC				31U
+#define XHC_ECHHST__CCC_L			31U
+#define XHC_ECHHST__CCC_R			31U
+#define XHC_ECHHST__CCC_WIDTH			1U
+#define XHC_ECHHST__CCC_RESETVALUE		0x1U
+#define XHC_ECHHST__PME				30U
+#define XHC_ECHHST__PME_L			30U
+#define XHC_ECHHST__PME_R			30U
+#define XHC_ECHHST__PME_WIDTH			1U
+#define XHC_ECHHST__PME_RESETVALUE		0x0U
+#define XHC_ECHHST__AUX_L			29U
+#define XHC_ECHHST__AUX_R			24U
+#define XHC_ECHHST__AUX_WIDTH			6U
+#define XHC_ECHHST__AUX_RESETVALUE		0x0U
+#define XHC_ECHHST__IRA				20U
+#define XHC_ECHHST__IRA_L			20U
+#define XHC_ECHHST__IRA_R			20U
+#define XHC_ECHHST__IRA_WIDTH			1U
+#define XHC_ECHHST__IRA_RESETVALUE		0x0U
+#define XHC_ECHHST__ULS				19U
+#define XHC_ECHHST__ULS_L			19U
+#define XHC_ECHHST__ULS_R			19U
+#define XHC_ECHHST__ULS_WIDTH			1U
+#define XHC_ECHHST__ULS_RESETVALUE		0x0U
+#define XHC_ECHHST__reserved			18U
+#define XHC_ECHHST__reserved_L			18U
+#define XHC_ECHHST__reserved_R			18U
+#define XHC_ECHHST__reserved_WIDTH		1U
+#define XHC_ECHHST__reserved_RESETVALUE		0x0U
+#define XHC_ECHHST__TEDA			17U
+#define XHC_ECHHST__TEDA_L			17U
+#define XHC_ECHHST__TEDA_R			17U
+#define XHC_ECHHST__TEDA_WIDTH			1U
+#define XHC_ECHHST__TEDA_RESETVALUE		0x0U
+#define XHC_ECHHST__FSW				16U
+#define XHC_ECHHST__FSW_L			16U
+#define XHC_ECHHST__FSW_R			16U
+#define XHC_ECHHST__FSW_WIDTH			1U
+#define XHC_ECHHST__FSW_RESETVALUE		0x1U
+#define XHC_ECHHST__NCP_L			15U
+#define XHC_ECHHST__NCP_R			8U
+#define XHC_ECHHST__NCP_WIDTH			8U
+#define XHC_ECHHST__NCP_RESETVALUE		0x04U
+#define XHC_ECHHST__CID_L			7U
+#define XHC_ECHHST__CID_R			0U
+#define XHC_ECHHST__CID_WIDTH			8U
+#define XHC_ECHHST__CID_RESETVALUE		0xfcU
+#define XHC_ECHHST__RESERVED_L			23U
+#define XHC_ECHHST__RESERVED_R			21U
+#define XHC_ECHHST_WIDTH			32U
+#define XHC_ECHHST__WIDTH			32U
+#define XHC_ECHHST_ALL_L			31U
+#define XHC_ECHHST_ALL_R			0U
+#define XHC_ECHHST__ALL_L			31U
+#define XHC_ECHHST__ALL_R			0U
+#define XHC_ECHHST_DATAMASK			0xff1fffffU
+#define XHC_ECHHST_RDWRMASK			0x00e00000U
+#define XHC_ECHHST_RESETVALUE			0x800104fcU
+
+#define XHC_HSTDBG_OFFSET			0xfa4U
+#define XHC_HSTDBG_BASE				0xfa4U
+#define XHC_HSTDBG__ETE				31U
+#define XHC_HSTDBG__ETE_L			31U
+#define XHC_HSTDBG__ETE_R			31U
+#define XHC_HSTDBG__ETE_WIDTH			1U
+#define XHC_HSTDBG__ETE_RESETVALUE		0x0U
+#define XHC_HSTDBG__reserved_L			30U
+#define XHC_HSTDBG__reserved_R			16U
+#define XHC_HSTDBG__reserved_WIDTH		15U
+#define XHC_HSTDBG__reserved_RESETVALUE		0x0U
+#define XHC_HSTDBG__OUTP_L			15U
+#define XHC_HSTDBG__OUTP_R			8U
+#define XHC_HSTDBG__OUTP_WIDTH			8U
+#define XHC_HSTDBG__OUTP_RESETVALUE		0x00U
+#define XHC_HSTDBG__INP_L			7U
+#define XHC_HSTDBG__INP_R			0U
+#define XHC_HSTDBG__INP_WIDTH			8U
+#define XHC_HSTDBG__INP_RESETVALUE		0x00U
+#define XHC_HSTDBG_WIDTH			32U
+#define XHC_HSTDBG__WIDTH			32U
+#define XHC_HSTDBG_ALL_L			31U
+#define XHC_HSTDBG_ALL_R			0U
+#define XHC_HSTDBG__ALL_L			31U
+#define XHC_HSTDBG__ALL_R			0U
+#define XHC_HSTDBG_DATAMASK			0xffffffffU
+#define XHC_HSTDBG_RDWRMASK			0x00000000U
+#define XHC_HSTDBG_RESETVALUE			0x00000000U
+
+#define XHC_HSTNPL_OFFSET			0xfa8U
+#define XHC_HSTNPL_BASE				0xfa8U
+#define XHC_HSTNPL__NPL_L			31U
+#define XHC_HSTNPL__NPL_R			9U
+#define XHC_HSTNPL__NPL_WIDTH			23U
+#define XHC_HSTNPL__NPL_RESETVALUE		0x0U
+#define XHC_HSTNPL__reserved_L			8U
+#define XHC_HSTNPL__reserved_R			0U
+#define XHC_HSTNPL__reserved_WIDTH		9U
+#define XHC_HSTNPL__reserved_RESETVALUE		0x0U
+#define XHC_HSTNPL_WIDTH			32U
+#define XHC_HSTNPL__WIDTH			32U
+#define XHC_HSTNPL_ALL_L			31U
+#define XHC_HSTNPL_ALL_R			0U
+#define XHC_HSTNPL__ALL_L			31U
+#define XHC_HSTNPL__ALL_R			0U
+#define XHC_HSTNPL_DATAMASK			0xffffffffU
+#define XHC_HSTNPL_RDWRMASK			0x00000000U
+#define XHC_HSTNPL_RESETVALUE			0x00000000U
+
+#define XHC_HSTNPH_OFFSET			0xfacU
+#define XHC_HSTNPH_BASE				0xfacU
+#define XHC_HSTNPH__NPH_L			31U
+#define XHC_HSTNPH__NPH_R			0U
+#define XHC_HSTNPH__NPH_WIDTH			32U
+#define XHC_HSTNPH__NPH_RESETVALUE		0x00000000U
+#define XHC_HSTNPH_WIDTH			32U
+#define XHC_HSTNPH__WIDTH			32U
+#define XHC_HSTNPH_ALL_L			31U
+#define XHC_HSTNPH_ALL_R			0U
+#define XHC_HSTNPH__ALL_L			31U
+#define XHC_HSTNPH__ALL_R			0U
+#define XHC_HSTNPH_DATAMASK			0xffffffffU
+#define XHC_HSTNPH_RDWRMASK			0x00000000U
+#define XHC_HSTNPH_RESETVALUE			0x00000000U
+
+#define XHC_ECHRBV_OFFSET			0xfb0U
+#define XHC_ECHRBV_BASE				0xfb0U
+#define XHC_ECHRBV__MAJ_L			31U
+#define XHC_ECHRBV__MAJ_R			28U
+#define XHC_ECHRBV__MAJ_WIDTH			4U
+#define XHC_ECHRBV__MAJ_RESETVALUE		0x0U
+#define XHC_ECHRBV__MIN_L			27U
+#define XHC_ECHRBV__MIN_R			24U
+#define XHC_ECHRBV__MIN_WIDTH			4U
+#define XHC_ECHRBV__MIN_RESETVALUE		0x0U
+#define XHC_ECHRBV__RLS_L			23U
+#define XHC_ECHRBV__RLS_R			16U
+#define XHC_ECHRBV__RLS_WIDTH			8U
+#define XHC_ECHRBV__RLS_RESETVALUE		0x00U
+#define XHC_ECHRBV__NCP_L			15U
+#define XHC_ECHRBV__NCP_R			8U
+#define XHC_ECHRBV__NCP_WIDTH			8U
+#define XHC_ECHRBV__NCP_RESETVALUE		0x00U
+#define XHC_ECHRBV__CID_L			7U
+#define XHC_ECHRBV__CID_R			0U
+#define XHC_ECHRBV__CID_WIDTH			8U
+#define XHC_ECHRBV__CID_RESETVALUE		0xfeU
+#define XHC_ECHRBV_WIDTH			32U
+#define XHC_ECHRBV__WIDTH			32U
+#define XHC_ECHRBV_ALL_L			31U
+#define XHC_ECHRBV_ALL_R			0U
+#define XHC_ECHRBV__ALL_L			31U
+#define XHC_ECHRBV__ALL_R			0U
+#define XHC_ECHRBV_DATAMASK			0xffffffffU
+#define XHC_ECHRBV_RDWRMASK			0x00000000U
+#define XHC_ECHRBV_RESETVALUE			0x000000feU
+
+#define XHC_RBVPDT_OFFSET			0xfb4U
+#define XHC_RBVPDT_BASE				0xfb4U
+#define XHC_RBVPDT__VDR_L			31U
+#define XHC_RBVPDT__VDR_R			16U
+#define XHC_RBVPDT__VDR_WIDTH			16U
+#define XHC_RBVPDT__VDR_RESETVALUE		0x0a5cU
+#define XHC_RBVPDT__PDT_L			15U
+#define XHC_RBVPDT__PDT_R			0U
+#define XHC_RBVPDT__PDT_WIDTH			16U
+#define XHC_RBVPDT__PDT_RESETVALUE		0x0000U
+#define XHC_RBVPDT_WIDTH			32U
+#define XHC_RBVPDT__WIDTH			32U
+#define XHC_RBVPDT_ALL_L			31U
+#define XHC_RBVPDT_ALL_R			0U
+#define XHC_RBVPDT__ALL_L			31U
+#define XHC_RBVPDT__ALL_R			0U
+#define XHC_RBVPDT_DATAMASK			0xffffffffU
+#define XHC_RBVPDT_RDWRMASK			0x00000000U
+#define XHC_RBVPDT_RESETVALUE			0x0a5c0000U
+
+#define XHC_RBVMGN_OFFSET			0xfbcU
+#define XHC_RBVMGN_BASE				0xfbcU
+#define XHC_RBVMGN__MGN_L			31U
+#define XHC_RBVMGN__MGN_R			0U
+#define XHC_RBVMGN__MGN_WIDTH			32U
+#define XHC_RBVMGN__MGN_RESETVALUE		0x52535354U
+#define XHC_RBVMGN_WIDTH			32U
+#define XHC_RBVMGN__WIDTH			32U
+#define XHC_RBVMGN_ALL_L			31U
+#define XHC_RBVMGN_ALL_R			0U
+#define XHC_RBVMGN__ALL_L			31U
+#define XHC_RBVMGN__ALL_R			0U
+#define XHC_RBVMGN_DATAMASK			0xffffffffU
+#define XHC_RBVMGN_RDWRMASK			0x00000000U
+#define XHC_RBVMGN_RESETVALUE			0x52535354U
+
+/* PORTSC field defines */
+#define XHC_PORTSC__PS_LINK_STATE_U0		0U
+#define XHC_PORTSC__PS_LINK_STATE_U1		1U
+#define XHC_PORTSC__PS_LINK_STATE_U2		2U
+#define XHC_PORTSC__PS_LINK_STATE_U3		3U
+#define XHC_PORTSC__PS_LINK_STATE_DISABLED	4U
+#define XHC_PORTSC__PS_LINK_STATE_RX_DETECT	5U
+#define XHC_PORTSC__PS_LINK_STATE_INACTIVE	6U
+#define XHC_PORTSC__PS_LINK_STATE_POLLING	7U
+#define XHC_PORTSC__PS_LINK_STATE_RECOVERY	8U
+#define XHC_PORTSC__PS_LINK_STATE_HOT_RESET	9U
+#define XHC_PORTSC__PS_LINK_STATE_COMPLIANCE	10U
+#define XHC_PORTSC__PS_LINK_STATE_TEST		11U
+#define XHC_PORTSC__PS_LINK_STATE_RESUME	15U
+
+#define XHC_PORTSC__PS_SPEED_UNDEFINED		0U
+#define XHC_PORTSC__PS_FS			1U
+#define XHC_PORTSC__PS_LS			2U
+#define XHC_PORTSC__PS_HS			3U
+#define XHC_PORTSC__PS_SS			4U
+
+/* macros and inline functions */
+
+/* write 64bit ptr 'p' to destination 'd' with offset 'v' */
+inline void WRITE64_REG_PTRL(uint32_t r, uint32_t *p)
+{
+	uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r);
+
+	*ptr = (uint32_t) ((uint64_t) p & (uint64_t) 0xffffffffU);
+}
+
+inline void WRITE64_REG_PTRH(uint32_t r, uint32_t *p)
+{
+	uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r);
+
+	*ptr = (uint32_t) ((uint64_t) p >> 32U);
+}
+
+#define XHC_REG_RD(addr)   mmio_read_32(XHC_BASE + addr)
+
+#define XHC_REG_WR(addr, val) mmio_write_32(XHC_BASE+addr, val)
+
+#endif				/* USBH_XHCI_REGS_H */
+
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index 7611f01..834a80f 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -60,10 +60,16 @@
 #define CMD_EXTCSD_PARTITION_CONFIG	179
 #define CMD_EXTCSD_BUS_WIDTH		183
 #define CMD_EXTCSD_HS_TIMING		185
+#define CMD_EXTCSD_PART_SWITCH_TIME	199
 #define CMD_EXTCSD_SEC_CNT		212
 
+#define EXT_CSD_PART_CONFIG_ACC_MASK	GENMASK(2, 0)
 #define PART_CFG_BOOT_PARTITION1_ENABLE	(U(1) << 3)
-#define PART_CFG_PARTITION1_ACCESS	(U(1) << 0)
+#define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0)
+#define PART_CFG_BOOT_PART_EN_MASK		GENMASK(5, 3)
+#define PART_CFG_BOOT_PART_EN_SHIFT		3
+#define PART_CFG_CURRENT_BOOT_PARTITION(x)	(((x) & PART_CFG_BOOT_PART_EN_MASK) >> \
+	PART_CFG_BOOT_PART_EN_SHIFT)
 
 /* Values in EXT CSD register */
 #define MMC_BUS_WIDTH_1			U(0)
@@ -230,6 +236,7 @@
 size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
 size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
 size_t mmc_rpmb_erase_blocks(int lba, size_t size);
+size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size);
 int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
 	     unsigned int width, unsigned int flags,
 	     struct mmc_device_info *device_info);
diff --git a/include/drivers/st/io_mmc.h b/include/drivers/st/io_mmc.h
index b35b4b5..6179e89 100644
--- a/include/drivers/st/io_mmc.h
+++ b/include/drivers/st/io_mmc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,10 @@
 
 #include <drivers/io/io_driver.h>
 
+struct io_mmc_dev_spec {
+	bool use_boot_part;
+};
+
 int register_io_dev_mmc(const io_dev_connector_t **dev_con);
 
 #endif /* IO_MMC_H */
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index aa9158c..803cd9c 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -1,21 +1,26 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
 /*
+ * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
  * This header provides constants for the ARM GIC.
  */
 
 #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
 #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 /* interrupt specifier cell 0 */
 
 #define GIC_SPI 0
 #define GIC_PPI 1
 
-#define IRQ_TYPE_NONE		0
-#define IRQ_TYPE_EDGE_RISING	1
-#define IRQ_TYPE_EDGE_FALLING	2
-#define IRQ_TYPE_EDGE_BOTH	(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
-#define IRQ_TYPE_LEVEL_HIGH	4
-#define IRQ_TYPE_LEVEL_LOW	8
+/*
+ * Interrupt specifier cell 2.
+ * The flags in irq.h are valid, plus those below.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
 
 #endif
diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h
new file mode 100644
index 0000000..94e7f95
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/irq.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE		0
+#define IRQ_TYPE_EDGE_RISING	1
+#define IRQ_TYPE_EDGE_FALLING	2
+#define IRQ_TYPE_EDGE_BOTH	(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH	4
+#define IRQ_TYPE_LEVEL_LOW	8
+
+#endif
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h
new file mode 100644
index 0000000..6a4cfdf
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A510_H
+#define CORTEX_A510_H
+
+#define CORTEX_A510_MIDR					U(0x410FD460)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A510_CPUECTLR_EL1				S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A510_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+
+#endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
new file mode 100644
index 0000000..44c540c
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A710_H
+#define CORTEX_A710_H
+
+#define CORTEX_A710_MIDR					U(0x410FD470)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A710_CPUECTLR_EL1				S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A710_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+
+#endif /* CORTEX_A710_H */
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index 0a42a5d..5753e90 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,6 +24,12 @@
 #define CORTEX_A77_CPUPWRCTLR_EL1			S3_0_C15_C2_7
 #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	(U(1) << 0)
 
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A77_ACTLR2_EL1				S3_0_C15_C1_1
+#define CORTEX_A77_ACTLR2_EL1_BIT_2			(ULL(1) << 2)
+
 #define CORTEX_A77_CPUPSELR_EL3				S3_6_C15_C8_0
 #define CORTEX_A77_CPUPCR_EL3				S3_6_C15_C8_1
 #define CORTEX_A77_CPUPOR_EL3				S3_6_C15_C8_2
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index caa5120..4bc49f3 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -30,6 +30,7 @@
 
 #define CORTEX_A78_ACTLR2_EL1				S3_0_C15_C1_1
 #define CORTEX_A78_ACTLR2_EL1_BIT_1			(ULL(1) << 1)
+#define CORTEX_A78_ACTLR2_EL1_BIT_2			(ULL(1) << 2)
 
 /*******************************************************************************
  * CPU Activity Monitor Unit register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h
new file mode 100644
index 0000000..adb13bc
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a78c.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A78C_H
+#define CORTEX_A78C_H
+
+
+#define CORTEX_A78C_MIDR			        U(0x410FD4B1)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A78C_CPUECTLR_EL1		        S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A78C_CPUPWRCTLR_EL1			S3_0_C15_C2_7
+#define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT	U(1)
+
+#endif /* CORTEX_A78C_H */
diff --git a/include/lib/cpus/aarch64/cortex_klein.h b/include/lib/cpus/aarch64/cortex_klein.h
deleted file mode 100644
index 729b3bf..0000000
--- a/include/lib/cpus/aarch64/cortex_klein.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_KLEIN_H
-#define CORTEX_KLEIN_H
-
-#define CORTEX_KLEIN_MIDR					U(0x410FD460)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_KLEIN_CPUECTLR_EL1				S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_KLEIN_CPUPWRCTLR_EL1				S3_0_C15_C2_7
-#define CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
-
-#endif /* CORTEX_KLEIN_H */
diff --git a/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h b/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h
new file mode 100644
index 0000000..a0d788e
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_MAKALU_ELP_ARM_H
+#define CORTEX_MAKALU_ELP_ARM_H
+
+#define CORTEX_MAKALU_ELP_ARM_MIDR				U(0x410FD4E0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1			S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1			S3_0_C15_C2_7
+#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
+
+#endif /* CORTEX_MAKALU_ELP_ARM_H */
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn.h b/include/lib/cpus/aarch64/cortex_matterhorn.h
deleted file mode 100644
index 0185533..0000000
--- a/include/lib/cpus/aarch64/cortex_matterhorn.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_MATTERHORN_H
-#define CORTEX_MATTERHORN_H
-
-#define CORTEX_MATTERHORN_MIDR					U(0x410FD470)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_CPUECTLR_EL1				S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1			S3_0_C15_C2_7
-#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
-
-#endif /* CORTEX_MATTERHORN_H */
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h b/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h
deleted file mode 100644
index 309578e..0000000
--- a/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_MATTERHORN_ELP_ARM_H
-#define CORTEX_MATTERHORN_ELP_ARM_H
-
-#define CORTEX_MATTERHORN_ELP_ARM_MIDR					U(0x410FD480)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1				S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1			S3_0_C15_C2_7
-#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
-
-#endif /* CORTEX_MATTERHORN_ELP_ARM_H */
diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
new file mode 100644
index 0000000..9ce1223
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_x2.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_X2_H
+#define CORTEX_X2_H
+
+#define CORTEX_X2_MIDR						U(0x410FD480)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUECTLR_EL1					S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT			U(1)
+
+#endif /* CORTEX_X2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 650eb4d..cea2659 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,4 +20,10 @@
 #define NEOVERSE_V1_CPUPWRCTLR_EL1				S3_0_C15_C2_7
 #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
 
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V1_ACTLR2_EL1					S3_0_C15_C1_1
+#define NEOVERSE_V1_ACTLR2_EL1_BIT_2				(ULL(1) << 2)
+
 #endif /* NEOVERSE_V1_H */
diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h
new file mode 100644
index 0000000..14da170
--- /dev/null
+++ b/include/lib/cpus/aarch64/qemu_max.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QEMU_MAX_H
+#define QEMU_MAX_H
+
+#include <lib/utils_def.h>
+
+/*
+ *  QEMU MAX midr for revision 0
+ *  00   - Reserved for software use
+ *  0    - Variant
+ *  F    - Architectural features identified in ID_* registers
+ *  051  - 'Q', in a 12-bit field.
+ *  0    - Revision
+ */
+#define QEMU_MAX_MIDR		U(0x000F0510)
+
+#endif /* QEMU_MAX_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 3135fb4..d449a65 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -61,7 +61,9 @@
 #define CTX_ELR_EL3		U(0x20)
 #define CTX_PMCR_EL0		U(0x28)
 #define CTX_IS_IN_EL3		U(0x30)
-#define CTX_EL3STATE_END	U(0x40) /* Align to the next 16 byte boundary */
+#define CTX_CPTR_EL3		U(0x38)
+#define CTX_ZCR_EL3		U(0x40)
+#define CTX_EL3STATE_END	U(0x50) /* Align to the next 16 byte boundary */
 
 /*******************************************************************************
  * Constants that allow assembler code to access members of and the
@@ -160,86 +162,74 @@
 #define CTX_AFSR1_EL2		U(0x10)
 #define CTX_AMAIR_EL2		U(0x18)
 #define CTX_CNTHCTL_EL2		U(0x20)
-#define CTX_CNTHP_CTL_EL2	U(0x28)
-#define CTX_CNTHP_CVAL_EL2	U(0x30)
-#define CTX_CNTHP_TVAL_EL2	U(0x38)
-#define CTX_CNTVOFF_EL2		U(0x40)
-#define CTX_CPTR_EL2		U(0x48)
-#define CTX_DBGVCR32_EL2	U(0x50)
-#define CTX_ELR_EL2		U(0x58)
-#define CTX_ESR_EL2		U(0x60)
-#define CTX_FAR_EL2		U(0x68)
-#define CTX_HACR_EL2		U(0x70)
-#define CTX_HCR_EL2		U(0x78)
-#define CTX_HPFAR_EL2		U(0x80)
-#define CTX_HSTR_EL2		U(0x88)
-#define CTX_ICC_SRE_EL2		U(0x90)
-#define CTX_ICH_HCR_EL2		U(0x98)
-#define CTX_ICH_VMCR_EL2	U(0xa0)
-#define CTX_MAIR_EL2		U(0xa8)
-#define CTX_MDCR_EL2		U(0xb0)
-#define CTX_PMSCR_EL2		U(0xb8)
-#define CTX_SCTLR_EL2		U(0xc0)
-#define CTX_SPSR_EL2		U(0xc8)
-#define CTX_SP_EL2		U(0xd0)
-#define CTX_TCR_EL2		U(0xd8)
-#define CTX_TPIDR_EL2		U(0xe0)
-#define CTX_TTBR0_EL2		U(0xe8)
-#define CTX_VBAR_EL2		U(0xf0)
-#define CTX_VMPIDR_EL2		U(0xf8)
-#define CTX_VPIDR_EL2		U(0x100)
-#define CTX_VTCR_EL2		U(0x108)
-#define CTX_VTTBR_EL2		U(0x110)
+#define CTX_CNTVOFF_EL2		U(0x28)
+#define CTX_CPTR_EL2		U(0x30)
+#define CTX_DBGVCR32_EL2	U(0x38)
+#define CTX_ELR_EL2		U(0x40)
+#define CTX_ESR_EL2		U(0x48)
+#define CTX_FAR_EL2		U(0x50)
+#define CTX_HACR_EL2		U(0x58)
+#define CTX_HCR_EL2		U(0x60)
+#define CTX_HPFAR_EL2		U(0x68)
+#define CTX_HSTR_EL2		U(0x70)
+#define CTX_ICC_SRE_EL2		U(0x78)
+#define CTX_ICH_HCR_EL2		U(0x80)
+#define CTX_ICH_VMCR_EL2	U(0x88)
+#define CTX_MAIR_EL2		U(0x90)
+#define CTX_MDCR_EL2		U(0x98)
+#define CTX_PMSCR_EL2		U(0xa0)
+#define CTX_SCTLR_EL2		U(0xa8)
+#define CTX_SPSR_EL2		U(0xb0)
+#define CTX_SP_EL2		U(0xb8)
+#define CTX_TCR_EL2		U(0xc0)
+#define CTX_TPIDR_EL2		U(0xc8)
+#define CTX_TTBR0_EL2		U(0xd0)
+#define CTX_VBAR_EL2		U(0xd8)
+#define CTX_VMPIDR_EL2		U(0xe0)
+#define CTX_VPIDR_EL2		U(0xe8)
+#define CTX_VTCR_EL2		U(0xf0)
+#define CTX_VTTBR_EL2		U(0xf8)
 
 // Only if MTE registers in use
-#define CTX_TFSR_EL2		U(0x118)
+#define CTX_TFSR_EL2		U(0x100)
 
 // Only if ENABLE_MPAM_FOR_LOWER_ELS==1
-#define CTX_MPAM2_EL2		U(0x120)
-#define CTX_MPAMHCR_EL2		U(0x128)
-#define CTX_MPAMVPM0_EL2	U(0x130)
-#define CTX_MPAMVPM1_EL2	U(0x138)
-#define CTX_MPAMVPM2_EL2	U(0x140)
-#define CTX_MPAMVPM3_EL2	U(0x148)
-#define CTX_MPAMVPM4_EL2	U(0x150)
-#define CTX_MPAMVPM5_EL2	U(0x158)
-#define CTX_MPAMVPM6_EL2	U(0x160)
-#define CTX_MPAMVPM7_EL2	U(0x168)
-#define CTX_MPAMVPMV_EL2	U(0x170)
+#define CTX_MPAM2_EL2		U(0x108)
+#define CTX_MPAMHCR_EL2		U(0x110)
+#define CTX_MPAMVPM0_EL2	U(0x118)
+#define CTX_MPAMVPM1_EL2	U(0x120)
+#define CTX_MPAMVPM2_EL2	U(0x128)
+#define CTX_MPAMVPM3_EL2	U(0x130)
+#define CTX_MPAMVPM4_EL2	U(0x138)
+#define CTX_MPAMVPM5_EL2	U(0x140)
+#define CTX_MPAMVPM6_EL2	U(0x148)
+#define CTX_MPAMVPM7_EL2	U(0x150)
+#define CTX_MPAMVPMV_EL2	U(0x158)
 
 // Starting with Armv8.6
-#define CTX_HAFGRTR_EL2		U(0x178)
-#define CTX_HDFGRTR_EL2		U(0x180)
-#define CTX_HDFGWTR_EL2		U(0x188)
-#define CTX_HFGITR_EL2		U(0x190)
-#define CTX_HFGRTR_EL2		U(0x198)
-#define CTX_HFGWTR_EL2		U(0x1a0)
-#define CTX_CNTPOFF_EL2		U(0x1a8)
+#define CTX_HAFGRTR_EL2		U(0x160)
+#define CTX_HDFGRTR_EL2		U(0x168)
+#define CTX_HDFGWTR_EL2		U(0x170)
+#define CTX_HFGITR_EL2		U(0x178)
+#define CTX_HFGRTR_EL2		U(0x180)
+#define CTX_HFGWTR_EL2		U(0x188)
+#define CTX_CNTPOFF_EL2		U(0x190)
 
 // Starting with Armv8.4
-#define CTX_CNTHPS_CTL_EL2	U(0x1b0)
-#define CTX_CNTHPS_CVAL_EL2	U(0x1b8)
-#define CTX_CNTHPS_TVAL_EL2	U(0x1c0)
-#define CTX_CNTHVS_CTL_EL2	U(0x1c8)
-#define CTX_CNTHVS_CVAL_EL2	U(0x1d0)
-#define CTX_CNTHVS_TVAL_EL2	U(0x1d8)
-#define CTX_CNTHV_CTL_EL2	U(0x1e0)
-#define CTX_CNTHV_CVAL_EL2	U(0x1e8)
-#define CTX_CNTHV_TVAL_EL2	U(0x1f0)
-#define CTX_CONTEXTIDR_EL2	U(0x1f8)
-#define CTX_SDER32_EL2		U(0x200)
-#define CTX_TTBR1_EL2		U(0x208)
-#define CTX_VDISR_EL2		U(0x210)
-#define CTX_VNCR_EL2		U(0x218)
-#define CTX_VSESR_EL2		U(0x220)
-#define CTX_VSTCR_EL2		U(0x228)
-#define CTX_VSTTBR_EL2		U(0x230)
-#define CTX_TRFCR_EL2		U(0x238)
+#define CTX_CONTEXTIDR_EL2	U(0x198)
+#define CTX_SDER32_EL2		U(0x1a0)
+#define CTX_TTBR1_EL2		U(0x1a8)
+#define CTX_VDISR_EL2		U(0x1b0)
+#define CTX_VNCR_EL2		U(0x1b8)
+#define CTX_VSESR_EL2		U(0x1c0)
+#define CTX_VSTCR_EL2		U(0x1c8)
+#define CTX_VSTTBR_EL2		U(0x1d0)
+#define CTX_TRFCR_EL2		U(0x1d8)
 
 // Starting with Armv8.5
-#define CTX_SCXTNUM_EL2		U(0x240)
+#define CTX_SCXTNUM_EL2		U(0x1e0)
 /* Align to the next 16 byte boundary */
-#define CTX_EL2_SYSREGS_END	U(0x250)
+#define CTX_EL2_SYSREGS_END	U(0x1f0)
 
 #endif /* CTX_INCLUDE_EL2_REGS */
 
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index 3a70e4f..3a254c9 100644
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -13,6 +13,7 @@
 #include <lib/cassert.h>
 #include <lib/utils_def.h>
 
+#include <context.h>
 #include <platform_def.h>
 
 /* All group 0 counters */
@@ -80,7 +81,11 @@
 };
 
 unsigned int amu_get_version(void);
+#if __aarch64__
+void amu_enable(bool el2_unused, cpu_context_t *ctx);
+#else
 void amu_enable(bool el2_unused);
+#endif
 
 /* Group 0 configuration helpers */
 uint64_t amu_group0_cnt_read(unsigned int idx);
diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h
index ac8c00a..414adcb 100644
--- a/include/lib/extensions/mpam.h
+++ b/include/lib/extensions/mpam.h
@@ -9,7 +9,6 @@
 
 #include <stdbool.h>
 
-bool mpam_supported(void);
 void mpam_enable(bool el2_unused);
 
 #endif /* MPAM_H */
diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h
index 83df177..c85e08c 100644
--- a/include/lib/extensions/sve.h
+++ b/include/lib/extensions/sve.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,9 +7,8 @@
 #ifndef SVE_H
 #define SVE_H
 
-#include <stdbool.h>
+#include <context.h>
 
-bool sve_supported(void);
-void sve_enable(bool el2_unused);
+void sve_enable(cpu_context_t *context);
 
 #endif /* SVE_H */
diff --git a/include/lib/libc/arm_acle.h b/include/lib/libc/arm_acle.h
index 953933f..eb08552 100644
--- a/include/lib/libc/arm_acle.h
+++ b/include/lib/libc/arm_acle.h
@@ -14,8 +14,10 @@
 #define ARM_ACLE_H
 
 #if !defined(__aarch64__) || defined(__clang__)
+#	define __crc32b __builtin_arm_crc32b
 #	define __crc32w __builtin_arm_crc32w
 #else
+#	define __crc32b __builtin_aarch64_crc32b
 #	define __crc32w __builtin_aarch64_crc32w
 #endif
 
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index 470317d..deaeb1d 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -51,6 +51,23 @@
 					 FUNCID_OEN_MASK)
 
 /*******************************************************************************
+ * SMCCC_ARCH_SOC_ID SoC version & revision bit definition
+ ******************************************************************************/
+#define SOC_ID_JEP_106_BANK_IDX_MASK	GENMASK_32(30, 24)
+#define SOC_ID_JEP_106_BANK_IDX_SHIFT	U(24)
+#define SOC_ID_JEP_106_ID_CODE_MASK	GENMASK_32(23, 16)
+#define SOC_ID_JEP_106_ID_CODE_SHIFT	U(16)
+#define SOC_ID_IMPL_DEF_MASK		GENMASK_32(15, 0)
+#define SOC_ID_IMPL_DEF_SHIFT		U(0)
+#define SOC_ID_SET_JEP_106(bkid, mfid)	((((bkid) << SOC_ID_JEP_106_BANK_IDX_SHIFT) & \
+					  SOC_ID_JEP_106_BANK_IDX_MASK) | \
+					 (((mfid) << SOC_ID_JEP_106_ID_CODE_SHIFT) & \
+					  SOC_ID_JEP_106_ID_CODE_MASK))
+
+#define SOC_ID_REV_MASK			GENMASK_32(30, 0)
+#define SOC_ID_REV_SHIFT		U(0)
+
+/*******************************************************************************
  * Owning entity number definitions inside the function id as per the SMC
  * calling convention
  ******************************************************************************/
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index b79e0d5..1963bf0 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -44,8 +44,18 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#if ARM_GPT_SUPPORT
+/*
+ * Offset of the FIP in the GPT image. BL1 component uses this option
+ * as it does not load the partition table to get the FIP base
+ * address. At sector 34 by default (i.e. after reserved sectors 0-33)
+ * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
+ */
+#define PLAT_ARM_FIP_OFFSET_IN_GPT		0x4400
+#endif /* ARM_GPT_SUPPORT */
 
 #define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
 #define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 00746c6..ae80628 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -465,12 +465,16 @@
  * BL32 specific defines for EL3 runtime in AArch32 mode
  ******************************************************************************/
 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
+/* Ensure Position Independent support (PIE) is enabled for this config.*/
+# if !ENABLE_PIE
+#  error "BL32 must be a PIE if RESET_TO_SP_MIN=1."
+#endif
 /*
- * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
- * the page reserved for fw_configs) to BL32
+ * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely
+ * used for building BL32 and not used for loading BL32.
  */
-#  define BL32_BASE			ARM_FW_CONFIGS_LIMIT
-#  define BL32_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+#  define BL32_BASE			0x0
+#  define BL32_LIMIT			PLAT_ARM_MAX_BL32_SIZE
 # else
 /* Put BL32 below BL2 in the Trusted SRAM.*/
 #  define BL32_BASE			((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h
index 85fdb28..2eeed95 100644
--- a/include/plat/arm/common/arm_sip_svc.h
+++ b/include/plat/arm/common/arm_sip_svc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,6 +25,12 @@
 /* DEBUGFS_SMC_32			0x82000030U */
 /* DEBUGFS_SMC_64			0xC2000030U */
 
+/*
+ * Arm Ethos-N NPU SiP SMC function IDs
+ * 0xC2000050-0xC200005F
+ * 0x82000050-0x8200005F
+ */
+
 /* ARM SiP Service Calls version numbers */
 #define ARM_SIP_SVC_VERSION_MAJOR		U(0x0)
 #define ARM_SIP_SVC_VERSION_MINOR		U(0x2)
diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h
new file mode 100644
index 0000000..0fd1f02
--- /dev/null
+++ b/include/plat/arm/common/fconf_ethosn_getter.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FCONF_ETHOSN_GETTER_H
+#define FCONF_ETHOSN_GETTER_H
+
+#include <assert.h>
+
+#include <lib/fconf/fconf.h>
+
+#define hw_config__ethosn_config_getter(prop) ethosn_config.prop
+#define hw_config__ethosn_core_addr_getter(idx) __extension__ ({	\
+	assert(idx < ethosn_config.num_cores);				\
+	ethosn_config.core_addr[idx];					\
+})
+
+#define ETHOSN_STATUS_DISABLED U(0)
+#define ETHOSN_STATUS_ENABLED  U(1)
+
+#define ETHOSN_CORE_NUM_MAX U(64)
+
+struct ethosn_config_t {
+	uint8_t status;
+	uint32_t num_cores;
+	uint64_t core_addr[ETHOSN_CORE_NUM_MAX];
+};
+
+int fconf_populate_arm_ethosn(uintptr_t config);
+
+extern struct ethosn_config_t ethosn_config;
+
+#endif /* FCONF_ETHOSN_GETTER_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 95fc18e..846c9a4 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -152,6 +152,9 @@
 /* IO storage utility functions */
 int arm_io_setup(void);
 
+/* Set image specification in IO block policy */
+int arm_set_image_source(unsigned int image_id, const char *part_name);
+
 /* Security utility functions */
 void arm_tzc400_setup(uintptr_t tzc_base,
 			const arm_tzc_regions_info_t *tzc_regions);
diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h
index 6e698e5..0f4e573 100644
--- a/include/plat/arm/common/smccc_def.h
+++ b/include/plat/arm/common/smccc_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,5 @@
 /* Defines used to retrieve ARM SOC revision */
 #define ARM_SOC_CONTINUATION_CODE	U(0x4)
 #define ARM_SOC_IDENTIFICATION_CODE	U(0x3B)
-#define ARM_SOC_CONTINUATION_SHIFT	U(24)
-#define ARM_SOC_IDENTIFICATION_SHIFT	U(16)
 
 #endif /* SMCCC_DEF_H */
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index d599352..dde174c 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -137,6 +137,8 @@
 #define SSC_DBGCFG_SET		0x14
 #define SSC_DBGCFG_CLR		0x18
 
+#define SPNIDEN_INT_CLR_SHIFT	4
+#define SPNIDEN_SEL_SET_SHIFT	5
 #define SPIDEN_INT_CLR_SHIFT	6
 #define SPIDEN_SEL_SET_SHIFT	7
 
diff --git a/include/plat/marvell/armada/a3k/common/plat_marvell.h b/include/plat/marvell/armada/a3k/common/plat_marvell.h
index ea7cdcd..cb31481 100644
--- a/include/plat/marvell/armada/a3k/common/plat_marvell.h
+++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h
@@ -100,4 +100,6 @@
 
 const mmap_region_t *plat_marvell_get_mmap(void);
 
+uint32_t get_ref_clk(void);
+
 #endif /* PLAT_MARVELL_H */
diff --git a/include/plat/marvell/armada/a8k/common/efuse_def.h b/include/plat/marvell/armada/a8k/common/efuse_def.h
new file mode 100644
index 0000000..ff1d4a3
--- /dev/null
+++ b/include/plat/marvell/armada/a8k/common/efuse_def.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef EFUSE_DEF_H
+#define EFUSE_DEF_H
+
+#include <platform_def.h>
+
+#define MVEBU_AP_EFUSE_SRV_CTRL_REG	(MVEBU_AP_GEN_MGMT_BASE + 0x8)
+#define EFUSE_SRV_CTRL_LD_SELECT_OFFS	6
+#define EFUSE_SRV_CTRL_LD_SELECT_MASK	(1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
+
+#define MVEBU_AP_LD_EFUSE_BASE		(MVEBU_AP_GEN_MGMT_BASE + 0xF00)
+/* Bits [31:0] - 32 data bits total */
+#define MVEBU_AP_LDX_31_0_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE)
+/* Bits [62:32] - 31 data bits total 32nd bit is parity for bits [62:0]*/
+#define MVEBU_AP_LDX_62_32_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0x4)
+/* Bits [94:63] - 32 data bits total */
+#define MVEBU_AP_LDX_94_63_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0x8)
+/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */
+#define MVEBU_AP_LDX_125_95_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0xC)
+/* Bits [157:126] - 32 data bits total */
+#define MVEBU_AP_LDX_126_157_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0x10)
+/* Bits [188:158] - 31 data bits total, 32nd bit is parity for bits [188:126] */
+#define MVEBU_AP_LDX_188_158_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0x14)
+/* Bits [220:189] - 32 data bits total */
+#define MVEBU_AP_LDX_220_189_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0x18)
+
+#endif /* EFUSE_DEF_H */
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index ec75bc9..5b39c42 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h
@@ -22,7 +22,7 @@
 
 /* The macros below are used to identify FFA calls from the SMC function ID */
 #define FFA_FNUM_MIN_VALUE	U(0x60)
-#define FFA_FNUM_MAX_VALUE	U(0x84)
+#define FFA_FNUM_MAX_VALUE	U(0x85)
 #define is_ffa_fid(fid) __extension__ ({		\
 	__typeof__(fid) _fid = (fid);			\
 	((GET_SMC_NUM(_fid) >= FFA_FNUM_MIN_VALUE) &&	\
@@ -70,7 +70,7 @@
 #define FFA_FNUM_RXTX_MAP		U(0x66)
 #define FFA_FNUM_RXTX_UNMAP		U(0x67)
 #define FFA_FNUM_PARTITION_INFO_GET	U(0x68)
-#define FFA_FNUM_ID_GET		U(0x69)
+#define FFA_FNUM_ID_GET			U(0x69)
 #define FFA_FNUM_MSG_POLL		U(0x6A)
 #define FFA_FNUM_MSG_WAIT		U(0x6B)
 #define FFA_FNUM_MSG_YIELD		U(0x6C)
@@ -86,6 +86,7 @@
 #define FFA_FNUM_MEM_RELINQUISH	U(0x76)
 #define FFA_FNUM_MEM_RECLAIM		U(0x77)
 #define FFA_FNUM_SECONDARY_EP_REGISTER	U(0x84)
+#define FFA_FNUM_SPM_ID_GET		U(0x85)
 
 /* FFA SMC32 FIDs */
 #define FFA_ERROR		FFA_FID(SMC_32, FFA_FNUM_ERROR)
@@ -115,6 +116,7 @@
 #define FFA_MEM_RETRIEVE_RESP	FFA_FID(SMC_32, FFA_FNUM_MEM_RETRIEVE_RESP)
 #define FFA_MEM_RELINQUISH	FFA_FID(SMC_32, FFA_FNUM_MEM_RELINQUISH)
 #define FFA_MEM_RECLAIM	FFA_FID(SMC_32, FFA_FNUM_MEM_RECLAIM)
+#define FFA_SPM_ID_GET		FFA_FID(SMC_32, FFA_FNUM_SPM_ID_GET)
 
 /* FFA SMC64 FIDs */
 #define FFA_ERROR_SMC64		FFA_FID(SMC_64, FFA_FNUM_ERROR)
diff --git a/include/services/pci_svc.h b/include/services/pci_svc.h
new file mode 100644
index 0000000..664a742
--- /dev/null
+++ b/include/services/pci_svc.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCI_SVC_H
+#define PCI_SVC_H
+
+#include <lib/utils_def.h>
+
+/* SMCCC PCI platform functions */
+#define SMC_PCI_VERSION			U(0x84000130)
+#define SMC_PCI_FEATURES		U(0x84000131)
+#define SMC_PCI_READ			U(0x84000132)
+#define SMC_PCI_WRITE			U(0x84000133)
+#define SMC_PCI_SEG_INFO		U(0x84000134)
+
+#define is_pci_fid(_fid) (((_fid) >= SMC_PCI_VERSION) &&  \
+			  ((_fid) <= SMC_PCI_SEG_INFO))
+
+uint64_t pci_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+			 u_register_t x3,  u_register_t x4, void *cookie,
+			 void *handle, u_register_t flags);
+
+#define PCI_ADDR_FUN(dev) ((dev) & U(0x7))
+#define PCI_ADDR_DEV(dev) (((dev) >> U(3))  & U(0x001F))
+#define PCI_ADDR_BUS(dev) (((dev) >> U(8))  & U(0x00FF))
+#define PCI_ADDR_SEG(dev) (((dev) >> U(16)) & U(0xFFFF))
+#define PCI_OFFSET_MASK   U(0xFFF)
+typedef union {
+	struct {
+		uint16_t minor;
+		uint16_t major;
+	} __packed;
+	uint32_t val;
+} pcie_version;
+
+/*
+ * platforms are responsible for providing implementations of these
+ * three functions in a manner which conforms to the Arm PCI Configuration
+ * Space Access Firmware Interface (DEN0115) and the PCIe specification's
+ * sections on PCI configuration access. See the rpi4_pci_svc.c example.
+ */
+uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val);
+uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val);
+uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg);
+
+/* Return codes for Arm PCI Config Space Access Firmware SMC calls */
+#define SMC_PCI_CALL_SUCCESS	       U(0)
+#define SMC_PCI_CALL_NOT_SUPPORTED	-1
+#define SMC_PCI_CALL_INVAL_PARAM	-2
+#define SMC_PCI_CALL_NOT_IMPL		-3
+
+#define SMC_PCI_SZ_8BIT			U(1)
+#define SMC_PCI_SZ_16BIT		U(2)
+#define SMC_PCI_SZ_32BIT		U(4)
+
+#endif /* PCI_SVC_H */
diff --git a/include/tools_share/uuid.h b/include/tools_share/uuid.h
index a6891d1..2ced3a3 100644
--- a/include/tools_share/uuid.h
+++ b/include/tools_share/uuid.h
@@ -66,7 +66,6 @@
 union uuid_helper_t {
 	struct uuid uuid_struct;
 	struct efi_guid efi_guid;
-	uint32_t word[4];
 };
 
 /* XXX namespace pollution? */
diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S
index e9734ac..8b16f93 100644
--- a/lib/aarch32/misc_helpers.S
+++ b/lib/aarch32/misc_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,8 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <assert_macros.S>
+#include <common/bl_common.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
 
 	.globl	smc
 	.globl	zeromem
@@ -14,6 +16,9 @@
 	.globl	memcpy4
 	.globl	disable_mmu_icache_secure
 	.globl	disable_mmu_secure
+	.globl	fixup_gdt_reloc
+
+#define PAGE_START_MASK		~(PAGE_SIZE_MASK)
 
 func smc
 	/*
@@ -187,3 +192,124 @@
 	ldr	r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
 	b	do_disable_mmu
 endfunc disable_mmu_icache_secure
+
+/* ---------------------------------------------------------------------------
+ * Helper to fixup Global Descriptor table (GDT) and dynamic relocations
+ * (.rel.dyn) at runtime.
+ *
+ * This function is meant to be used when the firmware is compiled with -fpie
+ * and linked with -pie options. We rely on the linker script exporting
+ * appropriate markers for start and end of the section. For GOT, we
+ * expect __GOT_START__ and __GOT_END__. Similarly for .rela.dyn, we expect
+ * __RELA_START__ and __RELA_END__.
+ *
+ * The function takes the limits of the memory to apply fixups to as
+ * arguments (which is usually the limits of the relocable BL image).
+ *   r0 -  the start of the fixup region
+ *   r1 -  the limit of the fixup region
+ * These addresses have to be 4KB page aligned.
+ * ---------------------------------------------------------------------------
+ */
+
+/* Relocation codes */
+#define R_ARM_RELATIVE 	23
+
+func fixup_gdt_reloc
+	mov	r6, r0
+	mov	r7, r1
+
+#if ENABLE_ASSERTIONS
+	/* Test if the limits are 4K aligned */
+	orr	r0, r0, r1
+	mov	r1, #(PAGE_SIZE_MASK)
+	tst	r0, r1
+	ASM_ASSERT(eq)
+#endif
+	/*
+	 * Calculate the offset based on return address in lr.
+	 * Assume that this function is called within a page at the start of
+	 * fixup region.
+	 */
+	ldr	r1, =PAGE_START_MASK
+	and	r2, lr, r1
+	subs	r0, r2, r6	/* Diff(S) = Current Address - Compiled Address */
+	beq	3f		/* Diff(S) = 0. No relocation needed */
+
+	ldr	r1, =__GOT_START__
+	add	r1, r1, r0
+	ldr	r2, =__GOT_END__
+	add	r2, r2, r0
+
+	/*
+	 * GOT is an array of 32_bit addresses which must be fixed up as
+	 * new_addr = old_addr + Diff(S).
+	 * The new_addr is the address currently the binary is executing from
+	 * and old_addr is the address at compile time.
+	 */
+1:	ldr	r3, [r1]
+
+	/* Skip adding offset if address is < lower limit */
+	cmp	r3, r6
+	blo	2f
+
+	/* Skip adding offset if address is > upper limit */
+	cmp	r3, r7
+	bhi	2f
+	add	r3, r3, r0
+	str	r3, [r1]
+
+2:	add	r1, r1, #4
+	cmp	r1, r2
+	blo	1b
+
+	/* Starting dynamic relocations. Use ldr to get RELA_START and END */
+3:	ldr	r1, =__RELA_START__
+	add	r1, r1, r0
+	ldr	r2, =__RELA_END__
+	add	r2, r2, r0
+
+	/*
+	 * According to ELF-32 specification, the RELA data structure is as
+	 * follows:
+	 *	typedef struct {
+	 *		Elf32_Addr r_offset;
+	 *		Elf32_Xword r_info;
+	 *	} Elf32_Rela;
+	 *
+	 * r_offset is address of reference
+	 * r_info is symbol index and type of relocation (in this case
+	 * code 23  which corresponds to R_ARM_RELATIVE).
+	 *
+	 * Size of Elf32_Rela structure is 8 bytes.
+	 */
+
+	/* Skip R_ARM_NONE entry with code 0 */
+1:	ldr	r3, [r1, #4]
+	ands	r3, r3, #0xff
+	beq	2f
+
+#if ENABLE_ASSERTIONS
+	/* Assert that the relocation type is R_ARM_RELATIVE */
+	cmp	r3, #R_ARM_RELATIVE
+	ASM_ASSERT(eq)
+#endif
+	ldr	r3, [r1]	/* r_offset */
+	add	r3, r0, r3	/* Diff(S) + r_offset */
+	ldr 	r4, [r3]
+
+	/* Skip adding offset if address is < lower limit */
+	cmp	r4, r6
+	blo	2f
+
+	/* Skip adding offset if address is >= upper limit */
+	cmp	r4, r7
+	bhs	2f
+
+	add 	r4, r0, r4
+	str	r4, [r3]
+
+2:	add	r1, r1, #8
+	cmp	r1, r2
+	blo	1b
+	bx	lr
+endfunc fixup_gdt_reloc
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
new file mode 100644
index 0000000..3310322
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a510.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+	/* ----------------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ----------------------------------------------------
+	 */
+func cortex_a510_core_pwr_dwn
+	/* ---------------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------------
+	 */
+	mrs	x0, CORTEX_A510_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_A510_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_a510_core_pwr_dwn
+
+	/*
+	 * Errata printing function for Cortex A510. Must follow AAPCS.
+	 */
+#if REPORT_ERRATA
+func cortex_a510_errata_report
+	ret
+endfunc cortex_a510_errata_report
+#endif
+
+func cortex_a510_reset_func
+	/* Disable speculative loads */
+	msr	SSBS, xzr
+	isb
+	ret
+endfunc cortex_a510_reset_func
+
+	/* ---------------------------------------------
+	 * This function provides Cortex-A510 specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.cortex_a510_regs, "aS"
+cortex_a510_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_a510_cpu_reg_dump
+	adr	x6, cortex_a510_regs
+	mrs	x8, CORTEX_A510_CPUECTLR_EL1
+	ret
+endfunc cortex_a510_cpu_reg_dump
+
+declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \
+	cortex_a510_reset_func, \
+	cortex_a510_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
new file mode 100644
index 0000000..4f979f8
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a710.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+	/* ----------------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ----------------------------------------------------
+	 */
+func cortex_a710_core_pwr_dwn
+	/* ---------------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------------
+	 */
+	mrs	x0, CORTEX_A710_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_A710_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_a710_core_pwr_dwn
+
+	/*
+	 * Errata printing function for Cortex A710. Must follow AAPCS.
+	 */
+#if REPORT_ERRATA
+func cortex_a710_errata_report
+	ret
+endfunc cortex_a710_errata_report
+#endif
+
+func cortex_a710_reset_func
+	/* Disable speculative loads */
+	msr	SSBS, xzr
+	isb
+	ret
+endfunc cortex_a710_reset_func
+
+	/* ---------------------------------------------
+	 * This function provides Cortex-A710 specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.cortex_a710_regs, "aS"
+cortex_a710_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_a710_cpu_reg_dump
+	adr	x6, cortex_a710_regs
+	mrs	x8, CORTEX_A710_CPUECTLR_EL1
+	ret
+endfunc cortex_a710_cpu_reg_dump
+
+declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \
+	cortex_a710_reset_func, \
+	cortex_a710_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index e3a6f5f..8c8f4d3 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -114,6 +114,86 @@
 	b	cpu_rev_var_ls
 endfunc check_errata_1925769
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex A77 Errata #1946167.
+	 * This applies to revision <= r1p1 of Cortex A77.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_a77_1946167_wa
+	/* Compare x0 against revision <= r1p1 */
+	mov	x17, x30
+	bl	check_errata_1946167
+	cbz	x0, 1f
+
+	ldr	x0,=0x4
+	msr	CORTEX_A77_CPUPSELR_EL3,x0
+	ldr	x0,=0x10E3900002
+	msr	CORTEX_A77_CPUPOR_EL3,x0
+	ldr	x0,=0x10FFF00083
+	msr	CORTEX_A77_CPUPMR_EL3,x0
+	ldr	x0,=0x2001003FF
+	msr	CORTEX_A77_CPUPCR_EL3,x0
+
+	ldr	x0,=0x5
+	msr	CORTEX_A77_CPUPSELR_EL3,x0
+	ldr	x0,=0x10E3800082
+	msr	CORTEX_A77_CPUPOR_EL3,x0
+	ldr	x0,=0x10FFF00083
+	msr	CORTEX_A77_CPUPMR_EL3,x0
+	ldr	x0,=0x2001003FF
+	msr	CORTEX_A77_CPUPCR_EL3,x0
+
+	ldr	x0,=0x6
+	msr	CORTEX_A77_CPUPSELR_EL3,x0
+	ldr	x0,=0x10E3800200
+	msr	CORTEX_A77_CPUPOR_EL3,x0
+	ldr	x0,=0x10FFF003E0
+	msr	CORTEX_A77_CPUPMR_EL3,x0
+	ldr	x0,=0x2001003FF
+	msr	CORTEX_A77_CPUPCR_EL3,x0
+
+	isb
+1:
+	ret	x17
+endfunc errata_a77_1946167_wa
+
+func check_errata_1946167
+	/* Applies to everything <= r1p1 */
+	mov	x1, #0x11
+	b	cpu_rev_var_ls
+endfunc check_errata_1946167
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex A77 Errata #1791578.
+	 * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_a77_1791578_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_1791578
+	cbz	x0, 1f
+
+	/* Set bit 2 in ACTLR2_EL1 */
+	mrs     x1, CORTEX_A77_ACTLR2_EL1
+	orr	x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
+	msr     CORTEX_A77_ACTLR2_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a77_1791578_wa
+
+func check_errata_1791578
+	/* Applies to r0p0, r1p0, and r1p1 right now */
+	mov	x1, #0x11
+	b	cpu_rev_var_ls
+endfunc check_errata_1791578
+
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A77.
 	 * Shall clobber: x0-x19
@@ -134,6 +214,16 @@
 	bl	errata_a77_1925769_wa
 #endif
 
+#if ERRATA_A77_1946167
+	mov	x0, x18
+	bl	errata_a77_1946167_wa
+#endif
+
+#if ERRATA_A77_1791578
+	mov	x0, x18
+	bl	errata_a77_1791578_wa
+#endif
+
 	ret	x19
 endfunc cortex_a77_reset_func
 
@@ -169,6 +259,8 @@
 	 */
 	report_errata ERRATA_A77_1508412, cortex_a77, 1508412
 	report_errata ERRATA_A77_1925769, cortex_a77, 1925769
+	report_errata ERRATA_A77_1946167, cortex_a77, 1946167
+	report_errata ERRATA_A77_1791578, cortex_a77, 1791578
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index f61726b..8c5a45a 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -44,13 +44,13 @@
 	b	cpu_rev_var_ls
 endfunc check_errata_1688305
 
-	/* --------------------------------------------------
-	 * Errata Workaround for Cortex A78 Errata #1941498.
-	 * This applies to revisions r0p0, r1p0, and r1p1.
-	 * x0: variant[4:7] and revision[0:3] of current cpu.
-	 * Shall clobber: x0-x17
-	 * --------------------------------------------------
-	 */
+/* --------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata #1941498.
+ * This applies to revisions r0p0, r1p0, and r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
 func errata_a78_1941498_wa
 	/* Compare x0 against revision <= r1p1 */
 	mov	x17, x30
@@ -72,16 +72,16 @@
 	b	cpu_rev_var_ls
 endfunc check_errata_1941498
 
-	/* --------------------------------------------------
-	 * Errata Workaround for A78 Erratum 1951500.
-	 * This applies to revisions r1p0 and r1p1 of A78.
-	 * The issue also exists in r0p0 but there is no fix
-	 * in that revision.
-	 * Inputs:
-	 * x0: variant[4:7] and revision[0:3] of current cpu.
-	 * Shall clobber: x0-x17
-	 * --------------------------------------------------
-	 */
+/* --------------------------------------------------
+ * Errata Workaround for A78 Erratum 1951500.
+ * This applies to revisions r1p0 and r1p1 of A78.
+ * The issue also exists in r0p0 but there is no fix
+ * in that revision.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
 func errata_a78_1951500_wa
 	/* Compare x0 against revisions r1p0 - r1p1 */
 	mov	x17, x30
@@ -126,6 +126,34 @@
 	b	cpu_rev_var_range
 endfunc check_errata_1951500
 
+/* --------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata #1821534.
+ * This applies to revisions r0p0 and r1p0.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_1821534_wa
+	/* Check revision. */
+	mov	x17, x30
+	bl	check_errata_1821534
+	cbz	x0, 1f
+
+	/* Set bit 2 in ACTLR2_EL1 */
+	mrs     x1, CORTEX_A78_ACTLR2_EL1
+	orr	x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
+	msr     CORTEX_A78_ACTLR2_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a78_1821534_wa
+
+func check_errata_1821534
+	/* Applies to r0p0 and r1p0 */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_1821534
+
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A78
 	 * -------------------------------------------------
@@ -150,6 +178,11 @@
 	bl	errata_a78_1951500_wa
 #endif
 
+#if ERRATA_A78_1821534
+	mov	x0, x18
+	bl	errata_a78_1821534_wa
+#endif
+
 #if ENABLE_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
@@ -207,6 +240,7 @@
 	report_errata ERRATA_A78_1688305, cortex_a78, 1688305
 	report_errata ERRATA_A78_1941498, cortex_a78, 1941498
 	report_errata ERRATA_A78_1951500, cortex_a78, 1951500
+	report_errata ERRATA_A78_1821534, cortex_a78, 1821534
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
new file mode 100644
index 0000000..1b170fe
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a78c.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+	/* ----------------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ----------------------------------------------------
+	 */
+func cortex_a78c_core_pwr_dwn
+	/* ---------------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------------
+	 */
+	mrs	x0, CORTEX_A78C_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+	msr	CORTEX_A78C_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_a78c_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex A78C. Must follow AAPCS.
+ */
+func cortex_a78c_errata_report
+        ret
+endfunc cortex_a78c_errata_report
+#endif
+
+	/* ---------------------------------------------
+	 * This function provides cortex_a78c specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.cortex_a78c_regs, "aS"
+cortex_a78c_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_a78c_cpu_reg_dump
+	adr	x6, cortex_a78c_regs
+	mrs	x8, CORTEX_A78C_CPUECTLR_EL1
+	ret
+endfunc cortex_a78c_cpu_reg_dump
+
+declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
+	CPU_NO_RESET_FUNC, \
+	cortex_a78c_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_klein.S b/lib/cpus/aarch64/cortex_klein.S
deleted file mode 100644
index d3a8ab4..0000000
--- a/lib/cpus/aarch64/cortex_klein.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_klein.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Klein must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Klein supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-	/* ----------------------------------------------------
-	 * HW will do the cache maintenance while powering down
-	 * ----------------------------------------------------
-	 */
-func cortex_klein_core_pwr_dwn
-	/* ---------------------------------------------------
-	 * Enable CPU power down bit in power control register
-	 * ---------------------------------------------------
-	 */
-	mrs	x0, CORTEX_KLEIN_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_KLEIN_CPUPWRCTLR_EL1, x0
-	isb
-	ret
-endfunc cortex_klein_core_pwr_dwn
-
-	/*
-	 * Errata printing function for Cortex Klein. Must follow AAPCS.
-	 */
-#if REPORT_ERRATA
-func cortex_klein_errata_report
-	ret
-endfunc cortex_klein_errata_report
-#endif
-
-func cortex_klein_reset_func
-	/* Disable speculative loads */
-	msr	SSBS, xzr
-	isb
-	ret
-endfunc cortex_klein_reset_func
-
-	/* ---------------------------------------------
-	 * This function provides Cortex-Klein specific
-	 * register information for crash reporting.
-	 * It needs to return with x6 pointing to
-	 * a list of register names in ascii and
-	 * x8 - x15 having values of registers to be
-	 * reported.
-	 * ---------------------------------------------
-	 */
-.section .rodata.cortex_klein_regs, "aS"
-cortex_klein_regs:  /* The ascii list of register names to be reported */
-	.asciz	"cpuectlr_el1", ""
-
-func cortex_klein_cpu_reg_dump
-	adr	x6, cortex_klein_regs
-	mrs	x8, CORTEX_KLEIN_CPUECTLR_EL1
-	ret
-endfunc cortex_klein_cpu_reg_dump
-
-declare_cpu_ops cortex_klein, CORTEX_KLEIN_MIDR, \
-	cortex_klein_reset_func, \
-	cortex_klein_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_makalu_elp_arm.S b/lib/cpus/aarch64/cortex_makalu_elp_arm.S
new file mode 100644
index 0000000..fbbf205
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_makalu_elp_arm.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_makalu_elp_arm.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+	/* ----------------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ----------------------------------------------------
+	 */
+func cortex_makalu_elp_arm_core_pwr_dwn
+	/* ---------------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------------
+	 */
+	mrs	x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_makalu_elp_arm_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex Makalu ELP. Must follow AAPCS.
+ */
+func cortex_makalu_elp_arm_errata_report
+	ret
+endfunc cortex_makalu_elp_arm_errata_report
+#endif
+
+func cortex_makalu_elp_arm_reset_func
+	/* Disable speculative loads */
+	msr	SSBS, xzr
+	isb
+	ret
+endfunc cortex_makalu_elp_arm_reset_func
+
+	/* ---------------------------------------------
+	 * This function provides Cortex Makalu ELP-
+	 * specific register information for crash
+	 * reporting. It needs to return with x6
+	 * pointing to a list of register names in ascii
+	 * and x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.cortex_makalu_elp_arm_regs, "aS"
+cortex_makalu_elp_arm_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_makalu_elp_arm_cpu_reg_dump
+	adr	x6, cortex_makalu_elp_arm_regs
+	mrs	x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1
+	ret
+endfunc cortex_makalu_elp_arm_cpu_reg_dump
+
+declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \
+	cortex_makalu_elp_arm_reset_func, \
+	cortex_makalu_elp_arm_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_matterhorn.S b/lib/cpus/aarch64/cortex_matterhorn.S
deleted file mode 100644
index 4156f3c..0000000
--- a/lib/cpus/aarch64/cortex_matterhorn.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_matterhorn.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Matterhorn must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Matterhorn supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-	/* ----------------------------------------------------
-	 * HW will do the cache maintenance while powering down
-	 * ----------------------------------------------------
-	 */
-func cortex_matterhorn_core_pwr_dwn
-	/* ---------------------------------------------------
-	 * Enable CPU power down bit in power control register
-	 * ---------------------------------------------------
-	 */
-	mrs	x0, CORTEX_MATTERHORN_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_MATTERHORN_CPUPWRCTLR_EL1, x0
-	isb
-	ret
-endfunc cortex_matterhorn_core_pwr_dwn
-
-	/*
-	 * Errata printing function for Cortex Matterhorn. Must follow AAPCS.
-	 */
-#if REPORT_ERRATA
-func cortex_matterhorn_errata_report
-	ret
-endfunc cortex_matterhorn_errata_report
-#endif
-
-func cortex_matterhorn_reset_func
-	/* Disable speculative loads */
-	msr	SSBS, xzr
-	isb
-	ret
-endfunc cortex_matterhorn_reset_func
-
-	/* ---------------------------------------------
-	 * This function provides Cortex-Matterhorn specific
-	 * register information for crash reporting.
-	 * It needs to return with x6 pointing to
-	 * a list of register names in ascii and
-	 * x8 - x15 having values of registers to be
-	 * reported.
-	 * ---------------------------------------------
-	 */
-.section .rodata.cortex_matterhorn_regs, "aS"
-cortex_matterhorn_regs:  /* The ascii list of register names to be reported */
-	.asciz	"cpuectlr_el1", ""
-
-func cortex_matterhorn_cpu_reg_dump
-	adr	x6, cortex_matterhorn_regs
-	mrs	x8, CORTEX_MATTERHORN_CPUECTLR_EL1
-	ret
-endfunc cortex_matterhorn_cpu_reg_dump
-
-declare_cpu_ops cortex_matterhorn, CORTEX_MATTERHORN_MIDR, \
-	cortex_matterhorn_reset_func, \
-	cortex_matterhorn_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S b/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
deleted file mode 100644
index b0f81a2..0000000
--- a/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_matterhorn_elp_arm.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Matterhorn ELP ARM must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Matterhorn ELP ARM supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-	/* ----------------------------------------------------
-	 * HW will do the cache maintenance while powering down
-	 * ----------------------------------------------------
-	 */
-func cortex_matterhorn_elp_arm_core_pwr_dwn
-	/* ---------------------------------------------------
-	 * Enable CPU power down bit in power control register
-	 * ---------------------------------------------------
-	 */
-	mrs	x0, CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1, x0
-	isb
-	ret
-endfunc cortex_matterhorn_elp_arm_core_pwr_dwn
-
-	/*
-	 * Errata printing function for Cortex Matterhorn_elp_arm. Must follow AAPCS.
-	 */
-#if REPORT_ERRATA
-func cortex_matterhorn_elp_arm_errata_report
-	ret
-endfunc cortex_matterhorn_elp_arm_errata_report
-#endif
-
-func cortex_matterhorn_elp_arm_reset_func
-	/* Disable speculative loads */
-	msr	SSBS, xzr
-	isb
-	ret
-endfunc cortex_matterhorn_elp_arm_reset_func
-
-	/* ---------------------------------------------
-	 * This function provides Cortex-Matterhorn_elp_arm specific
-	 * register information for crash reporting.
-	 * It needs to return with x6 pointing to
-	 * a list of register names in ascii and
-	 * x8 - x15 having values of registers to be
-	 * reported.
-	 * ---------------------------------------------
-	 */
-.section .rodata.cortex_matterhorn_elp_arm_regs, "aS"
-cortex_matterhorn_elp_arm_regs:  /* The ascii list of register names to be reported */
-	.asciz	"cpuectlr_el1", ""
-
-func cortex_matterhorn_elp_arm_cpu_reg_dump
-	adr	x6, cortex_matterhorn_elp_arm_regs
-	mrs	x8, CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1
-	ret
-endfunc cortex_matterhorn_elp_arm_cpu_reg_dump
-
-declare_cpu_ops cortex_matterhorn_elp_arm, CORTEX_MATTERHORN_ELP_ARM_MIDR, \
-	cortex_matterhorn_elp_arm_reset_func, \
-	cortex_matterhorn_elp_arm_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
new file mode 100644
index 0000000..87a9bdf
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_x2.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+	/* ----------------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ----------------------------------------------------
+	 */
+func cortex_x2_core_pwr_dwn
+	/* ---------------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------------
+	 */
+	mrs	x0, CORTEX_X2_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_X2_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_x2_core_pwr_dwn
+
+	/*
+	 * Errata printing function for Cortex X2. Must follow AAPCS.
+	 */
+#if REPORT_ERRATA
+func cortex_x2_errata_report
+	ret
+endfunc cortex_x2_errata_report
+#endif
+
+func cortex_x2_reset_func
+	/* Disable speculative loads */
+	msr	SSBS, xzr
+	isb
+	ret
+endfunc cortex_x2_reset_func
+
+	/* ---------------------------------------------
+	 * This function provides Cortex X2 specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.cortex_x2_regs, "aS"
+cortex_x2_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_x2_cpu_reg_dump
+	adr	x6, cortex_x2_regs
+	mrs	x8, CORTEX_X2_CPUECTLR_EL1
+	ret
+endfunc cortex_x2_cpu_reg_dump
+
+declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \
+	cortex_x2_reset_func, \
+	cortex_x2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 730b09b..bd8f85f 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -144,7 +144,7 @@
 	 * If cpu_ops for the MIDR_EL1 cannot be found and
 	 * SUPPORT_UNKNOWN_MPID is enabled, it will try to look for a
 	 * default cpu_ops with an MIDR value of 0.
-	 * (Implementation number 0x0 should be reseverd for software use
+	 * (Implementation number 0x0 should be reserved for software use
 	 * and therefore no clashes should happen with that default value).
 	 *
 	 * Return :
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 7336294..cee0bb7 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -21,6 +21,89 @@
 #error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Neoverse V1 Errata #1791573.
+	 * This applies to revisions r0p0 and r1p0, fixed in r1p1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_neoverse_v1_1791573_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_1791573
+	cbz	x0, 1f
+
+	/* Set bit 2 in ACTLR2_EL1 */
+	mrs     x1, NEOVERSE_V1_ACTLR2_EL1
+	orr	x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2
+	msr     NEOVERSE_V1_ACTLR2_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_neoverse_v1_1791573_wa
+
+func check_errata_1791573
+	/* Applies to r0p0 and r1p0. */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_1791573
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Neoverse V1 Erratum #1940577
+	 * This applies to revisions r1p0 - r1p1 and is open.
+	 * It also exists in r0p0 but there is no fix in that
+	 * revision.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_neoverse_v1_1940577_wa
+	/* Compare x0 against revisions r1p0 - r1p1 */
+	mov	x17, x30
+	bl	check_errata_1940577
+	cbz	x0, 1f
+
+	mov	x0, #0
+	msr	S3_6_C15_C8_0, x0
+	ldr	x0, =0x10E3900002
+	msr	S3_6_C15_C8_2, x0
+	ldr	x0, =0x10FFF00083
+	msr	S3_6_C15_C8_3, x0
+	ldr	x0, =0x2001003FF
+	msr	S3_6_C15_C8_1, x0
+
+	mov	x0, #1
+	msr	S3_6_C15_C8_0, x0
+	ldr	x0, =0x10E3800082
+	msr	S3_6_C15_C8_2, x0
+	ldr	x0, =0x10FFF00083
+	msr	S3_6_C15_C8_3, x0
+	ldr	x0, =0x2001003FF
+	msr	S3_6_C15_C8_1, x0
+
+	mov	x0, #2
+	msr	S3_6_C15_C8_0, x0
+	ldr	x0, =0x10E3800200
+	msr	S3_6_C15_C8_2, x0
+	ldr	x0, =0x10FFF003E0
+	msr	S3_6_C15_C8_3, x0
+	ldr	x0, =0x2001003FF
+	msr	S3_6_C15_C8_1, x0
+
+	isb
+1:
+	ret	x17
+endfunc errata_neoverse_v1_1940577_wa
+
+func check_errata_1940577
+	/* Applies to revisions r1p0 - r1p1. */
+	mov	x1, #0x10
+	mov	x2, #0x11
+	b	cpu_rev_var_range
+endfunc check_errata_1940577
+
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------
@@ -42,6 +125,19 @@
 	 */
 #if REPORT_ERRATA
 func neoverse_v1_errata_report
+	stp	x8, x30, [sp, #-16]!
+
+	bl	cpu_get_rev_var
+	mov	x8, x0
+
+	/*
+	 * Report all errata. The revision-variant information is passed to
+	 * checking functions of each errata.
+	 */
+	report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
+	report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
+
+	ldp	x8, x30, [sp], #16
 	ret
 endfunc neoverse_v1_errata_report
 #endif
@@ -51,8 +147,18 @@
 
 	/* Disable speculative loads */
 	msr	SSBS, xzr
-
 	isb
+
+#if ERRATA_V1_1791573
+	mov	x0, x18
+	bl	errata_neoverse_v1_1791573_wa
+#endif
+
+#if ERRATA_V1_1940577
+	mov	x0, x18
+	bl	errata_neoverse_v1_1940577_wa
+#endif
+
 	ret	x19
 endfunc neoverse_v1_reset_func
 
diff --git a/lib/cpus/aarch64/qemu_max.S b/lib/cpus/aarch64/qemu_max.S
new file mode 100644
index 0000000..8948fda
--- /dev/null
+++ b/lib/cpus/aarch64/qemu_max.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <qemu_max.h>
+
+func qemu_max_core_pwr_dwn
+	/* ---------------------------------------------
+	 * Disable the Data Cache.
+	 * ---------------------------------------------
+	 */
+	mrs	x1, sctlr_el3
+	bic	x1, x1, #SCTLR_C_BIT
+	msr	sctlr_el3, x1
+	isb
+
+	/* ---------------------------------------------
+	 * Flush L1 cache to L2.
+	 * ---------------------------------------------
+	 */
+	mov	x18, lr
+	mov	x0, #DCCISW
+	bl	dcsw_op_level1
+	mov	lr, x18
+	ret
+endfunc qemu_max_core_pwr_dwn
+
+func qemu_max_cluster_pwr_dwn
+	/* ---------------------------------------------
+	 * Disable the Data Cache.
+	 * ---------------------------------------------
+	 */
+	mrs	x1, sctlr_el3
+	bic	x1, x1, #SCTLR_C_BIT
+	msr	sctlr_el3, x1
+	isb
+
+	/* ---------------------------------------------
+	 * Flush all caches to PoC.
+	 * ---------------------------------------------
+	 */
+	mov	x0, #DCCISW
+	b	dcsw_op_all
+endfunc qemu_max_cluster_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for QEMU "max". Must follow AAPCS.
+ */
+func qemu_max_errata_report
+	ret
+endfunc qemu_max_errata_report
+#endif
+
+	/* ---------------------------------------------
+	 * This function provides cpu specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.qemu_max_regs, "aS"
+qemu_max_regs:  /* The ascii list of register names to be reported */
+	.asciz	"" /* no registers to report */
+
+func qemu_max_cpu_reg_dump
+	adr	x6, qemu_max_regs
+	ret
+endfunc qemu_max_cpu_reg_dump
+
+
+/* cpu_ops for QEMU MAX */
+declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \
+	qemu_max_core_pwr_dwn, \
+	qemu_max_cluster_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 64a4b4d..6f80d2d 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -290,6 +290,14 @@
 # only to revision <= r1p1 of the Cortex A77 cpu.
 ERRATA_A77_1925769	?=0
 
+# Flag to apply erratum 1946167 workaround during reset. This erratum applies
+# only to revision <= r1p1 of the Cortex A77 cpu.
+ERRATA_A77_1946167	?=0
+
+# Flag to apply erratum 1791578 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0, and r1p1, it is still open.
+ERRATA_A77_1791578	?=0
+
 # Flag to apply erratum 1688305 workaround during reset. This erratum applies
 # to revisions r0p0 - r1p0 of the A78 cpu.
 ERRATA_A78_1688305	?=0
@@ -303,6 +311,10 @@
 # well but there is no workaround for that revision.
 ERRATA_A78_1951500	?=0
 
+# Flag to apply erratum 1821534 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the A78 cpu.
+ERRATA_A78_1821534	?=0
+
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202	?=0
@@ -360,6 +372,14 @@
 # exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround.
 ERRATA_N1_1946160	?=0
 
+# Flag to apply erratum 1791573 workaround during reset.  This erratum applies
+# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
+ERRATA_V1_1791573	?=0
+
+# Flag to apply erratum 1940577 workaround during reset. This erratum applies
+# to revisions r1p0 and r1p1 of the Neoverse V1 cpu.
+ERRATA_V1_1940577	?=0
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 ERRATA_DSU_798953	?=0
@@ -585,6 +605,14 @@
 $(eval $(call assert_boolean,ERRATA_A77_1925769))
 $(eval $(call add_define,ERRATA_A77_1925769))
 
+# Process ERRATA_A77_1946167 flag
+$(eval $(call assert_boolean,ERRATA_A77_1946167))
+$(eval $(call add_define,ERRATA_A77_1946167))
+
+# Process ERRATA_A77_1791578 flag
+$(eval $(call assert_boolean,ERRATA_A77_1791578))
+$(eval $(call add_define,ERRATA_A77_1791578))
+
 # Process ERRATA_A78_1688305 flag
 $(eval $(call assert_boolean,ERRATA_A78_1688305))
 $(eval $(call add_define,ERRATA_A78_1688305))
@@ -597,6 +625,10 @@
 $(eval $(call assert_boolean,ERRATA_A78_1951500))
 $(eval $(call add_define,ERRATA_A78_1951500))
 
+# Process ERRATA_A78_1821534 flag
+$(eval $(call assert_boolean,ERRATA_A78_1821534))
+$(eval $(call add_define,ERRATA_A78_1821534))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))
@@ -653,6 +685,14 @@
 $(eval $(call assert_boolean,ERRATA_N1_1946160))
 $(eval $(call add_define,ERRATA_N1_1946160))
 
+# Process ERRATA_V1_1791573 flag
+$(eval $(call assert_boolean,ERRATA_V1_1791573))
+$(eval $(call add_define,ERRATA_V1_1791573))
+
+# Process ERRATA_V1_1940577 flag
+$(eval $(call assert_boolean,ERRATA_V1_1940577))
+$(eval $(call add_define,ERRATA_V1_1940577))
+
 # Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 2443001..81d793b 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -49,7 +49,7 @@
  *
  * To prepare the register state for entry call cm_prepare_el3_exit() and
  * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
- * cm_e1_sysreg_context_restore().
+ * cm_el1_sysregs_context_restore().
  ******************************************************************************/
 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
 {
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 75e214d..40e7ddf 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -30,7 +30,7 @@
 
 /* -----------------------------------------------------
  * The following function strictly follows the AArch64
- * PCS to use x9-x17 (temporary caller-saved registers)
+ * PCS to use x9-x16 (temporary caller-saved registers)
  * to save EL2 system register context. It assumes that
  * 'x0' is pointing to a 'el2_sys_regs' structure where
  * the register context will be saved.
@@ -43,7 +43,6 @@
  * ICH_LR<n>_EL2
  * -----------------------------------------------------
  */
-
 func el2_sysregs_context_save
 	mrs	x9, actlr_el2
 	mrs	x10, afsr0_el2
@@ -54,185 +53,153 @@
 	stp	x11, x12, [x0, #CTX_AFSR1_EL2]
 
 	mrs	x13, cnthctl_el2
-	mrs	x14, cnthp_ctl_el2
+	mrs	x14, cntvoff_el2
 	stp	x13, x14, [x0, #CTX_CNTHCTL_EL2]
 
-	mrs	x15, cnthp_cval_el2
-	mrs	x16, cnthp_tval_el2
-	stp	x15, x16, [x0, #CTX_CNTHP_CVAL_EL2]
+	mrs	x15, cptr_el2
+	str	x15, [x0, #CTX_CPTR_EL2]
 
-	mrs	x17, cntvoff_el2
-	mrs	x9, cptr_el2
-	stp	x17, x9, [x0, #CTX_CNTVOFF_EL2]
-
-	mrs	x11, elr_el2
 #if CTX_INCLUDE_AARCH32_REGS
-	mrs	x10, dbgvcr32_el2
-	stp	x10, x11, [x0, #CTX_DBGVCR32_EL2]
-#else
-	str	x11, [x0, #CTX_ELR_EL2]
+	mrs	x16, dbgvcr32_el2
+	str	x16, [x0, #CTX_DBGVCR32_EL2]
 #endif
 
-	mrs	x14, esr_el2
-	mrs	x15, far_el2
-	stp	x14, x15, [x0, #CTX_ESR_EL2]
+	mrs	x9, elr_el2
+	mrs	x10, esr_el2
+	stp	x9, x10, [x0, #CTX_ELR_EL2]
 
-	mrs	x16, hacr_el2
-	mrs	x17, hcr_el2
-	stp	x16, x17, [x0, #CTX_HACR_EL2]
+	mrs	x11, far_el2
+	mrs	x12, hacr_el2
+	stp	x11, x12, [x0, #CTX_FAR_EL2]
 
-	mrs	x9, hpfar_el2
-	mrs	x10, hstr_el2
-	stp	x9, x10, [x0, #CTX_HPFAR_EL2]
+	mrs	x13, hcr_el2
+	mrs	x14, hpfar_el2
+	stp	x13, x14, [x0, #CTX_HCR_EL2]
 
-	mrs	x11, ICC_SRE_EL2
-	mrs	x12, ICH_HCR_EL2
-	stp	x11, x12, [x0, #CTX_ICC_SRE_EL2]
+	mrs	x15, hstr_el2
+	mrs	x16, ICC_SRE_EL2
+	stp	x15, x16, [x0, #CTX_HSTR_EL2]
 
-	mrs	x13, ICH_VMCR_EL2
-	mrs	x14, mair_el2
-	stp	x13, x14, [x0, #CTX_ICH_VMCR_EL2]
+	mrs	x9, ICH_HCR_EL2
+	mrs	x10, ICH_VMCR_EL2
+	stp	x9, x10, [x0, #CTX_ICH_HCR_EL2]
 
-	mrs	x15, mdcr_el2
+	mrs	x11, mair_el2
+	mrs	x12, mdcr_el2
+	stp	x11, x12, [x0, #CTX_MAIR_EL2]
+
 #if ENABLE_SPE_FOR_LOWER_ELS
-	mrs	x16, PMSCR_EL2
-	stp	x15, x16, [x0, #CTX_MDCR_EL2]
-#else
-	str	x15, [x0, #CTX_MDCR_EL2]
+	mrs	x13, PMSCR_EL2
+	str	x13, [x0, #CTX_PMSCR_EL2]
 #endif
+	mrs	x14, sctlr_el2
+	str	x14, [x0, #CTX_SCTLR_EL2]
 
-	mrs	x17, sctlr_el2
-	mrs	x9, spsr_el2
-	stp	x17, x9, [x0, #CTX_SCTLR_EL2]
+	mrs	x15, spsr_el2
+	mrs	x16, sp_el2
+	stp	x15, x16, [x0, #CTX_SPSR_EL2]
 
-	mrs	x10, sp_el2
-	mrs	x11, tcr_el2
-	stp	x10, x11, [x0, #CTX_SP_EL2]
+	mrs	x9, tcr_el2
+	mrs	x10, tpidr_el2
+	stp	x9, x10, [x0, #CTX_TCR_EL2]
 
-	mrs	x12, tpidr_el2
-	mrs	x13, ttbr0_el2
-	stp	x12, x13, [x0, #CTX_TPIDR_EL2]
+	mrs	x11, ttbr0_el2
+	mrs	x12, vbar_el2
+	stp	x11, x12, [x0, #CTX_TTBR0_EL2]
 
-	mrs	x14, vbar_el2
-	mrs	x15, vmpidr_el2
-	stp	x14, x15, [x0, #CTX_VBAR_EL2]
+	mrs	x13, vmpidr_el2
+	mrs	x14, vpidr_el2
+	stp	x13, x14, [x0, #CTX_VMPIDR_EL2]
 
-	mrs	x16, vpidr_el2
-	mrs	x17, vtcr_el2
-	stp	x16, x17, [x0, #CTX_VPIDR_EL2]
-
-	mrs	x9, vttbr_el2
-	str	x9, [x0, #CTX_VTTBR_EL2]
+	mrs	x15, vtcr_el2
+	mrs	x16, vttbr_el2
+	stp	x15, x16, [x0, #CTX_VTCR_EL2]
 
 #if CTX_INCLUDE_MTE_REGS
-	mrs	x10, TFSR_EL2
-	str	x10, [x0, #CTX_TFSR_EL2]
+	mrs	x9, TFSR_EL2
+	str	x9, [x0, #CTX_TFSR_EL2]
 #endif
 
 #if ENABLE_MPAM_FOR_LOWER_ELS
-	mrs	x9, MPAM2_EL2
-	mrs	x10, MPAMHCR_EL2
-	stp	x9, x10, [x0, #CTX_MPAM2_EL2]
+	mrs	x10, MPAM2_EL2
+	str	x10, [x0, #CTX_MPAM2_EL2]
 
-	mrs	x11, MPAMVPM0_EL2
-	mrs	x12, MPAMVPM1_EL2
-	stp	x11, x12, [x0, #CTX_MPAMVPM0_EL2]
+	mrs	x11, MPAMHCR_EL2
+	mrs	x12, MPAMVPM0_EL2
+	stp	x11, x12, [x0, #CTX_MPAMHCR_EL2]
 
-	mrs	x13, MPAMVPM2_EL2
-	mrs	x14, MPAMVPM3_EL2
-	stp	x13, x14, [x0, #CTX_MPAMVPM2_EL2]
+	mrs	x13, MPAMVPM1_EL2
+	mrs	x14, MPAMVPM2_EL2
+	stp	x13, x14, [x0, #CTX_MPAMVPM1_EL2]
 
-	mrs	x15, MPAMVPM4_EL2
-	mrs	x16, MPAMVPM5_EL2
-	stp	x15, x16, [x0, #CTX_MPAMVPM4_EL2]
+	mrs	x15, MPAMVPM3_EL2
+	mrs	x16, MPAMVPM4_EL2
+	stp	x15, x16, [x0, #CTX_MPAMVPM3_EL2]
 
-	mrs	x17, MPAMVPM6_EL2
-	mrs	x9, MPAMVPM7_EL2
-	stp	x17, x9, [x0, #CTX_MPAMVPM6_EL2]
+	mrs	x9, MPAMVPM5_EL2
+	mrs	x10, MPAMVPM6_EL2
+	stp	x9, x10, [x0, #CTX_MPAMVPM5_EL2]
 
-	mrs	x10, MPAMVPMV_EL2
-	str	x10, [x0, #CTX_MPAMVPMV_EL2]
+	mrs	x11, MPAMVPM7_EL2
+	mrs	x12, MPAMVPMV_EL2
+	stp	x11, x12, [x0, #CTX_MPAMVPM7_EL2]
 #endif
 
-
 #if ARM_ARCH_AT_LEAST(8, 6)
-	mrs	x11, HAFGRTR_EL2
-	mrs	x12, HDFGRTR_EL2
-	stp	x11, x12, [x0, #CTX_HAFGRTR_EL2]
+	mrs	x13, HAFGRTR_EL2
+	mrs	x14, HDFGRTR_EL2
+	stp	x13, x14, [x0, #CTX_HAFGRTR_EL2]
 
-	mrs	x13, HDFGWTR_EL2
-	mrs	x14, HFGITR_EL2
-	stp	x13, x14, [x0, #CTX_HDFGWTR_EL2]
+	mrs	x15, HDFGWTR_EL2
+	mrs	x16, HFGITR_EL2
+	stp	x15, x16, [x0, #CTX_HDFGWTR_EL2]
 
-	mrs	x15, HFGRTR_EL2
-	mrs	x16, HFGWTR_EL2
-	stp	x15, x16, [x0, #CTX_HFGRTR_EL2]
+	mrs	x9, HFGRTR_EL2
+	mrs	x10, HFGWTR_EL2
+	stp	x9, x10, [x0, #CTX_HFGRTR_EL2]
 
-	mrs	x17, CNTPOFF_EL2
-	str	x17, [x0, #CTX_CNTPOFF_EL2]
+	mrs	x11, CNTPOFF_EL2
+	str	x11, [x0, #CTX_CNTPOFF_EL2]
 #endif
 
 #if ARM_ARCH_AT_LEAST(8, 4)
-	mrs	x9, cnthps_ctl_el2
-	mrs	x10, cnthps_cval_el2
-	stp	x9, x10, [x0, #CTX_CNTHPS_CTL_EL2]
-
-	mrs	x11, cnthps_tval_el2
-	mrs	x12, cnthvs_ctl_el2
-	stp	x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2]
-
-	mrs	x13, cnthvs_cval_el2
-	mrs	x14, cnthvs_tval_el2
-	stp	x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2]
-
-	mrs	x15, cnthv_ctl_el2
-	mrs	x16, cnthv_cval_el2
-	stp	x15, x16, [x0, #CTX_CNTHV_CTL_EL2]
-
-	mrs	x17, cnthv_tval_el2
-	mrs	x9, contextidr_el2
-	stp	x17, x9, [x0, #CTX_CNTHV_TVAL_EL2]
+	mrs	x12, contextidr_el2
+	str	x12, [x0, #CTX_CONTEXTIDR_EL2]
 
 #if CTX_INCLUDE_AARCH32_REGS
-	mrs	x10, sder32_el2
-	str	x10, [x0, #CTX_SDER32_EL2]
+	mrs	x13, sder32_el2
+	str	x13, [x0, #CTX_SDER32_EL2]
 #endif
-
-	mrs	x11, ttbr1_el2
-	str	x11, [x0, #CTX_TTBR1_EL2]
-
-	mrs	x12, vdisr_el2
-	str	x12, [x0, #CTX_VDISR_EL2]
+	mrs	x14, ttbr1_el2
+	mrs	x15, vdisr_el2
+	stp	x14, x15, [x0, #CTX_TTBR1_EL2]
 
 #if CTX_INCLUDE_NEVE_REGS
-	mrs	x13, vncr_el2
-	str	x13, [x0, #CTX_VNCR_EL2]
+	mrs	x16, vncr_el2
+	str	x16, [x0, #CTX_VNCR_EL2]
 #endif
 
-	mrs	x14, vsesr_el2
-	str	x14, [x0, #CTX_VSESR_EL2]
-
-	mrs	x15, vstcr_el2
-	str	x15, [x0, #CTX_VSTCR_EL2]
+	mrs	x9, vsesr_el2
+	mrs	x10, vstcr_el2
+	stp	x9, x10, [x0, #CTX_VSESR_EL2]
 
-	mrs	x16, vsttbr_el2
-	str	x16, [x0, #CTX_VSTTBR_EL2]
-
-	mrs	x17, TRFCR_EL2
-	str	x17, [x0, #CTX_TRFCR_EL2]
+	mrs	x11, vsttbr_el2
+	mrs	x12, TRFCR_EL2
+	stp	x11, x12, [x0, #CTX_VSTTBR_EL2]
 #endif
 
 #if ARM_ARCH_AT_LEAST(8, 5)
-	mrs	x9, scxtnum_el2
-	str	x9, [x0, #CTX_SCXTNUM_EL2]
+	mrs	x13, scxtnum_el2
+	str	x13, [x0, #CTX_SCXTNUM_EL2]
 #endif
 
 	ret
 endfunc el2_sysregs_context_save
 
+
 /* -----------------------------------------------------
  * The following function strictly follows the AArch64
- * PCS to use x9-x17 (temporary caller-saved registers)
+ * PCS to use x9-x16 (temporary caller-saved registers)
  * to restore EL2 system register context.  It assumes
  * that 'x0' is pointing to a 'el2_sys_regs' structure
  * from where the register context will be restored
@@ -246,7 +213,6 @@
  * -----------------------------------------------------
  */
 func el2_sysregs_context_restore
-
 	ldp	x9, x10, [x0, #CTX_ACTLR_EL2]
 	msr	actlr_el2, x9
 	msr	afsr0_el2, x10
@@ -257,74 +223,66 @@
 
 	ldp	x13, x14, [x0, #CTX_CNTHCTL_EL2]
 	msr	cnthctl_el2, x13
-	msr	cnthp_ctl_el2, x14
+	msr	cntvoff_el2, x14
 
-	ldp	x15, x16, [x0, #CTX_CNTHP_CVAL_EL2]
-	msr	cnthp_cval_el2, x15
-	msr	cnthp_tval_el2, x16
-
-	ldp	x17, x9, [x0, #CTX_CNTVOFF_EL2]
-	msr	cntvoff_el2, x17
-	msr	cptr_el2, x9
+	ldr	x15, [x0, #CTX_CPTR_EL2]
+	msr	cptr_el2, x15
 
 #if CTX_INCLUDE_AARCH32_REGS
-	ldp	x10, x11, [x0, #CTX_DBGVCR32_EL2]
-	msr	dbgvcr32_el2, x10
-#else
-	ldr	x11, [x0, #CTX_ELR_EL2]
+	ldr	x16, [x0, #CTX_DBGVCR32_EL2]
+	msr	dbgvcr32_el2, x16
 #endif
-	msr	elr_el2, x11
 
-	ldp	x14, x15, [x0, #CTX_ESR_EL2]
-	msr	esr_el2, x14
-	msr	far_el2, x15
+	ldp	x9, x10, [x0, #CTX_ELR_EL2]
+	msr	elr_el2, x9
+	msr	esr_el2, x10
 
-	ldp	x16, x17, [x0, #CTX_HACR_EL2]
-	msr	hacr_el2, x16
-	msr	hcr_el2, x17
+	ldp	x11, x12, [x0, #CTX_FAR_EL2]
+	msr	far_el2, x11
+	msr	hacr_el2, x12
 
-	ldp	x9, x10, [x0, #CTX_HPFAR_EL2]
-	msr	hpfar_el2, x9
-	msr	hstr_el2, x10
+	ldp	x13, x14, [x0, #CTX_HCR_EL2]
+	msr	hcr_el2, x13
+	msr	hpfar_el2, x14
 
-	ldp	x11, x12, [x0, #CTX_ICC_SRE_EL2]
-	msr	ICC_SRE_EL2, x11
-	msr	ICH_HCR_EL2, x12
+	ldp	x15, x16, [x0, #CTX_HSTR_EL2]
+	msr	hstr_el2, x15
+	msr	ICC_SRE_EL2, x16
 
-	ldp	x13, x14, [x0, #CTX_ICH_VMCR_EL2]
-	msr	ICH_VMCR_EL2, x13
-	msr	mair_el2, x14
+	ldp	x9, x10, [x0, #CTX_ICH_HCR_EL2]
+	msr	ICH_HCR_EL2, x9
+	msr	ICH_VMCR_EL2, x10
+
+	ldp	x11, x12, [x0, #CTX_MAIR_EL2]
+	msr	mair_el2, x11
+	msr	mdcr_el2, x12
 
 #if ENABLE_SPE_FOR_LOWER_ELS
-	ldp	x15, x16, [x0, #CTX_MDCR_EL2]
-	msr	PMSCR_EL2, x16
-#else
-	ldr	x15, [x0, #CTX_MDCR_EL2]
+	ldr	x13, [x0, #CTX_PMSCR_EL2]
+	msr	PMSCR_EL2, x13
 #endif
-	msr	mdcr_el2, x15
+	ldr	x14, [x0, #CTX_SCTLR_EL2]
+	msr	sctlr_el2, x14
 
-	ldp	x17, x9, [x0, #CTX_SCTLR_EL2]
-	msr	sctlr_el2, x17
-	msr	spsr_el2, x9
+	ldp	x15, x16, [x0, #CTX_SPSR_EL2]
+	msr	spsr_el2, x15
+	msr	sp_el2, x16
 
-	ldp	x10, x11, [x0, #CTX_SP_EL2]
-	msr	sp_el2, x10
-	msr	tcr_el2, x11
+	ldp	x9, x10, [x0, #CTX_TCR_EL2]
+	msr	tcr_el2, x9
+	msr	tpidr_el2, x10
 
-	ldp	x12, x13, [x0, #CTX_TPIDR_EL2]
-	msr	tpidr_el2, x12
-	msr	ttbr0_el2, x13
+	ldp	x11, x12, [x0, #CTX_TTBR0_EL2]
+	msr	ttbr0_el2, x11
+	msr	vbar_el2, x12
 
-	ldp	x13, x14, [x0, #CTX_VBAR_EL2]
-	msr	vbar_el2, x13
-	msr	vmpidr_el2, x14
+	ldp	x13, x14, [x0, #CTX_VMPIDR_EL2]
+	msr	vmpidr_el2, x13
+	msr	vpidr_el2, x14
 
-	ldp	x15, x16, [x0, #CTX_VPIDR_EL2]
-	msr	vpidr_el2, x15
-	msr	vtcr_el2, x16
-
-	ldr	x17, [x0, #CTX_VTTBR_EL2]
-	msr	vttbr_el2, x17
+	ldp	x15, x16, [x0, #CTX_VTCR_EL2]
+	msr	vtcr_el2, x15
+	msr	vttbr_el2, x16
 
 #if CTX_INCLUDE_MTE_REGS
 	ldr	x9, [x0, #CTX_TFSR_EL2]
@@ -332,100 +290,76 @@
 #endif
 
 #if ENABLE_MPAM_FOR_LOWER_ELS
-	ldp	x10, x11, [x0, #CTX_MPAM2_EL2]
+	ldr	x10, [x0, #CTX_MPAM2_EL2]
 	msr	MPAM2_EL2, x10
-	msr	MPAMHCR_EL2, x11
 
-	ldp	x12, x13, [x0, #CTX_MPAMVPM0_EL2]
+	ldp	x11, x12, [x0, #CTX_MPAMHCR_EL2]
+	msr	MPAMHCR_EL2, x11
 	msr	MPAMVPM0_EL2, x12
-	msr	MPAMVPM1_EL2, x13
 
-	ldp	x14, x15, [x0, #CTX_MPAMVPM2_EL2]
+	ldp	x13, x14, [x0, #CTX_MPAMVPM1_EL2]
+	msr	MPAMVPM1_EL2, x13
 	msr	MPAMVPM2_EL2, x14
-	msr	MPAMVPM3_EL2, x15
 
-	ldp	x16, x17, [x0, #CTX_MPAMVPM4_EL2]
+	ldp	x15, x16, [x0, #CTX_MPAMVPM3_EL2]
+	msr	MPAMVPM3_EL2, x15
 	msr	MPAMVPM4_EL2, x16
-	msr	MPAMVPM5_EL2, x17
 
-	ldp	x9, x10, [x0, #CTX_MPAMVPM6_EL2]
-	msr	MPAMVPM6_EL2, x9
-	msr	MPAMVPM7_EL2, x10
+	ldp	x9, x10, [x0, #CTX_MPAMVPM5_EL2]
+	msr	MPAMVPM5_EL2, x9
+	msr	MPAMVPM6_EL2, x10
 
-	ldr	x11, [x0, #CTX_MPAMVPMV_EL2]
-	msr	MPAMVPMV_EL2, x11
+	ldp	x11, x12, [x0, #CTX_MPAMVPM7_EL2]
+	msr	MPAMVPM7_EL2, x11
+	msr	MPAMVPMV_EL2, x12
 #endif
 
 #if ARM_ARCH_AT_LEAST(8, 6)
-	ldp	x12, x13, [x0, #CTX_HAFGRTR_EL2]
-	msr	HAFGRTR_EL2, x12
-	msr	HDFGRTR_EL2, x13
+	ldp	x13, x14, [x0, #CTX_HAFGRTR_EL2]
+	msr	HAFGRTR_EL2, x13
+	msr	HDFGRTR_EL2, x14
 
-	ldp	x14, x15, [x0, #CTX_HDFGWTR_EL2]
-	msr	HDFGWTR_EL2, x14
-	msr	HFGITR_EL2, x15
+	ldp	x15, x16, [x0, #CTX_HDFGWTR_EL2]
+	msr	HDFGWTR_EL2, x15
+	msr	HFGITR_EL2, x16
 
-	ldp	x16, x17, [x0, #CTX_HFGRTR_EL2]
-	msr	HFGRTR_EL2, x16
-	msr	HFGWTR_EL2, x17
+	ldp	x9, x10, [x0, #CTX_HFGRTR_EL2]
+	msr	HFGRTR_EL2, x9
+	msr	HFGWTR_EL2, x10
 
-	ldr	x9, [x0, #CTX_CNTPOFF_EL2]
-	msr	CNTPOFF_EL2, x9
+	ldr	x11, [x0, #CTX_CNTPOFF_EL2]
+	msr	CNTPOFF_EL2, x11
 #endif
 
 #if ARM_ARCH_AT_LEAST(8, 4)
-	ldp	x10, x11, [x0, #CTX_CNTHPS_CTL_EL2]
-	msr	cnthps_ctl_el2, x10
-	msr	cnthps_cval_el2, x11
-
-	ldp	x12, x13, [x0, #CTX_CNTHPS_TVAL_EL2]
-	msr	cnthps_tval_el2, x12
-	msr	cnthvs_ctl_el2, x13
-
-	ldp	x14, x15, [x0, #CTX_CNTHVS_CVAL_EL2]
-	msr	cnthvs_cval_el2, x14
-	msr	cnthvs_tval_el2, x15
-
-	ldp	x16, x17, [x0, #CTX_CNTHV_CTL_EL2]
-	msr	cnthv_ctl_el2, x16
-	msr	cnthv_cval_el2, x17
-
-	ldp	x9, x10, [x0, #CTX_CNTHV_TVAL_EL2]
-	msr	cnthv_tval_el2, x9
-	msr	contextidr_el2, x10
+	ldr	x12, [x0, #CTX_CONTEXTIDR_EL2]
+	msr	contextidr_el2, x12
 
 #if CTX_INCLUDE_AARCH32_REGS
-	ldr	x11, [x0, #CTX_SDER32_EL2]
-	msr	sder32_el2, x11
+	ldr	x13, [x0, #CTX_SDER32_EL2]
+	msr	sder32_el2, x13
 #endif
-
-	ldr	x12, [x0, #CTX_TTBR1_EL2]
-	msr	ttbr1_el2, x12
-
-	ldr	x13, [x0, #CTX_VDISR_EL2]
-	msr	vdisr_el2, x13
+	ldp	x14, x15, [x0, #CTX_TTBR1_EL2]
+	msr	ttbr1_el2, x14
+	msr	vdisr_el2, x15
 
 #if CTX_INCLUDE_NEVE_REGS
-	ldr	x14, [x0, #CTX_VNCR_EL2]
-	msr	vncr_el2, x14
+	ldr	x16, [x0, #CTX_VNCR_EL2]
+	msr	vncr_el2, x16
 #endif
 
-	ldr	x15, [x0, #CTX_VSESR_EL2]
-	msr	vsesr_el2, x15
+	ldp	x9, x10, [x0, #CTX_VSESR_EL2]
+	msr	vsesr_el2, x9
+	msr	vstcr_el2, x10
 
-	ldr	x16, [x0, #CTX_VSTCR_EL2]
-	msr	vstcr_el2, x16
-
-	ldr	x17, [x0, #CTX_VSTTBR_EL2]
-	msr	vsttbr_el2, x17
-
-	ldr	x9, [x0, #CTX_TRFCR_EL2]
-	msr	TRFCR_EL2, x9
+	ldp	x11, x12, [x0, #CTX_VSTTBR_EL2]
+	msr	vsttbr_el2, x11
+	msr	TRFCR_EL2, x12
 #endif
 
 #if ARM_ARCH_AT_LEAST(8, 5)
-	ldr	x10, [x0, #CTX_SCXTNUM_EL2]
-	msr	scxtnum_el2, x10
+	ldr	x13, [x0, #CTX_SCXTNUM_EL2]
+	msr	scxtnum_el2, x13
 #endif
 
 	ret
@@ -763,13 +697,14 @@
 	str	x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
 
 	/* ----------------------------------------------------------
-	 * Check if earlier initialization MDCR_EL3.SCCD to 1 failed,
-	 * meaning that ARMv8-PMU is not implemented and PMCR_EL0
-	 * should be saved in non-secure context.
+	 * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1
+	 * failed, meaning that FEAT_PMUv3p5/7 is not implemented and
+	 * PMCR_EL0 should be saved in non-secure context.
 	 * ----------------------------------------------------------
 	 */
+	mov_imm	x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
 	mrs	x9, mdcr_el3
-	tst	x9, #MDCR_SCCD_BIT
+	tst	x9, x10
 	bne	1f
 
 	/* Secure Cycle Counter is not disabled */
@@ -858,13 +793,14 @@
 
 	/* ----------------------------------------------------------
 	 * Back to Non-secure state.
-	 * Check if earlier initialization MDCR_EL3.SCCD to 1 failed,
-	 * meaning that ARMv8-PMU is not implemented and PMCR_EL0
-	 * should be restored from non-secure context.
+	 * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1
+	 * failed, meaning that FEAT_PMUv3p5/7 is not implemented and
+	 * PMCR_EL0 should be restored from non-secure context.
 	 * ----------------------------------------------------------
 	 */
+	mov_imm	x1, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
 	mrs	x0, mdcr_el3
-	tst	x0, #MDCR_SCCD_BIT
+	tst	x0, x1
 	bne	2f
 	ldr	x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
 	msr	pmcr_el0, x0
@@ -965,6 +901,24 @@
 	msr	spsr_el3, x16
 	msr	elr_el3, x17
 
+#if IMAGE_BL31
+	/* ----------------------------------------------------------
+	 * Restore CPTR_EL3.
+	 * ZCR is only restored if SVE is supported and enabled.
+	 * Synchronization is required before zcr_el3 is addressed.
+	 * ----------------------------------------------------------
+	 */
+	ldp	x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3]
+	msr	cptr_el3, x19
+
+	ands	x19, x19, #CPTR_EZ_BIT
+	beq	sve_not_enabled
+
+	isb
+	msr	S3_6_C1_C2_0, x20 /* zcr_el3 */
+sve_not_enabled:
+#endif
+
 #if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639
 	/* ----------------------------------------------------------
 	 * Restore mitigation state as it was on entry to EL3
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index e0e4298..7c6f953 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -25,6 +25,7 @@
 #include <lib/extensions/twed.h>
 #include <lib/utils.h>
 
+static void enable_extensions_secure(cpu_context_t *ctx);
 
 /*******************************************************************************
  * Context management library initialisation routine. This library is used by
@@ -60,7 +61,7 @@
  *
  * To prepare the register state for entry call cm_prepare_el3_exit() and
  * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
- * cm_e1_sysreg_context_restore().
+ * cm_el1_sysregs_context_restore().
  ******************************************************************************/
 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
 {
@@ -180,6 +181,12 @@
 	scr_el3 |= get_scr_el3_from_routing_model(security_state);
 #endif
 
+	/* Save the initialized value of CPTR_EL3 register */
+	write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3());
+	if (security_state == SECURE) {
+		enable_extensions_secure(ctx);
+	}
+
 	/*
 	 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
 	 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
@@ -286,7 +293,7 @@
 
 	/*
 	 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
-	 * and other EL2 registers are set up by cm_prepare_ns_entry() as they
+	 * and other EL2 registers are set up by cm_prepare_el3_exit() as they
 	 * are not part of the stored cpu_context.
 	 */
 	write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
@@ -323,7 +330,7 @@
  * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
  * it is zero.
  ******************************************************************************/
-static void enable_extensions_nonsecure(bool el2_unused)
+static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
 {
 #if IMAGE_BL31
 #if ENABLE_SPE_FOR_LOWER_ELS
@@ -331,11 +338,11 @@
 #endif
 
 #if ENABLE_AMU
-	amu_enable(el2_unused);
+	amu_enable(el2_unused, ctx);
 #endif
 
 #if ENABLE_SVE_FOR_NS
-	sve_enable(el2_unused);
+	sve_enable(ctx);
 #endif
 
 #if ENABLE_MPAM_FOR_LOWER_ELS
@@ -345,6 +352,18 @@
 }
 
 /*******************************************************************************
+ * Enable architecture extensions on first entry to Secure world.
+ ******************************************************************************/
+static void enable_extensions_secure(cpu_context_t *ctx)
+{
+#if IMAGE_BL31
+#if ENABLE_SVE_FOR_SWD
+	sve_enable(ctx);
+#endif
+#endif
+}
+
+/*******************************************************************************
  * The following function initializes the cpu_context for a CPU specified by
  * its `cpu_idx` for first use, and sets the initial entrypoint state as
  * specified by the entry_point_info structure.
@@ -578,7 +597,7 @@
 			write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
 						~(CNTHP_CTL_ENABLE_BIT));
 		}
-		enable_extensions_nonsecure(el2_unused);
+		enable_extensions_nonsecure(el2_unused, ctx);
 	}
 
 	cm_el1_sysregs_context_restore(security_state);
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index 24c3737..295c0d5 100644
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -46,7 +46,7 @@
  * Enable counters. This function is meant to be invoked
  * by the context management library before exiting from EL3.
  */
-void amu_enable(bool el2_unused)
+void amu_enable(bool el2_unused, cpu_context_t *ctx)
 {
 	uint64_t v;
 	unsigned int amu_version = amu_get_version();
@@ -88,12 +88,13 @@
 	}
 
 	/*
-	 * CPTR_EL3.TAM: Set to zero so that any accesses to
+	 * Retrieve and update the CPTR_EL3 value from the context mentioned
+	 * in 'ctx'. Set CPTR_EL3.TAM to zero so that any accesses to
 	 * the Activity Monitor registers do not trap to EL3.
 	 */
-	v = read_cptr_el3();
+	v = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
 	v &= ~TAM_BIT;
-	write_cptr_el3(v);
+	write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, v);
 
 	/* Enable group 0 counters */
 	write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c
index fa4ac77..2702c30 100644
--- a/lib/extensions/sve/sve.c
+++ b/lib/extensions/sve/sve.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,7 +11,13 @@
 #include <lib/el3_runtime/pubsub.h>
 #include <lib/extensions/sve.h>
 
-bool sve_supported(void)
+/*
+ * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
+ * VECTOR_SIZE = (LEN+1) * 128
+ */
+#define CONVERT_SVE_LENGTH(x)	(((x / 128) - 1))
+
+static bool sve_supported(void)
 {
 	uint64_t features;
 
@@ -19,113 +25,21 @@
 	return (features & ID_AA64PFR0_SVE_MASK) == 1U;
 }
 
-static void *disable_sve_hook(const void *arg)
-{
-	uint64_t cptr;
-
-	if (!sve_supported())
-		return (void *)-1;
-
-	/*
-	 * Disable SVE, SIMD and FP access for the Secure world.
-	 * As the SIMD/FP registers are part of the SVE Z-registers, any
-	 * use of SIMD/FP functionality will corrupt the SVE registers.
-	 * Therefore it is necessary to prevent use of SIMD/FP support
-	 * in the Secure world as well as SVE functionality.
-	 */
-	cptr = read_cptr_el3();
-	cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT);
-	write_cptr_el3(cptr);
-
-	/*
-	 * No explicit ISB required here as ERET to switch to Secure
-	 * world covers it
-	 */
-	return (void *)0;
-}
-
-static void *enable_sve_hook(const void *arg)
+void sve_enable(cpu_context_t *context)
 {
-	uint64_t cptr;
+	u_register_t cptr_el3;
 
-	if (!sve_supported())
-		return (void *)-1;
-
-	/*
-	 * Enable SVE, SIMD and FP access for the Non-secure world.
-	 */
-	cptr = read_cptr_el3();
-	cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT);
-	write_cptr_el3(cptr);
-
-	/*
-	 * No explicit ISB required here as ERET to switch to Non-secure
-	 * world covers it
-	 */
-	return (void *)0;
-}
-
-void sve_enable(bool el2_unused)
-{
-	uint64_t cptr;
-
-	if (!sve_supported())
+	if (!sve_supported()) {
 		return;
-
-#if CTX_INCLUDE_FPREGS
-	/*
-	 * CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
-	 */
-	assert(0);
-#endif
-	/*
-	 * Update CPTR_EL3 to enable access to SVE functionality for the
-	 * Non-secure world.
-	 * NOTE - assumed that CPTR_EL3.TFP is set to allow access to
-	 * the SIMD, floating-point and SVE support.
-	 *
-	 * CPTR_EL3.EZ: Set to 1 to enable access to SVE  functionality
-	 *  in the Non-secure world.
-	 */
-	cptr = read_cptr_el3();
-	cptr |= CPTR_EZ_BIT;
-	write_cptr_el3(cptr);
-
-	/*
-	 * Need explicit ISB here to guarantee that update to ZCR_ELx
-	 * and CPTR_EL2.TZ do not result in trap to EL3.
-	 */
-	isb();
+	}
 
-	/*
-	 * Ensure lower ELs have access to full vector length.
-	 */
-	write_zcr_el3(ZCR_EL3_LEN_MASK);
+	cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3);
 
-	if (el2_unused) {
-		/*
-		 * Update CPTR_EL2 to enable access to SVE functionality
-		 * for Non-secure world, EL2 and Non-secure EL1 and EL0.
-		 * NOTE - assumed that CPTR_EL2.TFP is set to allow
-		 * access to the SIMD, floating-point and SVE support.
-		 *
-		 * CPTR_EL2.TZ: Set to 0 to enable access to SVE support
-		 *  for EL2 and Non-secure EL1 and EL0.
-		 */
-		cptr = read_cptr_el2();
-		cptr &= ~(CPTR_EL2_TZ_BIT);
-		write_cptr_el2(cptr);
+	/* Enable access to SVE functionality for all ELs. */
+	cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
+	write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3);
 
-		/*
-		 * Ensure lower ELs have access to full vector length.
-		 */
-		write_zcr_el2(ZCR_EL2_LEN_MASK);
-	}
-	/*
-	 * No explicit ISB required here as ERET to switch to
-	 * Non-secure world covers it.
-	 */
+	/* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */
+	write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3,
+		(ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512)));
 }
-
-SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook);
-SUBSCRIBE_TO_EVENT(cm_entering_normal_world, enable_sve_hook);
diff --git a/licenses/LICENSE.MIT b/licenses/LICENSE.MIT
new file mode 100644
index 0000000..8aa2645
--- /dev/null
+++ b/licenses/LICENSE.MIT
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) [year] [fullname]
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 8d0cd04..b2d1ee2 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -212,6 +212,9 @@
 # True Random Number firmware Interface
 TRNG_SUPPORT            	:= 0
 
+# SMCCC PCI support
+SMC_PCI_SUPPORT            	:= 0
+
 # Whether code and read-only data should be put on separate memory pages. The
 # platform Makefile is free to override this value.
 SEPARATE_CODE_AND_RODATA	:= 0
@@ -296,13 +299,15 @@
 ENABLE_AMU			:= 0
 AMU_RESTRICT_COUNTERS		:= 0
 
-# By default, enable Scalable Vector Extension if implemented for Non-secure
+# By default, enable Scalable Vector Extension if implemented only for Non-secure
 # lower ELs
 # Note SVE is only supported on AArch64 - therefore do not enable in AArch32
 ifneq (${ARCH},aarch32)
     ENABLE_SVE_FOR_NS		:= 1
+    ENABLE_SVE_FOR_SWD		:= 0
 else
     override ENABLE_SVE_FOR_NS	:= 0
+    override ENABLE_SVE_FOR_SWD  := 0
 endif
 
 SANITIZE_UB := off
diff --git a/package-lock.json b/package-lock.json
new file mode 100644
index 0000000..46d8bf3
--- /dev/null
+++ b/package-lock.json
@@ -0,0 +1,2070 @@
+{
+  "requires": true,
+  "lockfileVersion": 1,
+  "dependencies": {
+    "@babel/code-frame": {
+      "version": "7.12.13",
+      "resolved": "https://registry.npmjs.org/@babel/code-frame/-/code-frame-7.12.13.tgz",
+      "integrity": "sha512-HV1Cm0Q3ZrpCR93tkWOYiuYIgLxZXZFVG2VgK+MBWjUqZTundupbfx2aXarXuw5Ko5aMcjtJgbSs4vUGBS5v6g==",
+      "dev": true,
+      "requires": {
+        "@babel/highlight": "^7.12.13"
+      }
+    },
+    "@babel/helper-validator-identifier": {
+      "version": "7.14.0",
+      "resolved": "https://registry.npmjs.org/@babel/helper-validator-identifier/-/helper-validator-identifier-7.14.0.tgz",
+      "integrity": "sha512-V3ts7zMSu5lfiwWDVWzRDGIN+lnCEUdaXgtVHJgLb1rGaA6jMrtB9EmE7L18foXJIE8Un/A/h6NJfGQp/e1J4A==",
+      "dev": true
+    },
+    "@babel/highlight": {
+      "version": "7.14.0",
+      "resolved": "https://registry.npmjs.org/@babel/highlight/-/highlight-7.14.0.tgz",
+      "integrity": "sha512-YSCOwxvTYEIMSGaBQb5kDDsCopDdiUGsqpatp3fOlI4+2HQSkTmEVWnVuySdAC5EWCqSWWTv0ib63RjR7dTBdg==",
+      "dev": true,
+      "requires": {
+        "@babel/helper-validator-identifier": "^7.14.0",
+        "chalk": "^2.0.0",
+        "js-tokens": "^4.0.0"
+      },
+      "dependencies": {
+        "ansi-styles": {
+          "version": "3.2.1",
+          "resolved": "https://registry.npmjs.org/ansi-styles/-/ansi-styles-3.2.1.tgz",
+          "integrity": "sha512-VT0ZI6kZRdTh8YyJw3SMbYm/u+NqfsAxEpWO0Pf9sq8/e94WxxOpPKx9FR1FlyCtOVDNOQ+8ntlqFxiRc+r5qA==",
+          "dev": true,
+          "requires": {
+            "color-convert": "^1.9.0"
+          }
+        },
+        "chalk": {
+          "version": "2.4.2",
+          "resolved": "https://registry.npmjs.org/chalk/-/chalk-2.4.2.tgz",
+          "integrity": "sha512-Mti+f9lpJNcwF4tWV8/OrTTtF1gZi+f8FqlyAdouralcFWFQWF2+NgCHShjkCb+IFBLq9buZwE1xckQU4peSuQ==",
+          "dev": true,
+          "requires": {
+            "ansi-styles": "^3.2.1",
+            "escape-string-regexp": "^1.0.5",
+            "supports-color": "^5.3.0"
+          }
+        },
+        "color-convert": {
+          "version": "1.9.3",
+          "resolved": "https://registry.npmjs.org/color-convert/-/color-convert-1.9.3.tgz",
+          "integrity": "sha512-QfAUtd+vFdAtFQcC8CCyYt1fYWxSqAiK2cSD6zDB8N3cpsEBAvRxp9zOGg6G/SHHJYAT88/az/IuDGALsNVbGg==",
+          "dev": true,
+          "requires": {
+            "color-name": "1.1.3"
+          }
+        },
+        "color-name": {
+          "version": "1.1.3",
+          "resolved": "https://registry.npmjs.org/color-name/-/color-name-1.1.3.tgz",
+          "integrity": "sha1-p9BVi9icQveV3UIyj3QIMcpTvCU=",
+          "dev": true
+        },
+        "has-flag": {
+          "version": "3.0.0",
+          "resolved": "https://registry.npmjs.org/has-flag/-/has-flag-3.0.0.tgz",
+          "integrity": "sha1-tdRU3CGZriJWmfNGfloH87lVuv0=",
+          "dev": true
+        },
+        "supports-color": {
+          "version": "5.5.0",
+          "resolved": "https://registry.npmjs.org/supports-color/-/supports-color-5.5.0.tgz",
+          "integrity": "sha512-QjVjwdXIt408MIiAqCX4oUKsgU2EqAGzs2Ppkm4aQYbjm+ZEWEcW4SfFNTr4uMNZma0ey4f5lgLrkB0aX0QMow==",
+          "dev": true,
+          "requires": {
+            "has-flag": "^3.0.0"
+          }
+        }
+      }
+    },
+    "@babel/runtime": {
+      "version": "7.14.0",
+      "resolved": "https://registry.npmjs.org/@babel/runtime/-/runtime-7.14.0.tgz",
+      "integrity": "sha512-JELkvo/DlpNdJ7dlyw/eY7E0suy5i5GQH+Vlxaq1nsNJ+H7f4Vtv3jMeCEgRhZZQFXTjldYfQgv2qmM6M1v5wA==",
+      "dev": true,
+      "requires": {
+        "regenerator-runtime": "^0.13.4"
+      }
+    },
+    "@commitlint/cli": {
+      "version": "11.0.0",
+      "resolved": "https://registry.npmjs.org/@commitlint/cli/-/cli-11.0.0.tgz",
+      "integrity": "sha512-YWZWg1DuqqO5Zjh7vUOeSX76vm0FFyz4y0cpGMFhrhvUi5unc4IVfCXZ6337R9zxuBtmveiRuuhQqnRRer+13g==",
+      "dev": true,
+      "requires": {
+        "@babel/runtime": "^7.11.2",
+        "@commitlint/format": "^11.0.0",
+        "@commitlint/lint": "^11.0.0",
+        "@commitlint/load": "^11.0.0",
+        "@commitlint/read": "^11.0.0",
+        "chalk": "4.1.0",
+        "core-js": "^3.6.1",
+        "get-stdin": "8.0.0",
+        "lodash": "^4.17.19",
+        "resolve-from": "5.0.0",
+        "resolve-global": "1.0.0",
+        "yargs": "^15.1.0"
+      }
+    },
+    "@commitlint/config-conventional": {
+      "version": "11.0.0",
+      "resolved": "https://registry.npmjs.org/@commitlint/config-conventional/-/config-conventional-11.0.0.tgz",
+      "integrity": "sha512-SNDRsb5gLuDd2PL83yCOQX6pE7gevC79UPFx+GLbLfw6jGnnbO9/tlL76MLD8MOViqGbo7ZicjChO9Gn+7tHhA==",
+      "dev": true,
+      "requires": {
+        "conventional-changelog-conventionalcommits": "^4.3.1"
+      }
+    },
+    "@commitlint/ensure": {
+      "version": "11.0.0",
+      "resolved": "https://registry.npmjs.org/@commitlint/ensure/-/ensure-11.0.0.tgz",
+      "integrity": "sha512-/T4tjseSwlirKZdnx4AuICMNNlFvRyPQimbZIOYujp9DSO6XRtOy9NrmvWujwHsq9F5Wb80QWi4WMW6HMaENug==",
+      "dev": true,
+      "requires": {
+        "@commitlint/types": "^11.0.0",
+        "lodash": "^4.17.19"
+      }
+    },
+    "@commitlint/execute-rule": {
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+      "dev": true
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+}
diff --git a/package.json b/package.json
new file mode 100644
index 0000000..ebd5d55
--- /dev/null
+++ b/package.json
@@ -0,0 +1,13 @@
+{
+  "private": true,
+  "scripts": {
+    "postinstall": "husky install"
+  },
+  "devDependencies": {
+    "@commitlint/cli": "^11.0.0",
+    "@commitlint/config-conventional": "^11.0.0",
+    "commitizen": "^4.2.4",
+    "cz-conventional-changelog": "^3.3.0",
+    "husky": "^5.0.4"
+  }
+}
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index da83b5e..61ae9b6 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -85,9 +85,6 @@
 # Allow mapping read-only data as execute-never.
 SEPARATE_CODE_AND_RODATA	:=	1
 
-# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
-SEPARATE_NOBITS_REGION		:=	1
-
 # BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
 RESET_TO_BL31			:=	1
 
diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
index 93720ff..56a2ad6 100644
--- a/plat/allwinner/common/include/platform_def.h
+++ b/plat/allwinner/common/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,20 +13,36 @@
 
 #include <sunxi_mmap.h>
 
+#ifdef SUNXI_BL31_IN_DRAM
+
+#define BL31_BASE			SUNXI_DRAM_BASE
+#define BL31_LIMIT			(SUNXI_DRAM_BASE + 0x40000)
+
+#define MAX_XLAT_TABLES			4
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+
+#define SUNXI_BL33_VIRT_BASE		PRELOADED_BL33_BASE
+
+#else	/* !SUNXI_BL31_IN_DRAM */
+
 #define BL31_BASE			(SUNXI_SRAM_A2_BASE + 0x4000)
 #define BL31_LIMIT			(SUNXI_SRAM_A2_BASE + \
 					 SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
 
-/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
-#define SUNXI_SCP_BASE			BL31_LIMIT
-#define SUNXI_SCP_SIZE			0x4000
-
 /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
 #define BL31_NOBITS_BASE		(SUNXI_SRAM_A1_BASE + 0x1000)
 #define BL31_NOBITS_LIMIT		(SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
 
-/* How much memory to reserve as secure for BL32, if configured */
-#define SUNXI_DRAM_SEC_SIZE		(32U << 20)
+#define MAX_XLAT_TABLES			1
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 28)
+
+#define SUNXI_BL33_VIRT_BASE		SUNXI_DRAM_VIRT_BASE
+
+/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
+#define SUNXI_SCP_BASE			BL31_LIMIT
+#define SUNXI_SCP_SIZE			0x4000
+
+#endif /* SUNXI_BL31_IN_DRAM */
 
 /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
 #define SUNXI_DRAM_MAP_SIZE		(64U << 20)
@@ -34,8 +50,8 @@
 #define CACHE_WRITEBACK_SHIFT		6
 #define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
 
-#define MAX_MMAP_REGIONS		(3 + PLATFORM_MMAP_REGIONS)
-#define MAX_XLAT_TABLES			1
+#define MAX_STATIC_MMAP_REGIONS		3
+#define MAX_MMAP_REGIONS		(5 + MAX_STATIC_MMAP_REGIONS)
 
 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
 	(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
@@ -50,13 +66,11 @@
 					 PLATFORM_CORE_COUNT)
 
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 28)
 
 #define PLATFORM_CLUSTER_COUNT		U(1)
 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER_COUNT * \
 					 PLATFORM_MAX_CPUS_PER_CLUSTER)
 #define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
-#define PLATFORM_MMAP_REGIONS		5
 #define PLATFORM_STACK_SIZE		(0x1000 / PLATFORM_CORE_COUNT)
 
 #ifndef SPD_none
diff --git a/plat/allwinner/common/include/sunxi_def.h b/plat/allwinner/common/include/sunxi_def.h
index 73c4453..f036816 100644
--- a/plat/allwinner/common/include/sunxi_def.h
+++ b/plat/allwinner/common/include/sunxi_def.h
@@ -17,5 +17,6 @@
 #define SUNXI_SOC_A64			0x1689
 #define SUNXI_SOC_H5			0x1718
 #define SUNXI_SOC_H6			0x1728
+#define SUNXI_SOC_H616			0x1823
 
 #endif /* SUNXI_DEF_H */
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h
index b68d23f..6cf4670 100644
--- a/plat/allwinner/common/include/sunxi_private.h
+++ b/plat/allwinner/common/include/sunxi_private.h
@@ -41,4 +41,12 @@
 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb);
 void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param);
 
+#ifdef SUNXI_BL31_IN_DRAM
+void sunxi_prepare_dtb(void *fdt);
+#else
+static inline void sunxi_prepare_dtb(void *fdt)
+{
+}
+#endif
+
 #endif /* SUNXI_PRIVATE_H */
diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index b619b18..72bfbd9 100644
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -13,6 +13,8 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
 #include <drivers/arm/gicv2.h>
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
@@ -52,7 +54,7 @@
 	uint64_t *u_boot_base;
 	int i;
 
-	u_boot_base = (void *)(SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE);
+	u_boot_base = (void *)SUNXI_BL33_VIRT_BASE;
 
 	for (i = 0; i < 2048 / sizeof(uint64_t); i++) {
 		uint32_t *dtb_base;
@@ -123,6 +125,9 @@
 	case SUNXI_SOC_H6:
 		soc_name = "H6";
 		break;
+	case SUNXI_SOC_H616:
+		soc_name = "H616";
+		break;
 	default:
 		soc_name = "unknown";
 		break;
@@ -172,6 +177,8 @@
 
 	sunxi_pmic_setup(soc_id, fdt);
 
+	sunxi_prepare_dtb(fdt);
+
 	INFO("BL31: Platform setup done\n");
 }
 
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index 5b536a0..82410b1 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -1,36 +1,26 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <errno.h>
 
-#include <platform_def.h>
-
-#include <arch_helpers.h>
 #include <common/debug.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
-#include <plat/common/platform.h>
 
 #include <sunxi_def.h>
 #include <sunxi_mmap.h>
 #include <sunxi_private.h>
 
-static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
+static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
 	MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
-			MT_RW_DATA | MT_SECURE),
-	MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
 	MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
-	MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
-		   MT_RW_DATA | MT_SECURE),
-	MAP_REGION(PRELOADED_BL33_BASE,
-		   SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE,
-		   SUNXI_DRAM_MAP_SIZE,
-		   MT_RO_DATA | MT_NS),
+	MAP_REGION(PRELOADED_BL33_BASE, SUNXI_BL33_VIRT_BASE,
+		   SUNXI_DRAM_MAP_SIZE, MT_RW_DATA | MT_NS),
 	{},
 };
 
@@ -44,12 +34,24 @@
 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
 			BL_CODE_END - BL_CODE_BASE,
 			MT_CODE | MT_SECURE);
+	mmap_add_region(BL_CODE_END, BL_CODE_END,
+			BL_END - BL_CODE_END,
+			MT_RW_DATA | MT_SECURE);
+#if SEPARATE_CODE_AND_RODATA
 	mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
 			BL_RO_DATA_END - BL_RO_DATA_BASE,
 			MT_RO_DATA | MT_SECURE);
+#endif
+#if SEPARATE_NOBITS_REGION
+	mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE,
+			BL_NOBITS_END - BL_NOBITS_BASE,
+			MT_RW_DATA | MT_SECURE);
+#endif
+#if USE_COHERENT_MEM
 	mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
 			BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
 			MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
+#endif
 
 	mmap_add(sunxi_mmap);
 	init_xlat_tables();
@@ -116,6 +118,7 @@
 		device_bit = BIT(6);
 		break;
 	case SUNXI_SOC_H6:
+	case SUNXI_SOC_H616:
 		pin_func = use_rsb ? 0x22 : 0x33;
 		device_bit = BIT(16);
 		reset_offset = use_rsb ? 0x1bc : 0x19c;
@@ -130,7 +133,7 @@
 	}
 
 	/* un-gate R_PIO clock */
-	if (socid != SUNXI_SOC_H6)
+	if (socid != SUNXI_SOC_H6 && socid != SUNXI_SOC_H616)
 		mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0));
 
 	/* switch pins PL0 and PL1 to the desired function */
@@ -143,7 +146,7 @@
 	mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U);
 
 	/* un-gate clock */
-	if (socid != SUNXI_SOC_H6)
+	if (socid != SUNXI_SOC_H6 && socid != SUNXI_SOC_H616)
 		mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
 	else
 		mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0));
@@ -154,50 +157,3 @@
 
 	return 0;
 }
-
-/* This lock synchronises access to the arisc management processor. */
-DEFINE_BAKERY_LOCK(arisc_lock);
-
-/*
- * Tell the "arisc" SCP core (an OpenRISC core) to execute some code.
- * We don't have any service running there, so we place some OpenRISC code
- * in SRAM, put the address of that into the reset vector and release the
- * arisc reset line. The SCP will execute that code and pull the line up again.
- */
-void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param)
-{
-	uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100;
-
-	do {
-		bakery_lock_get(&arisc_lock);
-		/* Wait until the arisc is in reset state. */
-		if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0)))
-			break;
-
-		bakery_lock_release(&arisc_lock);
-	} while (1);
-
-	/* Patch up the code to feed in an input parameter. */
-	code[0] = (code[0] & ~0xffff) | param;
-	clean_dcache_range((uintptr_t)code, size);
-
-	/*
-	 * The OpenRISC unconditional branch has opcode 0, the branch offset
-	 * is in the lower 26 bits, containing the distance to the target,
-	 * in instruction granularity (32 bits).
-	 */
-	mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
-	clean_dcache_range(arisc_reset_vec, 4);
-
-	/* De-assert the arisc reset line to let it run. */
-	mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
-
-	/*
-	 * We release the lock here, although the arisc is still busy.
-	 * But as long as it runs, the reset line is high, so other users
-	 * won't leave the loop above.
-	 * Once it has finished, the code is supposed to clear the reset line,
-	 * to signal this to other users.
-	 */
-	bakery_lock_release(&arisc_lock);
-}
diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c
index 43c03ac..420b507 100644
--- a/plat/allwinner/common/sunxi_cpu_ops.c
+++ b/plat/allwinner/common/sunxi_cpu_ops.c
@@ -19,10 +19,6 @@
 #include <sunxi_mmap.h>
 #include <sunxi_private.h>
 
-#ifndef SUNXI_CPUIDLE_EN_REG
-#include <core_off_arisc.h>
-#endif
-
 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
 {
 	if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
@@ -67,32 +63,6 @@
 	sunxi_cpu_disable_power(cluster, core);
 }
 
-void sunxi_cpu_power_off_self(void)
-{
-	u_register_t mpidr = read_mpidr();
-	unsigned int core  = MPIDR_AFFLVL0_VAL(mpidr);
-
-	/* Simplifies assembly, all SoCs so far are single cluster anyway. */
-	assert(MPIDR_AFFLVL1_VAL(mpidr) == 0);
-
-#ifdef SUNXI_CPUIDLE_EN_REG
-	/* Enable the CPUIDLE hardware (only really needs to be done once). */
-	mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
-	mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
-
-	/* Trigger power off for this core. */
-	mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
-#else
-	/*
-	 * If we are supposed to turn ourself off, tell the arisc SCP
-	 * to do that work for us. The code expects the core mask to be
-	 * patched into the first instruction.
-	 */
-	sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
-				 BIT_32(core));
-#endif
-}
-
 void sunxi_cpu_on(u_register_t mpidr)
 {
 	unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
index 74763ef..eb37daa 100644
--- a/plat/allwinner/common/sunxi_scpi_pm.c
+++ b/plat/allwinner/common/sunxi_scpi_pm.c
@@ -212,7 +212,6 @@
 		uint32_t offset = SUNXI_SCP_BASE - vector;
 
 		mmio_write_32(vector, offset >> 2);
-		clean_dcache_range(vector, sizeof(uint32_t));
 	}
 
 	/* Take the SCP out of reset. */
diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk
index 5f41035..e3c7c52 100644
--- a/plat/allwinner/sun50i_a64/platform.mk
+++ b/plat/allwinner/sun50i_a64/platform.mk
@@ -12,3 +12,6 @@
 
 FDT_ASSUME_MASK := "(ASSUME_LATEST | ASSUME_NO_ROLLBACK | ASSUME_LIBFDT_ORDER)"
 $(eval $(call add_define,FDT_ASSUME_MASK))
+
+# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
+SEPARATE_NOBITS_REGION	:=	1
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
index 80a69c3..a35b9dd 100644
--- a/plat/allwinner/sun50i_a64/sunxi_power.c
+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
@@ -14,6 +14,7 @@
 #include <drivers/allwinner/sunxi_rsb.h>
 #include <lib/mmio.h>
 
+#include <core_off_arisc.h>
 #include <sunxi_def.h>
 #include <sunxi_mmap.h>
 #include <sunxi_private.h>
@@ -205,3 +206,54 @@
 	}
 
 }
+
+/* This lock synchronises access to the arisc management processor. */
+static DEFINE_BAKERY_LOCK(arisc_lock);
+
+/*
+ * If we are supposed to turn ourself off, tell the arisc SCP to do that
+ * work for us. Without any SCPI provider running there, we place some
+ * OpenRISC code into SRAM, put the address of that into the reset vector
+ * and release the arisc reset line. The SCP will wait for the core to enter
+ * WFI, then execute that code and pull the line up again.
+ * The code expects the core mask to be patched into the first instruction.
+ */
+void sunxi_cpu_power_off_self(void)
+{
+	u_register_t mpidr = read_mpidr();
+	unsigned int core  = MPIDR_AFFLVL0_VAL(mpidr);
+	uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100;
+	uint32_t *code = arisc_core_off;
+
+	do {
+		bakery_lock_get(&arisc_lock);
+		/* Wait until the arisc is in reset state. */
+		if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0)))
+			break;
+
+		bakery_lock_release(&arisc_lock);
+	} while (1);
+
+	/* Patch up the code to feed in an input parameter. */
+	code[0] = (code[0] & ~0xffff) | BIT_32(core);
+	clean_dcache_range((uintptr_t)code, sizeof(arisc_core_off));
+
+	/*
+	 * The OpenRISC unconditional branch has opcode 0, the branch offset
+	 * is in the lower 26 bits, containing the distance to the target,
+	 * in instruction granularity (32 bits).
+	 */
+	mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
+
+	/* De-assert the arisc reset line to let it run. */
+	mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
+
+	/*
+	 * We release the lock here, although the arisc is still busy.
+	 * But as long as it runs, the reset line is high, so other users
+	 * won't leave the loop above.
+	 * Once it has finished, the code is supposed to clear the reset line,
+	 * to signal this to other users.
+	 */
+	bakery_lock_release(&arisc_lock);
+}
diff --git a/plat/allwinner/sun50i_h6/include/core_off_arisc.h b/plat/allwinner/sun50i_h6/include/core_off_arisc.h
deleted file mode 100644
index 63a5d8d..0000000
--- a/plat/allwinner/sun50i_h6/include/core_off_arisc.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-static uint32_t arisc_core_off[] = {
-	0x18600000, /* l.movhi	r3, <corenr>	*/
-	0x18000000, /* l.movhi	r0, 0x0		*/
-	0x19a00901, /* l.movhi	r13, 0x901	*/
-	0x84ad0080, /* l.lwz	r5, 0x80(r13)	*/
-	0xe0a51803, /* l.and	r5, r5, r3	*/
-	0xe4050000, /* l.sfeq	r5, r0		*/
-	0x13fffffd, /* l.bf	-12		*/
-	0xb8c30050, /* l.srli	r6, r3, 16	*/
-
-	0xbc060001, /* l.sfeqi	r6, 1		*/
-	0x10000005, /* l.bf	+20		*/
-	0x19a00700, /* l.movhi	r13, 0x700	*/
-	0x84ad0444, /* l.lwz	r5, 0x0444(r13)	*/
-	0xe0a53004, /* l.or	r5, r5, r6	*/
-	0xd40d2c44, /* l.sw	0x0444(r13), r5	*/
-
-	0x84ad0440, /* l.lwz	r5, 0x0440(r13)	*/
-	0xacc6ffff, /* l.xori	r6, r6, -1	*/
-	0xe0a53003, /* l.and	r5, r5, r6	*/
-	0xd40d2c40, /* l.sw	0x0440(r13), r5	*/
-
-	0xe0c3000f, /* l.ff1	r6, r3		*/
-	0x9cc6ffef, /* l.addi	r6, r6, -17	*/
-	0xb8c60002, /* l.slli	r6, r6, 2	*/
-	0xe0c66800, /* l.add	r6, r6, r13	*/
-	0xa8a000ff, /* l.ori	r5, r0, 0xff	*/
-	0xd4062c50, /* l.sw	0x0450(r6), r5	*/
-
-	0xd40d0400, /* l.sw	0x0400(r13), r0	*/
-	0x03ffffff, /* l.j	-1		*/
-	0x15000000, /* l.nop			*/
-};
diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk
index 1c98919..e13e8cb 100644
--- a/plat/allwinner/sun50i_h6/platform.mk
+++ b/plat/allwinner/sun50i_h6/platform.mk
@@ -9,3 +9,6 @@
 
 BL31_SOURCES		+=	drivers/allwinner/axp/axp805.c		\
 				drivers/allwinner/sunxi_rsb.c
+
+# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
+SEPARATE_NOBITS_REGION	:=	1
diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
index a7865a5..d298e6b 100644
--- a/plat/allwinner/sun50i_h6/sunxi_power.c
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -10,7 +10,9 @@
 #include <common/debug.h>
 #include <drivers/allwinner/axp.h>
 #include <drivers/allwinner/sunxi_rsb.h>
+#include <lib/mmio.h>
 
+#include <sunxi_cpucfg.h>
 #include <sunxi_def.h>
 #include <sunxi_mmap.h>
 #include <sunxi_private.h>
@@ -102,3 +104,16 @@
 		break;
 	}
 }
+
+void sunxi_cpu_power_off_self(void)
+{
+	u_register_t mpidr = read_mpidr();
+	unsigned int core  = MPIDR_AFFLVL0_VAL(mpidr);
+
+	/* Enable the CPUIDLE hardware (only really needs to be done once). */
+	mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
+	mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
+
+	/* Trigger power off for this core. */
+	mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
+}
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_ccu.h b/plat/allwinner/sun50i_h616/include/sunxi_ccu.h
new file mode 100644
index 0000000..85fbb90
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/include/sunxi_ccu.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CCU_H
+#define SUNXI_CCU_H
+
+#define SUNXI_CCU_SEC_SWITCH_REG	(SUNXI_CCU_BASE + 0x0f00)
+
+#define SUNXI_R_PRCM_SEC_SWITCH_REG	(SUNXI_R_PRCM_BASE + 0x0290)
+
+#endif /* SUNXI_CCU_H */
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
new file mode 100644
index 0000000..a637554
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CPUCFG_H
+#define SUNXI_CPUCFG_H
+
+#include <sunxi_mmap.h>
+
+/* c = cluster, n = core */
+#define SUNXI_CPUCFG_CLS_CTRL_REG0(c)	(SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
+#define SUNXI_CPUCFG_CLS_CTRL_REG1(c)	(SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
+#define SUNXI_CPUCFG_CACHE_CFG_REG	(SUNXI_CPUCFG_BASE + 0x0024)
+#define SUNXI_CPUCFG_DBG_REG0		(SUNXI_CPUCFG_BASE + 0x00c0)
+
+#define SUNXI_CPUCFG_RST_CTRL_REG(c)	(SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
+#define SUNXI_CPUCFG_RVBAR_LO_REG(n)	(SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
+#define SUNXI_CPUCFG_RVBAR_HI_REG(n)	(SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
+
+#define SUNXI_POWERON_RST_REG(c)	(SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
+#define SUNXI_POWEROFF_GATING_REG(c)	(SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
+#define SUNXI_CPU_POWER_CLAMP_REG(c, n)	(SUNXI_R_CPUCFG_BASE + 0x0050 + \
+					(c) * 0x10 + (n) * 4)
+
+#define SUNXI_CPUIDLE_EN_REG		(SUNXI_R_CPUCFG_BASE + 0x0100)
+#define SUNXI_CORE_CLOSE_REG		(SUNXI_R_CPUCFG_BASE + 0x0104)
+#define SUNXI_PWR_SW_DELAY_REG		(SUNXI_R_CPUCFG_BASE + 0x0140)
+#define SUNXI_CONFIG_DELAY_REG		(SUNXI_R_CPUCFG_BASE + 0x0144)
+
+#endif /* SUNXI_CPUCFG_H */
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_mmap.h b/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
new file mode 100644
index 0000000..3b4f4a0
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_MMAP_H
+#define SUNXI_MMAP_H
+
+/* Memory regions */
+#define SUNXI_ROM_BASE			0x00000000
+#define SUNXI_ROM_SIZE			0x00010000
+#define SUNXI_SRAM_BASE			0x00020000
+#define SUNXI_SRAM_SIZE			0x00038000
+#define SUNXI_SRAM_A1_BASE		0x00020000
+#define SUNXI_SRAM_A1_SIZE		0x00008000
+#define SUNXI_SRAM_C_BASE		0x00028000
+#define SUNXI_SRAM_C_SIZE		0x00030000
+#define SUNXI_DEV_BASE			0x01000000
+#define SUNXI_DEV_SIZE			0x09000000
+#define SUNXI_DRAM_BASE			0x40000000
+#define SUNXI_DRAM_VIRT_BASE		SUNXI_DRAM_BASE
+
+/* Memory-mapped devices */
+#define SUNXI_SYSCON_BASE		0x03000000
+#define SUNXI_CCU_BASE			0x03001000
+#define SUNXI_DMA_BASE			0x03002000
+#define SUNXI_SID_BASE			0x03006000
+#define SUNXI_SPC_BASE			0x03008000
+#define SUNXI_WDOG_BASE			0x030090a0
+#define SUNXI_PIO_BASE			0x0300b000
+#define SUNXI_GICD_BASE			0x03021000
+#define SUNXI_GICC_BASE			0x03022000
+#define SUNXI_UART0_BASE		0x05000000
+#define SUNXI_SPI0_BASE			0x05010000
+#define SUNXI_R_CPUCFG_BASE		0x07000400
+#define SUNXI_R_PRCM_BASE		0x07010000
+//#define SUNXI_R_WDOG_BASE		0x07020400
+#define SUNXI_R_WDOG_BASE		SUNXI_WDOG_BASE
+#define SUNXI_R_PIO_BASE		0x07022000
+#define SUNXI_R_UART_BASE		0x07080000
+#define SUNXI_R_I2C_BASE		0x07081400
+#define SUNXI_R_RSB_BASE		0x07083000
+#define SUNXI_CPUCFG_BASE		0x09010000
+
+#endif /* SUNXI_MMAP_H */
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_spc.h b/plat/allwinner/sun50i_h616/include/sunxi_spc.h
new file mode 100644
index 0000000..0f5965b
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/include/sunxi_spc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_SPC_H
+#define SUNXI_SPC_H
+
+#define SUNXI_SPC_NUM_PORTS		14
+
+#define SUNXI_SPC_DECPORT_STA_REG(p)	(SUNXI_SPC_BASE + 0x0000 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_SET_REG(p)	(SUNXI_SPC_BASE + 0x0004 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_CLR_REG(p)	(SUNXI_SPC_BASE + 0x0008 + 0x10 * (p))
+
+#endif /* SUNXI_SPC_H */
diff --git a/plat/allwinner/sun50i_h616/platform.mk b/plat/allwinner/sun50i_h616/platform.mk
new file mode 100644
index 0000000..fc09af7
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/platform.mk
@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Without a management processor there is no SCPI support.
+SUNXI_PSCI_USE_SCPI	:=	0
+SUNXI_PSCI_USE_NATIVE	:=	1
+
+# The differences between the platforms are covered by the include files.
+include plat/allwinner/common/allwinner-common.mk
+
+# the above could be overwritten on the command line
+ifeq (${SUNXI_PSCI_USE_SCPI}, 1)
+    $(error "H616 does not support SCPI PSCI ops")
+endif
+
+BL31_SOURCES		+=	drivers/allwinner/axp/axp805.c		\
+				drivers/allwinner/sunxi_rsb.c		\
+				common/fdt_fixup.c			\
+				${AW_PLAT}/${PLAT}/prepare_dtb.c
+
+$(eval $(call add_define,SUNXI_BL31_IN_DRAM))
diff --git a/plat/allwinner/sun50i_h616/prepare_dtb.c b/plat/allwinner/sun50i_h616/prepare_dtb.c
new file mode 100644
index 0000000..e94b0b4
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/prepare_dtb.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <libfdt.h>
+
+#include <common/debug.h>
+#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
+
+#include <sunxi_private.h>
+
+void sunxi_prepare_dtb(void *fdt)
+{
+	int ret;
+
+	if (fdt == NULL || fdt_check_header(fdt) != 0) {
+		return;
+	}
+	ret = fdt_open_into(fdt, fdt, 0x100000);
+	if (ret < 0) {
+		ERROR("Preparing devicetree at %p: error %d\n", fdt, ret);
+		return;
+	}
+
+	/* Reserve memory used by Trusted Firmware. */
+	if (fdt_add_reserved_memory(fdt, "tf-a@40000000", BL31_BASE,
+				    BL31_LIMIT - BL31_BASE)) {
+		WARN("Failed to add reserved memory nodes to DT.\n");
+		return;
+	}
+
+	ret = fdt_pack(fdt);
+	if (ret < 0) {
+		ERROR("Failed to pack devicetree at %p: error %d\n",
+		      fdt, ret);
+	} else {
+		clean_dcache_range((uintptr_t)fdt, fdt_blob_size(fdt));
+		INFO("Changed devicetree to reserve BL31 memory.\n");
+	}
+}
diff --git a/plat/allwinner/sun50i_h616/sunxi_power.c b/plat/allwinner/sun50i_h616/sunxi_power.c
new file mode 100644
index 0000000..dd6ebba
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/sunxi_power.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
+#include <drivers/allwinner/sunxi_rsb.h>
+#include <lib/mmio.h>
+
+#include <sunxi_cpucfg.h>
+#include <sunxi_def.h>
+#include <sunxi_mmap.h>
+#include <sunxi_private.h>
+
+#define AXP305_I2C_ADDR	0x36
+#define AXP305_HW_ADDR	0x745
+#define AXP305_RT_ADDR	0x3a
+
+static enum pmic_type {
+	UNKNOWN,
+	AXP305,
+} pmic;
+
+int axp_read(uint8_t reg)
+{
+	return rsb_read(AXP305_RT_ADDR, reg);
+}
+
+int axp_write(uint8_t reg, uint8_t val)
+{
+	return rsb_write(AXP305_RT_ADDR, reg, val);
+}
+
+static int rsb_init(void)
+{
+	int ret;
+
+	ret = rsb_init_controller();
+	if (ret)
+		return ret;
+
+	/* Switch to the recommended 3 MHz bus clock. */
+	ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
+	if (ret)
+		return ret;
+
+	/* Initiate an I2C transaction to switch the PMIC to RSB mode. */
+	ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
+	if (ret)
+		return ret;
+
+	/* Associate the 8-bit runtime address with the 12-bit bus address. */
+	ret = rsb_assign_runtime_address(AXP305_HW_ADDR, AXP305_RT_ADDR);
+	if (ret)
+		return ret;
+
+	return axp_check_id();
+}
+
+int sunxi_pmic_setup(uint16_t socid, const void *fdt)
+{
+	int ret;
+
+	INFO("PMIC: Probing AXP305 on RSB\n");
+
+	ret = sunxi_init_platform_r_twi(socid, true);
+	if (ret) {
+		INFO("Could not init platform bus: %d\n", ret);
+		return ret;
+	}
+
+	ret = rsb_init();
+	if (ret) {
+		INFO("Could not init RSB: %d\n", ret);
+		return ret;
+	}
+
+	pmic = AXP305;
+	axp_setup_regulators(fdt);
+
+	/* Switch the PMIC back to I2C mode. */
+	ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void sunxi_power_down(void)
+{
+	switch (pmic) {
+	case AXP305:
+		/* Re-initialise after rich OS might have used it. */
+		sunxi_init_platform_r_twi(SUNXI_SOC_H616, true);
+		rsb_init();
+		axp_power_off();
+		break;
+	default:
+		break;
+	}
+}
+
+void sunxi_cpu_power_off_self(void)
+{
+	u_register_t mpidr = read_mpidr();
+	unsigned int core  = MPIDR_AFFLVL0_VAL(mpidr);
+
+	/* Enable the CPUIDLE hardware (only really needs to be done once). */
+	mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
+	mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
+
+	/* Trigger power off for this core. */
+	mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
+}
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
index 792a754..9f3df1e 100644
--- a/plat/arm/board/a5ds/include/platform_def.h
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -315,8 +315,8 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		BOOT_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	BOOT_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 #define PLAT_ARM_NVM_BASE		BOOT_BASE
 #define PLAT_ARM_NVM_SIZE		(BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 7bc6a40..f1fd777 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -67,9 +67,11 @@
 				lib/cpus/aarch64/cortex_a78_ae.S	\
 				lib/cpus/aarch64/cortex_a65.S		\
 				lib/cpus/aarch64/cortex_a65ae.S		\
-				lib/cpus/aarch64/cortex_klein.S		\
-				lib/cpus/aarch64/cortex_matterhorn.S	\
-				lib/cpus/aarch64/cortex_makalu.S
+				lib/cpus/aarch64/cortex_a510.S		\
+				lib/cpus/aarch64/cortex_a710.S	\
+				lib/cpus/aarch64/cortex_makalu.S	\
+				lib/cpus/aarch64/cortex_makalu_elp_arm.S \
+				lib/cpus/aarch64/cortex_a78c.S
 
 # AArch64/AArch32 cores
 	FPGA_CPU_LIBS	+=	lib/cpus/aarch64/cortex_a55.S	\
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index 6db0c00..5cdf1bf 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -33,7 +33,7 @@
 $(warning Development keys support for FVP is deprecated. Use `regs` \
 option instead)
 else
-	$(error "Unsupported ARM_ROTPK_LOCATION value")
+$(error "Unsupported ARM_ROTPK_LOCATION value")
 endif
 
 $(eval $(call add_define,ARM_ROTPK_LOCATION_ID))
diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
index 80f2192..38f91fe 100644
--- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S
+++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
@@ -1,10 +1,17 @@
 /*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+/* diphda platform provides custom values for the macros defined in
+ * arm_def.h , so only platform_def.h needs to be included
+ */
+#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
 #include "plat/arm/common/arm_def.h"
+#else
+#include <platform_def.h>
+#endif
 
 	.global arm_rotpk_header
 	.global arm_rotpk_header_end
diff --git a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c b/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
new file mode 100644
index 0000000..916c868
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/desc_image_load.h>
+
+#include <platform_def.h>
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+
+	/* Fill BL31 related information */
+	{
+		.image_id = BL31_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
+			.ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+
+		.next_handoff_image_id = BL32_IMAGE_ID,
+	},
+
+	/* Fill BL32 related information */
+	{
+		.image_id = BL32_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
+			.ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
+
+	/* Fill TOS_FW_CONFIG related information */
+	{
+		.image_id = TOS_FW_CONFIG_ID,
+		.image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE,
+		.image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \
+			DIPHDA_TOS_FW_CONFIG_BASE,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+		VERSION_2, image_info_t, 0),
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+
+	/* Fill BL33 related information */
+	{
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+		.ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+		.image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+			- PLAT_ARM_NS_IMAGE_BASE,
+
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/board/diphda/common/diphda_err.c b/plat/arm/board/diphda/common/diphda_err.c
new file mode 100644
index 0000000..89a3b82
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * diphda error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+	while (1) {
+		wfi();
+	}
+}
diff --git a/plat/arm/board/diphda/common/diphda_helpers.S b/plat/arm/board/diphda/common/diphda_helpers.S
new file mode 100644
index 0000000..c9d2a88
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_helpers.S
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_get_my_entrypoint
+	.globl	plat_is_my_cpu_primary
+	.globl	plat_arm_calc_core_pos
+
+	/* --------------------------------------------------------------------
+	 * void plat_secondary_cold_boot_setup (void);
+	 *
+	 * For AArch32, cold-booting secondary CPUs is not yet
+	 * implemented and they panic.
+	 * --------------------------------------------------------------------
+	 */
+func plat_secondary_cold_boot_setup
+cb_panic:
+	b	cb_panic
+endfunc plat_secondary_cold_boot_setup
+
+	/* ---------------------------------------------------------------------
+	 * unsigned long plat_get_my_entrypoint (void);
+	 *
+	 * Main job of this routine is to distinguish between a cold and warm
+	 * boot. On diphda, this information can be queried from the power
+	 * controller. The Power Control SYS Status Register (PSYSR) indicates
+	 * the wake-up reason for the CPU.
+	 *
+	 * For a cold boot, return 0.
+	 * For a warm boot, Not yet supported.
+	 *
+	 * TODO: PSYSR is a common register and should be
+	 * 	accessed using locks. Since it is not possible
+	 * 	to use locks immediately after a cold reset
+	 * 	we are relying on the fact that after a cold
+	 * 	reset all cpus will read the same WK field
+	 * ---------------------------------------------------------------------
+	 */
+func plat_get_my_entrypoint
+	/* TODO support warm boot */
+	/* Cold reset */
+	mov	x0, #0
+	ret
+endfunc plat_get_my_entrypoint
+
+	/* -----------------------------------------------------
+	 * unsigned int plat_is_my_cpu_primary (void);
+	 *
+	 * Find out whether the current CPU is the primary
+	 * CPU.
+	 * -----------------------------------------------------
+	 */
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	mov_imm	x1, MPIDR_AFFINITY_MASK
+	and	x0, x0, x1
+	cmp	x0, #DIPHDA_PRIMARY_CPU
+	cset	w0, eq
+	ret
+endfunc plat_is_my_cpu_primary
diff --git a/plat/arm/board/diphda/common/diphda_plat.c b/plat/arm/board/diphda/common/diphda_plat.c
new file mode 100644
index 0000000..28d15a5
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_plat.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/bl_common.h>
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+/*
+ * Table of regions to map using the MMU.
+ * Replace or extend the below regions as required
+ */
+
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	ARM_MAP_NS_SHARED_RAM,
+	ARM_MAP_NS_DRAM1,
+	DIPHDA_MAP_DEVICE,
+	DIPHDA_EXTERNAL_FLASH,
+	{0}
+};
+
+/* diphda only has one always-on power domain and there
+ * is no power control present
+ */
+void __init plat_arm_pwrc_setup(void)
+{
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	/* Returning the Generic Timer Frequency */
+	return SYS_COUNTER_FREQ_IN_TICKS;
+}
+
+
+/*
+ * Helper function to initialize ARM interconnect driver.
+ */
+void plat_arm_interconnect_init(void)
+{
+}
+
+/*
+ * Helper function to place current master into coherency
+ */
+void plat_arm_interconnect_enter_coherency(void)
+{
+}
+
+/*
+ * Helper function to remove current master from coherency
+ */
+void plat_arm_interconnect_exit_coherency(void)
+{
+}
+
+/*
+ * This function is invoked during Mbed TLS library initialisation to get a heap
+ * The function simply returns the default allocated heap.
+ */
+
+#if TRUSTED_BOARD_BOOT
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+	assert(heap_addr != NULL);
+	assert(heap_size != NULL);
+
+	return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
diff --git a/plat/arm/board/diphda/common/diphda_pm.c b/plat/arm/board/diphda/common/diphda_pm.c
new file mode 100644
index 0000000..12b322e
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_pm.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+
+/*******************************************************************************
+ * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
+ * platform layer will take care of registering the handlers with PSCI.
+ ******************************************************************************/
+plat_psci_ops_t plat_arm_psci_pm_ops = {
+	/* dummy struct */
+	.validate_ns_entrypoint = NULL
+};
+
+const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+{
+	return ops;
+}
diff --git a/plat/arm/board/diphda/common/diphda_security.c b/plat/arm/board/diphda/common/diphda_security.c
new file mode 100644
index 0000000..bf172af
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_security.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * We assume that all security programming is done by the primary core.
+ */
+void plat_arm_security_setup(void)
+{
+	/*
+	 * If the platform had additional peripheral specific security
+	 * configurations, those would be configured here.
+	 */
+}
diff --git a/plat/arm/board/diphda/common/diphda_stack_protector.c b/plat/arm/board/diphda/common/diphda_stack_protector.c
new file mode 100644
index 0000000..6228b63
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_stack_protector.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <plat/common/platform.h>
+
+static uint32_t plat_generate_random_number(void)
+{
+	uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U);
+	uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U);
+	uint64_t cntpct = read_cntpct_el0();
+
+	/* Generate 32-bit pattern: saving the 2 least significant bytes
+	 * in random_lo and random_hi
+	 */
+	uint16_t random_lo = (uint16_t)(
+			(((uint64_t)return_addr) << 13) ^ frame_addr ^ cntpct
+			);
+
+	uint16_t random_hi = (uint16_t)(
+			(((uint64_t)frame_addr) << 15) ^ return_addr ^ cntpct
+			);
+
+	return (((uint32_t)random_hi) << 16) | random_lo;
+}
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+	return  plat_generate_random_number(); /* a 32-bit pattern returned */
+}
diff --git a/plat/arm/board/diphda/common/diphda_topology.c b/plat/arm/board/diphda/common/diphda_topology.c
new file mode 100644
index 0000000..9dfd05d
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_topology.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+/* The diphda power domain tree descriptor */
+static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
+							+ 2];
+/*******************************************************************************
+ * This function dynamically constructs the topology according to
+ * CLUSTER_COUNT and returns it.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	int i;
+
+	/*
+	 * The highest level is the system level. The next level is constituted
+	 * by clusters and then cores in clusters.
+	 */
+	diphda_power_domain_tree_desc[0] = 1;
+	diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
+
+	for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
+		diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
+
+	return diphda_power_domain_tree_desc;
+}
+
+/******************************************************************************
+ * This function implements a part of the critical interface between the PSCI
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is
+ * returned in case the MPIDR is invalid.
+ *****************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	return plat_arm_calc_core_pos(mpidr);
+}
diff --git a/plat/arm/board/diphda/common/diphda_trusted_boot.c b/plat/arm/board/diphda/common/diphda_trusted_boot.c
new file mode 100644
index 0000000..ddb41fa
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_trusted_boot.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * Return the ROTPK hash in the following ASN.1 structure in DER format:
+ *
+ * AlgorithmIdentifier  ::=  SEQUENCE  {
+ *     algorithm         OBJECT IDENTIFIER,
+ *     parameters        ANY DEFINED BY algorithm OPTIONAL
+ * }
+ *
+ * DigestInfo ::= SEQUENCE {
+ *     digestAlgorithm   AlgorithmIdentifier,
+ *     digest            OCTET STRING
+ * }
+ *
+ * The function returns 0 on success. Any other value is treated as error by the
+ * Trusted Board Boot. The function also reports extra information related
+ * to the ROTPK in the flags parameter: ROTPK_IS_HASH, ROTPK_NOT_DEPLOYED.
+ *
+ * Refer to the TF-A porting-guide document for more details.
+ */
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+			unsigned int *flags)
+{
+	return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
+}
+
+/*
+ * STUB overriding the non-volatile counter reading.
+ * NV counters are not implemented at this stage of development.
+ * Return: 0 = success
+ */
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+    *nv_ctr = DIPHDA_FW_NVCTR_VAL;
+    return 0;
+}
+
+/*
+ * STUB overriding the non-volatile counter updating.
+ * NV counters are not implemented at this stage of development.
+ * Return: 0 = success
+ */
+int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
+{
+    return 0;
+}
diff --git a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts b/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
new file mode 100644
index 0000000..def04cd
--- /dev/null
+++ b/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+/ {
+	compatible = "arm,ffa-core-manifest-1.0";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	/*
+	 * BL32 image details needed by SPMC
+	 *
+	 * Note:
+	 * binary_size: size of BL32 + TOS_FW_CONFIG
+	 */
+
+	attribute {
+		spmc_id = <0x8000>;
+		maj_ver = <0x1>;
+		min_ver = <0x0>;
+		exec_state = <0x0>;
+		load_address = <0x0 0x2002000>;
+		entrypoint = <0x0 0x2002000>;
+		binary_size = <0xae000>;
+	};
+
+};
diff --git a/plat/arm/board/diphda/common/include/platform_def.h b/plat/arm/board/diphda/common/include/platform_def.h
new file mode 100644
index 0000000..37fd71b
--- /dev/null
+++ b/plat/arm/board/diphda/common/include/platform_def.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <common/tbbr/tbbr_img_def.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/common/smccc_def.h>
+#include <plat/common/common_def.h>
+#include <plat/arm/soc/common/soc_css_def.h>
+
+#define ARM_ROTPK_HEADER_LEN			19
+#define ARM_ROTPK_HASH_LEN			32
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define ARM_BL31_PLAT_PARAM_VAL		ULL(0x0f1e2d3c4b5a6978)
+
+/* PL011 UART related constants */
+#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
+#undef V2M_IOFPGA_UART0_CLK_IN_HZ
+#endif
+
+#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ
+#undef V2M_IOFPGA_UART1_CLK_IN_HZ
+#endif
+
+#define V2M_IOFPGA_UART0_CLK_IN_HZ		50000000
+#define V2M_IOFPGA_UART1_CLK_IN_HZ		50000000
+
+/* Core/Cluster/Thread counts for diphda */
+#define DIPHDA_CLUSTER_COUNT			U(1)
+#define DIPHDA_MAX_CPUS_PER_CLUSTER		U(4)
+#define DIPHDA_MAX_PE_PER_CPU			U(1)
+#define DIPHDA_PRIMARY_CPU			U(0)
+
+#define PLAT_ARM_CLUSTER_COUNT		DIPHDA_CLUSTER_COUNT
+
+#define PLATFORM_CORE_COUNT			(PLAT_ARM_CLUSTER_COUNT *      \
+						DIPHDA_MAX_CPUS_PER_CLUSTER *  \
+						DIPHDA_MAX_PE_PER_CPU)
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE		0x1a510000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ		V2M_IOFPGA_UART0_CLK_IN_HZ
+#define PLAT_ARM_RUN_UART_BASE		0x1a520000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ		V2M_IOFPGA_UART1_CLK_IN_HZ
+#define ARM_CONSOLE_BAUDRATE			115200
+#define PLAT_ARM_CRASH_UART_BASE		PLAT_ARM_RUN_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ		PLAT_ARM_RUN_UART_CLK_IN_HZ
+
+/* Memory related constants */
+
+/* SRAM (CVM) memory layout
+ *
+ * <ARM_TRUSTED_SRAM_BASE>
+ *
+ *         partition size: sizeof(meminfo_t) = 16 bytes
+ *
+ *         content: memory info area used by the next BL
+ *
+ * <ARM_FW_CONFIG_BASE>
+ *
+ *         partition size: 4080 bytes
+ *
+ * <ARM_BL2_MEM_DESC_BASE>
+ *
+ *         partition size: 4 KB
+ *
+ *         content:
+ *
+ *             Area where BL2 copies the images descriptors
+ *
+ * <ARM_BL_RAM_BASE> = <BL32_BASE>
+ *
+ *         partition size: 688 KB
+ *
+ *         content:
+ *
+ *             BL32 (optee-os)
+ *
+ * <DIPHDA_TOS_FW_CONFIG_BASE> = 0x20ae000
+ *
+ *         partition size: 8 KB
+ *
+ *         content:
+ *
+ *             BL32 config (TOS_FW_CONFIG)
+ *
+ * <BL31_BASE>
+ *
+ *         partition size: 140 KB
+ *
+ *         content:
+ *
+ *             BL31
+ *
+ * <BL2_SIGNATURE_BASE>
+ *
+ *     partition size: 4 KB
+ *
+ *     content:
+ *
+ *         MCUBOOT data needed to verify TF-A BL2
+ *
+ * <BL2_BASE>
+ *
+ *     partition size: 176 KB
+ *
+ *         content:
+ *
+ *             BL2
+ *
+ * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
+ *
+ *         partition size: 3 MB
+ *
+ *         content:
+ *
+ *             BL33 (u-boot)
+ */
+
+/* DDR memory */
+#define ARM_DRAM1_BASE			UL(0x80000000)
+#define ARM_DRAM1_SIZE			UL(0x80000000)
+#define ARM_DRAM1_END				(ARM_DRAM1_BASE +	\
+						ARM_DRAM1_SIZE - 1)
+
+/* DRAM1 and DRAM2 are the same for diphda */
+#define ARM_DRAM2_BASE			ARM_DRAM1_BASE
+#define ARM_DRAM2_SIZE			ARM_DRAM1_SIZE
+#define ARM_DRAM2_END				ARM_DRAM1_END
+
+#define ARM_NS_DRAM1_BASE			ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE			ARM_DRAM1_SIZE
+#define ARM_NS_DRAM1_END			(ARM_NS_DRAM1_BASE +	\
+						ARM_NS_DRAM1_SIZE - 1)
+
+/* The first 8 KB of Trusted SRAM are used as shared memory */
+#define ARM_TRUSTED_SRAM_BASE			UL(0x02000000)
+#define ARM_SHARED_RAM_SIZE			UL(0x00002000)  /* 8 KB */
+#define ARM_SHARED_RAM_BASE			ARM_TRUSTED_SRAM_BASE
+
+/* The remaining Trusted SRAM is used to load the BL images */
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE		UL(0x00100000)  /* 1 MB */
+
+#define PLAT_ARM_MAX_BL2_SIZE			UL(0x0002d000)  /* 180 KB */
+
+#define PLAT_ARM_MAX_BL31_SIZE		UL(0x00023000)  /* 140 KB */
+
+#define ARM_BL_RAM_BASE			(ARM_SHARED_RAM_BASE +	\
+						ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE			(PLAT_ARM_TRUSTED_SRAM_SIZE -	\
+						ARM_SHARED_RAM_SIZE)
+
+#define BL2_SIGNATURE_SIZE			UL(0x00001000)  /* 4 KB */
+#define BL2_SIGNATURE_BASE			(BL2_LIMIT - \
+						PLAT_ARM_MAX_BL2_SIZE)
+#define BL2_BASE				(BL2_LIMIT - \
+						PLAT_ARM_MAX_BL2_SIZE + \
+						BL2_SIGNATURE_SIZE)
+#define BL2_LIMIT				(ARM_BL_RAM_BASE + \
+						ARM_BL_RAM_SIZE)
+
+#define BL31_BASE				(BL2_SIGNATURE_BASE - \
+						PLAT_ARM_MAX_BL31_SIZE)
+#define BL31_LIMIT				BL2_SIGNATURE_BASE
+
+#define DIPHDA_TOS_FW_CONFIG_BASE		(BL31_BASE - \
+						DIPHDA_TOS_FW_CONFIG_SIZE)
+#define DIPHDA_TOS_FW_CONFIG_SIZE		UL(0x00002000)  /* 8 KB */
+#define DIPHDA_TOS_FW_CONFIG_LIMIT		BL31_BASE
+
+#define BL32_BASE				ARM_BL_RAM_BASE
+#define PLAT_ARM_MAX_BL32_SIZE		(DIPHDA_TOS_FW_CONFIG_BASE - \
+						BL32_BASE)     /* 688 KB */
+#define BL32_LIMIT				(BL32_BASE + \
+						PLAT_ARM_MAX_BL32_SIZE)
+
+/* SPD_spmd settings */
+
+#define PLAT_ARM_SPMC_BASE			BL32_BASE
+#define PLAT_ARM_SPMC_SIZE			PLAT_ARM_MAX_BL32_SIZE
+
+/* NS memory */
+
+/* The last 3 MB of the SRAM is allocated to the non secure area */
+#define ARM_NS_SHARED_RAM_BASE		(ARM_TRUSTED_SRAM_BASE + \
+						PLAT_ARM_TRUSTED_SRAM_SIZE)
+#define ARM_NS_SHARED_RAM_SIZE		UL(0x00300000)  /* 3 MB */
+
+/* end of the definition of SRAM memory layout */
+
+/* NOR Flash */
+
+#define PLAT_ARM_FIP_BASE			UL(0x08131000)
+#define PLAT_ARM_FIP_MAX_SIZE			UL(0x1ff000)  /* 1.996 MB */
+
+#define PLAT_ARM_NVM_BASE			V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE			UL(0x02000000)  /* 32 MB */
+
+#define PLAT_ARM_FLASH_IMAGE_BASE		PLAT_ARM_FIP_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE		PLAT_ARM_FIP_MAX_SIZE
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE		(U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+#define ARM_CACHE_WRITEBACK_SHIFT		6
+
+/*
+ * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
+ * FW_CONFIG is intended to host the device tree. Currently, This area is not
+ * used because diphda platform doesn't use a device tree at TF-A level.
+ */
+#define ARM_FW_CONFIG_BASE			(ARM_SHARED_RAM_BASE \
+						+ sizeof(meminfo_t))
+#define ARM_FW_CONFIG_LIMIT			(ARM_SHARED_RAM_BASE \
+						+ (ARM_SHARED_RAM_SIZE >> 1))
+
+/*
+ * Boot parameters passed from BL2 to BL31/BL32 are stored here
+ */
+#define ARM_BL2_MEM_DESC_BASE			ARM_FW_CONFIG_LIMIT
+#define ARM_BL2_MEM_DESC_LIMIT		ARM_BL_RAM_BASE
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS			3
+#define PLAT_ARM_MMAP_ENTRIES			8
+#define MAX_XLAT_TABLES			5
+#define MAX_MMAP_REGIONS			(PLAT_ARM_MMAP_ENTRIES + \
+						ARM_BL_REGIONS)
+#define MAX_IO_DEVICES			2
+#define MAX_IO_HANDLES			3
+#define MAX_IO_BLOCK_DEVICES			1
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE			0x1C010000
+#define PLAT_ARM_GICC_BASE			0x1C02F000
+
+/* MHUv2 Secure Channel receiver and sender */
+#define PLAT_SDK700_MHU0_SEND			0x1B800000
+#define PLAT_SDK700_MHU0_RECV			0x1B810000
+
+/* Timer/watchdog related constants */
+#define ARM_SYS_CNTCTL_BASE			UL(0x1a200000)
+#define ARM_SYS_CNTREAD_BASE			UL(0x1a210000)
+#define ARM_SYS_TIMCTL_BASE			UL(0x1a220000)
+
+#define SYS_COUNTER_FREQ_IN_TICKS	UL(50000000) /* 50MHz */
+
+#define DIPHDA_IRQ_TZ_WDOG			32
+#define DIPHDA_IRQ_SEC_SYS_TIMER		34
+
+#define PLAT_MAX_PWR_LVL			2
+/*
+ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
+ * power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+#define ARM_PWR_LVL0				MPIDR_AFFLVL0
+#define ARM_PWR_LVL1				MPIDR_AFFLVL1
+#define ARM_PWR_LVL2				MPIDR_AFFLVL2
+
+/*
+ *  Macros for local power states in ARM platforms encoded by State-ID field
+ *  within the power-state parameter.
+ */
+/* Local power state for power domains in Run state. */
+#define ARM_LOCAL_STATE_RUN			U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define ARM_LOCAL_STATE_RET			U(1)
+/* Local power state for OFF/power-down. Valid for CPU and cluster
+ * power domains
+ */
+#define ARM_LOCAL_STATE_OFF			U(2)
+
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE		ARM_TRUSTED_SRAM_BASE
+#define PLAT_ARM_NSTIMER_FRAME_ID		U(1)
+
+#define PLAT_ARM_NS_IMAGE_BASE		(ARM_NS_SHARED_RAM_BASE)
+
+#define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 32)
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * ID will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE			1
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE			2
+
+#define PLATFORM_STACK_SIZE			UL(0x440)
+
+#define DIPHDA_EXTERNAL_FLASH			MAP_REGION_FLAT(	\
+						PLAT_ARM_NVM_BASE,	\
+						PLAT_ARM_NVM_SIZE,	\
+						MT_DEVICE | MT_RO | MT_SECURE)
+
+#define ARM_MAP_SHARED_RAM			MAP_REGION_FLAT(	\
+						ARM_SHARED_RAM_BASE,	\
+						ARM_SHARED_RAM_SIZE,	\
+						MT_MEMORY | MT_RW | MT_SECURE)
+
+#define ARM_MAP_NS_SHARED_RAM			MAP_REGION_FLAT(	\
+						ARM_NS_SHARED_RAM_BASE, \
+						ARM_NS_SHARED_RAM_SIZE, \
+						MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_NS_DRAM1			MAP_REGION_FLAT(	\
+						ARM_NS_DRAM1_BASE,	\
+						ARM_NS_DRAM1_SIZE,	\
+						MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_BL_RO				MAP_REGION_FLAT(	\
+						BL_CODE_BASE,		\
+						BL_CODE_END		\
+							- BL_CODE_BASE, \
+						MT_CODE | MT_SECURE),	\
+						MAP_REGION_FLAT(	\
+						BL_RO_DATA_BASE,	\
+						BL_RO_DATA_END	\
+						- BL_RO_DATA_BASE,	\
+						MT_RO_DATA | MT_SECURE)
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM		MAP_REGION_FLAT(	\
+						BL_COHERENT_RAM_BASE,	\
+						BL_COHERENT_RAM_END	\
+						- BL_COHERENT_RAM_BASE, \
+						MT_DEVICE | MT_RW | MT_SECURE)
+#endif
+
+/*
+ * Map the region for the optional device tree configuration with read and
+ * write permissions
+ */
+#define ARM_MAP_BL_CONFIG_REGION		MAP_REGION_FLAT(	\
+						ARM_FW_CONFIG_BASE,	\
+						(ARM_FW_CONFIG_LIMIT-   \
+						ARM_FW_CONFIG_BASE),   \
+						MT_MEMORY | MT_RW | MT_SECURE)
+
+#define DIPHDA_DEVICE_BASE			(0x1A000000)
+#define DIPHDA_DEVICE_SIZE			(0x26000000)
+#define DIPHDA_MAP_DEVICE			MAP_REGION_FLAT(	\
+						DIPHDA_DEVICE_BASE,	\
+						DIPHDA_DEVICE_SIZE,	\
+						MT_DEVICE | MT_RW | MT_SECURE)
+
+#define ARM_IRQ_SEC_PHY_TIMER			29
+
+#define ARM_IRQ_SEC_SGI_0			8
+#define ARM_IRQ_SEC_SGI_1			9
+#define ARM_IRQ_SEC_SGI_2			10
+#define ARM_IRQ_SEC_SGI_3			11
+#define ARM_IRQ_SEC_SGI_4			12
+#define ARM_IRQ_SEC_SGI_5			13
+#define ARM_IRQ_SEC_SGI_6			14
+#define ARM_IRQ_SEC_SGI_7			15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+		(grp), GIC_INTR_CFG_LEVEL), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+		GIC_INTR_CFG_EDGE)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_ARM_G1S_IRQ_PROPS(grp)	\
+	ARM_G1S_IRQ_PROPS(grp), \
+	INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
+		(grp), GIC_INTR_CFG_LEVEL), \
+	INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \
+		GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/diphda/include/plat_macros.S b/plat/arm/board/diphda/include/plat_macros.S
new file mode 100644
index 0000000..4de8f95
--- /dev/null
+++ b/plat/arm/board/diphda/include/plat_macros.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <css_macros.S>
+
+/* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * ---------------------------------------------
+ */
+	.macro plat_crash_print_regs
+	css_print_gic_regs
+	.endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/arm/board/diphda/platform.mk b/plat/arm/board/diphda/platform.mk
new file mode 100644
index 0000000..5ff0862
--- /dev/null
+++ b/plat/arm/board/diphda/platform.mk
@@ -0,0 +1,76 @@
+#
+# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Making sure the diphda platform type is specified
+ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
+	$(error TARGET_PLATFORM must be fpga or fvp)
+endif
+
+DIPHDA_CPU_LIBS	+=lib/cpus/aarch64/cortex_a35.S
+
+PLAT_INCLUDES		:=	-Iplat/arm/board/diphda/common/include	\
+				-Iplat/arm/board/diphda/include		\
+				-Iinclude/plat/arm/common			\
+				-Iinclude/plat/arm/css/common/aarch64
+
+
+DIPHDA_FW_NVCTR_VAL	:=	255
+TFW_NVCTR_VAL		:=	${DIPHDA_FW_NVCTR_VAL}
+NTFW_NVCTR_VAL		:=	${DIPHDA_FW_NVCTR_VAL}
+
+override NEED_BL1	:=	no
+
+override NEED_BL2	:=	yes
+FIP_BL2_ARGS := tb-fw
+
+override NEED_BL2U	:=	no
+override NEED_BL31	:=	yes
+NEED_BL32		:=	yes
+override NEED_BL33	:=	yes
+
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+
+DIPHDA_GIC_SOURCES	:=	${GICV2_SOURCES}			\
+				plat/common/plat_gicv2.c		\
+				plat/arm/common/arm_gicv2.c
+
+
+BL2_SOURCES		+=	plat/arm/board/diphda/common/diphda_security.c		\
+				plat/arm/board/diphda/common/diphda_err.c		\
+				plat/arm/board/diphda/common/diphda_trusted_boot.c	\
+				lib/utils/mem_region.c					\
+				plat/arm/board/diphda/common/diphda_helpers.S		\
+				plat/arm/board/diphda/common/diphda_plat.c		\
+				plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \
+				${DIPHDA_CPU_LIBS}					\
+
+
+BL31_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c				\
+			lib/utils/mem_region.c					\
+			plat/arm/board/diphda/common/diphda_helpers.S		\
+			plat/arm/board/diphda/common/diphda_topology.c		\
+			plat/arm/board/diphda/common/diphda_security.c		\
+			plat/arm/board/diphda/common/diphda_plat.c		\
+			plat/arm/board/diphda/common/diphda_pm.c		\
+			${DIPHDA_CPU_LIBS}					\
+			${DIPHDA_GIC_SOURCES}
+
+
+FDT_SOURCES		+=	plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
+DIPHDA_TOS_FW_CONFIG	:=	${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb
+
+# Add the SPMC manifest to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG}))
+
+# Adding TARGET_PLATFORM as a GCC define (-D option)
+$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
+
+# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option)
+$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL))
+
+include plat/arm/common/arm_common.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index 9fb566b..cad888f 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -36,16 +36,21 @@
 			id = <SOC_FW_CONFIG_ID>;
 		};
 
+/* If required, SPD should enable loading of trusted OS fw config */
+#if defined(SPD_tspd) || defined(SPD_spmd)
 		tos_fw-config {
 			load-address = <0x0 0x04001500>;
 			max-size = <0xB00>;
 			id = <TOS_FW_CONFIG_ID>;
 		};
+#endif
 
+#if !defined(SPD_spmd)
 		nt_fw-config {
 			load-address = <0x0 0x80000000>;
 			max-size = <0x200>;
 			id = <NT_FW_CONFIG_ID>;
 		};
+#endif
 	};
 };
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index 4838396..67e5504 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -50,6 +50,13 @@
 			vcpu_count = <1>;
 			mem_size = <1048576>;
 		};
+		vm4 {
+			is_ffa_partition;
+			debug_name = "ivy";
+			load_address = <0x7600000>;
+			vcpu_count = <1>;
+			mem_size = <1048576>;
+		};
 	};
 
 	cpus {
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
index 57d6792..088179b 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,7 +33,6 @@
 			is_ffa_partition;
 			debug_name = "op-tee";
 			load_address = <0x6280000>;
-			smc_whitelist = <0xbe000000>;
 			vcpu_count = <8>;
 			mem_size = <1048576>;
 		};
diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
index fe154e9..62ab27c 100644
--- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -48,26 +48,26 @@
 	arm-io_policies {
 		fip-handles {
 			compatible = "arm,io-fip-handle";
-			scp_bl2_uuid = <0x9766fd3d 0x89bee849 0xae5d78a1 0x40608213>;
-			bl31_uuid = <0x47d4086d 0x4cfe9846 0x9b952950 0xcbbd5a00>;
-			bl32_uuid = <0x05d0e189 0x53dc1347 0x8d2b500a 0x4b7a3e38>;
-			bl32_extra1_uuid = <0x0b70c28b 0x2a5a7840 0x9f650a56 0x82738288>;
-			bl32_extra2_uuid = <0x8ea87bb1 0xcfa23f4d 0x85fde7bb 0xa50220d9>;
-			bl33_uuid = <0xd6d0eea7 0xfcead54b 0x97829934 0xf234b6e4>;
-			hw_cfg_uuid = <0x08b8f1d9 0xc9cf9349 0xa9626fbc 0x6b7265cc>;
-			soc_fw_cfg_uuid = <0x9979814b 0x0376fb46 0x8c8e8d26 0x7f7859e0>;
-			tos_fw_cfg_uuid = <0x26257c1a 0xdbc67f47 0x8d96c4c4 0xb0248021>;
-			nt_fw_cfg_uuid = <0x28da9815 0x93e87e44 0xac661aaf 0x801550f9>;
-			t_key_cert_uuid = <0x827ee890 0xf860e411 0xa1b477a7 0x21b4f94c>;
-			scp_fw_key_uuid = <0x024221a1 0xf860e411 0x8d9bf33c 0x0e15a014>;
-			soc_fw_key_uuid = <0x8ab8becc 0xf960e411 0x9ad0eb48 0x22d8dcf8>;
-			tos_fw_key_cert_uuid = <0x9477d603 0xfb60e411 0x85ddb710 0x5b8cee04>;
-			nt_fw_key_cert_uuid = <0x8ad5832a 0xfb60e411 0x8aafdf30 0xbbc49859>;
-			scp_fw_content_cert_uuid = <0x44be6f04 0x5e63e411 0xb28b73d8 0xeaae9656>;
-			soc_fw_content_cert_uuid = <0xe2b20c20 0x5e63e411 0x9ce8abcc 0xf92bb666>;
-			tos_fw_content_cert_uuid = <0xa49f4411 0x5e63e411 0x87283f05 0x722af33d>;
-			nt_fw_content_cert_uuid = <0x8ec4c1f3 0x5d63e411 0xa7a987ee 0x40b23fa7>;
-			sp_content_cert_uuid = <0x776dfd44 0x86974c3b 0x91ebc13e 0x025a2a6f>;
+			scp_bl2_uuid = "9766fd3d-89be-e849-ae5d-78a140608213";
+			bl31_uuid = "47d4086d-4cfe-9846-9b95-2950cbbd5a00";
+			bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38";
+			bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288";
+			bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9";
+			bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4";
+			hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc";
+			soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0";
+			tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021";
+			nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9";
+			t_key_cert_uuid = "827ee890-f860-e411-a1b4-777a21b4f94c";
+			scp_fw_key_uuid = "024221a1-f860-e411-8d9b-f33c0e15a014";
+			soc_fw_key_uuid = "8ab8becc-f960-e411-9ad0-eb4822d8dcf8";
+			tos_fw_key_cert_uuid = "9477d603-fb60-e411-85dd-b7105b8cee04";
+			nt_fw_key_cert_uuid = "8ad5832a-fb60-e411-8aaf-df30bbc49859";
+			scp_fw_content_cert_uuid = "44be6f04-5e63-e411-b28b-73d8eaae9656";
+			soc_fw_content_cert_uuid = "e2b20c20-5e63-e411-9ce8-abccf92bb666";
+			tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d";
+			nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7";
+			sp_content_cert_uuid = "776dfd44-8697-4c3b-91eb-c13e025a2a6f";
 		};
 	};
 #endif /* ARM_IO_IN_DTB */
@@ -76,25 +76,32 @@
 		compatible = "arm,sp";
 #ifdef OPTEE_SP_FW_CONFIG
 		op-tee {
-			uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
+			uuid = "486178e0-e7f8-11e3-bc5e-0002a5d5c51b";
 			load-address = <0x6280000>;
 		};
 #else
 		cactus-primary {
-			uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>;
+			uuid = "b4b5671e-4a90-4fe1-b81f-fb13dae1dacb";
 			load-address = <0x7000000>;
 			owner = "SiP";
 		};
 
 		cactus-secondary {
-			uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>;
+			uuid = "d1582309-f023-47b9-827c-4464f5578fc8";
 			load-address = <0x7100000>;
 			owner = "Plat";
 		};
 
 		cactus-tertiary {
-			uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>;
+			uuid = "79b55c73-1d8c-44b9-8593-61e1770ad8d2";
 			load-address = <0x7200000>;
+			owner = "Plat";
+		};
+
+		ivy {
+			uuid = "eaba83d8-baaf-4eaf-8144-f7fdcbe544a7";
+			load-address = <0x7600000>;
+			owner = "Plat";
 		};
 #endif
 	};
diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c
index e713bbc..06ee037 100644
--- a/plat/arm/board/fvp/fvp_bl1_setup.c
+++ b/plat/arm/board/fvp/fvp_bl1_setup.c
@@ -1,15 +1,17 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
+#include <errno.h>
 
 #include <bl1/bl1.h>
 #include <common/tbbr/tbbr_img_def.h>
 #include <drivers/arm/smmu_v3.h>
 #include <drivers/arm/sp805.h>
+#include <lib/mmio.h>
 #include <plat/arm/common/arm_config.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/arm/common/arm_def.h>
@@ -61,6 +63,12 @@
 
 __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
 {
+	uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
+
+	/* Clear the NV flags register. */
+	mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR),
+		      nv_flags);
+
 	/* Setup the watchdog to reset the system as soon as possible */
 	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
 
@@ -124,3 +132,15 @@
 	return 0;
 }
 #endif /* MEASURED_BOOT */
+
+/*******************************************************************************
+ * The following function checks if Firmware update is needed by checking error
+ * reported in NV flag.
+ ******************************************************************************/
+bool plat_arm_bl1_fwu_needed(void)
+{
+	int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
+
+	/* if image load/authentication failed */
+	return ((nv_flags == -EAUTH) || (nv_flags == -ENOENT));
+}
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 52686fa..9d3c031 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -72,14 +72,11 @@
  * Table of memory regions for various BL stages to map using the MMU.
  * This doesn't include Trusted SRAM as setup_page_tables() already takes care
  * of mapping it.
- *
- * The flash needs to be mapped as writable in order to erase the FIP's Table of
- * Contents in case of unrecoverable error (see plat_error_handler()).
  */
 #ifdef IMAGE_BL1
 const mmap_region_t plat_arm_mmap[] = {
 	ARM_MAP_SHARED_RAM,
-	V2M_MAP_FLASH0_RW,
+	V2M_MAP_FLASH0_RO,
 	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
@@ -483,9 +480,9 @@
 int32_t plat_get_soc_version(void)
 {
 	return (int32_t)
-		((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
-		 | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
-		 | FVP_SOC_ID);
+		(SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
+				    ARM_SOC_IDENTIFICATION_CODE) |
+		 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
 }
 
 /* Get SOC revision */
@@ -494,6 +491,6 @@
 	unsigned int sys_id;
 
 	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
-	return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
-			V2M_SYS_ID_REV_MASK);
+	return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
+			  V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
 }
diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c
index c9b2090..1f9f0dd 100644
--- a/plat/arm/board/fvp/fvp_err.c
+++ b/plat/arm/board/fvp/fvp_err.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #include <common/debug.h>
 #include <drivers/arm/sp805.h>
 #include <drivers/cfi/v2m_flash.h>
+#include <lib/mmio.h>
 #include <plat/arm/common/plat_arm.h>
 #include <platform_def.h>
 
@@ -17,25 +18,8 @@
  */
 __dead2 void plat_arm_error_handler(int err)
 {
-	int ret;
-
-	switch (err) {
-	case -ENOENT:
-	case -EAUTH:
-		/* Image load or authentication error. Erase the ToC */
-		INFO("Erasing FIP ToC from flash...\n");
-		(void)nor_unlock(PLAT_ARM_FIP_BASE);
-		ret = nor_word_program(PLAT_ARM_FIP_BASE, 0);
-		if (ret != 0) {
-			ERROR("Cannot erase ToC\n");
-		} else {
-			INFO("Done\n");
-		}
-		break;
-	default:
-		/* Unexpected error */
-		break;
-	}
+	/* Propagate the err code in the NV-flags register */
+	mmio_write_32(V2M_SYS_NVFLAGS_ADDR, (uint32_t)err);
 
 	console_flush();
 
diff --git a/plat/arm/board/fvp/fvp_measured_boot.c b/plat/arm/board/fvp/fvp_measured_boot.c
index b145aae..5dcadba 100644
--- a/plat/arm/board/fvp/fvp_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_measured_boot.c
@@ -15,12 +15,10 @@
 	{ BL32_EXTRA1_IMAGE_ID, BL32_EXTRA1_IMAGE_STRING, PCR_0 },
 	{ BL32_EXTRA2_IMAGE_ID, BL32_EXTRA2_IMAGE_STRING, PCR_0 },
 	{ BL33_IMAGE_ID, BL33_STRING, PCR_0 },
-	{ GPT_IMAGE_ID, GPT_IMAGE_STRING, PCR_0 },
 	{ HW_CONFIG_ID, HW_CONFIG_STRING, PCR_0 },
 	{ NT_FW_CONFIG_ID, NT_FW_CONFIG_STRING, PCR_0 },
 	{ SCP_BL2_IMAGE_ID, SCP_BL2_IMAGE_STRING, PCR_0 },
 	{ SOC_FW_CONFIG_ID, SOC_FW_CONFIG_STRING, PCR_0 },
-	{ STM32_IMAGE_ID, STM32_IMAGE_STRING, PCR_0 },
 	{ TOS_FW_CONFIG_ID, TOS_FW_CONFIG_STRING, PCR_0 },
 	{ INVALID_ID, NULL, (unsigned int)(-1) }	/* Terminator */
 };
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 8defcf8..8b25a54 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -115,7 +115,7 @@
 #if USE_ROMLIB
 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0x1000)
 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0xe000)
-#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
+#define FVP_BL2_ROMLIB_OPTIMIZATION	UL(0x5000)
 #else
 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0)
 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0)
@@ -150,12 +150,18 @@
 #endif /* RESET_TO_BL31 */
 
 #ifndef __aarch64__
+#if RESET_TO_SP_MIN
+/* Size of Trusted SRAM - the first 4KB of shared memory */
+#define PLAT_ARM_MAX_BL32_SIZE		(PLAT_ARM_TRUSTED_SRAM_SIZE - \
+					 ARM_SHARED_RAM_SIZE)
+#else
 /*
  * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
  * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
  * BL2 and BL1-RW
  */
 # define PLAT_ARM_MAX_BL32_SIZE		UL(0x3B000)
+#endif /* RESET_TO_SP_MIN */
 #endif
 
 /*
@@ -185,8 +191,18 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#if ARM_GPT_SUPPORT
+/*
+ * Offset of the FIP in the GPT image. BL1 component uses this option
+ * as it does not load the partition table to get the FIP base
+ * address. At sector 34 by default (i.e. after reserved sectors 0-33)
+ * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
+ */
+#define PLAT_ARM_FIP_OFFSET_IN_GPT	0x4400
+#endif /* ARM_GPT_SUPPORT */
 
 #define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
 #define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 3bcfe91..10258ad 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -131,11 +131,13 @@
 					lib/cpus/aarch64/neoverse_e1.S		\
 					lib/cpus/aarch64/neoverse_v1.S		\
 					lib/cpus/aarch64/cortex_a78_ae.S	\
-					lib/cpus/aarch64/cortex_klein.S	        \
-					lib/cpus/aarch64/cortex_matterhorn.S	\
+					lib/cpus/aarch64/cortex_a510.S		\
+					lib/cpus/aarch64/cortex_a710.S	\
 					lib/cpus/aarch64/cortex_makalu.S	\
+					lib/cpus/aarch64/cortex_makalu_elp_arm.S \
 					lib/cpus/aarch64/cortex_a65.S		\
-					lib/cpus/aarch64/cortex_a65ae.S
+					lib/cpus/aarch64/cortex_a65ae.S		\
+					lib/cpus/aarch64/cortex_a78c.S
 	endif
 	# AArch64/AArch32 cores
 	FVP_CPU_LIBS	+=	lib/cpus/aarch64/cortex_a55.S		\
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index 3f2fcee..bd8ef6a 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -303,8 +303,8 @@
 #define MAX_IO_HANDLES			4
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH1_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH1_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
 
 #define PLAT_ARM_NVM_BASE		V2M_FLASH1_BASE
 #define PLAT_ARM_NVM_SIZE		(V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/juno/fdts/juno_fw_config.dts b/plat/arm/board/juno/fdts/juno_fw_config.dts
index c0538f8..4b88efe 100644
--- a/plat/arm/board/juno/fdts/juno_fw_config.dts
+++ b/plat/arm/board/juno/fdts/juno_fw_config.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,5 +17,11 @@
 			max-size = <0x200>;
 			id = <TB_FW_CONFIG_ID>;
 		};
+
+		hw-config {
+			load-address = <0x0 0x82000000>;
+			max-size = <0x8000>;
+			id = <HW_CONFIG_ID>;
+		};
 	};
 };
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 91c3ae7..5299a7b 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -53,6 +53,14 @@
 #define PLAT_ARM_DRAM2_BASE		ULL(0x880000000)
 #define PLAT_ARM_DRAM2_SIZE		ULL(0x180000000)
 
+#define PLAT_HW_CONFIG_DTB_BASE		ULL(0x82000000)
+#define PLAT_HW_CONFIG_DTB_SIZE		ULL(0x00008000) /* 32KB */
+
+#define ARM_DTB_DRAM_NS			MAP_REGION_FLAT(		\
+					PLAT_HW_CONFIG_DTB_BASE,	\
+					PLAT_HW_CONFIG_DTB_SIZE,	\
+					MT_MEMORY | MT_RO | MT_NS)
+
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 
@@ -108,7 +116,7 @@
 
 #ifdef IMAGE_BL31
 #  define PLAT_ARM_MMAP_ENTRIES		7
-#  define MAX_XLAT_TABLES		3
+#  define MAX_XLAT_TABLES		5
 #endif
 
 #ifdef IMAGE_BL32
diff --git a/plat/arm/board/juno/juno_bl1_setup.c b/plat/arm/board/juno/juno_bl1_setup.c
index 2234055..a9d5cc3 100644
--- a/plat/arm/board/juno/juno_bl1_setup.c
+++ b/plat/arm/board/juno/juno_bl1_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -62,11 +62,11 @@
  ******************************************************************************/
 bool plat_arm_bl1_fwu_needed(void)
 {
-	const int32_t *nv_flags_ptr = (const int32_t *)V2M_SYS_NVFLAGS_ADDR;
+	int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
 
 	/* Check if TOC is invalid or watchdog reset happened. */
-	return (!arm_io_is_toc_valid() || (((*nv_flags_ptr == -EAUTH) ||
-		(*nv_flags_ptr == -ENOENT)) && is_watchdog_reset()));
+	return (!arm_io_is_toc_valid() || (((nv_flags == -EAUTH) ||
+		(nv_flags == -ENOENT)) && is_watchdog_reset()));
 }
 
 /*******************************************************************************
@@ -86,13 +86,11 @@
  ******************************************************************************/
 __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
 {
-	unsigned int *nv_flags_clr = (unsigned int *)
-			(V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR);
-	unsigned int *nv_flags_ptr = (unsigned int *)
-			(V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS);
+	uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
 
 	/* Clear the NV flags register. */
-	*nv_flags_clr = *nv_flags_ptr;
+	mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR),
+		      nv_flags);
 
 	/* Setup the watchdog to reset the system as soon as possible */
 	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
diff --git a/plat/arm/board/juno/juno_bl2_setup.c b/plat/arm/board/juno/juno_bl2_setup.c
index 95ef77c..849acd6 100644
--- a/plat/arm/board/juno/juno_bl2_setup.c
+++ b/plat/arm/board/juno/juno_bl2_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017,2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,9 @@
 
 #include <common/bl_common.h>
 #include <common/desc_image_load.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
+
 #include <plat/arm/common/plat_arm.h>
 
 #if JUNO_AARCH32_EL3_RUNTIME
@@ -30,4 +33,41 @@
 
 	return err;
 }
+
+#else
+
+/*******************************************************************************
+ * This function returns the list of executable images
+ ******************************************************************************/
+struct bl_params *plat_get_next_bl_params(void)
+{
+	struct bl_params *arm_bl_params = arm_get_next_bl_params();
+
+#if __aarch64__
+	const struct dyn_cfg_dtb_info_t *fw_config_info;
+	bl_mem_params_node_t *param_node;
+	uintptr_t fw_config_base = 0U;
+	entry_point_info_t *ep_info;
+
+	/* Get BL31 image node */
+	param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
+	assert(param_node != NULL);
+
+	/* Get fw_config load address */
+	fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
+	assert(fw_config_info != NULL);
+
+	fw_config_base = fw_config_info->config_addr;
+	assert(fw_config_base != 0U);
+
+	/*
+	 * Get the entry point info of BL31 image and override
+	 * arg1 of entry point info with fw_config base address
+	 */
+	ep_info = &param_node->ep_info;
+	ep_info->args.arg1 = (uint32_t)fw_config_base;
+#endif /* __aarch64__ */
+
+	return arm_bl_params;
+}
 #endif /* JUNO_AARCH32_EL3_RUNTIME */
diff --git a/plat/arm/board/juno/juno_bl31_setup.c b/plat/arm/board/juno/juno_bl31_setup.c
new file mode 100644
index 0000000..7a0a6d9
--- /dev/null
+++ b/plat/arm/board/juno/juno_bl31_setup.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
+
+#include <plat/arm/common/plat_arm.h>
+
+void __init bl31_early_platform_setup2(u_register_t arg0,
+		u_register_t arg1, u_register_t arg2, u_register_t arg3)
+{
+	const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
+
+	INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
+
+	/* Fill the properties struct with the info from the config dtb */
+	fconf_populate("FW_CONFIG", arg1);
+
+	soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID);
+	if (soc_fw_config_info != NULL) {
+		arg1 = soc_fw_config_info->config_addr;
+	}
+
+	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+
+	/*
+	 * Initialize Interconnect for this cluster during cold boot.
+	 * No need for locks as no other CPU is active.
+	 */
+	plat_arm_interconnect_init();
+
+	/*
+	 * Enable Interconnect coherency for the primary CPU's cluster.
+	 * Earlier bootloader stages might already do this (e.g. Trusted
+	 * Firmware's BL1 does it) but we can't assume so. There is no harm in
+	 * executing this code twice anyway.
+	 * Platform specific PSCI code will enable coherency for other
+	 * clusters.
+	 */
+	plat_arm_interconnect_enter_coherency();
+}
+
+void __init bl31_plat_arch_setup(void)
+{
+	arm_bl31_plat_arch_setup();
+
+	/* HW_CONFIG was also loaded by BL2 */
+	const struct dyn_cfg_dtb_info_t *hw_config_info;
+
+	hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
+	assert(hw_config_info != NULL);
+
+	fconf_populate("HW_CONFIG", hw_config_info->config_addr);
+}
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index da4918c..038f604 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -75,6 +75,7 @@
 	ARM_V2M_MAP_MEM_PROTECT,
 #endif
 	SOC_CSS_MAP_DEVICE,
+	ARM_DTB_DRAM_NS,
 	{0}
 };
 #endif
@@ -117,9 +118,9 @@
 int32_t plat_get_soc_version(void)
 {
 	return (int32_t)
-		((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
-		 | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
-		 | JUNO_SOC_ID);
+		(SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
+				    ARM_SOC_IDENTIFICATION_CODE) |
+		 (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK));
 }
 
 /* Get SOC revision */
@@ -128,6 +129,6 @@
 	unsigned int sys_id;
 
 	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
-	return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
-			V2M_SYS_ID_REV_MASK);
+	return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
+			  V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
 }
diff --git a/plat/arm/board/juno/juno_err.c b/plat/arm/board/juno/juno_err.c
index 60699cc..02d751e 100644
--- a/plat/arm/board/juno/juno_err.c
+++ b/plat/arm/board/juno/juno_err.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,10 +16,8 @@
  */
 void __dead2 plat_arm_error_handler(int err)
 {
-	uint32_t *flags_ptr = (uint32_t *)V2M_SYS_NVFLAGS_ADDR;
-
 	/* Propagate the err code in the NV-flags register */
-	*flags_ptr = err;
+	mmio_write_32(V2M_SYS_NVFLAGS_ADDR, (uint32_t)err);
 
 	/* Setup the watchdog to reset the system as soon as possible */
 	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c
index 1e64c02..654a7f1 100644
--- a/plat/arm/board/juno/juno_security.c
+++ b/plat/arm/board/juno/juno_security.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -115,6 +115,14 @@
 	/* Drive SPIDEN LOW to disable invasive debug of secure state. */
 	mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
 		1U << SPIDEN_INT_CLR_SHIFT);
+
+	/* Set internal drive selection for SPNIDEN. */
+	mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
+		1U << SPNIDEN_SEL_SET_SHIFT);
+
+	/* Drive SPNIDEN LOW to disable non-invasive debug of secure state. */
+	mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
+		1U << SPNIDEN_INT_CLR_SHIFT);
 #endif
 }
 
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 5cf5749..92fbf35 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -83,6 +83,10 @@
 				lib/cpus/aarch64/cortex_a57.S		\
 				lib/cpus/aarch64/cortex_a72.S		\
 				lib/utils/mem_region.c			\
+				common/fdt_wrappers.c			\
+				lib/fconf/fconf.c			\
+				lib/fconf/fconf_dyn_cfg_getter.c	\
+				plat/arm/board/juno/juno_bl31_setup.c	\
 				plat/arm/board/juno/juno_pm.c		\
 				plat/arm/board/juno/juno_topology.c	\
 				plat/arm/common/arm_nor_psci_mem_protect.c \
@@ -174,15 +178,19 @@
 
 # Add the FDT_SOURCES and options for Dynamic Config
 FDT_SOURCES		+=	plat/arm/board/juno/fdts/${PLAT}_fw_config.dts	\
-				plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts
+				plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \
+				fdts/${PLAT}.dts
 
 FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
 TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+HW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}.dtb
 
 # Add the FW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
 # Add the TB_FW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
 
 include plat/arm/board/common/board_common.mk
 include plat/arm/common/arm_common.mk
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
index 53074f4..0f9dd49 100644
--- a/plat/arm/board/rde1edge/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -58,4 +58,9 @@
    ${CSS_SGI_CHIP_COUNT}.")
 endif
 
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-E1-Edge should always be 0, \
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
+
 override CTX_INCLUDE_AARCH32_REGS	:= 0
diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk
index d65854f..22ab312 100644
--- a/plat/arm/board/rdn1edge/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -65,4 +65,9 @@
    set to ${CSS_SGI_CHIP_COUNT}.")
 endif
 
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
+
 override CTX_INCLUDE_AARCH32_REGS	:= 0
diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h
index 3f753f7..30a0c5c 100644
--- a/plat/arm/board/rdn2/include/platform_def.h
+++ b/plat/arm/board/rdn2/include/platform_def.h
@@ -11,7 +11,12 @@
 
 #include <sgi_soc_platform_def_v2.h>
 
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_CLUSTER_COUNT		U(8)
+#else
 #define PLAT_ARM_CLUSTER_COUNT		U(16)
+#endif
+
 #define CSS_SGI_MAX_CPUS_PER_CLUSTER	U(1)
 #define CSS_SGI_MAX_PE_PER_CPU		U(1)
 
@@ -26,7 +31,12 @@
 #define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
 
 #define TZC400_OFFSET			UL(0x1000000)
+
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define TZC400_COUNT			U(2)
+#else
 #define TZC400_COUNT			U(8)
+#endif
 
 #define TZC400_BASE(n)			(PLAT_ARM_TZC_BASE + \
 						(n * TZC400_OFFSET))
@@ -60,6 +70,11 @@
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE		UL(0x30000000)
 #define PLAT_ARM_GICC_BASE		UL(0x2C000000)
+
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_GICR_BASE		UL(0x30100000)
+#else
 #define PLAT_ARM_GICR_BASE		UL(0x301C0000)
+#endif
 
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 03771dc..794f897 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -58,3 +58,10 @@
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
 override ENABLE_AMU			:= 1
+
+RD_N2_VARIANTS	:= 0 1
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
+	$(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0 or 1, currently set \
+     to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/rdn2/rdn2_topology.c b/plat/arm/board/rdn2/rdn2_topology.c
index 5c2e287..cad6c37 100644
--- a/plat/arm/board/rdn2/rdn2_topology.c
+++ b/plat/arm/board/rdn2/rdn2_topology.c
@@ -20,6 +20,7 @@
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#if (CSS_SGI_PLATFORM_VARIANT == 0)
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -28,6 +29,7 @@
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#endif
 };
 
 /*******************************************************************************
@@ -51,6 +53,7 @@
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+#if (CSS_SGI_PLATFORM_VARIANT == 0)
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
@@ -59,4 +62,5 @@
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
+#endif
 };
diff --git a/plat/arm/board/rdv1/platform.mk b/plat/arm/board/rdv1/platform.mk
index 2ffd139..1ae85de 100644
--- a/plat/arm/board/rdv1/platform.mk
+++ b/plat/arm/board/rdv1/platform.mk
@@ -58,3 +58,8 @@
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
 override ENABLE_AMU			:= 1
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-V1 should always be 0, \
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/rdv1mc/platform.mk b/plat/arm/board/rdv1mc/platform.mk
index fb05793..df0b09a 100644
--- a/plat/arm/board/rdv1mc/platform.mk
+++ b/plat/arm/board/rdv1mc/platform.mk
@@ -68,3 +68,9 @@
 $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
+override ENABLE_AMU			:= 1
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index 89abcfe..0761b77 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -58,3 +58,8 @@
  $(error  "Chip count for SGI575 should be 1, currently set to \
    ${CSS_SGI_CHIP_COUNT}.")
 endif
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for SGI575 should always be 0,\
+     currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk
index a649939..f8df1a7 100644
--- a/plat/arm/board/sgm775/platform.mk
+++ b/plat/arm/board/sgm775/platform.mk
@@ -4,6 +4,8 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected)
+
 include plat/arm/css/sgm/sgm-common.mk
 
 SGM775_BASE= plat/arm/board/sgm775
diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
index 2f459b0..44c7008 100644
--- a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -40,7 +40,7 @@
 			is_ffa_partition;
 			debug_name = "cactus-tertiary";
 			load_address = <0xfe200000>;
-			vcpu_count = <8>;
+			vcpu_count = <1>;
 			mem_size = <1048576>;
 		};
 	};
diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
index 221039c..0830d5c 100644
--- a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
@@ -27,8 +27,28 @@
 			debug_name = "op-tee";
 			load_address = <0xfd280000>;
 			vcpu_count = <8>;
-			mem_size = <30928896>; /* 32MB TZC DRAM - SPMC region */
+#ifdef TS_SP_FW_CONFIG
+			mem_size = <26738688>; /* 25MB TZC DRAM */
+#else
+			mem_size = <30928896>; /* 29MB TZC DRAM */
+#endif
+		};
+#ifdef TS_SP_FW_CONFIG
+		vm2 {
+			is_ffa_partition;
+			debug_name = "secure-storage";
+			load_address = <0xfee00000>;
+			vcpu_count = <1>;
+			mem_size = <2097152>; /* 2MB TZC DRAM */
+		};
+		vm3 {
+			is_ffa_partition;
+			debug_name = "crypto";
+			load_address = <0xfec00000>;
+			vcpu_count = <1>;
+			mem_size = <2097152>; /* 2MB TZC DRAM */
 		};
+#endif
 	};
 
 	cpus {
diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
index de5f95d..28ed7ae 100644
--- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
+++ b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,26 +27,36 @@
 
 	secure-partitions {
 		compatible = "arm,sp";
+#ifdef TS_SP_FW_CONFIG
+		secure-storage {
+		       uuid = "dc1eef48-b17a-4ccf-ac8b-dfcff7711b14";
+		       load-address = <0xfee00000>;
+		};
+		crypto {
+		       uuid = "d9df52d5-16a2-4bb2-9aa4-d26d3b84e8c0";
+		       load-address = <0xfec00000>;
+		};
+#endif
 #if OPTEE_SP_FW_CONFIG
 		op-tee {
-		       uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
+		       uuid = "486178e0-e7f8-11e3-bc5e-0002a5d5c51b";
 		       load-address = <0xfd280000>;
 		};
 #else
 		cactus-primary {
-			uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>;
+			uuid = "b4b5671e-4a90-4fe1-b81f-fb13dae1dacb";
 			load-address = <0xfe000000>;
 			owner = "SiP";
 		};
 
 		cactus-secondary {
-			uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>;
+			uuid = "d1582309-f023-47b9-827c-4464f5578fc8";
 			load-address = <0xfe100000>;
 			owner = "Plat";
 		};
 
 		cactus-tertiary {
-			uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>;
+			uuid = "79b55c73-1d8c-44b9-8593-61e1770ad8d2";
 			load-address = <0xfe200000>;
 		};
 #endif
diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h
index 30b5ab7..b169d77 100644
--- a/plat/arm/board/tc0/include/platform_def.h
+++ b/plat/arm/board/tc0/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -220,7 +220,7 @@
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE		UL(0x30000000)
 #define PLAT_ARM_GICC_BASE		UL(0x2C000000)
-#define PLAT_ARM_GICR_BASE		UL(0x30140000)
+#define PLAT_ARM_GICR_BASE		UL(0x30080000)
 
 /*
  * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc0/platform.mk
index 20ea6e3..5ae87d1 100644
--- a/plat/arm/board/tc0/platform.mk
+++ b/plat/arm/board/tc0/platform.mk
@@ -43,9 +43,9 @@
 
 PLAT_INCLUDES		+=	-I${TC0_BASE}/include/
 
-TC0_CPU_SOURCES	:=	lib/cpus/aarch64/cortex_klein.S         \
-			lib/cpus/aarch64/cortex_matterhorn.S \
-			lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
+TC0_CPU_SOURCES	:=	lib/cpus/aarch64/cortex_a510.S         \
+			lib/cpus/aarch64/cortex_a710.S \
+			lib/cpus/aarch64/cortex_x2.S
 
 INTERCONNECT_SOURCES	:=	${TC0_BASE}/tc0_interconnect.c
 
@@ -114,6 +114,8 @@
 
 override ENABLE_SPE_FOR_LOWER_ELS	:= 0
 
+override ENABLE_AMU := 1
+
 include plat/arm/common/arm_common.mk
 include plat/arm/css/common/css_common.mk
 include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index c90e93c..63ed9fe 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,6 +14,7 @@
 #include <common/debug.h>
 #include <common/desc_image_load.h>
 #include <drivers/generic_delay_timer.h>
+#include <drivers/partition/partition.h>
 #include <lib/fconf/fconf.h>
 #include <lib/fconf/fconf_dyn_cfg_getter.h>
 #ifdef SPD_opteed
@@ -70,6 +71,12 @@
 
 	/* Initialise the IO layer and register platform IO devices */
 	plat_arm_io_setup();
+
+	/* Load partition table */
+#if ARM_GPT_SUPPORT
+	partition_init(GPT_IMAGE_ID);
+#endif /* ARM_GPT_SUPPORT */
+
 }
 
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
@@ -86,6 +93,14 @@
 void bl2_plat_preload_setup(void)
 {
 	arm_bl2_dyn_cfg_init();
+
+#if ARM_GPT_SUPPORT
+	int result = arm_set_image_source(FIP_IMAGE_ID, "FIP_A");
+
+	if (result != 0) {
+		panic();
+	}
+#endif /* ARM_GPT_SUPPORT */
 }
 
 /*
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 6dd4587..b819888 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -148,14 +148,6 @@
 	bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 
-#if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33)
-	/*
-	 * Hafnium in normal world expects its manifest address in x0, which
-	 * is loaded at base of DRAM.
-	 */
-	bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
-#endif
-
 #else /* RESET_TO_BL31 */
 
 	/*
@@ -206,6 +198,14 @@
 	bl33_image_ep_info.args.arg2 = 0U;
 	bl33_image_ep_info.args.arg3 = 0U;
 # endif
+
+#if defined(SPD_spmd)
+	/*
+	 * Hafnium in normal world expects its manifest address in x0, In CI
+	 * configuration manifest is preloaded at 0x80000000(start of DRAM).
+	 */
+	bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
+#endif
 }
 
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 7d9fd6c..946b732 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -151,10 +151,10 @@
 	 */
 	mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
 
-#if defined(PLAT_juno) || defined(PLAT_n1sdp)
+#if defined(PLAT_juno) || defined(PLAT_n1sdp) || defined(PLAT_morello)
 	/*
 	 * Initialize CNTFRQ register in Non-secure CNTBase frame.
-	 * This is only required for Juno and N1SDP, because they do not
+	 * This is required for Juno, N1SDP and Morello because they do not
 	 * follow ARM ARM in that the value updated in CNTFRQ is not
 	 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
 	 */
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index a225b40..de25a53 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -100,6 +100,11 @@
   $(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
 endif
 
+# Arm Ethos-N NPU SiP service
+ARM_ETHOSN_NPU_DRIVER			:=	0
+$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
+$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
+
 # Use an implementation of SHA-256 with a smaller memory footprint but reduced
 # speed.
 $(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
@@ -149,9 +154,9 @@
 $(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
 $(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
 
-# Enable PIE support for RESET_TO_BL31 case
-ifeq (${RESET_TO_BL31},1)
-    ENABLE_PIE			:=	1
+# Enable PIE support for RESET_TO_BL31/RESET_TO_SP_MIN case
+ifneq ($(filter 1,${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
+	ENABLE_PIE			:=	1
 endif
 
 # CryptoCell integration relies on coherent buffers for passing data from
@@ -162,6 +167,24 @@
     endif
 endif
 
+# Disable GPT parser support, use FIP image by default
+ARM_GPT_SUPPORT			:=	0
+$(eval $(call assert_boolean,ARM_GPT_SUPPORT))
+$(eval $(call add_define,ARM_GPT_SUPPORT))
+
+# Include necessary sources to parse GPT image
+ifeq (${ARM_GPT_SUPPORT}, 1)
+  BL2_SOURCES	+=	drivers/partition/gpt.c		\
+			drivers/partition/partition.c
+endif
+
+# Enable CRC instructions via extension for ARMv8-A CPUs.
+# For ARMv8.1-A, and onwards CRC instructions are default enabled.
+# Enable HW computed CRC support unconditionally in BL2 component.
+ifeq (${ARM_ARCH_MINOR},0)
+  BL2_CPPFLAGS += -march=armv8-a+crc
+endif
+
 ifeq (${ARCH}, aarch64)
 PLAT_INCLUDES		+=	-Iinclude/plat/arm/common/aarch64
 endif
@@ -207,6 +230,7 @@
 				drivers/io/io_storage.c				\
 				plat/arm/common/arm_bl2_setup.c			\
 				plat/arm/common/arm_err.c			\
+				common/hw_crc32.c				\
 				${ARM_IO_SOURCES}
 
 # Firmware Configuration Framework sources
@@ -217,7 +241,8 @@
 
 DYN_CFG_SOURCES		+=	plat/arm/common/arm_dyn_cfg.c		\
 				plat/arm/common/arm_dyn_cfg_helpers.c	\
-				common/fdt_wrappers.c
+				common/fdt_wrappers.c			\
+				common/uuid.c
 
 BL1_SOURCES		+=	${DYN_CFG_SOURCES}
 BL2_SOURCES		+=	${DYN_CFG_SOURCES}
@@ -231,8 +256,10 @@
 ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
 BL2_SOURCES		+=	plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
 else
+ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
 BL2_SOURCES		+=	plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
 endif
+endif
 BL2_SOURCES		+=	plat/arm/common/arm_image_load.c		\
 				common/desc_image_load.c
 ifeq (${SPD},opteed)
@@ -248,14 +275,26 @@
 				plat/arm/common/arm_topology.c			\
 				plat/common/plat_psci_common.c
 
+ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),)
+ARM_SVC_HANDLER_SRCS :=
+
+ifeq (${ENABLE_PMF},1)
+ARM_SVC_HANDLER_SRCS	+=	lib/pmf/pmf_smc.c
+endif
+
+ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+ARM_SVC_HANDLER_SRCS	+=	plat/arm/common/fconf/fconf_ethosn_getter.c	\
+				drivers/delay_timer/delay_timer.c		\
+				drivers/arm/ethosn/ethosn_smc.c
+endif
+
-ifeq (${ENABLE_PMF}, 1)
 ifeq (${ARCH}, aarch64)
 BL31_SOURCES		+=	plat/arm/common/aarch64/execution_state_switch.c\
 				plat/arm/common/arm_sip_svc.c			\
-				lib/pmf/pmf_smc.c
+				${ARM_SVC_HANDLER_SRCS}
 else
 BL32_SOURCES		+=	plat/arm/common/arm_sip_svc.c			\
-				lib/pmf/pmf_smc.c
+				${ARM_SVC_HANDLER_SRCS}
 endif
 endif
 
@@ -285,6 +324,7 @@
 ifeq (${SPD},spmd)
 BL31_SOURCES		+=	plat/common/plat_spmd_manifest.c	\
 				common/fdt_wrappers.c			\
+				common/uuid.c				\
 				${LIBFDT_SRCS}
 
 endif
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index 6b3a611..30473be 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -208,10 +208,7 @@
 			HW_CONFIG_ID,
 			SOC_FW_CONFIG_ID,
 			NT_FW_CONFIG_ID,
-#if defined(SPD_tspd) || defined(SPD_spmd)
-			/* tos_fw_config is only present for TSPD/SPMD */
 			TOS_FW_CONFIG_ID
-#endif
 	};
 
 	const struct dyn_cfg_dtb_info_t *dtb_info;
diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c
index ed7f1f5..ebf6dff 100644
--- a/plat/arm/common/arm_image_load.c
+++ b/plat/arm/common/arm_image_load.c
@@ -38,38 +38,36 @@
  ******************************************************************************/
 static void plat_add_sp_images_load_info(struct bl_load_info *load_info)
 {
-	bl_load_info_node_t *node_info = load_info->head;
-	unsigned int index = 0;
+	bl_load_info_node_t *curr_node = load_info->head;
+	bl_load_info_node_t *prev_node;
 
-	if (sp_mem_params_descs[index].image_id == 0) {
+	/* Shortcut for empty SP list */
+	if (sp_mem_params_descs[0].image_id == 0) {
 		ERROR("No Secure Partition Image available\n");
 		return;
 	}
 
 	/* Traverse through the bl images list */
 	do {
-		node_info = node_info->next_load_info;
-	} while (node_info->next_load_info != NULL);
+		curr_node = curr_node->next_load_info;
+	} while (curr_node->next_load_info != NULL);
 
-	for (; index < MAX_SP_IDS; index++) {
-		/* Populate the image information */
-		node_info->image_id = sp_mem_params_descs[index].image_id;
-		node_info->image_info = &sp_mem_params_descs[index].image_info;
-
-		if ((index + 1U) == MAX_SP_IDS) {
-			INFO("Reached Max number of SPs\n");
-			return;
-		}
+	prev_node = curr_node;
 
-		if (sp_mem_params_descs[index + 1U].image_id == 0) {
+	for (unsigned int index = 0; index < MAX_SP_IDS; index++) {
+		if (sp_mem_params_descs[index].image_id == 0) {
 			return;
 		}
-
-		node_info->next_load_info =
-			&sp_mem_params_descs[index + 1U].load_node_mem;
-		node_info = node_info->next_load_info;
+		curr_node = &sp_mem_params_descs[index].load_node_mem;
+		/* Populate the image information */
+		curr_node->image_id = sp_mem_params_descs[index].image_id;
+		curr_node->image_info = &sp_mem_params_descs[index].image_info;
 
+		prev_node->next_load_info = curr_node;
+		prev_node = curr_node;
 	}
+
+	INFO("Reached Max number of SPs\n");
 }
 #endif
 
diff --git a/plat/arm/common/arm_io_storage.c b/plat/arm/common/arm_io_storage.c
index 34b4101..c5d913e 100644
--- a/plat/arm/common/arm_io_storage.c
+++ b/plat/arm/common/arm_io_storage.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #include <drivers/io/io_fip.h>
 #include <drivers/io/io_memmap.h>
 #include <drivers/io/io_storage.h>
+#include <drivers/partition/partition.h>
 #include <lib/utils.h>
 
 #include <plat/arm/common/arm_fconf_getter.h>
@@ -136,3 +137,40 @@
 {
 	return (io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID) == 0);
 }
+
+#if ARM_GPT_SUPPORT
+/**********************************************************************
+ * arm_set_image_source: Set image specification in IO policy
+ *
+ * @image_id: id of the image whose specification to be set
+ *
+ * @part_name: name of the partition that to be read for entry details
+ *
+ * set the entry and offset details of partition in global IO policy
+ * of the image
+ *********************************************************************/
+int arm_set_image_source(unsigned int image_id, const char *part_name)
+{
+	const partition_entry_t *entry = get_partition_entry(part_name);
+
+	if (entry == NULL) {
+		ERROR("Unable to find the %s partition\n", part_name);
+		return -ENOENT;
+	}
+
+	const struct plat_io_policy *policy = FCONF_GET_PROPERTY(arm,
+								 io_policies,
+								 image_id);
+
+	assert(policy != NULL);
+	assert(policy->image_spec != 0UL);
+
+	/* set offset and length of the image */
+	io_block_spec_t *image_spec = (io_block_spec_t *)policy->image_spec;
+
+	image_spec->offset = PLAT_ARM_FLASH_IMAGE_BASE + entry->start;
+	image_spec->length = entry->length;
+
+	return 0;
+}
+#endif
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index 9f5d455..6456c78 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 
 #include <common/debug.h>
 #include <common/runtime_svc.h>
+#include <drivers/arm/ethosn.h>
 #include <lib/debugfs.h>
 #include <lib/pmf/pmf.h>
 #include <plat/arm/common/arm_sip_svc.h>
@@ -50,6 +51,8 @@
 {
 	int call_count = 0;
 
+#if ENABLE_PMF
+
 	/*
 	 * Dispatch PMF calls to PMF SMC handler and return its return
 	 * value
@@ -59,6 +62,8 @@
 				handle, flags);
 	}
 
+#endif /* ENABLE_PMF */
+
 #if USE_DEBUGFS
 
 	if (is_debugfs_fid(smc_fid)) {
@@ -68,6 +73,15 @@
 
 #endif /* USE_DEBUGFS */
 
+#if ARM_ETHOSN_NPU_DRIVER
+
+	if (is_ethosn_fid(smc_fid)) {
+		return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+					  handle, flags);
+	}
+
+#endif /* ARM_ETHOSN_NPU_DRIVER */
+
 	switch (smc_fid) {
 	case ARM_SIP_SVC_EXE_STATE_SWITCH: {
 		/* Execution state can be switched only if EL3 is AArch64 */
@@ -92,6 +106,11 @@
 		/* PMF calls */
 		call_count += PMF_NUM_SMC_CALLS;
 
+#if ARM_ETHOSN_NPU_DRIVER
+		/* ETHOSN calls */
+		call_count += ETHOSN_NUM_SMC_CALLS;
+#endif /* ARM_ETHOSN_NPU_DRIVER */
+
 		/* State switch call */
 		call_count += 1;
 
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 48286c2..8e4469f 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #include <common/debug.h>
 #include <common/fdt_wrappers.h>
 #include <drivers/io/io_storage.h>
+#include <drivers/partition/partition.h>
 #include <lib/object_pool.h>
 #include <libfdt.h>
 #include <tools_share/firmware_image_package.h>
@@ -17,11 +18,35 @@
 #include <plat/arm/common/arm_fconf_io_storage.h>
 #include <platform_def.h>
 
-const io_block_spec_t fip_block_spec = {
-	.offset = PLAT_ARM_FIP_BASE,
-	.length = PLAT_ARM_FIP_MAX_SIZE
+io_block_spec_t fip_block_spec = {
+/*
+ * This is fixed FIP address used by BL1, BL2 loads partition table
+ * to get FIP address.
+ */
+#if ARM_GPT_SUPPORT
+	.offset = PLAT_ARM_FLASH_IMAGE_BASE + PLAT_ARM_FIP_OFFSET_IN_GPT,
+#else
+	.offset = PLAT_ARM_FLASH_IMAGE_BASE,
+#endif /* ARM_GPT_SUPPORT */
+	.length = PLAT_ARM_FLASH_IMAGE_MAX_SIZE
 };
 
+#if ARM_GPT_SUPPORT
+static const io_block_spec_t gpt_spec = {
+	.offset         = PLAT_ARM_FLASH_IMAGE_BASE,
+	/*
+	 * PLAT_PARTITION_BLOCK_SIZE = 512
+	 * PLAT_PARTITION_MAX_ENTRIES = 128
+	 * each sector has 4 partition entries, and there are
+	 * 2 reserved sectors i.e. protective MBR and primary
+	 * GPT header hence length gets calculated as,
+	 * length = 512 * (128/4 + 2)
+	 */
+	.length         = PLAT_PARTITION_BLOCK_SIZE *
+			  (PLAT_PARTITION_MAX_ENTRIES / 4 + 2),
+};
+#endif /* ARM_GPT_SUPPORT */
+
 const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = {
 	[BL2_IMAGE_ID] = {UUID_TRUSTED_BOOT_FIRMWARE_BL2},
 	[TB_FW_CONFIG_ID] = {UUID_TB_FW_CONFIG},
@@ -60,6 +85,13 @@
 
 /* By default, ARM platforms load images from the FIP */
 struct plat_io_policy policies[MAX_NUMBER_IDS] = {
+#if ARM_GPT_SUPPORT
+	[GPT_IMAGE_ID] = {
+		&memmap_dev_handle,
+		(uintptr_t)&gpt_spec,
+		open_memmap
+	},
+#endif /* ARM_GPT_SUPPORT */
 	[FIP_IMAGE_ID] = {
 		&memmap_dev_handle,
 		(uintptr_t)&fip_block_spec,
@@ -249,7 +281,6 @@
 {
 	int err, node;
 	unsigned int i;
-	unsigned int j;
 
 	union uuid_helper_t uuid_helper;
 	io_uuid_spec_t *uuid_ptr;
@@ -268,26 +299,26 @@
 	/* Locate the uuid cells and read the value for all the load info uuid */
 	for (i = 0; i < FCONF_ARM_IO_UUID_NUMBER; i++) {
 		uuid_ptr = pool_alloc(&fconf_arm_uuids_pool);
-		err = fdt_read_uint32_array(dtb, node, load_info[i].name,
-					    4, uuid_helper.word);
+		err = fdtw_read_uuid(dtb, node, load_info[i].name, 16,
+				     (uint8_t *)&uuid_helper);
 		if (err < 0) {
 			WARN("FCONF: Read cell failed for %s\n", load_info[i].name);
 			return err;
 		}
 
-		/* Convert uuid from big endian to little endian */
-		for (j = 0U; j < 4U; j++) {
-			uuid_helper.word[j] =
-				((uuid_helper.word[j] >> 24U) & 0xff) |
-				((uuid_helper.word[j] << 8U) & 0xff0000) |
-				((uuid_helper.word[j] >> 8U) & 0xff00) |
-				((uuid_helper.word[j] << 24U) & 0xff000000);
-		}
-
-		VERBOSE("FCONF: arm-io_policies.%s cell found with value = 0x%x 0x%x 0x%x 0x%x\n",
+		VERBOSE("FCONF: arm-io_policies.%s cell found with value = "
+			"%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x\n",
 			load_info[i].name,
-			uuid_helper.word[0], uuid_helper.word[1],
-			uuid_helper.word[2], uuid_helper.word[3]);
+			uuid_helper.uuid_struct.time_low[0], uuid_helper.uuid_struct.time_low[1],
+			uuid_helper.uuid_struct.time_low[2], uuid_helper.uuid_struct.time_low[3],
+			uuid_helper.uuid_struct.time_mid[0], uuid_helper.uuid_struct.time_mid[1],
+			uuid_helper.uuid_struct.time_hi_and_version[0],
+			uuid_helper.uuid_struct.time_hi_and_version[1],
+			uuid_helper.uuid_struct.clock_seq_hi_and_reserved,
+			uuid_helper.uuid_struct.clock_seq_low,
+			uuid_helper.uuid_struct.node[0], uuid_helper.uuid_struct.node[1],
+			uuid_helper.uuid_struct.node[2], uuid_helper.uuid_struct.node[3],
+			uuid_helper.uuid_struct.node[4], uuid_helper.uuid_struct.node[5]);
 
 		uuid_ptr->uuid = uuid_helper.uuid_struct;
 		policies[load_info[i].image_id].image_spec = (uintptr_t)uuid_ptr;
diff --git a/plat/arm/common/fconf/arm_fconf_sp.c b/plat/arm/common/fconf/arm_fconf_sp.c
index 7950e7f..552393c 100644
--- a/plat/arm/common/fconf/arm_fconf_sp.c
+++ b/plat/arm/common/fconf/arm_fconf_sp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -37,7 +37,6 @@
 	const unsigned int plat_start = SP_PKG5_ID;
 	unsigned int plat_index = plat_start;
 	const unsigned int plat_end = plat_start + MAX_SP_IDS / 2;
-	unsigned int j;
 
 	/* As libfdt use void *, we can't avoid this cast */
 	const void *dtb = (void *)config;
@@ -59,29 +58,28 @@
 		}
 
 		/* Read UUID */
-		err = fdt_read_uint32_array(dtb, sp_node, "uuid", 4,
-					    uuid_helper.word);
+		err = fdtw_read_uuid(dtb, sp_node, "uuid", 16,
+				     (uint8_t *)&uuid_helper);
 		if (err < 0) {
 			ERROR("FCONF: cannot read SP uuid\n");
 			return -1;
 		}
 
-		/* Convert uuid from big endian to little endian */
-		for (j = 0U; j < 4U; j++) {
-			uuid_helper.word[j] =
-				((uuid_helper.word[j] >> 24U) & 0xff) |
-				((uuid_helper.word[j] << 8U) & 0xff0000) |
-				((uuid_helper.word[j] >> 8U) & 0xff00) |
-				((uuid_helper.word[j] << 24U) & 0xff000000);
-		}
-
 		arm_sp.uuids[index] = uuid_helper;
-		VERBOSE("FCONF: %s UUID %x-%x-%x-%x load_addr=%lx\n",
+		VERBOSE("FCONF: %s UUID"
+			" %02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x"
+			" load_addr=%lx\n",
 			__func__,
-			uuid_helper.word[0],
-			uuid_helper.word[1],
-			uuid_helper.word[2],
-			uuid_helper.word[3],
+			uuid_helper.uuid_struct.time_low[0], uuid_helper.uuid_struct.time_low[1],
+			uuid_helper.uuid_struct.time_low[2], uuid_helper.uuid_struct.time_low[3],
+			uuid_helper.uuid_struct.time_mid[0], uuid_helper.uuid_struct.time_mid[1],
+			uuid_helper.uuid_struct.time_hi_and_version[0],
+			uuid_helper.uuid_struct.time_hi_and_version[1],
+			uuid_helper.uuid_struct.clock_seq_hi_and_reserved,
+			uuid_helper.uuid_struct.clock_seq_low,
+			uuid_helper.uuid_struct.node[0], uuid_helper.uuid_struct.node[1],
+			uuid_helper.uuid_struct.node[2], uuid_helper.uuid_struct.node[3],
+			uuid_helper.uuid_struct.node[4], uuid_helper.uuid_struct.node[5],
 			arm_sp.load_addr[index]);
 
 		/* Read Load address */
diff --git a/plat/arm/common/fconf/fconf_ethosn_getter.c b/plat/arm/common/fconf/fconf_ethosn_getter.c
new file mode 100644
index 0000000..1ba9f3a
--- /dev/null
+++ b/plat/arm/common/fconf/fconf_ethosn_getter.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
+#include <libfdt.h>
+#include <plat/arm/common/fconf_ethosn_getter.h>
+
+struct ethosn_config_t ethosn_config;
+
+static uint8_t fdt_node_get_status(const void *fdt, int node)
+{
+	int len;
+	uint8_t status = ETHOSN_STATUS_DISABLED;
+	const char *node_status;
+
+	node_status = fdt_getprop(fdt, node, "status", &len);
+	if (node_status == NULL ||
+	    (len == 5 && /* Includes null character */
+	     strncmp(node_status, "okay", 4U) == 0)) {
+		status = ETHOSN_STATUS_ENABLED;
+	}
+
+	return status;
+}
+
+int fconf_populate_ethosn_config(uintptr_t config)
+{
+	int ethosn_node;
+	int sub_node;
+	uint8_t ethosn_status;
+	uint32_t core_count = 0U;
+	uint32_t core_addr_idx = 0U;
+	const void *hw_conf_dtb = (const void *)config;
+
+	/* Find offset to node with 'ethosn' compatible property */
+	ethosn_node = fdt_node_offset_by_compatible(hw_conf_dtb, -1, "ethosn");
+	if (ethosn_node < 0) {
+		ERROR("FCONF: Can't find 'ethosn' compatible node in dtb\n");
+		return ethosn_node;
+	}
+
+	/* If the Arm Ethos-N NPU is disabled the core check can be skipped */
+	ethosn_status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
+	if (ethosn_status == ETHOSN_STATUS_DISABLED) {
+		return 0;
+	}
+
+	fdt_for_each_subnode(sub_node, hw_conf_dtb, ethosn_node) {
+		int err;
+		uintptr_t addr;
+		uint8_t status;
+
+		/* Check that the sub node is "ethosn-core" compatible */
+		if (fdt_node_check_compatible(hw_conf_dtb, sub_node,
+					      "ethosn-core") != 0) {
+			/* Ignore incompatible sub node */
+			continue;
+		}
+
+		/* Including disabled cores */
+		if (core_addr_idx >= ETHOSN_CORE_NUM_MAX) {
+			ERROR("FCONF: Reached max number of Arm Ethos-N NPU cores\n");
+			return -1;
+		}
+
+		status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
+		if (status == ETHOSN_STATUS_DISABLED) {
+			++core_addr_idx;
+			continue;
+		}
+
+		err = fdt_get_reg_props_by_index(hw_conf_dtb, ethosn_node,
+						 core_addr_idx, &addr, NULL);
+		if (err < 0) {
+			ERROR("FCONF: Failed to read reg property for Arm Ethos-N NPU core %u\n",
+			      core_addr_idx);
+			return err;
+		}
+
+		ethosn_config.core_addr[core_count++] = addr;
+		++core_addr_idx;
+	}
+
+	if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) {
+		ERROR("FCONF: Failed to parse sub nodes\n");
+		return sub_node;
+	}
+
+	/* The Arm Ethos-N NPU can't be used if no cores were found */
+	if (core_count == 0) {
+		ERROR("FCONF: No Arm Ethos-N NPU cores found\n");
+		return -1;
+	}
+
+	ethosn_config.num_cores = core_count;
+	ethosn_config.status = ethosn_status;
+
+	return 0;
+}
+
+FCONF_REGISTER_POPULATOR(HW_CONFIG, ethosn_config, fconf_populate_ethosn_config);
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index 270093c..f15c137 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -32,7 +32,9 @@
  * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
  * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
  */
+#if !RESET_TO_SP_MIN
 CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
+#endif
 
 /*******************************************************************************
  * Return a pointer to the 'entry_point_info' structure of the next image for the
diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
index 103dd9a..bebc597 100644
--- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
+++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
@@ -184,8 +184,18 @@
 #define MAX_IO_HANDLES			U(4)
 
 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#if ARM_GPT_SUPPORT
+/*
+ * Offset of the FIP in the GPT image. BL1 component uses this option
+ * as it does not load the partition table to get the FIP base
+ * address. At sector 34 by default (i.e. after reserved sectors 0-33)
+ * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
+ */
+#define PLAT_ARM_FIP_OFFSET_IN_GPT		0x4400
+#endif /* ARM_GPT_SUPPORT */
 
 #define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
 #define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h
index ecf6d93..0062b97 100644
--- a/plat/arm/css/sgi/include/sgi_variant.h
+++ b/plat/arm/css/sgi/include/sgi_variant.h
@@ -20,6 +20,9 @@
 /* SID Version values for RD-N2 */
 #define RD_N2_SID_VER_PART_NUM			0x07B7
 
+/* SID Version values for RD-N2 variants */
+#define RD_N2_CFG1_SID_VER_PART_NUM		0x07B6
+
 /* Structure containing SGI platform variant information */
 typedef struct sgi_platform_info {
 	unsigned int platform_id;	/* Part Number of the platform */
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 615f53d..8baf4ee 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -18,6 +18,8 @@
 
 CSS_SGI_CHIP_COUNT		:=	1
 
+CSS_SGI_PLATFORM_VARIANT	:=	0
+
 INTERCONNECT_SOURCES	:=	${CSS_ENT_BASE}/sgi_interconnect.c
 
 PLAT_INCLUDES		+=	-I${CSS_ENT_BASE}/include
@@ -57,10 +59,14 @@
 
 $(eval $(call add_define,CSS_SGI_CHIP_COUNT))
 
+$(eval $(call add_define,CSS_SGI_PLATFORM_VARIANT))
+
 override CSS_LOAD_SCP_IMAGES	:=	0
 override NEED_BL2U		:=	no
 override ARM_BL31_IN_DRAM	:=	1
 override ARM_PLAT_MT		:=	1
+override PSCI_EXTENDED_STATE_ID	:=	1
+override ARM_RECOM_STATE_ID_ENC	:=	1
 
 # System coherency is managed in hardware
 HW_ASSISTED_COHERENCY	:=	1
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index e8238ba..541689b 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -75,7 +75,8 @@
 {
 	if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
 		sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
-		sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM) {
+		sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
+		sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
 		if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
 			panic();
 		return &plat_rd_scmi_info[channel_id];
diff --git a/plat/brcm/board/common/board_common.mk b/plat/brcm/board/common/board_common.mk
index 2945749..3b3e92d 100644
--- a/plat/brcm/board/common/board_common.mk
+++ b/plat/brcm/board/common/board_common.mk
@@ -118,7 +118,8 @@
 
 PLAT_INCLUDES		+=	-Iplat/brcm/board/common \
 				-Iinclude/drivers/brcm \
-				-Iinclude/drivers/brcm/emmc
+				-Iinclude/drivers/brcm/emmc \
+				-Iinclude/drivers/brcm/mdio
 
 PLAT_BL_COMMON_SOURCES	+=	plat/brcm/common/brcm_common.c \
 				plat/brcm/board/common/cmn_sec.c \
diff --git a/plat/brcm/board/stingray/driver/sr_usb.h b/plat/brcm/board/stingray/driver/sr_usb.h
new file mode 100644
index 0000000..5033683
--- /dev/null
+++ b/plat/brcm/board/stingray/driver/sr_usb.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2019 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SR_USB_H
+#define SR_USB_H
+
+#define CDRU_PM_RESET_N_R	BIT(CDRU_MISC_RESET_CONTROL__CDRU_PM_RESET_N_R)
+#define CDRU_USBSS_RESET_N	BIT(CDRU_MISC_RESET_CONTROL__CDRU_USBSS_RESET_N)
+#define CDRU_MISC_CLK_USBSS \
+			BIT(CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_USBSS_CLK_EN_R)
+
+#define RESCAL_I_RSTB			BIT(26)
+#define RESCAL_I_PWRDNB			BIT(27)
+
+#define DRDU3_U3PHY_CTRL		0x68500014
+#define	PHY_RESET			BIT(1)
+#define	POR_RESET			BIT(28)
+#define	MDIO_RESET			BIT(29)
+
+#define DRDU3_PWR_CTRL			0x6850002c
+#define POWER_CTRL_OVRD			BIT(2)
+
+#define USB3H_U3PHY_CTRL		0x68510014
+#define USB3H_U3SOFT_RST_N		BIT(30)
+
+#define USB3H_PWR_CTRL			0x68510028
+
+#define USB3_PHY_MDIO_BLOCK_BASE_REG	0x1f
+#define BDC_AXI_SOFT_RST_N_OFFSET	0
+#define XHC_AXI_SOFT_RST_N_OFFSET	1
+#define MDIO_BUS_ID			3
+#define USB3H_PHY_ID			5
+#define USB3DRD_PHY_ID			2
+
+#define USB3_PHY_RXPMD_BLOCK_BASE	0x8020
+#define USB3_PHY_RXPMD_REG1		0x1
+#define USB3_PHY_RXPMD_REG2		0x2
+#define USB3_PHY_RXPMD_REG5		0x5
+#define USB3_PHY_RXPMD_REG7		0x7
+
+#define USB3_PHY_TXPMD_BLOCK_BASE	0x8040
+#define USB3_PHY_TXPMD_REG1		0x1
+#define USB3_PHY_TXPMD_REG2		0x2
+
+#define USB3_PHY_ANA_BLOCK_BASE		0x8090
+#define USB3_PHY_ANA_REG0		0x0
+#define USB3_PHY_ANA_REG1		0x1
+#define USB3_PHY_ANA_REG2		0x2
+#define USB3_PHY_ANA_REG5		0x5
+#define USB3_PHY_ANA_REG8		0x8
+#define USB3_PHY_ANA_REG11		0xb
+
+#define USB3_PHY_AEQ_BLOCK_BASE		0x80e0
+#define USB3_PHY_AEQ_REG1		0x1
+#define USB3_PHY_AEQ_REG3		0x3
+
+#ifdef USB_DMA_COHERENT
+#define DRDU3_U3XHC_SOFT_RST_N		BIT(31)
+#define DRDU3_U3BDC_SOFT_RST_N		BIT(30)
+
+#define DRDU3_SOFT_RESET_CTRL		0x68500030
+#define DRDU3_XHC_AXI_SOFT_RST_N	BIT(1)
+#define DRDU3_BDC_AXI_SOFT_RST_N	BIT(0)
+
+#define DRDU2_PHY_CTRL			0x6852000c
+#define DRDU2_U2SOFT_RST_N		BIT(29)
+
+#define USB3H_SOFT_RESET_CTRL		0x6851002c
+#define USB3H_XHC_AXI_SOFT_RST_N	BIT(1)
+
+#define DRDU2_SOFT_RESET_CTRL		0x68520020
+#define DRDU2_BDC_AXI_SOFT_RST_N	BIT(0)
+
+#define DRD2U3H_XHC_REGS_AXIWRA		0x68511c08
+#define DRD2U3H_XHC_REGS_AXIRDA		0x68511c0c
+#define DRDU2D_BDC_REGS_AXIWRA		0x68521c08
+#define DRDU2D_BDC_REGS_AXIRDA		0x68521c0c
+#define DRDU3H_XHC_REGS_AXIWRA		0x68501c08
+#define DRDU3H_XHC_REGS_AXIRDA		0x68501c0c
+#define DRDU3D_BDC_REGS_AXIWRA		0x68502c08
+#define DRDU3D_BDC_REGS_AXIRDA		0x68502c0c
+/* cacheable write-back, allocate on both reads and writes */
+#define USBAXI_AWCACHE		0xf
+#define USBAXI_ARCACHE		0xf
+/* non-secure */
+#define USBAXI_AWPROT		0x8
+#define USBAXI_ARPROT		0x8
+#define USBAXIWR_SA_VAL		((USBAXI_AWCACHE << 4 | USBAXI_AWPROT) << 0)
+#define USBAXIWR_SA_MASK	((0xf << 4 | 0xf) << 0)
+#define USBAXIWR_UA_VAL		((USBAXI_AWCACHE << 4 | USBAXI_AWPROT) << 16)
+#define USBAXIWR_UA_MASK	((0xf << 4 | 0xf) << 0)
+#define USBAXIRD_SA_VAL		((USBAXI_ARCACHE << 4 | USBAXI_ARPROT) << 0)
+#define USBAXIRD_SA_MASK	((0xf << 4 | 0xf) << 0)
+#define USBAXIRD_UA_VAL		((USBAXI_ARCACHE << 4 | USBAXI_ARPROT) << 16)
+#define USBAXIRD_UA_MASK	((0xf << 4 | 0xf) << 0)
+#endif /* USB_DMA_COHERENT */
+
+#define ICFG_DRDU3_SID_CTRL		0x6850001c
+#define ICFG_USB3H_SID_CTRL		0x6851001c
+#define ICFG_DRDU2_SID_CTRL		0x68520010
+#define ICFG_USB_SID_SHIFT		5
+#define ICFG_USB_SID_AWADDR_OFFSET	0x0
+#define ICFG_USB_SID_ARADDR_OFFSET	0x4
+
+#define USBIC_GPV_BASE			0x68600000
+#define USBIC_GPV_SECURITY0		(USBIC_GPV_BASE + 0x8)
+#define USBIC_GPV_SECURITY0_FIELD	BIT(0)
+#define USBIC_GPV_SECURITY1		(USBIC_GPV_BASE + 0xc)
+#define USBIC_GPV_SECURITY1_FIELD	(BIT(0) | BIT(1))
+#define USBIC_GPV_SECURITY2		(USBIC_GPV_BASE + 0x10)
+#define USBIC_GPV_SECURITY2_FIELD	(BIT(0) | BIT(1))
+#define USBIC_GPV_SECURITY4		(USBIC_GPV_BASE + 0x18)
+#define USBIC_GPV_SECURITY4_FIELD	BIT(0)
+#define USBIC_GPV_SECURITY10		(USBIC_GPV_BASE + 0x30)
+#define USBIC_GPV_SECURITY10_FIELD	(0x7 << 0)
+
+#define USBSS_TZPCDECPROT_BASE		0x68540800
+#define USBSS_TZPCDECPROT0set		(USBSS_TZPCDECPROT_BASE + 0x4)
+#define USBSS_TZPCDECPROT0clr		(USBSS_TZPCDECPROT_BASE + 0x8)
+#define DECPROT0_USBSS_DRD2U3H		BIT(3)
+#define DECPROT0_USBSS_DRDU2H		BIT(2)
+#define DECPROT0_USBSS_DRDU3D		BIT(1)
+#define DECPROT0_USBSS_DRDU2D		BIT(0)
+#define USBSS_TZPCDECPROT0 \
+		(DECPROT0_USBSS_DRD2U3H | \
+		DECPROT0_USBSS_DRDU2H |   \
+		DECPROT0_USBSS_DRDU3D |   \
+		DECPROT0_USBSS_DRDU2D)
+
+int32_t usb_device_init(unsigned int);
+
+#endif /* SR_USB_H */
diff --git a/plat/brcm/board/stingray/driver/usb.c b/plat/brcm/board/stingray/driver/usb.c
new file mode 100644
index 0000000..4a84141
--- /dev/null
+++ b/plat/brcm/board/stingray/driver/usb.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2019 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mdio.h>
+#include <platform_usb.h>
+#include <sr_utils.h>
+#include "sr_usb.h"
+#include <usbh_xhci_regs.h>
+
+static uint32_t usb_func = USB3_DRD | USB3H_USB2DRD;
+
+static void usb_pm_rescal_init(void)
+{
+	uint32_t data;
+	uint32_t try;
+
+	mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_PM_RESET_N_R);
+	/* release reset */
+	mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, RESCAL_I_RSTB);
+	udelay(10U);
+	/* power up */
+	mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0,
+			RESCAL_I_RSTB | RESCAL_I_PWRDNB);
+	try = 1000U;
+	do {
+		udelay(1U);
+		data = mmio_read_32(CDRU_CHIP_TOP_SPARE_REG1);
+		try--;
+	} while ((data & RESCAL_I_PWRDNB) == 0x0U && (try != 0U));
+
+	if (try == 0U) {
+		ERROR("CDRU_CHIP_TOP_SPARE_REG1: 0x%x\n", data);
+	}
+
+	INFO("USB and PM Rescal Init done..\n");
+}
+
+const unsigned int xhc_portsc_reg_offset[MAX_USB_PORTS] = {
+	XHC_PORTSC1_OFFSET,
+	XHC_PORTSC2_OFFSET,
+	XHC_PORTSC3_OFFSET,
+};
+
+static void usb3h_usb2drd_init(void)
+{
+	uint32_t val;
+
+	INFO("USB3H + USB 2DRD init\n");
+	mmio_clrbits_32(USB3H_U3PHY_CTRL, POR_RESET);
+	val = mmio_read_32(USB3H_PWR_CTRL);
+	val &= ~(0x3U << POWER_CTRL_OVRD);
+	val |= (1U << POWER_CTRL_OVRD);
+	mmio_write_32(USB3H_PWR_CTRL, val);
+	mmio_setbits_32(USB3H_U3PHY_CTRL, PHY_RESET);
+	/* Phy to come out of reset */
+	udelay(2U);
+	mmio_clrbits_32(USB3H_U3PHY_CTRL, MDIO_RESET);
+
+	/* MDIO in reset */
+	udelay(2U);
+	mmio_setbits_32(USB3H_U3PHY_CTRL, MDIO_RESET);
+
+	/* After MDIO reset release */
+	udelay(2U);
+
+	/* USB 3.0 phy Analog Block Initialization */
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+			USB3_PHY_ANA_BLOCK_BASE);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG0, 0x4646U);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG1, 0x80c9U);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG2, 0x88a6U);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG5, 0x7c12U);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG8, 0x1d07U);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG11, 0x25cU);
+
+	/* USB 3.0 phy RXPMD Block initialization*/
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+			USB3_PHY_RXPMD_BLOCK_BASE);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG1, 0x4052U);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG2, 0x4cU);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG5, 0x7U);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG7, 0x173U);
+
+	/* USB 3.0 phy AEQ Block initialization*/
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+			USB3_PHY_AEQ_BLOCK_BASE);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_AEQ_REG1, 0x3000U);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_AEQ_REG3, 0x2c70U);
+
+	/* USB 3.0 phy TXPMD Block initialization*/
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+			USB3_PHY_TXPMD_BLOCK_BASE);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_TXPMD_REG1, 0x100fU);
+	mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_TXPMD_REG2, 0x238cU);
+}
+
+static void usb3drd_init(void)
+{
+	uint32_t val;
+
+	INFO("USB3DRD init\n");
+	mmio_clrbits_32(DRDU3_U3PHY_CTRL, POR_RESET);
+	val = mmio_read_32(DRDU3_PWR_CTRL);
+	val &= ~(0x3U << POWER_CTRL_OVRD);
+	val |= (1U << POWER_CTRL_OVRD);
+	mmio_write_32(DRDU3_PWR_CTRL, val);
+	mmio_setbits_32(DRDU3_U3PHY_CTRL, PHY_RESET);
+	/* Phy to come out of reset */
+	udelay(2U);
+	mmio_clrbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET);
+
+	/* MDIO in reset */
+	udelay(2U);
+	mmio_setbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET);
+
+	/* After MDIO reset release */
+	udelay(2U);
+
+	/* USB 3.0 DRD phy Analog Block Initialization */
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+			USB3_PHY_ANA_BLOCK_BASE);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG0, 0x4646U);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG1, 0x80c9U);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG2, 0x88a6U);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG5, 0x7c12U);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG8, 0x1d07U);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG11, 0x25cU);
+
+	/* USB 3.0 DRD phy RXPMD Block initialization*/
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+			USB3_PHY_RXPMD_BLOCK_BASE);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG1, 0x4052U);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG2, 0x4cU);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG5, 0x7U);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG7, 0x173U);
+
+	/* USB 3.0 DRD phy AEQ Block initialization*/
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+			USB3_PHY_AEQ_BLOCK_BASE);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_AEQ_REG1, 0x3000U);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_AEQ_REG3, 0x2c70U);
+
+	/* USB 3.0 DRD phy TXPMD Block initialization*/
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+			USB3_PHY_TXPMD_BLOCK_BASE);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_TXPMD_REG1, 0x100fU);
+	mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_TXPMD_REG2, 0x238cU);
+}
+
+static void usb3_phy_init(void)
+{
+	usb_pm_rescal_init();
+
+	if ((usb_func & USB3H_USB2DRD) != 0U) {
+		usb3h_usb2drd_init();
+	}
+
+	if ((usb_func & USB3_DRD) != 0U) {
+		usb3drd_init();
+	}
+}
+
+#ifdef USB_DMA_COHERENT
+void usb_enable_coherence(void)
+{
+	if (usb_func & USB3H_USB2DRD) {
+		mmio_setbits_32(USB3H_SOFT_RESET_CTRL,
+				USB3H_XHC_AXI_SOFT_RST_N);
+		mmio_setbits_32(DRDU2_SOFT_RESET_CTRL,
+				DRDU2_BDC_AXI_SOFT_RST_N);
+		mmio_setbits_32(USB3H_U3PHY_CTRL, USB3H_U3SOFT_RST_N);
+		mmio_setbits_32(DRDU2_PHY_CTRL, DRDU2_U2SOFT_RST_N);
+
+		mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIWRA,
+				   (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+				   (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+
+		mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIRDA,
+				   (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+				   (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+		mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIWRA,
+				   (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+				   (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+
+		mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIRDA,
+				   (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+				   (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+	}
+
+	if (usb_func & USB3_DRD) {
+		mmio_setbits_32(DRDU3_SOFT_RESET_CTRL,
+				(DRDU3_XHC_AXI_SOFT_RST_N |
+				DRDU3_BDC_AXI_SOFT_RST_N));
+		mmio_setbits_32(DRDU3_U3PHY_CTRL,
+				(DRDU3_U3XHC_SOFT_RST_N |
+				DRDU3_U3BDC_SOFT_RST_N));
+
+		mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIWRA,
+				   (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+				   (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+
+		mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIRDA,
+				   (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+				   (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+		mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIWRA,
+				   (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+				   (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+
+		mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIRDA,
+				   (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+				   (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+	}
+}
+#endif
+
+void xhci_phy_init(void)
+{
+	uint32_t val;
+
+	INFO("usb init start\n");
+	mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL,
+			CDRU_MISC_CLK_USBSS);
+
+	mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_USBSS_RESET_N);
+
+	if (usb_func & USB3_DRD) {
+		VERBOSE(" - configure stream_id = 0x6800 for DRDU3\n");
+		val = SR_SID_VAL(0x3U, 0x1U, 0x0U) << ICFG_USB_SID_SHIFT;
+		mmio_write_32(ICFG_DRDU3_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET,
+				val);
+		mmio_write_32(ICFG_DRDU3_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET,
+				val);
+
+		/*
+		 * DRDU3 Device USB Space, DRDU3 Host USB Space,
+		 * DRDU3 SS Config
+		 */
+		mmio_setbits_32(USBIC_GPV_SECURITY10,
+				USBIC_GPV_SECURITY10_FIELD);
+	}
+
+	if (usb_func & USB3H_USB2DRD) {
+		VERBOSE(" - configure stream_id = 0x6801 for USB3H\n");
+		val = SR_SID_VAL(0x3U, 0x1U, 0x1U) << ICFG_USB_SID_SHIFT;
+		mmio_write_32(ICFG_USB3H_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET,
+				val);
+		mmio_write_32(ICFG_USB3H_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET,
+				val);
+
+		VERBOSE(" - configure stream_id = 0x6802 for DRDU2\n");
+		val = SR_SID_VAL(0x3U, 0x1U, 0x2U) << ICFG_USB_SID_SHIFT;
+		mmio_write_32(ICFG_DRDU2_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET,
+				val);
+		mmio_write_32(ICFG_DRDU2_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET,
+				val);
+
+		/* DRDU2 APB Bridge:DRDU2 USB Device, USB3H SS Config */
+		mmio_setbits_32(USBIC_GPV_SECURITY1, USBIC_GPV_SECURITY1_FIELD);
+
+		/*
+		 * USB3H APB Bridge:DRDU2 Host + USB3 Host USB Space,
+		 * USB3H SS Config
+		 */
+		mmio_setbits_32(USBIC_GPV_SECURITY2, USBIC_GPV_SECURITY2_FIELD);
+	}
+
+	/* Configure Host masters as non-Secure */
+	mmio_setbits_32(USBSS_TZPCDECPROT0set, USBSS_TZPCDECPROT0);
+
+	/* CCN Slave on USBIC */
+	mmio_setbits_32(USBIC_GPV_SECURITY0, USBIC_GPV_SECURITY0_FIELD);
+
+	/* SLAVE_8:IDM Register Space */
+	mmio_setbits_32(USBIC_GPV_SECURITY4, USBIC_GPV_SECURITY4_FIELD);
+
+	usb3_phy_init();
+#ifdef USB_DMA_COHERENT
+	usb_enable_coherence();
+#endif
+
+	usb_device_init(usb_func);
+
+	INFO("PLAT USB: init done.\n");
+}
diff --git a/plat/brcm/board/stingray/driver/usb_phy.c b/plat/brcm/board/stingray/driver/usb_phy.c
new file mode 100644
index 0000000..54c98e1
--- /dev/null
+++ b/plat/brcm/board/stingray/driver/usb_phy.c
@@ -0,0 +1,601 @@
+/*
+ * Copyright (c) 2019 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_usb.h>
+#include <usb_phy.h>
+
+#define USB_PHY_ALREADY_STARTED	(-2)
+#define USB_MAX_DEVICES		 2
+#define USB3H_USB2DRD_PHY	 0
+#define USB3_DRD_PHY		 1
+
+/* Common bit fields for all the USB2 phy */
+#define USB2_PHY_ISO		DRDU2_U2PHY_ISO
+#define USB2_AFE_PLL_PWRDWNB	DRDU2_U2AFE_PLL_PWRDWNB
+#define USB2_AFE_BG_PWRDWNB	DRDU2_U2AFE_BG_PWRDWNB
+#define USB2_AFE_LDO_PWRDWNB	DRDU2_U2AFE_LDO_PWRDWNB
+#define USB2_CTRL_CORERDY	DRDU2_U2CTRL_CORERDY
+
+#define USB2_PHY_PCTL_MASK	DRDU2_U2PHY_PCTL_MASK
+#define USB2_PHY_PCTL_OFFSET	DRDU2_U2PHY_PCTL_OFFSET
+#define USB2_PHY_PCTL_VAL	U2PHY_PCTL_VAL
+
+#define USB2_PLL_RESETB		DRDU2_U2PLL_RESETB
+#define USB2_PHY_RESETB		DRDU2_U2PHY_RESETB
+
+static usb_phy_port_t usb_phy_port[2U][MAX_NR_PORTS];
+
+static usb_phy_t usb_phy_info[2U] = {
+	{DRDU2_U2PLL_NDIV_FRAC, USB3H_PIPE_CTRL, 0U, USB3H_DRDU2_PHY},
+	{0U, 0U, DRDU3_PIPE_CTRL, DRDU3_PHY}
+};
+
+typedef struct {
+	void *pcd_id;
+} usb_platform_dev;
+
+/* index 0: USB3H + USB2 DRD, 1: USB3 DRD */
+static usb_platform_dev xhci_devices_configs[USB_MAX_DEVICES] = {
+	{&usb_phy_info[0U]},
+	{&usb_phy_info[1U]}
+};
+
+static int32_t pll_lock_check(uint32_t address, uint32_t bit)
+{
+	uint32_t retry;
+	uint32_t data;
+
+	retry = PLL_LOCK_RETRY_COUNT;
+	do {
+		data = mmio_read_32(address);
+		if ((data & bit) != 0U) {
+			return 0;
+		}
+		udelay(1);
+	} while (--retry != 0);
+
+	ERROR("%s(): FAIL (0x%08x)\n", __func__, address);
+	return -1;
+}
+
+/*
+ * USB2 PHY using external FSM bringup sequence
+ * Total #3 USB2 phys. All phys has the same
+ * bringup sequence. Register bit fields for
+ * some of the PHY's are different.
+ * Bit fields which are different are passed using
+ * struct u2_phy_ext_fsm with bit-fields and register addr.
+ */
+
+static void u2_phy_ext_fsm_power_on(struct u2_phy_ext_fsm *u2_phy)
+{
+	mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO);
+	/* Delay as per external FSM spec */
+	udelay(10U);
+
+	mmio_setbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq);
+	/* Delay as per external FSM spec */
+	udelay(10U);
+
+	mmio_clrbits_32(u2_phy->phy_ctrl_reg,
+			(USB2_AFE_BG_PWRDWNB |
+			 USB2_AFE_PLL_PWRDWNB |
+			 USB2_AFE_LDO_PWRDWNB |
+			 USB2_CTRL_CORERDY));
+
+	mmio_clrsetbits_32(u2_phy->phy_ctrl_reg,
+			   (USB2_PHY_PCTL_MASK << USB2_PHY_PCTL_OFFSET),
+			   (USB2_PHY_PCTL_VAL << USB2_PHY_PCTL_OFFSET));
+	/* Delay as per external FSM spec */
+	udelay(160U);
+
+	mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_CTRL_CORERDY);
+	/* Delay as per external FSM spec */
+	udelay(50U);
+
+	mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_BG_PWRDWNB);
+	/* Delay as per external FSM spec */
+	udelay(200U);
+
+	mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_onin);
+	mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_LDO_PWRDWNB);
+	/* Delay as per external FSM spec */
+	udelay(10U);
+
+	mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_okin);
+	/* Delay as per external FSM spec */
+	udelay(10U);
+
+	mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_PLL_PWRDWNB);
+	/* Delay as per external FSM spec */
+	udelay(10U);
+
+	mmio_clrbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO);
+	/* Delay as per external FSM spec */
+	udelay(10U);
+	mmio_clrbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq);
+	/* Delay as per external FSM spec */
+	udelay(1U);
+
+	mmio_setbits_32(u2_phy->pll_ctrl_reg, USB2_PLL_RESETB);
+	mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_RESETB);
+
+}
+
+static int32_t usb3h_u2_phy_power_on(uint32_t base)
+{
+	int32_t status;
+	struct u2_phy_ext_fsm u2_phy;
+
+	u2_phy.pll_ctrl_reg = base + USB3H_U2PLL_CTRL;
+	u2_phy.phy_ctrl_reg = base + USB3H_U2PHY_CTRL;
+	u2_phy.phy_iddq = USB3H_U2PHY_IDDQ;
+	u2_phy.pwr_ctrl_reg = base + USB3H_PWR_CTRL;
+	u2_phy.pwr_okin = USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN;
+	u2_phy.pwr_onin = USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN;
+
+	u2_phy_ext_fsm_power_on(&u2_phy);
+
+	status = pll_lock_check(base + USB3H_U2PLL_CTRL, USB3H_U2PLL_LOCK);
+	if (status != 0) {
+		/* re-try by toggling the PLL reset */
+		mmio_clrbits_32(base + USB3H_U2PLL_CTRL,
+				(uint32_t)USB3H_U2PLL_RESETB);
+		mmio_setbits_32(base + USB3H_U2PLL_CTRL, USB3H_U2PLL_RESETB);
+		status = pll_lock_check(base + USB3H_U2PLL_CTRL,
+					USB3H_U2PLL_LOCK);
+		if (status != 0)
+			ERROR("%s() re-try PLL lock FAIL (0x%08x)\n", __func__,
+			      base + USB3H_U2PLL_CTRL);
+	}
+
+	mmio_clrsetbits_32(base + USB3H_U2PHY_CTRL,
+			   (USB3H_U2PHY_PCTL_MASK << USB3H_U2PHY_PCTL_OFFSET),
+			   (U2PHY_PCTL_NON_DRV_LOW << USB3H_U2PHY_PCTL_OFFSET));
+	return status;
+}
+
+static int32_t usb3h_u3_phy_power_on(uint32_t base)
+{
+	int32_t status;
+
+	/* Set pctl with mode and soft reset */
+	mmio_clrsetbits_32(base + USB3H_U3PHY_CTRL,
+			   (USB3H_U3PHY_PCTL_MASK << USB3H_U3PHY_PCTL_OFFSET),
+			   (U3PHY_PCTL_VAL << USB3H_U3PHY_PCTL_OFFSET));
+
+	mmio_clrbits_32(base + USB3H_U3PHY_PLL_CTRL,
+			(uint32_t) USB3H_U3SSPLL_SUSPEND_EN);
+	mmio_setbits_32(base + USB3H_U3PHY_PLL_CTRL, USB3H_U3PLL_SEQ_START);
+	mmio_setbits_32(base + USB3H_U3PHY_PLL_CTRL, USB3H_U3PLL_RESETB);
+
+	/* Time to stabilize the PLL Control */
+	mdelay(1U);
+
+	status = pll_lock_check(base + USB3H_U3PHY_PLL_CTRL,
+				USB3H_U3PLL_SS_LOCK);
+
+	return status;
+}
+
+static int32_t drdu3_u2_phy_power_on(uint32_t base)
+{
+	int32_t status;
+	struct u2_phy_ext_fsm u2_phy;
+
+	u2_phy.pll_ctrl_reg = base + DRDU3_U2PLL_CTRL;
+	u2_phy.phy_ctrl_reg = base + DRDU3_U2PHY_CTRL;
+	u2_phy.phy_iddq = DRDU3_U2PHY_IDDQ;
+	u2_phy.pwr_ctrl_reg = base + DRDU3_PWR_CTRL;
+	u2_phy.pwr_okin = DRDU3_U2PHY_DFE_SWITCH_PWROKIN;
+	u2_phy.pwr_onin = DRDU3_U2PHY_DFE_SWITCH_PWRONIN;
+
+	u2_phy_ext_fsm_power_on(&u2_phy);
+
+	status = pll_lock_check(base + DRDU3_U2PLL_CTRL, DRDU3_U2PLL_LOCK);
+	if (status != 0) {
+		/* re-try by toggling the PLL reset */
+		mmio_clrbits_32(base + DRDU3_U2PLL_CTRL,
+				(uint32_t)DRDU2_U2PLL_RESETB);
+		mmio_setbits_32(base + DRDU3_U2PLL_CTRL, DRDU3_U2PLL_RESETB);
+
+		status = pll_lock_check(base + DRDU3_U2PLL_CTRL,
+					DRDU3_U2PLL_LOCK);
+		if (status != 0) {
+			ERROR("%s() re-try PLL lock FAIL (0x%08x)\n", __func__,
+			      base + DRDU3_U2PLL_CTRL);
+		}
+	}
+	mmio_clrsetbits_32(base + DRDU3_U2PHY_CTRL,
+			   (DRDU3_U2PHY_PCTL_MASK << DRDU3_U2PHY_PCTL_OFFSET),
+			   (U2PHY_PCTL_NON_DRV_LOW << DRDU3_U2PHY_PCTL_OFFSET));
+
+	return status;
+}
+
+static int32_t drdu3_u3_phy_power_on(uint32_t base)
+{
+	int32_t status;
+
+	/* Set pctl with mode and soft reset */
+	mmio_clrsetbits_32(base + DRDU3_U3PHY_CTRL,
+			   (DRDU3_U3PHY_PCTL_MASK << DRDU3_U3PHY_PCTL_OFFSET),
+			   (U3PHY_PCTL_VAL << DRDU3_U3PHY_PCTL_OFFSET));
+
+	mmio_clrbits_32(base + DRDU3_U3PHY_PLL_CTRL,
+			(uint32_t) DRDU3_U3SSPLL_SUSPEND_EN);
+	mmio_setbits_32(base + DRDU3_U3PHY_PLL_CTRL, DRDU3_U3PLL_SEQ_START);
+	mmio_setbits_32(base + DRDU3_U3PHY_PLL_CTRL, DRDU3_U3PLL_RESETB);
+
+	/* Time to stabilize the PLL Control */
+	mdelay(1U);
+
+	status = pll_lock_check(base + DRDU3_U3PHY_PLL_CTRL,
+				DRDU3_U3PLL_SS_LOCK);
+
+	return status;
+}
+
+static int32_t drdu2_u2_phy_power_on(uint32_t base)
+{
+	int32_t status;
+	struct u2_phy_ext_fsm u2_phy;
+
+	u2_phy.pll_ctrl_reg = base + DRDU2_U2PLL_CTRL;
+	u2_phy.phy_ctrl_reg = base + DRDU2_PHY_CTRL;
+	u2_phy.phy_iddq = DRDU2_U2IDDQ;
+	u2_phy.pwr_ctrl_reg = base + DRDU2_PWR_CTRL;
+	u2_phy.pwr_okin = DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I;
+	u2_phy.pwr_onin = DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I;
+
+	u2_phy_ext_fsm_power_on(&u2_phy);
+
+	status = pll_lock_check(base + DRDU2_U2PLL_CTRL, DRDU2_U2PLL_LOCK);
+	if (status != 0) {
+		/* re-try by toggling the PLL reset */
+		mmio_clrbits_32(base + DRDU2_U2PLL_CTRL,
+				(uint32_t)DRDU2_U2PLL_RESETB);
+		mmio_setbits_32(base + DRDU2_U2PLL_CTRL, DRDU2_U2PLL_RESETB);
+
+		status = pll_lock_check(base + DRDU2_U2PLL_CTRL,
+					DRDU2_U2PLL_LOCK);
+		if (status != 0)
+			ERROR("%s() re-try PLL lock FAIL (0x%08x)\n", __func__,
+			      base + DRDU2_U2PLL_CTRL);
+	}
+	mmio_clrsetbits_32(base + DRDU2_PHY_CTRL,
+			   (DRDU2_U2PHY_PCTL_MASK << DRDU2_U2PHY_PCTL_OFFSET),
+			   (U2PHY_PCTL_NON_DRV_LOW << DRDU2_U2PHY_PCTL_OFFSET));
+
+	return status;
+}
+
+void u3h_u2drd_phy_reset(usb_phy_port_t *phy_port)
+{
+	usb_phy_t *phy = phy_port->p;
+
+	switch (phy_port->port_id) {
+	case USB3HS_PORT:
+		mmio_clrbits_32(phy->usb3hreg + USB3H_U2PHY_CTRL,
+				(uint32_t) USB3H_U2CTRL_CORERDY);
+		mmio_setbits_32(phy->usb3hreg + USB3H_U2PHY_CTRL,
+				USB3H_U2CTRL_CORERDY);
+		break;
+	case DRDU2_PORT:
+		mmio_clrbits_32(phy->drdu2reg + DRDU2_PHY_CTRL,
+				(uint32_t) DRDU2_U2CTRL_CORERDY);
+		mmio_setbits_32(phy->drdu2reg + DRDU2_PHY_CTRL,
+				DRDU2_U2CTRL_CORERDY);
+		break;
+	}
+}
+
+void u3drd_phy_reset(usb_phy_port_t *phy_port)
+{
+	usb_phy_t *phy = phy_port->p;
+
+	if (phy_port->port_id == DRD3HS_PORT) {
+		mmio_clrbits_32(phy->drdu3reg + DRDU3_U2PHY_CTRL,
+				(uint32_t) DRDU3_U2CTRL_CORERDY);
+		mmio_setbits_32(phy->drdu3reg + DRDU3_U2PHY_CTRL,
+				DRDU3_U2CTRL_CORERDY);
+	}
+}
+
+static int32_t u3h_u2drd_phy_power_on(usb_phy_port_t *phy_port)
+{
+	usb_phy_t *phy = phy_port->p;
+	int32_t status;
+
+	switch (phy_port->port_id) {
+	case USB3SS_PORT:
+		mmio_clrbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+				(uint32_t) USB3H_DISABLE_USB30_P0);
+		status = usb3h_u3_phy_power_on(phy->usb3hreg);
+		if (status != 0) {
+			goto err_usb3h_phy_on;
+		}
+		break;
+	case USB3HS_PORT:
+		mmio_clrbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+				(uint32_t) USB3H_DISABLE_EUSB_P1);
+		mmio_setbits_32(AXI_DEBUG_CTRL,
+				AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+		mmio_setbits_32(USB3H_DEBUG_CTRL,
+				USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+
+		mmio_clrbits_32(phy->usb3hreg + USB3H_PWR_CTRL,
+				USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN);
+		/* Delay as per external FSM spec */
+		udelay(10U);
+		mmio_clrbits_32(phy->usb3hreg + USB3H_PWR_CTRL,
+				USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN);
+		status = usb3h_u2_phy_power_on(phy->usb3hreg);
+		if (status != 0) {
+			goto err_usb3h_phy_on;
+		}
+		break;
+	case DRDU2_PORT:
+		mmio_clrbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+				(uint32_t) USB3H_DISABLE_EUSB_P0);
+		mmio_setbits_32(AXI_DEBUG_CTRL,
+				AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+		mmio_setbits_32(USB3H_DEBUG_CTRL,
+				USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+
+		mmio_clrbits_32(phy->usb3hreg + DRDU2_PWR_CTRL,
+				DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I);
+		/* Delay as per external FSM spec */
+		udelay(10U);
+		mmio_clrbits_32(phy->usb3hreg + DRDU2_PWR_CTRL,
+				DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I);
+
+		status = drdu2_u2_phy_power_on(phy->drdu2reg);
+		if (status != 0) {
+			mmio_setbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+					USB3H_DISABLE_EUSB_P0);
+			goto err_drdu2_phy_on;
+		}
+		break;
+	}
+
+	/* Device Mode */
+	if (phy_port->port_id == DRDU2_PORT) {
+		mmio_write_32(phy->drdu2reg + DRDU2_SOFT_RESET_CTRL,
+			      DRDU2_BDC_AXI_SOFT_RST_N);
+		mmio_setbits_32(phy->drdu2reg + DRDU2_PHY_CTRL,
+				DRDU2_U2SOFT_RST_N);
+	}
+	/* Host Mode */
+	mmio_write_32(phy->usb3hreg + USB3H_SOFT_RESET_CTRL,
+		      USB3H_XHC_AXI_SOFT_RST_N);
+	mmio_setbits_32(phy->usb3hreg + USB3H_U3PHY_CTRL, USB3H_U3SOFT_RST_N);
+
+	return 0U;
+ err_usb3h_phy_on:mmio_setbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+			(USB3H_DISABLE_EUSB_P1 |
+			 USB3H_DISABLE_USB30_P0));
+ err_drdu2_phy_on:
+
+	return status;
+}
+
+static int32_t u3drd_phy_power_on(usb_phy_port_t *phy_port)
+{
+	usb_phy_t *phy = phy_port->p;
+	int32_t status;
+
+	switch (phy_port->port_id) {
+	case DRD3SS_PORT:
+		mmio_clrbits_32(phy->drdu3reg + DRDU3_PHY_PWR_CTRL,
+				(uint32_t) DRDU3_DISABLE_USB30_P0);
+
+		status = drdu3_u3_phy_power_on(phy->drdu3reg);
+		if (status != 0) {
+			goto err_drdu3_phy_on;
+		}
+		break;
+	case DRD3HS_PORT:
+		mmio_clrbits_32(phy->drdu3reg + DRDU3_PHY_PWR_CTRL,
+				(uint32_t) DRDU3_DISABLE_EUSB_P0);
+		mmio_setbits_32(AXI_DEBUG_CTRL,
+				AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+		mmio_setbits_32(USB3H_DEBUG_CTRL,
+				USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+
+		mmio_clrbits_32(phy->drdu3reg + DRDU3_PWR_CTRL,
+				DRDU3_U2PHY_DFE_SWITCH_PWRONIN);
+		/* Delay as per external FSM spec */
+		udelay(10U);
+		mmio_clrbits_32(phy->drdu3reg + DRDU3_PWR_CTRL,
+				DRDU3_U2PHY_DFE_SWITCH_PWROKIN);
+
+		status = drdu3_u2_phy_power_on(phy->drdu3reg);
+		if (status != 0) {
+			goto err_drdu3_phy_on;
+		}
+
+		/* Host Mode */
+		mmio_setbits_32(phy->drdu3reg + DRDU3_SOFT_RESET_CTRL,
+				DRDU3_XHC_AXI_SOFT_RST_N);
+		mmio_setbits_32(phy->drdu3reg + DRDU3_U3PHY_CTRL,
+				DRDU3_U3XHC_SOFT_RST_N);
+		/* Device Mode */
+		mmio_setbits_32(phy->drdu3reg + DRDU3_SOFT_RESET_CTRL,
+				DRDU3_BDC_AXI_SOFT_RST_N);
+		mmio_setbits_32(phy->drdu3reg + DRDU3_U3PHY_CTRL,
+				DRDU3_U3BDC_SOFT_RST_N);
+		break;
+	}
+
+	return 0U;
+ err_drdu3_phy_on:mmio_setbits_32(phy->drdu3reg + DRDU3_PHY_PWR_CTRL,
+			(DRDU3_DISABLE_EUSB_P0 |
+			 DRDU3_DISABLE_USB30_P0));
+
+	return status;
+}
+
+static void u3h_u2drd_phy_power_off(usb_phy_port_t *phy_port)
+{
+	usb_phy_t *p = phy_port->p;
+
+	switch (phy_port->port_id) {
+	case USB3SS_PORT:
+		mmio_setbits_32(p->usb3hreg + USB3H_PHY_PWR_CTRL,
+				USB3H_DISABLE_USB30_P0);
+		break;
+	case USB3HS_PORT:
+		mmio_setbits_32(p->usb3hreg + USB3H_PHY_PWR_CTRL,
+				USB3H_DISABLE_EUSB_P1);
+		break;
+	case DRDU2_PORT:
+		mmio_setbits_32(p->usb3hreg + USB3H_PHY_PWR_CTRL,
+				USB3H_DISABLE_EUSB_P0);
+		break;
+	}
+}
+
+static void u3drd_phy_power_off(usb_phy_port_t *phy_port)
+{
+	usb_phy_t *p = phy_port->p;
+
+	switch (phy_port->port_id) {
+	case DRD3SS_PORT:
+		mmio_setbits_32(p->drdu3reg + DRDU3_PHY_PWR_CTRL,
+				DRDU3_DISABLE_USB30_P0);
+		break;
+	case DRD3HS_PORT:
+		mmio_setbits_32(p->drdu3reg + DRDU3_PHY_PWR_CTRL,
+				DRDU3_DISABLE_EUSB_P0);
+		break;
+	}
+}
+
+int32_t usb_info_fill(usb_phy_t *phy_info)
+{
+	int32_t index;
+
+	if (phy_info->initialized != 0U) {
+		return USB_PHY_ALREADY_STARTED;
+	}
+
+	if (phy_info->phy_id == USB3H_DRDU2_PHY) {
+		phy_info->phy_port = usb_phy_port[USB3H_DRDU2_PHY - 1U];
+		phy_info->ports_enabled = 0x7U;
+	} else {
+		phy_info->phy_port = usb_phy_port[DRDU3_PHY - 1U];
+		phy_info->ports_enabled = 0x3U;
+	}
+
+	for (index = MAX_NR_PORTS - 1U; index > -1; index--) {
+		phy_info->phy_port[index].enabled = (phy_info->ports_enabled
+						     >> index) & 0x1U;
+		phy_info->phy_port[index].p = phy_info;
+		phy_info->phy_port[index].port_id = index;
+	}
+
+	return 0U;
+}
+
+int32_t usb_phy_init(usb_platform_dev *device)
+{
+	int32_t status;
+	usb_phy_t *phy_info;
+	uint32_t index;
+
+	phy_info = (usb_phy_t *)device->pcd_id;
+
+	status = usb_info_fill(phy_info);
+	if (status != 0) {
+		return (status == USB_PHY_ALREADY_STARTED) ? 0 : status;
+	}
+
+	for (index = 0U; index < MAX_NR_PORTS; index++) {
+		if (phy_info->phy_port[index].enabled != 0U) {
+			switch (phy_info->phy_id) {
+			case USB3H_DRDU2_PHY:
+				status =
+				    u3h_u2drd_phy_power_on(&phy_info->
+							   phy_port[index]);
+				break;
+			default:
+				status =
+				    u3drd_phy_power_on(&phy_info->
+						       phy_port[index]);
+			}
+		}
+	}
+
+	phy_info->initialized = !status;
+	return status;
+}
+
+void usb_phy_shutdown(usb_platform_dev *device)
+{
+	usb_phy_t *phy_info;
+	uint32_t index;
+
+	phy_info = (usb_phy_t *)device->pcd_id;
+
+	phy_info->initialized = 0U;
+
+	for (index = 0U; index < MAX_NR_PORTS; index++) {
+		if (phy_info->phy_port[index].enabled != 0U) {
+			switch (phy_info->phy_id) {
+			case USB3H_DRDU2_PHY:
+				u3h_u2drd_phy_power_off(&phy_info->
+							phy_port[index]);
+				break;
+			case DRDU3_PHY:
+				u3drd_phy_power_off(&phy_info->phy_port[index]);
+				break;
+			default:
+				INFO("%s: invalid phy id 0x%x\n", __func__,
+				     phy_info->phy_id);
+			}
+		}
+	}
+}
+
+int32_t usb_xhci_init(usb_platform_dev *device)
+{
+	int32_t status;
+
+	status = usb_phy_init(device);
+	if (status == USB_PHY_ALREADY_STARTED) {
+		status = 0U;
+	}
+
+	return status;
+}
+
+int32_t usb_device_init(unsigned int usb_func)
+{
+	int32_t status;
+	int32_t devices_initialized = 0U;
+
+	if ((usb_func & USB3H_USB2DRD) != 0U) {
+		status = usb_xhci_init(
+				&xhci_devices_configs[USB3H_USB2DRD_PHY]);
+		if (status == 0) {
+			devices_initialized++;
+		} else {
+			ERROR("%s(): USB3H_USB2DRD init failure\n", __func__);
+		}
+	}
+
+	if ((usb_func & USB3_DRD) != 0U) {
+		status = usb_xhci_init(&xhci_devices_configs[USB3_DRD_PHY]);
+		if (status == 0) {
+			devices_initialized++;
+		} else {
+			ERROR("%s(): USB3_DRD init failure\n", __func__);
+		}
+	}
+
+	return devices_initialized;
+}
diff --git a/plat/brcm/board/stingray/include/platform_usb.h b/plat/brcm/board/stingray/include/platform_usb.h
new file mode 100644
index 0000000..5b5309f
--- /dev/null
+++ b/plat/brcm/board/stingray/include/platform_usb.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2019 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_USB_H
+#define PLATFORM_USB_H
+
+#include <platform_def.h>
+
+#define USB3_DRD		BIT(0U)
+#define USB3H_USB2DRD		BIT(1U)
+
+extern const unsigned int xhc_portsc_reg_offset[MAX_USB_PORTS];
+
+void xhci_phy_init(void);
+
+#endif /* PLATFORM_USB_H */
diff --git a/plat/brcm/board/stingray/include/sr_def.h b/plat/brcm/board/stingray/include/sr_def.h
index be0dee1..277836e 100644
--- a/plat/brcm/board/stingray/include/sr_def.h
+++ b/plat/brcm/board/stingray/include/sr_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, Broadcom
+ * Copyright (c) 2016-2021, Broadcom
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -193,6 +193,11 @@
 #define PLAT_CHIP_REV_GET	(mmio_read_32(ICFG_CHIP_REVISION_ID))
 
 /*******************************************************************************
+ * CMIC MII (MDIO) related constant
+ ******************************************************************************/
+#define PLAT_CMIC_MIIM_BASE	0x68920000U
+
+/*******************************************************************************
  * Timers related constants
  ******************************************************************************/
 /* ChipcommonG_tim0_TIM_TIMER1Load 0x68930000 */
diff --git a/plat/brcm/board/stingray/include/usb_phy.h b/plat/brcm/board/stingray/include/usb_phy.h
new file mode 100644
index 0000000..7d83182
--- /dev/null
+++ b/plat/brcm/board/stingray/include/usb_phy.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2017 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef USB_PHY_H
+#define USB_PHY_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+#define DRDU2_U2PLL_NDIV_FRAC_OFFSET            0x0U
+
+#define DRDU2_U2PLL_NDIV_INT                    0x4U
+
+#define DRDU2_U2PLL_CTRL                        0x8U
+#define DRDU2_U2PLL_LOCK                        BIT(6U)
+#define DRDU2_U2PLL_RESETB                      BIT(5U)
+#define DRDU2_U2PLL_PDIV_MASK                   0xFU
+#define DRDU2_U2PLL_PDIV_OFFSET                 1U
+#define DRDU2_U2PLL_SUSPEND_EN                  BIT(0U)
+
+#define DRDU2_PHY_CTRL                          0x0CU
+#define DRDU2_U2IDDQ                            BIT(30U)
+#define DRDU2_U2SOFT_RST_N                      BIT(29U)
+#define DRDU2_U2PHY_ON_FLAG                     BIT(22U)
+#define DRDU2_U2PHY_PCTL_MASK                   0xFFFFU
+#define DRDU2_U2PHY_PCTL_OFFSET                 6U
+#define DRDU2_U2PHY_RESETB                      BIT(5U)
+#define DRDU2_U2PHY_ISO                         BIT(4U)
+#define DRDU2_U2AFE_BG_PWRDWNB                  BIT(3U)
+#define DRDU2_U2AFE_PLL_PWRDWNB                 BIT(2U)
+#define DRDU2_U2AFE_LDO_PWRDWNB                 BIT(1U)
+#define DRDU2_U2CTRL_CORERDY                    BIT(0U)
+
+#define DRDU2_STRAP_CTRL                        0x18U
+#define DRDU2_FORCE_HOST_MODE                   BIT(5U)
+#define DRDU2_FORCE_DEVICE_MODE                 BIT(4U)
+#define BDC_USB_STP_SPD_MASK                    0x7U
+#define BDC_USB_STP_SPD_OFFSET                  0U
+
+#define DRDU2_PWR_CTRL                          0x1CU
+#define DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I        BIT(2U)
+#define DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I        BIT(1U)
+
+#define DRDU2_SOFT_RESET_CTRL                   0x20U
+#define DRDU2_BDC_AXI_SOFT_RST_N                BIT(0U)
+
+#define USB3H_U2PLL_NDIV_FRAC                   0x4U
+
+#define USB3H_U2PLL_NDIV_INT                    0x8U
+
+#define USB3H_U2PLL_CTRL                        0xCU
+#define USB3H_U2PLL_LOCK                        BIT(6U)
+#define USB3H_U2PLL_RESETB                      BIT(5U)
+#define USB3H_U2PLL_PDIV_MASK                   0xFU
+#define USB3H_U2PLL_PDIV_OFFSET                 1U
+
+#define USB3H_U2PHY_CTRL                        0x10U
+#define USB3H_U2PHY_ON_FLAG                     22U
+#define USB3H_U2PHY_PCTL_MASK                   0xFFFFU
+#define USB3H_U2PHY_PCTL_OFFSET                 6U
+#define USB3H_U2PHY_IDDQ                        BIT(29U)
+#define USB3H_U2PHY_RESETB                      BIT(5U)
+#define USB3H_U2PHY_ISO                         BIT(4U)
+#define USB3H_U2AFE_BG_PWRDWNB                  BIT(3U)
+#define USB3H_U2AFE_PLL_PWRDWNB                 BIT(2U)
+#define USB3H_U2AFE_LDO_PWRDWNB                 BIT(1U)
+#define USB3H_U2CTRL_CORERDY                    BIT(0U)
+
+#define USB3H_U3PHY_CTRL                        0x14U
+#define USB3H_U3SOFT_RST_N                      BIT(30U)
+#define USB3H_U3MDIO_RESETB_I                   BIT(29U)
+#define USB3H_U3POR_RESET_I                     BIT(28U)
+#define USB3H_U3PHY_PCTL_MASK                   0xFFFFU
+#define USB3H_U3PHY_PCTL_OFFSET                 2U
+#define USB3H_U3PHY_RESETB                      BIT(1U)
+
+#define USB3H_U3PHY_PLL_CTRL                    0x18U
+#define USB3H_U3PLL_REFCLK_MASK                 0x7U
+#define USB3H_U3PLL_REFCLK_OFFSET               4U
+#define USB3H_U3PLL_SS_LOCK                     BIT(3U)
+#define USB3H_U3PLL_SEQ_START                   BIT(2U)
+#define USB3H_U3SSPLL_SUSPEND_EN                BIT(1U)
+#define USB3H_U3PLL_RESETB                      BIT(0U)
+
+#define USB3H_PWR_CTRL                          0x28U
+#define USB3H_PWR_CTRL_OVERRIDE_I_R             4U
+#define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN BIT(11U)
+#define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN BIT(10U)
+
+#define USB3H_SOFT_RESET_CTRL                   0x2CU
+#define USB3H_XHC_AXI_SOFT_RST_N                BIT(1U)
+
+#define USB3H_PHY_PWR_CTRL                      0x38U
+#define USB3H_DISABLE_USB30_P0                  BIT(2U)
+#define USB3H_DISABLE_EUSB_P1                   BIT(1U)
+#define USB3H_DISABLE_EUSB_P0                   BIT(0U)
+
+
+#define DRDU3_U2PLL_NDIV_FRAC                   0x4U
+
+#define DRDU3_U2PLL_NDIV_INT                    0x8U
+
+#define DRDU3_U2PLL_CTRL                        0xCU
+#define DRDU3_U2PLL_LOCK                        BIT(6U)
+#define DRDU3_U2PLL_RESETB                      BIT(5U)
+#define DRDU3_U2PLL_PDIV_MASK                   0xFU
+#define DRDU3_U2PLL_PDIV_OFFSET                 1U
+
+#define DRDU3_U2PHY_CTRL                        0x10U
+#define DRDU3_U2PHY_IDDQ                        BIT(29U)
+#define DRDU3_U2PHY_ON_FLAG                     BIT(22U)
+#define DRDU3_U2PHY_PCTL_MASK                   0xFFFFU
+#define DRDU3_U2PHY_PCTL_OFFSET                 6U
+#define DRDU3_U2PHY_RESETB                      BIT(5U)
+#define DRDU3_U2PHY_ISO                         BIT(4U)
+#define DRDU3_U2AFE_BG_PWRDWNB                  BIT(3U)
+#define DRDU3_U2AFE_PLL_PWRDWNB                 BIT(2U)
+#define DRDU3_U2AFE_LDO_PWRDWNB                 BIT(1U)
+#define DRDU3_U2CTRL_CORERDY                    BIT(0U)
+
+#define DRDU3_U3PHY_CTRL                        0x14U
+#define DRDU3_U3XHC_SOFT_RST_N                  BIT(31U)
+#define DRDU3_U3BDC_SOFT_RST_N                  BIT(30U)
+#define DRDU3_U3MDIO_RESETB_I                   BIT(29U)
+#define DRDU3_U3POR_RESET_I                     BIT(28U)
+#define DRDU3_U3PHY_PCTL_MASK                   0xFFFFU
+#define DRDU3_U3PHY_PCTL_OFFSET                 2U
+#define DRDU3_U3PHY_RESETB                      BIT(1U)
+
+#define DRDU3_U3PHY_PLL_CTRL                    0x18U
+#define DRDU3_U3PLL_REFCLK_MASK                 0x7U
+#define DRDU3_U3PLL_REFCLK_OFFSET               4U
+#define DRDU3_U3PLL_SS_LOCK                     BIT(3U)
+#define DRDU3_U3PLL_SEQ_START                   BIT(2U)
+#define DRDU3_U3SSPLL_SUSPEND_EN                BIT(1U)
+#define DRDU3_U3PLL_RESETB                      BIT(0U)
+
+#define DRDU3_STRAP_CTRL                        0x28U
+#define BDC_USB_STP_SPD_MASK                    0x7U
+#define BDC_USB_STP_SPD_OFFSET                  0U
+#define BDC_USB_STP_SPD_SS                      0x0U
+#define BDC_USB_STP_SPD_HS                      0x2U
+
+#define DRDU3_PWR_CTRL                          0x2cU
+#define DRDU3_U2PHY_DFE_SWITCH_PWROKIN          BIT(12U)
+#define DRDU3_U2PHY_DFE_SWITCH_PWRONIN          BIT(11U)
+#define DRDU3_PWR_CTRL_OVERRIDE_I_R             4U
+
+#define DRDU3_SOFT_RESET_CTRL                   0x30U
+#define DRDU3_XHC_AXI_SOFT_RST_N                BIT(1U)
+#define DRDU3_BDC_AXI_SOFT_RST_N                BIT(0U)
+
+#define DRDU3_PHY_PWR_CTRL                      0x3cU
+#define DRDU3_DISABLE_USB30_P0                  BIT(2U)
+#define DRDU3_DISABLE_EUSB_P1                   BIT(1U)
+#define DRDU3_DISABLE_EUSB_P0                   BIT(0U)
+
+#define PLL_REFCLK_PAD                          0x0U
+#define PLL_REFCLK_25MHZ                        0x1U
+#define PLL_REFCLK_96MHZ                        0x2U
+#define PLL_REFCLK_INTERNAL                     0x3U
+/* USB PLL lock time out for 10 ms */
+#define PLL_LOCK_RETRY_COUNT                    10000U
+
+
+#define U2PLL_NDIV_INT_VAL                      0x13U
+#define U2PLL_NDIV_FRAC_VAL                     0x1005U
+#define U2PLL_PDIV_VAL                          0x1U
+/*
+ * Using external FSM
+ * BIT-3:2: device mode; mode is not effect
+ * BIT-1: soft reset active low
+ */
+#define U2PHY_PCTL_VAL                          0x0003U
+/* Non-driving signal low */
+#define U2PHY_PCTL_NON_DRV_LOW                  0x0002U
+#define U3PHY_PCTL_VAL                          0x0006U
+
+#define MAX_NR_PORTS                            3U
+
+#define USB3H_DRDU2_PHY                         1U
+#define DRDU3_PHY                               2U
+
+#define USB_HOST_MODE                           1U
+#define USB_DEV_MODE                            2U
+
+#define USB3SS_PORT                             0U
+#define DRDU2_PORT                              1U
+#define USB3HS_PORT                             2U
+
+#define DRD3SS_PORT                             0U
+#define DRD3HS_PORT                             1U
+
+#define SR_USB_PHY_COUNT                        2U
+
+#define DRDU3_PIPE_CTRL			0x68500000U
+#define DRDU3H_XHC_REGS_CPLIVER		0x68501000U
+#define USB3H_PIPE_CTRL			0x68510000U
+#define DRD2U3H_XHC_REGS_CPLIVER	0x68511000U
+#define DRDU2_U2PLL_NDIV_FRAC		0x68520000U
+
+#define AXI_DEBUG_CTRL				0x68500038U
+#define AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE	BIT(12U)
+
+#define USB3H_DEBUG_CTRL			0x68510034U
+#define USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE	BIT(7U)
+
+typedef struct _usb_phy_port usb_phy_port_t;
+
+typedef struct {
+	uint32_t drdu2reg;
+	uint32_t usb3hreg;
+	uint32_t drdu3reg;
+	uint32_t phy_id;
+	uint32_t ports_enabled;
+	uint32_t initialized;
+	usb_phy_port_t *phy_port;
+} usb_phy_t;
+
+struct _usb_phy_port {
+	uint32_t port_id;
+	uint32_t mode;
+	uint32_t enabled;
+	usb_phy_t *p;
+};
+
+struct u2_phy_ext_fsm {
+	uint32_t pll_ctrl_reg;
+	uint32_t phy_ctrl_reg;
+	uint32_t phy_iddq;
+	uint32_t pwr_ctrl_reg;
+	uint32_t pwr_okin;
+	uint32_t pwr_onin;
+};
+
+#endif /* USB_PHY_H */
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk
index c5509bb..aa2fe86 100644
--- a/plat/brcm/board/stingray/platform.mk
+++ b/plat/brcm/board/stingray/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019-2020, Broadcom
+# Copyright (c) 2019-2021, Broadcom
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -73,6 +73,12 @@
 BOARD_CFG := bcm958742t
 endif
 
+# Use USB
+ifeq (${USE_USB},yes)
+$(info Using USB)
+$(eval $(call add_define,USE_USB))
+endif
+
 # Use PAXB
 ifeq (${USE_PAXB},yes)
 $(info Using PAXB)
@@ -190,17 +196,22 @@
 				plat/${SOC_DIR}/src/tz_sec.c \
 				drivers/arm/tzc/tzc400.c \
 				plat/${SOC_DIR}/driver/plat_emmc.c \
-				plat/${SOC_DIR}/src/topology.c
+				plat/${SOC_DIR}/src/topology.c \
+				drivers/brcm/mdio/mdio.c
 
 ifeq (${USE_CHIMP},yes)
 PLAT_BL_COMMON_SOURCES	+=	drivers/brcm/chimp.c
 endif
 
+ifeq (${USE_USB},yes)
+PLAT_BL_COMMON_SOURCES	+=	plat/${SOC_DIR}/driver/usb.c \
+				plat/${SOC_DIR}/driver/usb_phy.c
+endif
+
 BL2_SOURCES		+=	plat/${SOC_DIR}/driver/ihost_pll_config.c \
 				plat/${SOC_DIR}/src/bl2_setup.c \
 				plat/${SOC_DIR}/driver/swreg.c
 
-
 ifeq (${USE_DDR},yes)
 PLAT_INCLUDES		+=	-Iplat/${SOC_DIR}/driver/ddr/soc/include
 else
diff --git a/plat/brcm/board/stingray/src/bl31_setup.c b/plat/brcm/board/stingray/src/bl31_setup.c
index a2a274d..04df6a0 100644
--- a/plat/brcm/board/stingray/src/bl31_setup.c
+++ b/plat/brcm/board/stingray/src/bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 - 2020, Broadcom
+ * Copyright (c) 2015 - 2021, Broadcom
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,6 +28,9 @@
 #include <paxb.h>
 #include <paxc.h>
 #include <platform_def.h>
+#ifdef USE_USB
+#include <platform_usb.h>
+#endif
 #include <sdio.h>
 #include <sr_utils.h>
 #include <timer_sync.h>
diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c
index 86e4fd6..01c48ec 100644
--- a/plat/hisilicon/hikey/hikey_bl1_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl1_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,6 +27,7 @@
 /* Data structure which holds the extents of the trusted RAM for BL1 */
 static meminfo_t bl1_tzram_layout;
 static console_t console;
+static struct mmc_device_info mmc_info;
 
 enum {
 	BOOT_NORMAL = 0,
@@ -78,7 +79,6 @@
 void bl1_platform_setup(void)
 {
 	dw_mmc_params_t params;
-	struct mmc_device_info info;
 
 	assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
 	       ((SRAM_BASE + SRAM_SIZE) >=
@@ -99,8 +99,8 @@
 	params.clk_rate = 24 * 1000 * 1000;
 	params.bus_width = MMC_BUS_WIDTH_8;
 	params.flags = MMC_FLAG_CMD23;
-	info.mmc_dev_type = MMC_IS_EMMC;
-	dw_mmc_init(&params, &info);
+	mmc_info.mmc_dev_type = MMC_IS_EMMC;
+	dw_mmc_init(&params, &mmc_info);
 
 	hikey_io_setup();
 }
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index feb7f8a..a90f12c 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,6 +33,7 @@
 
 static meminfo_t bl2_el3_tzram_layout;
 static console_t console;
+static struct mmc_device_info mmc_info;
 
 enum {
 	BOOT_MODE_RECOVERY = 0,
@@ -290,7 +291,6 @@
 void bl2_platform_setup(void)
 {
 	dw_mmc_params_t params;
-	struct mmc_device_info info;
 
 	hikey_sp804_init();
 	hikey_gpio_init();
@@ -322,8 +322,8 @@
 	params.clk_rate = 24 * 1000 * 1000;
 	params.bus_width = MMC_BUS_WIDTH_8;
 	params.flags = MMC_FLAG_CMD23;
-	info.mmc_dev_type = MMC_IS_EMMC;
-	dw_mmc_init(&params, &info);
+	mmc_info.mmc_dev_type = MMC_IS_EMMC;
+	dw_mmc_init(&params, &mmc_info);
 
 	hikey_io_setup();
 }
diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c
index 047ba62..acc1f0e 100644
--- a/plat/hisilicon/poplar/bl1_plat_setup.c
+++ b/plat/hisilicon/poplar/bl1_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -30,6 +30,10 @@
 static meminfo_t bl2_tzram_layout;
 static console_t console;
 
+#if !POPLAR_RECOVERY
+static struct mmc_device_info mmc_info;
+#endif
+
 /*
  * Cannot use default weak implementation in bl1_main.c because BL1 RW data is
  * not at the top of the secure memory.
@@ -90,7 +94,6 @@
 {
 	int i;
 #if !POPLAR_RECOVERY
-	struct mmc_device_info info;
 	dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
 #endif
 
@@ -103,8 +106,8 @@
 #if !POPLAR_RECOVERY
 	/* SoC-specific emmc register are initialized/configured by bootrom */
 	INFO("BL1: initializing emmc\n");
-	info.mmc_dev_type = MMC_IS_EMMC;
-	dw_mmc_init(&params, &info);
+	mmc_info.mmc_dev_type = MMC_IS_EMMC;
+	dw_mmc_init(&params, &mmc_info);
 #endif
 
 	plat_io_setup();
diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c
index 482935c..ee46772 100644
--- a/plat/hisilicon/poplar/bl2_plat_setup.c
+++ b/plat/hisilicon/poplar/bl2_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,6 +26,9 @@
 
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
 static console_t console;
+#if !POPLAR_RECOVERY
+static struct mmc_device_info mmc_info;
+#endif
 
 /*******************************************************************************
  * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
@@ -171,8 +174,6 @@
 {
 	struct meminfo *mem_layout = (struct meminfo *)arg1;
 #if !POPLAR_RECOVERY
-	struct mmc_device_info info;
-
 	dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
 #endif
 
@@ -187,8 +188,8 @@
 #if !POPLAR_RECOVERY
 	/* SoC-specific emmc register are initialized/configured by bootrom */
 	INFO("BL2: initializing emmc\n");
-	info.mmc_dev_type = MMC_IS_EMMC;
-	dw_mmc_init(&params, &info);
+	mmc_info.mmc_dev_type = MMC_IS_EMMC;
+	dw_mmc_init(&params, &mmc_info);
 #endif
 
 	plat_io_setup();
diff --git a/plat/imx/common/imx_sip_handler.c b/plat/imx/common/imx_sip_handler.c
index f9f5577..d4b3425 100644
--- a/plat/imx/common/imx_sip_handler.c
+++ b/plat/imx/common/imx_sip_handler.c
@@ -14,6 +14,7 @@
 #include <common/runtime_svc.h>
 #include <imx_sip_svc.h>
 #include <lib/el3_runtime/context_mgmt.h>
+#include <lib/mmio.h>
 #include <sci/sci.h>
 
 #if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
@@ -145,6 +146,37 @@
 
 #endif /* defined(PLAT_imx8qm) || defined(PLAT_imx8qx) */
 
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+int imx_src_handler(uint32_t smc_fid,
+		    u_register_t x1,
+		    u_register_t x2,
+		    u_register_t x3,
+		    void *handle)
+{
+	uint32_t val;
+
+	switch (x1) {
+	case IMX_SIP_SRC_SET_SECONDARY_BOOT:
+		if (x2 != 0U) {
+			mmio_setbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
+					SRC_GPR10_PERSIST_SECONDARY_BOOT);
+		} else {
+			mmio_clrbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
+					SRC_GPR10_PERSIST_SECONDARY_BOOT);
+		}
+		break;
+	case IMX_SIP_SRC_IS_SECONDARY_BOOT:
+		val = mmio_read_32(IMX_SRC_BASE + SRC_GPR10_OFFSET);
+		return !!(val & SRC_GPR10_PERSIST_SECONDARY_BOOT);
+	default:
+		return SMC_UNK;
+
+	};
+
+	return 0;
+}
+#endif /* defined(PLAT_imx8mm) || defined(PLAT_imx8mq) */
+
 static uint64_t imx_get_commit_hash(u_register_t x2,
 		    u_register_t x3,
 		    u_register_t x4)
diff --git a/plat/imx/common/imx_sip_svc.c b/plat/imx/common/imx_sip_svc.c
index 20e1479..fd54820 100644
--- a/plat/imx/common/imx_sip_svc.c
+++ b/plat/imx/common/imx_sip_svc.c
@@ -48,6 +48,11 @@
 	case IMX_SIP_MISC_SET_TEMP:
 		SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4));
 #endif
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+	case IMX_SIP_SRC:
+		SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle));
+		break;
+#endif
 	case  IMX_SIP_BUILDINFO:
 		SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4));
 	default:
diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h
index 0a2d750..6c7a760 100644
--- a/plat/imx/common/include/imx_sip_svc.h
+++ b/plat/imx/common/include/imx_sip_svc.h
@@ -17,6 +17,10 @@
 #define IMX_SIP_BUILDINFO			0xC2000003
 #define IMX_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
+#define IMX_SIP_SRC			0xC2000005
+#define IMX_SIP_SRC_SET_SECONDARY_BOOT	0x10
+#define IMX_SIP_SRC_IS_SECONDARY_BOOT	0x11
+
 #define IMX_SIP_GET_SOC_INFO		0xC2000006
 
 #define IMX_SIP_WAKEUP_SRC		0xC2000009
@@ -38,6 +42,11 @@
 			 u_register_t x2, u_register_t x3);
 #endif
 
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+int imx_src_handler(uint32_t smc_fid, u_register_t x1,
+		    u_register_t x2, u_register_t x3, void *handle);
+#endif
+
 #if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
 int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
 			u_register_t x2, u_register_t x3);
diff --git a/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
index 3cf5c36..2df96ae 100644
--- a/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
+++ b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -43,6 +43,8 @@
 	 IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW         | \
 	 IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
 
+static struct mmc_device_info mmc_info;
+
 static void picopi_setup_pinmux(void)
 {
 	/* Configure UART5 TX */
@@ -93,14 +95,13 @@
 static void picopi_usdhc_setup(void)
 {
 	imx_usdhc_params_t params;
-	struct mmc_device_info info;
 
 	zeromem(&params, sizeof(imx_usdhc_params_t));
 	params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
 	params.clk_rate = 25000000;
 	params.bus_width = MMC_BUS_WIDTH_8;
-	info.mmc_dev_type = MMC_IS_EMMC;
-	imx_usdhc_init(&params, &info);
+	mmc_info.mmc_dev_type = MMC_IS_EMMC;
+	imx_usdhc_init(&params, &mmc_info);
 }
 
 static void picopi_setup_usb_clocks(void)
diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
index 935a411..ec13ade 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
+++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -69,6 +69,8 @@
 	 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN		| \
 	 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4)
 
+static struct mmc_device_info mmc_info;
+
 static void warp7_setup_pinmux(void)
 {
 	/* Configure UART1 TX */
@@ -99,14 +101,13 @@
 static void warp7_usdhc_setup(void)
 {
 	imx_usdhc_params_t params;
-	struct mmc_device_info info;
 
 	zeromem(&params, sizeof(imx_usdhc_params_t));
 	params.reg_base = PLAT_WARP7_BOOT_MMC_BASE;
 	params.clk_rate = 25000000;
 	params.bus_width = MMC_BUS_WIDTH_8;
-	info.mmc_dev_type = MMC_IS_EMMC;
-	imx_usdhc_init(&params, &info);
+	mmc_info.mmc_dev_type = MMC_IS_EMMC;
+	imx_usdhc_init(&params, &mmc_info);
 }
 
 static void warp7_setup_usb_clocks(void)
diff --git a/plat/imx/imx8m/imx8m_psci_common.c b/plat/imx/imx8m/imx8m_psci_common.c
index dbb772d..9dfd311 100644
--- a/plat/imx/imx8m/imx8m_psci_common.c
+++ b/plat/imx/imx8m/imx8m_psci_common.c
@@ -152,19 +152,45 @@
 		req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
 }
 
-void __dead2 imx_system_reset(void)
+static void __dead2 imx_wdog_restart(bool external_reset)
 {
 	uintptr_t wdog_base = IMX_WDOG_BASE;
 	unsigned int val;
 
-	/* WDOG_B reset */
 	val = mmio_read_16(wdog_base);
-#ifdef IMX_WDOG_B_RESET
-	val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_WDE |
-		WDOG_WCR_WDT | WDOG_WCR_SRS;
-#else
-	val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_SRS;
-#endif
+	/*
+	 * Common watchdog init flags, for additional details check
+	 * 6.6.4.1 Watchdog Control Register (WDOGx_WCR)
+	 *
+	 * Initial bit selection:
+	 * WDOG_WCR_WDE - Enable the watchdog.
+	 *
+	 * 0x000E mask is used to keep previous values (that could be set
+	 * in SPL) of WDBG and WDE/WDT (both are write-one once-only bits).
+	 */
+	val = (val & 0x000E) | WDOG_WCR_WDE;
+	if (external_reset) {
+		/*
+		 * To assert WDOG_B (external reset) we have
+		 * to set WDA bit 0 (already set in previous step).
+		 * SRS bits are required to be set to 1 (no effect on the
+		 * system).
+		 */
+		val |= WDOG_WCR_SRS;
+	} else {
+		/*
+		 * To assert Software Reset Signal (internal reset) we have
+		 * to set SRS bit to 0 (already set in previous step).
+		 * SRE bit is required to be set to 1 when used in
+		 * conjunction with the Software Reset Signal before
+		 * SRS asserton, otherwise SRS bit will just automatically
+		 * reset to 1.
+		 *
+		 * Also we set WDA to 1 (no effect on system).
+		 */
+		val |= WDOG_WCR_SRE | WDOG_WCR_WDA;
+	}
+
 	mmio_write_16(wdog_base, val);
 
 	mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
@@ -173,6 +199,27 @@
 		;
 }
 
+void __dead2 imx_system_reset(void)
+{
+#ifdef IMX_WDOG_B_RESET
+	imx_wdog_restart(true);
+#else
+	imx_wdog_restart(false);
+#endif
+}
+
+int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
+{
+	imx_wdog_restart(false);
+
+	/*
+	 * imx_wdog_restart cannot return (as it's  a __dead function),
+	 * however imx_system_reset2 has to return some value according
+	 * to PSCI v1.1 spec.
+	 */
+	return 0;
+}
+
 void __dead2 imx_system_off(void)
 {
 	mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV |
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
new file mode 100644
index 0000000..937774c
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2017-2021 NXP
+ * Copyright 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <context.h>
+#include <drivers/console.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/mmc.h>
+#include <lib/mmio.h>
+#include <lib/optee_utils.h>
+#include <lib/utils.h>
+#include <stdbool.h>
+#include <tbbr_img_def.h>
+
+#include <imx_aipstz.h>
+#include <imx_csu.h>
+#include <imx_uart.h>
+#include <imx_usdhc.h>
+#include <plat/common/platform.h>
+
+#include "imx8mm_private.h"
+#include "platform_def.h"
+
+static const struct aipstz_cfg aipstz[] = {
+	{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+	{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+	{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+	{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+	{0},
+};
+
+static void imx8mm_usdhc_setup(void)
+{
+	imx_usdhc_params_t params;
+	struct mmc_device_info info;
+
+	params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE;
+	/*
+	   The imx8mm SD Card Speed modes for USDHC2
+	   +--------------+--------------------+--------------+--------------+
+	   |Bus Speed Mode|Max. Clock Frequency|Max. Bus Speed|Signal Voltage|
+	   +--------------+--------------------+--------------+--------------+
+	   |Default Speed | 25 MHz             | 12.5 MB/s    | 3.3V         |
+	   |High Speed    | 50 MHz             | 25 MB/s      | 3.3V         |
+	   +--------------+--------------------+--------------+--------------+
+
+	   We pick 50 Mhz here for High Speed access.
+	*/
+	params.clk_rate = 50000000;
+	params.bus_width = MMC_BUS_WIDTH_1;
+	params.flags = 0;
+	info.mmc_dev_type = MMC_IS_SD;
+	info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
+	imx_usdhc_init(&params, &info);
+}
+
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+				  u_register_t arg3, u_register_t arg4)
+{
+	int i;
+	static console_t console;
+
+	/* enable CSU NS access permission */
+	for (i = 0; i < MAX_CSU_NUM; i++) {
+		mmio_write_32(IMX_CSU_BASE + i * 4, CSU_CSL_OPEN_ACCESS);
+	}
+
+	/* config the aips access permission */
+	imx_aipstz_init(aipstz);
+
+	console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+		IMX_CONSOLE_BAUDRATE, &console);
+
+	generic_delay_timer_init();
+
+	/* select the CKIL source to 32K OSC */
+	mmio_write_32(0x30360124, 0x1);
+
+	imx8mm_usdhc_setup();
+
+	/* Open handles to a FIP image */
+	plat_imx8mm_io_setup();
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+}
+
+void bl2_platform_setup(void)
+{
+}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+	int err = 0;
+	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+	bl_mem_params_node_t *pager_mem_params = NULL;
+	bl_mem_params_node_t *paged_mem_params = NULL;
+
+	assert(bl_mem_params);
+
+	switch (image_id) {
+	case BL32_IMAGE_ID:
+		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+		assert(pager_mem_params);
+
+		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+		assert(paged_mem_params);
+
+		err = parse_optee_header(&bl_mem_params->ep_info,
+					 &pager_mem_params->image_info,
+					 &paged_mem_params->image_info);
+		if (err != 0) {
+			WARN("OPTEE header parse error.\n");
+		}
+
+		break;
+	default:
+		/* Do nothing in default case */
+		break;
+	}
+
+	return err;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	return COUNTER_FREQUENCY;
+}
+
+void bl2_plat_runtime_setup(void)
+{
+	return;
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c b/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c
new file mode 100644
index 0000000..e44345d
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <common/desc_image_load.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+	{
+		.image_id = BL31_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+					DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
+				      IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+	{
+		.image_id = BL32_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+				      image_info_t, 0),
+
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_SIZE,
+
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
+	{
+		.image_id = BL32_EXTRA1_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      SECURE | NON_EXECUTABLE),
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+				      image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size =  BL32_SIZE,
+
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+	{
+		/* This is a zero sized image so we don't set base or size */
+		.image_id = BL32_EXTRA2_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+				      VERSION_2, entry_point_info_t,
+				      SECURE | NON_EXECUTABLE),
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+				      VERSION_2, image_info_t,
+				      IMAGE_ATTRIB_SKIP_LOADING),
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
+	{
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+				      entry_point_info_t,
+				      NON_SECURE | EXECUTABLE),
+		# ifdef PRELOADED_BL33_BASE
+			.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
+
+			SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+					      VERSION_2, image_info_t,
+					      IMAGE_ATTRIB_SKIP_LOADING),
+		# else
+			.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
+
+			SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+					      VERSION_2, image_info_t, 0),
+			.image_info.image_base = PLAT_NS_IMAGE_OFFSET,
+			.image_info.image_max_size = PLAT_NS_IMAGE_SIZE,
+		# endif /* PRELOADED_BL33_BASE */
+
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_image_load.c b/plat/imx/imx8m/imx8mm/imx8mm_image_load.c
new file mode 100644
index 0000000..3a03069
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_image_load.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+
+#include <platform_def.h>
+#include <plat/common/platform.h>
+
+void plat_flush_next_bl_params(void)
+{
+	flush_bl_params_desc();
+}
+
+bl_load_info_t *plat_get_bl_image_load_info(void)
+{
+	return get_bl_load_info_from_mem_params_desc();
+}
+
+bl_params_t *plat_get_next_bl_params(void)
+{
+	return get_next_bl_params_from_mem_params_desc();
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c b/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c
new file mode 100644
index 0000000..ff6687e
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <drivers/io/io_block.h>
+#include <drivers/io/io_driver.h>
+#include <drivers/io/io_fip.h>
+#include <drivers/io/io_driver.h>
+#include <drivers/io/io_memmap.h>
+#include <drivers/mmc.h>
+#include <lib/utils_def.h>
+#include <tbbr_img_def.h>
+#include <tools_share/firmware_image_package.h>
+
+#include <platform_def.h>
+
+static const io_dev_connector_t *fip_dev_con;
+static uintptr_t fip_dev_handle;
+
+#ifndef IMX8MM_FIP_MMAP
+static const io_dev_connector_t *mmc_dev_con;
+static uintptr_t mmc_dev_handle;
+
+static const io_block_spec_t mmc_fip_spec = {
+	.offset = IMX8MM_FIP_MMC_BASE,
+	.length = IMX8MM_FIP_SIZE
+};
+
+static const io_block_dev_spec_t mmc_dev_spec = {
+	/* It's used as temp buffer in block driver. */
+	.buffer		= {
+		.offset	= IMX8MM_FIP_BASE,
+		/* do we need a new value? */
+		.length = IMX8MM_FIP_SIZE
+	},
+	.ops		= {
+		.read	= mmc_read_blocks,
+		.write	= mmc_write_blocks,
+	},
+	.block_size	= MMC_BLOCK_SIZE,
+};
+
+static int open_mmc(const uintptr_t spec);
+
+#else
+static const io_dev_connector_t *memmap_dev_con;
+static uintptr_t memmap_dev_handle;
+
+static const io_block_spec_t fip_block_spec = {
+	.offset = IMX8MM_FIP_BASE,
+	.length = IMX8MM_FIP_SIZE
+};
+static int open_memmap(const uintptr_t spec);
+#endif
+
+static int open_fip(const uintptr_t spec);
+
+static const io_uuid_spec_t bl31_uuid_spec = {
+	.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
+};
+
+static const io_uuid_spec_t bl32_uuid_spec = {
+	.uuid = UUID_SECURE_PAYLOAD_BL32,
+};
+
+static const io_uuid_spec_t bl32_extra1_uuid_spec = {
+	.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
+};
+
+static const io_uuid_spec_t bl32_extra2_uuid_spec = {
+	.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
+};
+
+static const io_uuid_spec_t bl33_uuid_spec = {
+	.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
+};
+
+#if TRUSTED_BOARD_BOOT
+static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
+	.uuid = UUID_TRUSTED_BOOT_FW_CERT,
+};
+
+static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
+	.uuid = UUID_TRUSTED_KEY_CERT,
+};
+
+static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
+	.uuid = UUID_SOC_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
+	.uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
+	.uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
+};
+
+static const io_uuid_spec_t soc_fw_content_cert_uuid_spec = {
+	.uuid = UUID_SOC_FW_CONTENT_CERT,
+};
+
+static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
+	.uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
+	.uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
+};
+#endif /* TRUSTED_BOARD_BOOT */
+
+struct plat_io_policy {
+	uintptr_t *dev_handle;
+	uintptr_t image_spec;
+	int (*check)(const uintptr_t spec);
+};
+
+static const struct plat_io_policy policies[] = {
+#ifndef IMX8MM_FIP_MMAP
+	[FIP_IMAGE_ID] = {
+		&mmc_dev_handle,
+		(uintptr_t)&mmc_fip_spec,
+		open_mmc
+	},
+#else
+	[FIP_IMAGE_ID] = {
+		&memmap_dev_handle,
+		(uintptr_t)&fip_block_spec,
+		open_memmap
+	},
+#endif
+	[BL31_IMAGE_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&bl31_uuid_spec,
+		open_fip
+	},
+	[BL32_IMAGE_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&bl32_uuid_spec,
+		open_fip
+	},
+	[BL32_EXTRA1_IMAGE_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&bl32_extra1_uuid_spec,
+		open_fip
+	},
+	[BL32_EXTRA2_IMAGE_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&bl32_extra2_uuid_spec,
+		open_fip
+	},
+	[BL33_IMAGE_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&bl33_uuid_spec,
+		open_fip
+	},
+#if TRUSTED_BOARD_BOOT
+	[TRUSTED_BOOT_FW_CERT_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&tb_fw_cert_uuid_spec,
+		open_fip
+	},
+	[SOC_FW_KEY_CERT_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&soc_fw_key_cert_uuid_spec,
+		open_fip
+	},
+	[TRUSTED_KEY_CERT_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&trusted_key_cert_uuid_spec,
+		open_fip
+	},
+	[TRUSTED_OS_FW_KEY_CERT_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&tos_fw_key_cert_uuid_spec,
+		open_fip
+	},
+	[NON_TRUSTED_FW_KEY_CERT_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&nt_fw_key_cert_uuid_spec,
+		open_fip
+	},
+	[SOC_FW_CONTENT_CERT_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&soc_fw_content_cert_uuid_spec,
+		open_fip
+	},
+	[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&tos_fw_cert_uuid_spec,
+		open_fip
+	},
+	[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
+		&fip_dev_handle,
+		(uintptr_t)&nt_fw_cert_uuid_spec,
+		open_fip
+	},
+#endif /* TRUSTED_BOARD_BOOT */
+};
+
+static int open_fip(const uintptr_t spec)
+{
+	int result;
+	uintptr_t local_image_handle;
+
+	/* See if a Firmware Image Package is available */
+	result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
+	if (result == 0) {
+		result = io_open(fip_dev_handle, spec, &local_image_handle);
+		if (result == 0) {
+			VERBOSE("Using FIP\n");
+			io_close(local_image_handle);
+		}
+	}
+	return result;
+}
+
+#ifndef IMX8MM_FIP_MMAP
+static int open_mmc(const uintptr_t spec)
+{
+	int result;
+	uintptr_t local_handle;
+
+	result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
+	if (result == 0) {
+		result = io_open(mmc_dev_handle, spec, &local_handle);
+		if (result == 0) {
+			io_close(local_handle);
+		}
+	}
+	return result;
+}
+#else
+static int open_memmap(const uintptr_t spec)
+{
+	int result;
+	uintptr_t local_image_handle;
+
+	result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
+	if (result == 0) {
+		result = io_open(memmap_dev_handle, spec, &local_image_handle);
+		if (result == 0) {
+			VERBOSE("Using Memmap\n");
+			io_close(local_image_handle);
+		}
+	}
+	return result;
+}
+#endif
+
+int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
+			  uintptr_t *image_spec)
+{
+	int result;
+	const struct plat_io_policy *policy;
+
+	assert(image_id < ARRAY_SIZE(policies));
+
+	policy = &policies[image_id];
+	result = policy->check(policy->image_spec);
+	assert(result == 0);
+
+	*image_spec = policy->image_spec;
+	*dev_handle = *policy->dev_handle;
+
+	return result;
+}
+
+void plat_imx8mm_io_setup(void)
+{
+	int result __unused;
+
+#ifndef IMX8MM_FIP_MMAP
+	result = register_io_dev_block(&mmc_dev_con);
+	assert(result == 0);
+
+	result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
+			     &mmc_dev_handle);
+	assert(result == 0);
+
+#else
+	result = register_io_dev_memmap(&memmap_dev_con);
+	assert(result == 0);
+
+	result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
+			     &memmap_dev_handle);
+	assert(result == 0);
+#endif
+
+	result = register_io_dev_fip(&fip_dev_con);
+	assert(result == 0);
+
+	result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
+			     &fip_dev_handle);
+	assert(result == 0);
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_psci.c b/plat/imx/imx8m/imx8mm/imx8mm_psci.c
index e558724..815d3a2 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_psci.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_psci.c
@@ -28,6 +28,7 @@
 	.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
 	.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
 	.system_reset = imx_system_reset,
+	.system_reset2 = imx_system_reset2,
 	.system_off = imx_system_off,
 };
 
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S b/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
new file mode 100644
index 0000000..544ee8a
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+	.global imx8mm_rotpk_hash
+	.global imx8mm_rotpk_hash_end
+imx8mm_rotpk_hash:
+	/* DER header */
+	.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
+	.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
+	/* SHA256 */
+	.incbin ROTPK_HASH
+imx8mm_rotpk_hash_end:
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c b/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c
new file mode 100644
index 0000000..a4384d7
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+
+extern char imx8mm_rotpk_hash[], imx8mm_rotpk_hash_end[];
+
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+			unsigned int *flags)
+{
+	*key_ptr = imx8mm_rotpk_hash;
+	*key_len = imx8mm_rotpk_hash_end - imx8mm_rotpk_hash;
+	*flags = ROTPK_IS_HASH;
+
+	return 0;
+}
+
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+	*nv_ctr = 0;
+
+	return 0;
+}
+
+int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
+{
+	return 1;
+}
+
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+	return get_mbedtls_heap_helper(heap_addr, heap_size);
+}
diff --git a/plat/imx/imx8m/imx8mm/include/imx8mm_private.h b/plat/imx/imx8m/imx8mm/include/imx8mm_private.h
new file mode 100644
index 0000000..52d13f0
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/include/imx8mm_private.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX8MM_PRIVATE_H
+#define IMX8MM_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_imx8mm_io_setup(void);
+
+#endif /* IMX8MM_PRIVATE_H */
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index 1041459..f8efa56 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -1,9 +1,11 @@
 /*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <common/tbbr/tbbr_img_def.h>
+
 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
 #define PLATFORM_LINKER_ARCH		aarch64
 
@@ -34,11 +36,27 @@
 #define PLAT_SDEI_NORMAL_PRI		0x20
 #define PLAT_SDEI_SGI_PRIVATE		U(9)
 
+#if defined(NEED_BL2)
+#define BL2_BASE			U(0x920000)
+#define BL2_LIMIT			U(0x940000)
+#define BL31_BASE			U(0x900000)
+#define BL31_LIMIT			U(0x920000)
+#define IMX8MM_FIP_BASE			U(0x40310000)
+#define IMX8MM_FIP_SIZE			U(0x000200000)
+#define IMX8MM_FIP_LIMIT		U(FIP_BASE + FIP_SIZE)
+
+/* Define FIP image location on eMMC */
+#define IMX8MM_FIP_MMC_BASE		U(0x100000)
+
+#define PLAT_IMX8MM_BOOT_MMC_BASE	U(0x30B50000) /* SD */
+#else
 #define BL31_BASE			U(0x920000)
 #define BL31_LIMIT			U(0x940000)
+#endif
 
 /* non-secure uboot base */
 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
+#define PLAT_NS_IMAGE_SIZE		U(0x00100000)
 
 /* GICv3 base address */
 #define PLAT_GICD_BASE			U(0x38800000)
@@ -106,6 +124,8 @@
 #define SRC_OTG1PHY_SCR			U(0x20)
 #define SRC_OTG2PHY_SCR			U(0x24)
 #define SRC_GPR1_OFFSET			U(0x74)
+#define SRC_GPR10_OFFSET		U(0x98)
+#define SRC_GPR10_PERSIST_SECONDARY_BOOT	BIT(30)
 
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
@@ -127,3 +147,7 @@
 #define COUNTER_FREQUENCY		8000000 /* 8MHz */
 
 #define IMX_WDOG_B_RESET
+
+#define MAX_IO_HANDLES			3U
+#define MAX_IO_DEVICES			2U
+#define MAX_IO_BLOCK_DEVICES		1U
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index ac636fa..1863233 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -6,7 +6,9 @@
 
 PLAT_INCLUDES		:=	-Iplat/imx/common/include		\
 				-Iplat/imx/imx8m/include		\
-				-Iplat/imx/imx8m/imx8mm/include
+				-Iplat/imx/imx8m/imx8mm/include		\
+				-Idrivers/imx/usdhc			\
+				-Iinclude/common/tbbr
 
 # Include GICv3 driver files
 include drivers/arm/gic/v3/gicv3.mk
@@ -39,6 +41,94 @@
 				drivers/delay_timer/generic_delay_timer.c	\
 				${IMX_GIC_SOURCES}
 
+ifeq (${NEED_BL2},yes)
+BL2_SOURCES		+=	common/desc_image_load.c			\
+				plat/imx/common/imx8_helpers.S			\
+				plat/imx/common/imx_uart_console.S		\
+				plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c	\
+				plat/imx/imx8m/imx8mm/gpc.c			\
+				plat/imx/imx8m/imx_aipstz.c			\
+				plat/common/plat_psci_common.c			\
+				lib/xlat_tables/aarch64/xlat_tables.c		\
+				lib/xlat_tables/xlat_tables_common.c		\
+				lib/cpus/aarch64/cortex_a53.S			\
+				drivers/delay_timer/delay_timer.c		\
+				drivers/delay_timer/generic_delay_timer.c	\
+				${PLAT_GIC_SOURCES}				\
+				${PLAT_DRAM_SOURCES}				\
+				drivers/mmc/mmc.c				\
+				drivers/io/io_block.c				\
+				drivers/io/io_fip.c				\
+				drivers/io/io_memmap.c				\
+				drivers/io/io_storage.c				\
+				drivers/imx/usdhc/imx_usdhc.c			\
+				plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c	\
+				plat/imx/imx8m/imx8mm/imx8mm_io_storage.c		\
+				plat/imx/imx8m/imx8mm/imx8mm_image_load.c		\
+				lib/optee/optee_utils.c
+endif
+
+# Add the build options to pack BLx images and kernel device tree
+# in the FIP if the platform requires.
+ifneq ($(BL2),)
+RESET_TO_BL31		:=	0
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
+endif
+ifneq ($(HW_CONFIG),)
+$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
+endif
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call add_define,NEED_BL2))
+LOAD_IMAGE_V2		:=	1
+# Non-TF Boot ROM
+BL2_AT_EL3		:=	1
+endif
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+
+include drivers/auth/mbedtls/mbedtls_crypto.mk
+include drivers/auth/mbedtls/mbedtls_x509.mk
+
+AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
+			drivers/auth/crypto_mod.c		\
+			drivers/auth/img_parser_mod.c		\
+			drivers/auth/tbbr/tbbr_cot_common.c     \
+			drivers/auth/tbbr/tbbr_cot_bl2.c
+
+BL2_SOURCES	+=	${AUTH_SOURCES}					\
+			plat/common/tbbr/plat_tbbr.c			\
+			plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c	\
+			plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
+
+ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
+ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
+
+$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
+$(eval $(call MAKE_LIB_DIRS))
+
+$(BUILD_PLAT)/bl2/imx8mm_rotpk.o: $(ROTPK_HASH)
+
+certificates: $(ROT_KEY)
+
+$(ROT_KEY): | $(BUILD_PLAT)
+	@echo "  OPENSSL $@"
+	@if [ ! -f $(ROT_KEY) ]; then \
+		openssl genrsa 2048 > $@ 2>/dev/null; \
+	fi
+
+$(ROTPK_HASH): $(ROT_KEY)
+	@echo "  OPENSSL $@"
+	$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+	openssl dgst -sha256 -binary > $@ 2>/dev/null
+endif
+
 USE_COHERENT_MEM	:=	1
 RESET_TO_BL31		:=	1
 A53_DISABLE_NON_TEMPORAL_HINT := 0
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h
index 2444e66..9c46d8d 100644
--- a/plat/imx/imx8m/imx8mn/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -34,6 +34,11 @@
 #define PLAT_WAIT_RET_STATE		U(1)
 #define PLAT_STOP_OFF_STATE		U(3)
 
+#define PLAT_PRI_BITS			U(3)
+#define PLAT_SDEI_CRITICAL_PRI		0x10
+#define PLAT_SDEI_NORMAL_PRI		0x20
+#define PLAT_SDEI_SGI_PRIVATE		U(9)
+
 #define BL31_BASE			U(0x960000)
 #define BL31_LIMIT			U(0x980000)
 
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index 8c4ad1c..2087089 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -31,6 +31,8 @@
 				plat/imx/common/imx_sip_handler.c		\
 				plat/imx/common/imx_sip_svc.c			\
 				plat/imx/common/imx_uart_console.S		\
+				plat/imx/common/imx_ehf.c                       \
+				plat/imx/common/imx_sdei.c                      \
 				lib/cpus/aarch64/cortex_a53.S			\
 				drivers/arm/tzc/tzc380.c			\
 				drivers/delay_timer/delay_timer.c		\
@@ -54,3 +56,6 @@
 
 IMX_BOOT_UART_BASE	?=	0x30890000
 $(eval $(call add_define,IMX_BOOT_UART_BASE))
+
+EL3_EXCEPTION_HANDLING := 1
+SDEI_SUPPORT := 1
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index 644adc7..832bed1 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -37,6 +37,11 @@
 #define BL31_BASE			U(0x960000)
 #define BL31_LIMIT			U(0x980000)
 
+#define PLAT_PRI_BITS			U(3)
+#define PLAT_SDEI_CRITICAL_PRI		0x10
+#define PLAT_SDEI_NORMAL_PRI		0x20
+#define PLAT_SDEI_SGI_PRIVATE		U(9)
+
 /* non-secure uboot base */
 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
 
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 1d11e3d..6be2f98 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -28,6 +28,8 @@
 				plat/imx/imx8m/imx8mp/imx8mp_psci.c		\
 				plat/imx/imx8m/imx8mp/gpc.c			\
 				plat/imx/common/imx8_topology.c			\
+				plat/imx/common/imx_ehf.c                       \
+				plat/imx/common/imx_sdei.c                      \
 				plat/imx/common/imx_sip_handler.c		\
 				plat/imx/common/imx_sip_svc.c			\
 				plat/imx/common/imx_uart_console.S		\
@@ -54,3 +56,6 @@
 
 IMX_BOOT_UART_BASE	?=	0x30890000
 $(eval $(call add_define,IMX_BOOT_UART_BASE))
+
+EL3_EXCEPTION_HANDLING := 1
+SDEI_SUPPORT := 1
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_psci.c b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
index 04e191f..662017d 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_psci.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
@@ -117,6 +117,7 @@
 	.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
 	.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
 	.system_reset = imx_system_reset,
+	.system_reset2 = imx_system_reset2,
 	.system_off = imx_system_off,
 };
 
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 9db3a13..6d6a865 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -103,6 +103,8 @@
 #define SRC_OTG1PHY_SCR			U(0x20)
 #define SRC_OTG2PHY_SCR			U(0x24)
 #define SRC_GPR1_OFFSET			U(0x74)
+#define SRC_GPR10_OFFSET		U(0x98)
+#define SRC_GPR10_PERSIST_SECONDARY_BOOT	BIT(30)
 
 #define SNVS_LPCR			U(0x38)
 #define SNVS_LPCR_SRTC_ENV		BIT(0)
diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h
index 075da91..29b8ecf 100644
--- a/plat/imx/imx8m/include/gpc.h
+++ b/plat/imx/imx8m/include/gpc.h
@@ -32,7 +32,7 @@
 		.pwr_req = name##_PWR_REQ,		\
 		.pgc_offset = name##_PGC,		\
 		.need_sync = false,			\
-		.always_on = true,			\
+		.always_on = (on),			\
 	}
 
 #define IMX_MIX_DOMAIN(name, on)			\
@@ -42,7 +42,7 @@
 		.adb400_sync = name##_ADB400_SYNC,	\
 		.adb400_ack = name##_ADB400_ACK,	\
 		.need_sync = true,			\
-		.always_on = true,			\
+		.always_on = (on),			\
 	}
 
 struct imx_pwr_domain {
diff --git a/plat/imx/imx8m/include/imx8m_psci.h b/plat/imx/imx8m/include/imx8m_psci.h
index c33d25e..7d14d11 100644
--- a/plat/imx/imx8m/include/imx8m_psci.h
+++ b/plat/imx/imx8m/include/imx8m_psci.h
@@ -19,5 +19,6 @@
 void imx_domain_suspend(const psci_power_state_t *target_state);
 void imx_domain_suspend_finish(const psci_power_state_t *target_state);
 void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state);
+int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie);
 
 #endif /* IMX8M_PSCI_H */
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index f002947..b6b3e16 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,6 +29,7 @@
 #include "socfpga_system_manager.h"
 #include "wdt/watchdog.h"
 
+static struct mmc_device_info mmc_info;
 
 const mmap_region_t agilex_plat_mmap[] = {
 	MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
@@ -87,7 +88,6 @@
 void bl2_el3_plat_arch_setup(void)
 {
 
-	struct mmc_device_info info;
 	const mmap_region_t bl_regions[] = {
 		MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
 			MT_MEMORY | MT_RW | MT_SECURE),
@@ -110,12 +110,12 @@
 
 	dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
 
-	info.mmc_dev_type = MMC_IS_SD;
-	info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
+	mmc_info.mmc_dev_type = MMC_IS_SD;
+	mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
 
 	switch (boot_source) {
 	case BOOT_SOURCE_SDMMC:
-		dw_mmc_init(&params, &info);
+		dw_mmc_init(&params, &mmc_info);
 		socfpga_io_setup(boot_source);
 		break;
 
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 721a690..ecf1f01 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,6 +27,7 @@
 #include "s10_pinmux.h"
 #include "wdt/watchdog.h"
 
+static struct mmc_device_info mmc_info;
 
 const mmap_region_t plat_stratix10_mmap[] = {
 	MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
@@ -83,7 +84,6 @@
 void bl2_el3_plat_arch_setup(void)
 {
 
-	struct mmc_device_info info;
 	const mmap_region_t bl_regions[] = {
 		MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
 			MT_MEMORY | MT_RW | MT_SECURE),
@@ -106,12 +106,12 @@
 
 	dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
 
-	info.mmc_dev_type = MMC_IS_SD;
-	info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
+	mmc_info.mmc_dev_type = MMC_IS_SD;
+	mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
 
 	switch (boot_source) {
 	case BOOT_SOURCE_SDMMC:
-		dw_mmc_init(&params, &info);
+		dw_mmc_init(&params, &mmc_info);
 		socfpga_io_setup(boot_source);
 		break;
 
diff --git a/plat/marvell/armada/a3k/a3700/board/pm_src.c b/plat/marvell/armada/a3k/a3700/board/pm_src.c
index d6eca5d..247f73b 100644
--- a/plat/marvell/armada/a3k/a3700/board/pm_src.c
+++ b/plat/marvell/armada/a3k/a3700/board/pm_src.c
@@ -8,7 +8,7 @@
 #include <a3700_pm.h>
 #include <plat_marvell.h>
 
-/* This struct provides the PM wake up src configuration */
+/* This struct provides the PM wake up src configuration for A3720 Development Board */
 static struct pm_wake_up_src_config wake_up_src_cfg = {
 	.wake_up_src_num = 3,
 	.wake_up_src[0] = {
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index 8775e89..0a89742 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -38,13 +38,12 @@
 				-I$/drivers/arm/gic/common/
 
 PLAT_BL_COMMON_SOURCES	:=	$(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
+				$(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \
 				$(MARVELL_DRV_BASE)/uart/a3700_console.S
 
 BL1_SOURCES		+=	$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
 				lib/cpus/aarch64/cortex_a53.S
 
-BL31_PORTING_SOURCES	:=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c
-
 MARVELL_DRV		:=	$(MARVELL_DRV_BASE)/comphy/phy-comphy-3700.c
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
@@ -61,7 +60,6 @@
 				$(MARVELL_COMMON_BASE)/marvell_gicv3.c	\
 				$(MARVELL_GIC_SOURCES)			\
 				drivers/arm/cci/cci.c			\
-				$(BL31_PORTING_SOURCES)			\
 				$(PLAT_COMMON_BASE)/a3700_sip_svc.c	\
 				$(MARVELL_DRV)
 
@@ -69,47 +67,52 @@
 BL31_SOURCES		+=	$(PLAT_COMMON_BASE)/cm3_system_reset.c
 endif
 
+ifeq ($(A3720_DB_PM_WAKEUP_SRC),1)
+BL31_SOURCES		+=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c
+endif
+
 ifdef WTP
 
 $(if $(wildcard $(value WTP)/*),,$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' directory does not exist"))
-$(if $(shell test -s "$(value WTP)/branch.txt" || git -C $(value WTP) rev-parse --show-cdup 2>&1),$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' does not contain valid Marvell a3700_utils release tarball nor git repository"))
+$(if $(shell git -C $(value WTP) rev-parse --show-cdup 2>&1),$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' does not contain valid A3700-utils-marvell git repository"))
 
-DOIMAGEPATH	:= $(WTP)
-DOIMAGETOOL	:= $(DOIMAGEPATH)/wtptp/src/TBB_Linux/release/TBB_linux
+TBB		:= $(WTP)/wtptp/src/TBB_Linux/release/TBB_linux
 
 BUILD_UART	:= uart-images
 UART_IMAGE	:= $(BUILD_UART).tgz.bin
 
 ifeq ($(MARVELL_SECURE_BOOT),1)
-DOIMAGE_CFG	:= $(BUILD_PLAT)/atf-tim.txt
-DOIMAGEUART_CFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-tim.txt
-IMAGESPATH	:= $(DOIMAGEPATH)/tim/trusted
-TIMNCFG		:= $(BUILD_PLAT)/atf-timN.txt
-TIMNUARTCFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-timN.txt
-TIMNSIG		:= $(IMAGESPATH)/timnsign.txt
-TIM2IMGARGS	:= -i $(DOIMAGE_CFG) -n $(TIMNCFG)
-TIMN_IMAGE	:= $$(grep "Image Filename:" -m 1 $(TIMNCFG) | cut -c 17-)
+TIM_CFG		:= $(BUILD_PLAT)/atf-tim.txt
+TIM_UART_CFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-tim.txt
+IMAGESPATH	:= $(WTP)/tim/trusted
+TIMN_CFG	:= $(BUILD_PLAT)/atf-timN.txt
+TIMN_UART_CFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-timN.txt
+TIMN_SIG	:= $(IMAGESPATH)/timnsign.txt
+TIM2IMGARGS	:= -i $(TIM_CFG) -n $(TIMN_CFG)
+TIMN_UART_IMAGE	:= $$(grep "Image Filename:" -m 1 $(TIMN_UART_CFG) | cut -c 17-)
 else #MARVELL_SECURE_BOOT
-DOIMAGE_CFG	:= $(BUILD_PLAT)/atf-ntim.txt
-DOIMAGEUART_CFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-ntim.txt
-IMAGESPATH	:= $(DOIMAGEPATH)/tim/untrusted
-TIM2IMGARGS	:= -i $(DOIMAGE_CFG)
+TIM_CFG		:= $(BUILD_PLAT)/atf-ntim.txt
+TIM_UART_CFG	:= $(BUILD_PLAT)/$(BUILD_UART)/atf-ntim.txt
+IMAGESPATH	:= $(WTP)/tim/untrusted
+TIM2IMGARGS	:= -i $(TIM_CFG)
 endif #MARVELL_SECURE_BOOT
 
-TIMBUILD	:= $(DOIMAGEPATH)/script/buildtim.sh
-TIM2IMG		:= $(DOIMAGEPATH)/script/tim2img.pl
-TIMDDRTOOL	:= $(DOIMAGEPATH)/tim/ddr/ddr_tool
+TIM_UART_IMAGE	:= $$(grep "Image Filename:" -m 1 $(TIM_UART_CFG) | cut -c 17-)
+
+TIMBUILD	:= $(WTP)/script/buildtim.sh
+TIM2IMG		:= $(WTP)/script/tim2img.pl
+TIMDDRTOOL	:= $(WTP)/tim/ddr/ddr_tool
 
 $(TIMBUILD): $(TIMDDRTOOL)
 
 # WTMI_IMG is used to specify the customized RTOS image running over
 # Service CPU (CM3 processor). By the default, it points to a
 # baremetal binary of fuse programming in A3700_utils.
-WTMI_IMG	:= $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin
+WTMI_IMG	:= $(WTP)/wtmi/fuse/build/fuse.bin
 
 # WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG)
 # and sys-init image.
-WTMI_MULTI_IMG		:= $(DOIMAGEPATH)/wtmi/build/wtmi.bin
+WTMI_MULTI_IMG		:= $(WTP)/wtmi/build/wtmi.bin
 
 WTMI_ENC_IMG		:= wtmi-enc.bin
 
@@ -122,16 +125,21 @@
 BOOTDEV			?= SPINOR
 PARTNUM			?= 0
 
-TIM_IMAGE		:= $$(grep "Image Filename:" -m 1 $(DOIMAGE_CFG) | cut -c 17-)
-TIMBLDARGS		:= $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
-				$(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 1
-TIMBLDUARTARGS		:= $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
-				$(DDR_TOPOLOGY) 0 0 $(DOIMAGEUART_CFG) $(TIMNUARTCFG) $(TIMNSIG) 0
+TIMBLDARGS		:= $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(WTP) $(CLOCKSPRESET) \
+				$(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(TIM_CFG) $(TIMN_CFG) $(TIMN_SIG) 1
+TIMBLDUARTARGS		:= $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(WTP) $(CLOCKSPRESET) \
+				$(DDR_TOPOLOGY) 0 0 $(TIM_UART_CFG) $(TIMN_UART_CFG) $(TIMN_SIG) 0
+
+UART_IMAGES		:= $(BUILD_UART)/$(TIM_UART_IMAGE)
+ifeq ($(MARVELL_SECURE_BOOT),1)
+UART_IMAGES		+= $(BUILD_UART)/$(TIMN_UART_IMAGE)
+endif
+UART_IMAGES		+= $(BUILD_UART)/wtmi_h.bin $(BUILD_UART)/boot-image_h.bin
 
 CRYPTOPP_LIBDIR		?= $(CRYPTOPP_PATH)
 CRYPTOPP_INCDIR		?= $(CRYPTOPP_PATH)
 
-$(DOIMAGETOOL): FORCE
+$(TBB): FORCE
 	$(if $(CRYPTOPP_LIBDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_LIBDIR. Please set CRYPTOPP_PATH or CRYPTOPP_LIBDIR to point to the right directory"))
 	$(if $(CRYPTOPP_INCDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_INCDIR. Please set CRYPTOPP_PATH or CRYPTOPP_INCDIR to point to the right directory"))
 	$(if $(wildcard $(CRYPTOPP_LIBDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_LIB' was set to '$(CRYPTOPP_LIBDIR)', but '$(CRYPTOPP_LIBDIR)' does not exist"))
@@ -139,10 +147,10 @@
 ifdef CRYPTOPP_PATH
 	$(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile
 endif
-	$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_LIBDIR) INCDIR=$(CRYPTOPP_INCDIR)
+	$(Q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_LIBDIR) INCDIR=$(CRYPTOPP_INCDIR)
 
 $(WTMI_MULTI_IMG): FORCE
-	$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) WTMI_IMG=$(WTMI_IMG) DDR_TOPOLOGY=$(DDR_TOPOLOGY) CLOCKSPRESET=$(CLOCKSPRESET) WTMI
+	$(Q)$(MAKE) --no-print-directory -C $(WTP) WTMI_IMG=$(WTMI_IMG) DDR_TOPOLOGY=$(DDR_TOPOLOGY) CLOCKSPRESET=$(CLOCKSPRESET) WTMI
 
 $(BUILD_PLAT)/wtmi.bin: $(WTMI_MULTI_IMG)
 	$(Q)cp -a $(WTMI_MULTI_IMG) $(BUILD_PLAT)/wtmi.bin
@@ -150,40 +158,40 @@
 $(TIMDDRTOOL): FORCE
 	$(if $(value MV_DDR_PATH),,$(error "Platform '${PLAT}' for ddr tool requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
 	$(if $(wildcard $(value MV_DDR_PATH)/*),,$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' directory does not exist"))
-	$(if $(shell test -s "$(value MV_DDR_PATH)/branch.txt" || git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid Marvell mv_ddr release tarball nor git repository"))
-	$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
+	$(if $(shell git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid mv-ddr-marvell git repository"))
+	$(Q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
 
-$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(DOIMAGETOOL) $(TIMBUILD) $(TIMDDRTOOL)
+$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL)
 	@$(ECHO_BLANK_LINE)
 	@echo "Building uart images"
 	$(Q)mkdir -p $(BUILD_PLAT)/$(BUILD_UART)
 	$(Q)cp -a $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/$(BUILD_UART)/wtmi.bin
 	$(Q)cp -a $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/$(BUILD_UART)/$(BOOT_IMAGE)
 	$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TIMBUILD) $(TIMBLDUARTARGS)
-	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(DOIMAGEUART_CFG)
-	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(DOIMAGEUART_CFG)
+	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIM_UART_CFG)
+	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIM_UART_CFG)
 ifeq ($(MARVELL_SECURE_BOOT),1)
-	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMNUARTCFG)
-	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMNUARTCFG)
+	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMN_UART_CFG)
+	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMN_UART_CFG)
 endif
-	$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(DOIMAGETOOL) -r $(DOIMAGEUART_CFG) -v -D
+	$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TBB) -r $(TIM_UART_CFG) -v -D
 ifeq ($(MARVELL_SECURE_BOOT),1)
-	$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(DOIMAGETOOL) -r $(TIMNUARTCFG)
+	$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TBB) -r $(TIMN_UART_CFG)
 endif
-	$(Q)tar czf $(BUILD_PLAT)/$(UART_IMAGE) -C $(BUILD_PLAT) $(BUILD_UART)/$(TIM_IMAGE) $(BUILD_UART)/wtmi_h.bin $(BUILD_UART)/boot-image_h.bin
+	$(Q)tar czf $(BUILD_PLAT)/$(UART_IMAGE) -C $(BUILD_PLAT) $(UART_IMAGES)
 	@$(ECHO_BLANK_LINE)
 	@echo "Built $@ successfully"
 	@$(ECHO_BLANK_LINE)
 
-$(BUILD_PLAT)/$(FLASH_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(DOIMAGETOOL) $(TIMBUILD) $(TIMDDRTOOL) $(TIM2IMG)
+$(BUILD_PLAT)/$(FLASH_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL) $(TIM2IMG)
 	@$(ECHO_BLANK_LINE)
 	@echo "Building flash image"
 	$(Q)cd $(BUILD_PLAT) && $(TIMBUILD) $(TIMBLDARGS)
-	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(DOIMAGE_CFG)
-	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(DOIMAGE_CFG)
+	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIM_CFG)
+	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIM_CFG)
 ifeq ($(MARVELL_SECURE_BOOT),1)
-	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMNCFG)
-	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMNCFG)
+	$(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMN_CFG)
+	$(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMN_CFG)
 	@$(ECHO_BLANK_LINE)
 	@echo "=======================================================";
 	@echo "  Secure boot. Encrypting wtmi and boot-image";
@@ -201,11 +209,11 @@
 	-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
 	-iv `cat $(IMAGESPATH)/iv.txt` -p
 endif
-	$(Q)cd $(BUILD_PLAT) && $(DOIMAGETOOL) -r $(DOIMAGE_CFG) -v -D
+	$(Q)cd $(BUILD_PLAT) && $(TBB) -r $(TIM_CFG) -v -D
 ifeq ($(MARVELL_SECURE_BOOT),1)
-	$(Q)cd $(BUILD_PLAT) && $(DOIMAGETOOL) -r $(TIMNCFG)
-	$(Q)sed -i 's|wtmi.bin|$(WTMI_ENC_IMG)|1' $(TIMNCFG)
-	$(Q)sed -i 's|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1' $(TIMNCFG)
+	$(Q)cd $(BUILD_PLAT) && $(TBB) -r $(TIMN_CFG)
+	$(Q)sed -i 's|wtmi.bin|$(WTMI_ENC_IMG)|1' $(TIMN_CFG)
+	$(Q)sed -i 's|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1' $(TIMN_CFG)
 endif
 	$(Q)cd $(BUILD_PLAT) && $(TIM2IMG) $(TIM2IMGARGS) -o $(BUILD_PLAT)/$(FLASH_IMAGE)
 	@$(ECHO_BLANK_LINE)
@@ -216,8 +224,8 @@
 
 .PHONY: mrvl_clean
 mrvl_clean:
-	-$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) MV_DDR_PATH=$(MV_DDR_PATH) clean
-	-$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak clean
+	-$(Q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) clean
+	-$(Q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak clean
 ifdef CRYPTOPP_PATH
 	-$(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile clean
 endif
diff --git a/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
new file mode 100644
index 0000000..f79516f
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <asm_macros.S>
+#include <platform_def.h>
+
+/*
+ * Below address in used only for reading, therefore no problem with concurrent
+ * Linux access.
+ */
+#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
+ #define MVEBU_XTAL_MODE_MASK		BIT(9)
+
+	/* -----------------------------------------------------
+	 * uint32_t get_ref_clk (void);
+	 *
+	 * returns reference clock in MHz (25 or 40)
+	 * -----------------------------------------------------
+	 */
+.globl	get_ref_clk
+func get_ref_clk
+	mov_imm	x0, MVEBU_TEST_PIN_LATCH_N
+	ldr	w0, [x0]
+	tst	w0, #MVEBU_XTAL_MODE_MASK
+	bne	40
+	mov	w0, #25
+	ret
+40:
+	mov	w0, #40
+	ret
+endfunc get_ref_clk
diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index 057ee2e..f19d96b 100644
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -163,14 +163,7 @@
 /*
  * PL011 related constants
  */
-#define PLAT_MARVELL_BOOT_UART_BASE		(MVEBU_REGS_BASE + 0x12000)
-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ	25804800
-
-#define PLAT_MARVELL_CRASH_UART_BASE		PLAT_MARVELL_BOOT_UART_BASE
-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ	PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
-
-#define PLAT_MARVELL_BL31_RUN_UART_BASE		PLAT_MARVELL_BOOT_UART_BASE
-#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ	PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+#define PLAT_MARVELL_UART_BASE			(MVEBU_REGS_BASE + 0x12000)
 
 /* Required platform porting definitions */
 #define PLAT_MAX_PWR_LVL			MPIDR_AFFLVL1
diff --git a/plat/marvell/armada/a3k/common/io_addr_dec.c b/plat/marvell/armada/a3k/common/io_addr_dec.c
index b27633c..fea7f81 100644
--- a/plat/marvell/armada/a3k/common/io_addr_dec.c
+++ b/plat/marvell/armada/a3k/common/io_addr_dec.c
@@ -67,17 +67,14 @@
 	mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base,
 		      win_id, dec_win->win_offset), ctrl);
 
-	INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x)",
+	INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x) remap(0x%x)\n",
 	     win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base,
 	     win_id, dec_win->win_offset)),
 	     mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base,
-			  win_id, dec_win->win_offset)));
-	if (win_id < dec_win->max_remap)
-		INFO(" remap(%x)\n",
-		     mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base,
-		     win_id, dec_win->win_offset)));
-	else
-		INFO("\n");
+			  win_id, dec_win->win_offset)),
+	     (win_id < dec_win->max_remap) ?
+		mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base,
+			     win_id, dec_win->win_offset)) : 0);
 }
 
 /* Set io decode window */
@@ -167,12 +164,11 @@
 			ERROR("Failed to set IO address decode\n");
 			return -1;
 		}
-		INFO("Set IO decode window successfully, base(0x%x)",
-		     io_dec_win->dec_reg_base);
-		INFO(" win_attr(%x) max_dram_win(%d) max_remap(%d)",
+		INFO("Set IO decode window successfully, base(0x%x)"
+		     " win_attr(%x) max_dram_win(%d) max_remap(%d)"
+		     " win_offset(%d)\n", io_dec_win->dec_reg_base,
 		     io_dec_win->win_attr, io_dec_win->max_dram_win,
-		     io_dec_win->max_remap);
-		INFO(" win_offset(%d)\n", io_dec_win->win_offset);
+		     io_dec_win->max_remap, io_dec_win->win_offset);
 	}
 
 	return 0;
diff --git a/plat/marvell/armada/a3k/common/plat_pm.c b/plat/marvell/armada/a3k/common/plat_pm.c
index 2bae37e..e2d15ab 100644
--- a/plat/marvell/armada/a3k/common/plat_pm.c
+++ b/plat/marvell/armada/a3k/common/plat_pm.c
@@ -590,6 +590,13 @@
 	return NULL;
 }
 
+#pragma weak mv_wake_up_src_config_get
+struct pm_wake_up_src_config *mv_wake_up_src_config_get(void)
+{
+	static struct pm_wake_up_src_config wake_up_src_cfg = {};
+	return &wake_up_src_cfg;
+}
+
 static void a3700_set_wake_up_source(void)
 {
 	struct pm_wake_up_src_config *wake_up_src;
diff --git a/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
index 5147dd5..eb00874 100644
--- a/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
+++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
@@ -41,8 +41,8 @@
 	len = sizeof(system_off_now);
 	system_off_now[len - 1] = add_xor_checksum(system_off_now, len);
 
-	console_16550_register(PLAT_MARVELL_BOOT_UART_BASE + 0x100,
-		PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, 115200, &console);
+	console_16550_register(PLAT_MARVELL_UART_BASE + 0x100,
+		PLAT_MARVELL_UART_CLK_IN_HZ, 115200, &console);
 
 	/* Send system_off_now to console */
 	for (i = 0; i < len; i++) {
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index 8a463ea..773b912 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -10,13 +10,14 @@
 MARVELL_DRV_BASE	:= drivers/marvell
 MARVELL_COMMON_BASE	:= plat/marvell/armada/common
 
-MARVELL_SVC_TEST		:= 0
+MARVELL_SVC_TEST	:= 0
 $(eval $(call add_define,MARVELL_SVC_TEST))
 
 ERRATA_A72_859971	:= 1
 
 # Enable MSS support for a8k family
 MSS_SUPPORT		:= 1
+$(eval $(call add_define,MSS_SUPPORT))
 
 # Disable EL3 cache for power management
 BL31_CACHE_DISABLE	:= 0
@@ -81,6 +82,7 @@
 
 PLAT_INCLUDES		:=	-I$(BOARD_DIR)				\
 				-I$(BOARD_DIR)/board			\
+				-I$(CURDIR)/drivers/marvell		\
 				-I$(PLAT_COMMON_BASE)/include		\
 				-I$(PLAT_INCLUDE_BASE)/common
 
@@ -112,11 +114,17 @@
 				$(MARVELL_DRV_BASE)/amb_adec.c	\
 				$(MARVELL_DRV_BASE)/ccu.c	\
 				$(MARVELL_DRV_BASE)/cache_llc.c	\
-				$(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
-				$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
-				$(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \
+				$(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c	\
+				$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c	\
+				$(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c	\
+				$(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c	\
+				$(MARVELL_DRV_BASE)/ddr_phy_access.c	\
 				drivers/rambus/trng_ip_76.c
 
+ifeq (${MSS_SUPPORT}, 1)
+MARVELL_DRV		+=	$(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c
+endif
+
 BL31_PORTING_SOURCES	:=	$(BOARD_DIR)/board/marvell_plat_config.c
 
 ifeq ($(SYSTEM_POWER_SUPPORT),1)
@@ -139,6 +147,8 @@
 # Add trace functionality for PM
 BL31_SOURCES		+=	$(PLAT_COMMON_BASE)/plat_pm_trace.c
 
+
+ifeq (${MSS_SUPPORT}, 1)
 # Force builds with BL2 image on a80x0 platforms
 ifndef SCP_BL2
  $(error "Error: SCP_BL2 image is mandatory for a8k family")
@@ -146,6 +156,7 @@
 
 # MSS (SCP) build
 include $(PLAT_COMMON_BASE)/mss/mss_a8k.mk
+endif
 
 # BLE (ROM context execution code, AKA binary extension)
 BLE_PATH	?=  $(PLAT_COMMON_BASE)/ble
diff --git a/plat/marvell/armada/a8k/common/ble/ble.mk b/plat/marvell/armada/a8k/common/ble/ble.mk
index d6d72c1..87e2ce0 100644
--- a/plat/marvell/armada/a8k/common/ble/ble.mk
+++ b/plat/marvell/armada/a8k/common/ble/ble.mk
@@ -3,8 +3,6 @@
 # SPDX-License-Identifier:     BSD-3-Clause
 # https://spdx.org/licenses
 
-MV_DDR_PATH		?=	drivers/marvell/mv_ddr
-
 MV_DDR_LIB		=	$(BUILD_PLAT)/ble/mv_ddr_lib.a
 LIBC_LIB		=	$(BUILD_PLAT)/lib/libc.a
 BLE_LIBS		=	$(MV_DDR_LIB) $(LIBC_LIB)
@@ -18,14 +16,19 @@
 				$(PLAT_MARVELL)/common/plat_delay_timer.c	\
 				$(PLAT_MARVELL)/common/marvell_console.c
 
-PLAT_INCLUDES		+= 	-I$(MV_DDR_PATH)				\
-				-I$(CURDIR)/include				\
+MV_DDR_INCLUDES		:=	-I$(CURDIR)/include				\
 				-I$(CURDIR)/include/arch/aarch64		\
 				-I$(CURDIR)/include/lib/libc			\
-				-I$(CURDIR)/include/lib/libc/aarch64		\
-				-I$(CURDIR)/drivers/marvell
+				-I$(CURDIR)/include/lib/libc/aarch64
 
 BLE_LINKERFILE		:=	$(BLE_PATH)/ble.ld.S
 
+BLE_OBJS := $(addprefix $(BUILD_PLAT)/ble/,$(call SOURCES_TO_OBJS,$(BLE_SOURCES)))
+$(BLE_OBJS): PLAT_INCLUDES += -I$(MV_DDR_PATH)
+$(BLE_OBJS): $(MV_DDR_LIB)
+
 $(MV_DDR_LIB): FORCE
-	@+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(PLAT_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(BUILD_PLAT)/ble
+	$(if $(value MV_DDR_PATH),,$(error "Platform '$(PLAT)' for BLE requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
+	$(if $(wildcard $(value MV_DDR_PATH)/*),,$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' directory does not exist"))
+	$(if $(shell git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid mv-ddr-marvell git repository"))
+	@+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(MV_DDR_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(BUILD_PLAT)/ble
diff --git a/plat/marvell/armada/a8k/common/include/a8k_plat_def.h b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h
index de80315..3a0fd4b 100644
--- a/plat/marvell/armada/a8k/common/include/a8k_plat_def.h
+++ b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h
@@ -64,7 +64,8 @@
 #define MVEBU_AP_GPIO_DATA_IN		(MVEBU_AP_GPIO_REGS + 0x10)
 #define MVEBU_AP_I2C_BASE		(MVEBU_REGS_BASE + 0x511000)
 #define MVEBU_CP0_I2C_BASE		(MVEBU_CP_REGS_BASE(0) + 0x701000)
-#define MVEBU_AP_EXT_TSEN_BASE		(MVEBU_RFU_BASE + 0x8084)
+#define MVEBU_AP_GEN_MGMT_BASE		(MVEBU_RFU_BASE + 0x8000)
+#define MVEBU_AP_EXT_TSEN_BASE		(MVEBU_AP_GEN_MGMT_BASE + 0x84)
 
 #define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win)	(MVEBU_REGS_BASE_AP(ap) + \
 							0x20080 + ((win) * 0x8))
diff --git a/plat/marvell/armada/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h
index 7d85059..45860ba 100644
--- a/plat/marvell/armada/a8k/common/include/platform_def.h
+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
@@ -168,14 +168,8 @@
 /*
  * PL011 related constants
  */
-#define PLAT_MARVELL_BOOT_UART_BASE		(MVEBU_REGS_BASE + 0x512000)
-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ	200000000
-
-#define PLAT_MARVELL_CRASH_UART_BASE		PLAT_MARVELL_BOOT_UART_BASE
-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ	PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
-
-#define PLAT_MARVELL_BL31_RUN_UART_BASE		PLAT_MARVELL_BOOT_UART_BASE
-#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ	PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+#define PLAT_MARVELL_UART_BASE			(MVEBU_REGS_BASE + 0x512000)
+#define PLAT_MARVELL_UART_CLK_IN_HZ		200000000
 
 /* Recovery image enable */
 #define PLAT_RECOVERY_IMAGE_ENABLE		0
diff --git a/plat/marvell/armada/a8k/common/mss/mss_a8k.mk b/plat/marvell/armada/a8k/common/mss/mss_a8k.mk
index d8d4921..315fc87 100644
--- a/plat/marvell/armada/a8k/common/mss/mss_a8k.mk
+++ b/plat/marvell/armada/a8k/common/mss/mss_a8k.mk
@@ -11,7 +11,8 @@
 BL2_SOURCES		+=	$(A8K_MSS_SOURCE)/mss_bl2_setup.c \
 				$(MARVELL_MOCHI_DRV)
 
-BL31_SOURCES		+=	$(A8K_MSS_SOURCE)/mss_pm_ipc.c
+BL31_SOURCES		+=	$(A8K_MSS_SOURCE)/mss_pm_ipc.c \
+				$(A8K_MSS_SOURCE)/mss_bl31_setup.c
 
 PLAT_INCLUDES		+=	-I$(A8K_MSS_SOURCE)
 
diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
index 71fa2b8..dee2d5b 100644
--- a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
@@ -16,7 +16,7 @@
 
 #include <armada_common.h>
 #include <marvell_plat_priv.h> /* timer functionality */
-
+#include "mss_defs.h"
 #include "mss_scp_bootloader.h"
 
 /* MSS windows configuration */
@@ -30,10 +30,6 @@
 #define MSS_EXTERNAL_ADDR_MASK		0xfffffff
 #define MSS_INTERNAL_ACCESS_BIT		28
 
-#define MSS_AP_REGS_OFFSET		0x580000
-#define MSS_CP_SRAM_OFFSET		0x220000
-#define MSS_CP_REGS_OFFSET		0x280000
-
 struct addr_map_win ccu_mem_map[] = {
 	{MVEBU_CP_REGS_BASE(0), 0x4000000, IO_0_TID}
 };
@@ -130,11 +126,7 @@
 
 uintptr_t bl2_plat_get_cp_mss_sram(int ap_idx, int cp_idx)
 {
-	if (is_secure()) {
-		return MVEBU_CP_REGS_BASE(cp_idx) + MSS_CP_SRAM_OFFSET;
-	}
-
-	return 0; /* SRAM will not be used */
+	return MVEBU_CP_REGS_BASE(cp_idx) + MSS_CP_SRAM_OFFSET;
 }
 
 uintptr_t bl2_plat_get_ap_mss_regs(int ap_idx)
diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c
new file mode 100644
index 0000000..52a8929
--- /dev/null
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <platform_def.h>
+
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <armada_common.h>
+
+#include "mss_defs.h"
+
+void mss_start_cp_cm3(int cp)
+{
+	uint32_t magic;
+	uintptr_t sram = MVEBU_CP_REGS_BASE(cp) + MSS_CP_SRAM_OFFSET;
+	uintptr_t regs = MVEBU_CP_REGS_BASE(cp) + MSS_CP_REGS_OFFSET;
+
+	magic = mmio_read_32(sram);
+
+	/* Make sure the FW was loaded */
+	if (magic != MSS_FW_READY_MAGIC) {
+		return;
+	}
+
+	NOTICE("Starting CP%d MSS CPU\n", cp);
+	/* remove the magic */
+	mmio_write_32(sram, 0);
+	/* Release M3 from reset */
+	mmio_write_32(MSS_M3_RSTCR(regs),
+		      (MSS_M3_RSTCR_RST_OFF << MSS_M3_RSTCR_RST_OFFSET));
+}
diff --git a/plat/marvell/armada/a8k/common/mss/mss_defs.h b/plat/marvell/armada/a8k/common/mss/mss_defs.h
new file mode 100644
index 0000000..6956461
--- /dev/null
+++ b/plat/marvell/armada/a8k/common/mss/mss_defs.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef MSS_DEFS_H
+#define MSS_DEFS_H
+
+#define MSS_DMA_SRCBR(base)		(base + 0xC0)
+#define MSS_DMA_DSTBR(base)		(base + 0xC4)
+#define MSS_DMA_CTRLR(base)		(base + 0xC8)
+#define MSS_M3_RSTCR(base)		(base + 0xFC)
+
+#define MSS_DMA_CTRLR_SIZE_OFFSET	(0)
+#define MSS_DMA_CTRLR_REQ_OFFSET	(15)
+#define MSS_DMA_CTRLR_REQ_SET		(1)
+#define MSS_DMA_CTRLR_ACK_OFFSET	(12)
+#define MSS_DMA_CTRLR_ACK_MASK		(0x1)
+#define MSS_DMA_CTRLR_ACK_READY		(1)
+#define MSS_M3_RSTCR_RST_OFFSET		(0)
+#define MSS_M3_RSTCR_RST_OFF		(1)
+
+#define MSS_FW_READY_MAGIC		0x46575144 /* FWRD */
+
+#define MSS_AP_REGS_OFFSET		0x00580000
+#define MSS_CP_SRAM_OFFSET		0x00220000
+#define MSS_CP_REGS_OFFSET		0x00280000
+
+void mss_start_cp_cm3(int cp);
+
+#endif /* MSS_DEFS_H */
diff --git a/plat/marvell/armada/a8k/common/plat_bl31_setup.c b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
index 552c9b2..db85cce 100644
--- a/plat/marvell/armada/a8k/common/plat_bl31_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
@@ -16,8 +16,11 @@
 #include <marvell_pm.h>
 #include <mc_trustzone/mc_trustzone.h>
 #include <plat_marvell.h>
+#if MSS_SUPPORT
 #include <mss_ipc_drv.h>
 #include <mss_mem.h>
+#include <mss_defs.h>
+#endif
 
 /* In Armada-8k family AP806/AP807, CP0 connected to PIDI
  * and CP1 connected to IHB via MCI #0
@@ -51,6 +54,7 @@
 	mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000);
 }
 
+#if MSS_SUPPORT
 void marvell_bl31_mss_init(void)
 {
 	struct mss_pm_ctrl_block *mss_pm_crtl =
@@ -70,6 +74,7 @@
 	if (mss_pm_crtl->ipc_state == IPC_INITIALIZED)
 		mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE);
 }
+#endif
 
 _Bool is_pm_fw_running(void)
 {
@@ -120,16 +125,22 @@
 			   STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
 
 		marvell_bl31_mpp_init(cp);
+
+#if MSS_SUPPORT
+		/* Release CP MSS CPU from reset once the CP init is done */
+		mss_start_cp_cm3(cp);
+#endif
 	}
 
 	for (cp = 1; cp < CP_COUNT; cp++)
 		mci_link_tune(cp - 1);
 
+#if MSS_SUPPORT
 	/* initialize IPC between MSS and ATF */
 	if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
 	    mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
 		marvell_bl31_mss_init();
-
+#endif
 	/* Configure GPIO */
 	marvell_gpio_config();
 
diff --git a/plat/marvell/armada/a8k/common/plat_ble_setup.c b/plat/marvell/armada/a8k/common/plat_ble_setup.c
index 4114327..9c5ee15 100644
--- a/plat/marvell/armada/a8k/common/plat_ble_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_ble_setup.c
@@ -14,6 +14,7 @@
 #include <drivers/marvell/mochi/cp110_setup.h>
 
 #include <armada_common.h>
+#include <efuse_def.h>
 #include <mv_ddr_if.h>
 #include <mvebu_def.h>
 #include <plat_marvell.h>
@@ -27,7 +28,6 @@
 #define MMAP_RESTORE_SAVED		1
 
 /* SAR clock settings */
-#define MVEBU_AP_GEN_MGMT_BASE		(MVEBU_RFU_BASE + 0x8000)
 #define MVEBU_AP_SAR_REG_BASE(r)	(MVEBU_AP_GEN_MGMT_BASE + 0x200 +\
 								((r) << 2))
 
@@ -82,11 +82,6 @@
 					 (0x1 << AVS_SOFT_RESET_OFFSET) | \
 					 (0x1 << AVS_ENABLE_OFFSET))
 
-#define MVEBU_AP_EFUSE_SRV_CTRL_REG	(MVEBU_AP_GEN_MGMT_BASE + 0x8)
-#define EFUSE_SRV_CTRL_LD_SELECT_OFFS	6
-#define EFUSE_SRV_CTRL_LD_SEL_USER_MASK	(1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
-
-
 /*
  * - Identification information in the LD-0 eFuse:
  *	DRO:           LD0[74:65] - Not used by the SW
@@ -96,14 +91,7 @@
  *	Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1
  *				  resulting in 2 CPUs active only (7020)
  */
-#define MVEBU_AP_LD_EFUSE_BASE		(MVEBU_AP_GEN_MGMT_BASE + 0xF00)
-/* Bits [94:63] - 32 data bits total */
-#define MVEBU_AP_LD0_94_63_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0x8)
-/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */
-#define MVEBU_AP_LD0_125_95_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0xC)
-/* Bits [220:189] - 32 data bits total */
-#define MVEBU_AP_LD0_220_189_EFUSE_OFFS	(MVEBU_AP_LD_EFUSE_BASE + 0x18)
-/* Offsets for the above 2 fields combined into single 64-bit value [125:63] */
+/* Offsets for 2 efuse fields combined into single 64-bit value [125:63] */
 #define EFUSE_AP_LD0_DRO_OFFS		2		/* LD0[74:65] */
 #define EFUSE_AP_LD0_DRO_MASK		0x3FF
 #define EFUSE_AP_LD0_REVID_OFFS		12		/* LD0[78:75] */
@@ -376,20 +364,20 @@
 	uint8_t	 avs_data_bits, min_sw_ver, svc_fields;
 	unsigned int ap_type;
 
-	/* Set access to LD0 */
+	/* Get test EERPOM data */
 	avs_workpoint = avs_update_from_eeprom(0);
 	if (avs_workpoint)
 		goto set_aws_wp;
 
 	/* Set access to LD0 */
 	reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
-	reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_OFFS;
+	reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK;
 	mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
 
 	/* Obtain the value of LD0[125:63] */
-	efuse = mmio_read_32(MVEBU_AP_LD0_125_95_EFUSE_OFFS);
+	efuse = mmio_read_32(MVEBU_AP_LDX_125_95_EFUSE_OFFS);
 	efuse <<= 32;
-	efuse |= mmio_read_32(MVEBU_AP_LD0_94_63_EFUSE_OFFS);
+	efuse |= mmio_read_32(MVEBU_AP_LDX_94_63_EFUSE_OFFS);
 
 	/* SW Revision:
 	 * Starting from SW revision 1 the SVC flow is supported.
@@ -452,7 +440,7 @@
 			perr[i] = 1; /* register the error */
 	}
 
-	single_cluster = mmio_read_32(MVEBU_AP_LD0_220_189_EFUSE_OFFS);
+	single_cluster = mmio_read_32(MVEBU_AP_LDX_220_189_EFUSE_OFFS);
 	single_cluster = (single_cluster >> EFUSE_AP_LD0_CLUSTER_DOWN_OFFS) & 1;
 
 	device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
diff --git a/plat/marvell/armada/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c
index 96e95c2..9ea9276 100644
--- a/plat/marvell/armada/a8k/common/plat_pm.c
+++ b/plat/marvell/armada/a8k/common/plat_pm.c
@@ -18,7 +18,9 @@
 
 #include <armada_common.h>
 #include <marvell_pm.h>
+#if MSS_SUPPORT
 #include <mss_pm_ipc.h>
+#endif
 #include <plat_marvell.h>
 #include <plat_pm_trace.h>
 
@@ -396,6 +398,7 @@
 	/* Power up CPU (CPUs 1-3 are powered off at start of BLE) */
 	plat_marvell_cpu_powerup(mpidr);
 
+#if MSS_SUPPORT
 	if (is_pm_fw_running()) {
 		unsigned int target =
 				((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2));
@@ -417,11 +420,12 @@
 
 		/* trace message */
 		PM_TRACE(TRACE_PWR_DOMAIN_ON | target);
-	} else {
+	} else
+#endif
+	{
 		/* proprietary CPU ON exection flow */
 		plat_marvell_cpu_on(mpidr);
 	}
-
 	return 0;
 }
 
@@ -441,6 +445,7 @@
  */
 static void a8k_pwr_domain_off(const psci_power_state_t *target_state)
 {
+#if MSS_SUPPORT
 	if (is_pm_fw_running()) {
 		unsigned int idx = plat_my_core_pos();
 
@@ -466,6 +471,7 @@
 	} else {
 		INFO("%s: is not supported without SCP\n", __func__);
 	}
+#endif
 }
 
 /* Get PM config to power off the SoC */
@@ -586,6 +592,7 @@
  */
 static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
+#if MSS_SUPPORT
 	if (is_pm_fw_running()) {
 		unsigned int idx;
 
@@ -610,7 +617,9 @@
 
 		/* trace message */
 		PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND);
-	} else {
+	} else
+#endif
+	{
 		uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
 
 		INFO("Suspending to RAM\n");
diff --git a/plat/marvell/armada/a8k/common/plat_pm_trace.c b/plat/marvell/armada/a8k/common/plat_pm_trace.c
index f589ff3..e02a893 100644
--- a/plat/marvell/armada/a8k/common/plat_pm_trace.c
+++ b/plat/marvell/armada/a8k/common/plat_pm_trace.c
@@ -8,10 +8,11 @@
 #include <lib/mmio.h>
 #include <plat/common/platform.h>
 
+#if MSS_SUPPORT
 #include <mss_mem.h>
-#include <plat_pm_trace.h>
 
 #ifdef PM_TRACE_ENABLE
+#include <plat_pm_trace.h>
 
 /* core trace APIs */
 core_trace_func funcTbl[PLATFORM_CORE_COUNT] = {
@@ -90,3 +91,4 @@
 		     AP_MSS_ATF_TRACE_SIZE_MASK));
 }
 #endif /* PM_TRACE_ENABLE */
+#endif /* MSS_SUPPORT */
diff --git a/plat/marvell/armada/common/aarch64/marvell_helpers.S b/plat/marvell/armada/common/aarch64/marvell_helpers.S
index b798f17..3038ec0 100644
--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
@@ -63,8 +63,16 @@
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_init
-	mov_imm	x0, PLAT_MARVELL_CRASH_UART_BASE
-	mov_imm	x1, PLAT_MARVELL_CRASH_UART_CLK_IN_HZ
+#ifdef PLAT_a3700
+	mov	x1, x30
+	bl	get_ref_clk
+	mov	x30, x1
+	mov_imm	x1, 1000000
+	mul	x1, x0, x1
+#else
+	mov_imm	x1, PLAT_MARVELL_UART_CLK_IN_HZ
+#endif
+	mov_imm	x0, PLAT_MARVELL_UART_BASE
 	mov_imm	x2, MARVELL_CONSOLE_BAUDRATE
 #ifdef PLAT_a3700
 	b	console_a3700_core_init
@@ -81,7 +89,7 @@
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_putc
-	mov_imm	x1, PLAT_MARVELL_CRASH_UART_BASE
+	mov_imm	x1, PLAT_MARVELL_UART_BASE
 #ifdef PLAT_a3700
 
 	b	console_a3700_core_putc
@@ -99,7 +107,7 @@
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_flush
-	mov_imm	x0, PLAT_MARVELL_CRASH_UART_BASE
+	mov_imm	x0, PLAT_MARVELL_UART_BASE
 #ifdef PLAT_a3700
 	b	console_a3700_core_flush
 #else
diff --git a/plat/marvell/armada/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk
index 04eb51c..f0e6edf 100644
--- a/plat/marvell/armada/common/marvell_common.mk
+++ b/plat/marvell/armada/common/marvell_common.mk
@@ -6,10 +6,6 @@
 MARVELL_PLAT_BASE		:= plat/marvell/armada
 MARVELL_PLAT_INCLUDE_BASE	:= include/plat/marvell/armada
 
-include plat/marvell/version.mk
-
-VERSION_STRING			+=(Marvell-${SUBVERSION})
-
 SEPARATE_CODE_AND_RODATA	:= 1
 
 # flag to switch from PLL to ARO
diff --git a/plat/marvell/armada/common/marvell_console.c b/plat/marvell/armada/common/marvell_console.c
index c84b004..ef54bff 100644
--- a/plat/marvell/armada/common/marvell_console.c
+++ b/plat/marvell/armada/common/marvell_console.c
@@ -14,6 +14,7 @@
 
 #ifdef PLAT_a3700
 #include <drivers/marvell/uart/a3700_console.h>
+#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)
 #define console_marvell_register console_a3700_register
 #else
 #include <drivers/ti/uart/uart_16550.h>
@@ -31,8 +32,8 @@
 void marvell_console_boot_init(void)
 {
 	int rc =
-	console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
-				 PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
+	console_marvell_register(PLAT_MARVELL_UART_BASE,
+				 PLAT_MARVELL_UART_CLK_IN_HZ,
 				 MARVELL_CONSOLE_BAUDRATE,
 				 &marvell_boot_console);
 	if (rc == 0) {
@@ -58,8 +59,8 @@
 void marvell_console_runtime_init(void)
 {
 	int rc =
-	console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
-				 PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
+	console_marvell_register(PLAT_MARVELL_UART_BASE,
+				 PLAT_MARVELL_UART_CLK_IN_HZ,
 				 MARVELL_CONSOLE_BAUDRATE,
 				 &marvell_runtime_console);
 	if (rc == 0)
diff --git a/plat/marvell/armada/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c
index 64187fb..c4c5c0e 100644
--- a/plat/marvell/armada/common/mrvl_sip_svc.c
+++ b/plat/marvell/armada/common/mrvl_sip_svc.c
@@ -16,6 +16,8 @@
 #include <plat_marvell.h>
 
 #include "comphy/phy-comphy-cp110.h"
+#include "secure_dfx_access/dfx.h"
+#include "ddr_phy_access.h"
 #include <stdbool.h>
 
 /* #define DEBUG_COMPHY */
@@ -37,6 +39,9 @@
 #define MV_SIP_LLC_ENABLE	0x82000011
 #define MV_SIP_PMU_IRQ_ENABLE	0x82000012
 #define MV_SIP_PMU_IRQ_DISABLE	0x82000013
+#define MV_SIP_DFX		0x82000014
+#define MV_SIP_DDR_PHY_WRITE	0x82000015
+#define MV_SIP_DDR_PHY_READ	0x82000016
 
 /* TRNG */
 #define MV_SIP_RNG_64		0xC200FF11
@@ -45,6 +50,9 @@
 #define MVEBU_COMPHY_OFFSET	0x441000
 #define MVEBU_CP_BASE_MASK	(~0xffffff)
 
+/* Common PHY register */
+#define COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS	0x120a2c
+
 /* This macro is used to identify COMPHY related calls from SMC function ID */
 #define is_comphy_fid(fid)	\
 	((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET)
@@ -71,8 +79,7 @@
 			       void *handle,
 			       u_register_t flags)
 {
-	u_register_t ret;
-	uint32_t w2[2] = {0, 0};
+	u_register_t ret, read, x5 = x1;
 	int i;
 
 	debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
@@ -86,6 +93,7 @@
 			SMC_RET1(handle, SMC_UNK);
 		}
 
+		x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS;
 		x1 += MVEBU_COMPHY_OFFSET;
 
 		if (x2 >= MAX_LANE_NR) {
@@ -100,7 +108,7 @@
 	/* Comphy related FID's */
 	case MV_SIP_COMPHY_POWER_ON:
 		/* x1:  comphy_base, x2: comphy_index, x3: comphy_mode */
-		ret = mvebu_cp110_comphy_power_on(x1, x2, x3);
+		ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5);
 		SMC_RET1(handle, ret);
 	case MV_SIP_COMPHY_POWER_OFF:
 		/* x1:  comphy_base, x2: comphy_index */
@@ -136,9 +144,33 @@
 		mvebu_pmu_interrupt_disable();
 		SMC_RET1(handle, 0);
 #endif
+	case MV_SIP_DFX:
+		if (x1 >= MV_SIP_DFX_THERMAL_INIT &&
+		    x1 <= MV_SIP_DFX_THERMAL_SEL_CHANNEL) {
+			ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3);
+			SMC_RET2(handle, ret, read);
+		}
+		if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) {
+			ret = mvebu_dfx_misc_handle(x1, &read, x2, x3);
+			SMC_RET2(handle, ret, read);
+		}
+
+		SMC_RET1(handle, SMC_UNK);
+	case MV_SIP_DDR_PHY_WRITE:
+		ret = mvebu_ddr_phy_write(x1, x2);
+		SMC_RET1(handle, ret);
+	case MV_SIP_DDR_PHY_READ:
+		read = 0;
+		ret = mvebu_ddr_phy_read(x1, (uint16_t *)&read);
+		SMC_RET2(handle, ret, read);
 	case MV_SIP_RNG_64:
-		ret = eip76_rng_get_random((uint8_t *)&w2, 4 * (x1 % 2 + 1));
-		SMC_RET3(handle, ret, w2[0], w2[1]);
+		if ((x1 % 2 + 1) > sizeof(read)/4) {
+			ERROR("%s: Maximum %ld random bytes per SMC call\n",
+			      __func__, sizeof(read));
+			SMC_RET1(handle, SMC_UNK);
+		}
+		ret = eip76_rng_get_random((uint8_t *)&read, 4 * (x1 % 2 + 1));
+		SMC_RET2(handle, ret, read);
 	default:
 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
 		SMC_RET1(handle, SMC_UNK);
diff --git a/plat/marvell/armada/common/mss/mss_scp_bootloader.c b/plat/marvell/armada/common/mss/mss_scp_bootloader.c
index f669a77..fbede1b 100644
--- a/plat/marvell/armada/common/mss/mss_scp_bootloader.c
+++ b/plat/marvell/armada/common/mss/mss_scp_bootloader.c
@@ -19,22 +19,9 @@
 #include <mss_scp_bootloader.h>
 #include <mss_ipc_drv.h>
 #include <mss_mem.h>
+#include <mss_defs.h>
 #include <mss_scp_bl2_format.h>
 
-#define MSS_DMA_SRCBR(base)		(base + 0xC0)
-#define MSS_DMA_DSTBR(base)		(base + 0xC4)
-#define MSS_DMA_CTRLR(base)		(base + 0xC8)
-#define MSS_M3_RSTCR(base)		(base + 0xFC)
-
-#define MSS_DMA_CTRLR_SIZE_OFFSET	(0)
-#define MSS_DMA_CTRLR_REQ_OFFSET	(15)
-#define MSS_DMA_CTRLR_REQ_SET		(1)
-#define MSS_DMA_CTRLR_ACK_OFFSET	(12)
-#define MSS_DMA_CTRLR_ACK_MASK		(0x1)
-#define MSS_DMA_CTRLR_ACK_READY		(1)
-#define MSS_M3_RSTCR_RST_OFFSET		(0)
-#define MSS_M3_RSTCR_RST_OFF		(1)
-
 #define MSS_DMA_TIMEOUT			1000
 #define MSS_EXTERNAL_SPACE		0x50000000
 #define MSS_EXTERNAL_ADDR_MASK		0xfffffff
@@ -85,9 +72,9 @@
 		/* Poll DMA_ACK at MSS_DMACTLR until it is ready */
 		timeout = MSS_DMA_TIMEOUT;
 		while (timeout > 0U) {
-			if ((mmio_read_32(MSS_DMA_CTRLR(mss_regs)) >>
-					  (MSS_DMA_CTRLR_ACK_OFFSET &
-					   MSS_DMA_CTRLR_ACK_MASK))
+			if (((mmio_read_32(MSS_DMA_CTRLR(mss_regs)) >>
+					  MSS_DMA_CTRLR_ACK_OFFSET) &
+					  MSS_DMA_CTRLR_ACK_MASK)
 					  == MSS_DMA_CTRLR_ACK_READY) {
 				break;
 			}
@@ -161,15 +148,20 @@
 
 	bl2_plat_configure_mss_windows(mss_regs);
 
-	/* Wipe the MSS SRAM after using it as copy buffer */
-	if (sram) {
+	if (sram != 0) {
+		/* Wipe the MSS SRAM after using it as copy buffer */
 		memset((void *)sram, 0, MSS_SRAM_SIZE);
+		NOTICE("CP MSS startup is postponed\n");
+		/* FW loaded, but CPU startup postponed until final CP setup */
+		mmio_write_32(sram, MSS_FW_READY_MAGIC);
+		dsb();
+	} else {
+		/* Release M3 from reset */
+		mmio_write_32(MSS_M3_RSTCR(mss_regs),
+			      (MSS_M3_RSTCR_RST_OFF <<
+			       MSS_M3_RSTCR_RST_OFFSET));
 	}
 
-	/* Release M3 from reset */
-	mmio_write_32(MSS_M3_RSTCR(mss_regs),
-		     (MSS_M3_RSTCR_RST_OFF << MSS_M3_RSTCR_RST_OFFSET));
-
 	NOTICE("Done\n");
 
 	return 0;
diff --git a/plat/marvell/version.mk b/plat/marvell/version.mk
deleted file mode 100644
index bb22255..0000000
--- a/plat/marvell/version.mk
+++ /dev/null
@@ -1 +0,0 @@
-SUBVERSION = devel-18.12.2
diff --git a/plat/mediatek/mt8192/plat_mt_gic.c b/plat/mediatek/common/drivers/gic600/mt_gic_v3.c
similarity index 100%
rename from plat/mediatek/mt8192/plat_mt_gic.c
rename to plat/mediatek/common/drivers/gic600/mt_gic_v3.c
diff --git a/plat/mediatek/mt8192/include/mt_gic_v3.h b/plat/mediatek/common/drivers/gic600/mt_gic_v3.h
similarity index 100%
rename from plat/mediatek/mt8192/include/mt_gic_v3.h
rename to plat/mediatek/common/drivers/gic600/mt_gic_v3.h
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.c b/plat/mediatek/common/drivers/gpio/mtgpio_common.c
new file mode 100644
index 0000000..89977a5
--- /dev/null
+++ b/plat/mediatek/common/drivers/gpio/mtgpio_common.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/gpio.h>
+#include <lib/mmio.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ *Macro Definition
+ ******************************************************************************/
+#define GPIO_MODE_BITS		4
+#define MAX_GPIO_MODE_PER_REG	8
+#define MAX_GPIO_REG_BITS	32
+#define DIR_BASE		(GPIO_BASE + 0x000)
+#define DOUT_BASE		(GPIO_BASE + 0x100)
+#define DIN_BASE		(GPIO_BASE + 0x200)
+#define MODE_BASE		(GPIO_BASE + 0x300)
+#define SET			0x4
+#define CLR			0x8
+
+static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
+{
+	uint32_t pos, bit;
+
+	assert(pin < MAX_GPIO_PIN);
+	assert(dir < MT_GPIO_DIR_MAX);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	if (dir == MT_GPIO_DIR_IN) {
+		mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
+	} else {
+		mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
+	}
+}
+
+static int mt_get_gpio_dir_chip(uint32_t pin)
+{
+	uint32_t pos, bit;
+	uint32_t reg;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	reg = mmio_read_32(DIR_BASE + 0x10U * pos);
+	return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
+}
+
+static void mt_set_gpio_out_chip(uint32_t pin, int output)
+{
+	uint32_t pos, bit;
+
+	assert(pin < MAX_GPIO_PIN);
+	assert(output < MT_GPIO_OUT_MAX);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	if (output == MT_GPIO_OUT_ZERO) {
+		mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
+	} else {
+		mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
+	}
+}
+
+static int mt_get_gpio_in_chip(uint32_t pin)
+{
+	uint32_t pos, bit;
+	uint32_t reg;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	reg = mmio_read_32(DIN_BASE + 0x10U * pos);
+	return (((reg & (1U << bit)) != 0U) ? 1 : 0);
+}
+
+static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
+			       int select)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 + (gpio_info.base & 0xf0);
+	if (enable == MT_GPIO_PULL_ENABLE) {
+		mmio_write_32(reg2 + SET, (1U << bit));
+		if (select == MT_GPIO_PULL_DOWN) {
+			mmio_write_32(reg1 + SET, (1U << bit));
+		} else {
+			mmio_write_32(reg1 + CLR, (1U << bit));
+		}
+	} else {
+		mmio_write_32(reg2 + CLR, (1U << bit));
+		mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
+	}
+}
+
+static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
+				 int select)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 - (gpio_info.base & 0xf0);
+
+	if (enable == MT_GPIO_PULL_ENABLE) {
+		if (select == MT_GPIO_PULL_DOWN) {
+			mmio_write_32(reg1 + CLR, (1U << bit));
+			mmio_write_32(reg2 + SET, (1U << bit));
+		} else {
+			mmio_write_32(reg2 + CLR, (1U << bit));
+			mmio_write_32(reg1 + SET, (1U << bit));
+		}
+	} else {
+		mmio_write_32(reg1 + CLR, (1U << bit));
+		mmio_write_32(reg2 + CLR, (1U << bit));
+	}
+}
+
+static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
+		   int select)
+{
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	if (gpio_info.flag) {
+		mt_gpio_set_spec_pull_pupd(pin, enable, select);
+	} else {
+		mt_gpio_set_pull_pu_pd(pin, enable, select);
+	}
+}
+
+static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	uint32_t r0;
+	uint32_t r1;
+
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 + (gpio_info.base & 0xf0);
+
+	r0 = (mmio_read_32(reg2) >> bit) & 1U;
+	r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
+	if (r0 == 0U && r1 == 0U) {
+		return MT_GPIO_PULL_NONE;
+	} else {
+		if (mmio_read_32(reg1) & (1U << bit)) {
+			return MT_GPIO_PULL_DOWN;
+		} else {
+			return MT_GPIO_PULL_UP;
+		}
+	}
+}
+
+static int mt_gpio_get_pull_pu_pd(uint32_t pin)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	uint32_t pu;
+	uint32_t pd;
+
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 - (gpio_info.base & 0xf0);
+	pu = (mmio_read_32(reg1) >> bit) & 1U;
+	pd = (mmio_read_32(reg2) >> bit) & 1U;
+	if (pu == 1U) {
+		return MT_GPIO_PULL_UP;
+	} else if (pd == 1U) {
+		return MT_GPIO_PULL_DOWN;
+	} else {
+		return MT_GPIO_PULL_NONE;
+	}
+}
+
+static int mt_gpio_get_pull_chip(uint32_t pin)
+{
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	if (gpio_info.flag) {
+		return mt_gpio_get_spec_pull_pupd(pin);
+	} else {
+		return mt_gpio_get_pull_pu_pd(pin);
+	}
+}
+
+static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
+{
+	assert(pin < MAX_GPIO_PIN);
+
+	if (sel == MT_GPIO_PULL_NONE) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
+	} else if (sel == MT_GPIO_PULL_UP) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
+	} else if (sel == MT_GPIO_PULL_DOWN) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
+	}
+}
+
+/* get pull-up or pull-down, regardless of resistor value */
+static int mt_get_gpio_pull_select_chip(uint32_t pin)
+{
+	assert(pin < MAX_GPIO_PIN);
+
+	return mt_gpio_get_pull_chip(pin);
+}
+
+static void mt_set_gpio_dir(int gpio, int direction)
+{
+	mt_set_gpio_dir_chip((uint32_t)gpio, direction);
+}
+
+static int mt_get_gpio_dir(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_dir_chip(pin);
+}
+
+static void mt_set_gpio_pull(int gpio, int pull)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	mt_set_gpio_pull_select_chip(pin, pull);
+}
+
+static int mt_get_gpio_pull(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_pull_select_chip(pin);
+}
+
+static void mt_set_gpio_out(int gpio, int value)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	mt_set_gpio_out_chip(pin, value);
+}
+
+static int mt_get_gpio_in(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_in_chip(pin);
+}
+
+const gpio_ops_t mtgpio_ops = {
+	 .get_direction = mt_get_gpio_dir,
+	 .set_direction = mt_set_gpio_dir,
+	 .get_value = mt_get_gpio_in,
+	 .set_value = mt_set_gpio_out,
+	 .set_pull = mt_set_gpio_pull,
+	 .get_pull = mt_get_gpio_pull,
+};
+
+void mt_gpio_init(void)
+{
+	gpio_init(&mtgpio_ops);
+}
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.h b/plat/mediatek/common/drivers/gpio/mtgpio_common.h
new file mode 100644
index 0000000..bf51055
--- /dev/null
+++ b/plat/mediatek/common/drivers/gpio/mtgpio_common.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_COMMON_H
+#define MT_GPIO_COMMON_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <plat/common/common_def.h>
+
+/*  Error Code No. */
+#define RSUCCESS        0
+#define ERACCESS        1
+#define ERINVAL         2
+#define ERWRAPPER       3
+#define MAX_GPIO_PIN    MT_GPIO_BASE_MAX
+
+/* GPIO MODE CONTROL VALUE*/
+typedef enum {
+	GPIO_MODE_UNSUPPORTED = -1,
+	GPIO_MODE_GPIO  = 0,
+	GPIO_MODE_00    = 0,
+	GPIO_MODE_01,
+	GPIO_MODE_02,
+	GPIO_MODE_03,
+	GPIO_MODE_04,
+	GPIO_MODE_05,
+	GPIO_MODE_06,
+	GPIO_MODE_07,
+
+	GPIO_MODE_MAX,
+	GPIO_MODE_DEFAULT = GPIO_MODE_00,
+} GPIO_MODE;
+
+/* GPIO DIRECTION */
+typedef enum {
+	MT_GPIO_DIR_UNSUPPORTED = -1,
+	MT_GPIO_DIR_OUT    = 0,
+	MT_GPIO_DIR_IN     = 1,
+	MT_GPIO_DIR_MAX,
+	MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
+} GPIO_DIR;
+
+/* GPIO PULL ENABLE*/
+typedef enum {
+	MT_GPIO_PULL_EN_UNSUPPORTED = -1,
+	MT_GPIO_PULL_DISABLE   = 0,
+	MT_GPIO_PULL_ENABLE    = 1,
+	MT_GPIO_PULL_ENABLE_R0 = 2,
+	MT_GPIO_PULL_ENABLE_R1 = 3,
+	MT_GPIO_PULL_ENABLE_R0R1 = 4,
+
+	MT_GPIO_PULL_EN_MAX,
+	MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
+} GPIO_PULL_EN;
+
+/* GPIO PULL-UP/PULL-DOWN*/
+typedef enum {
+	MT_GPIO_PULL_UNSUPPORTED = -1,
+	MT_GPIO_PULL_NONE        = 0,
+	MT_GPIO_PULL_UP          = 1,
+	MT_GPIO_PULL_DOWN        = 2,
+	MT_GPIO_PULL_MAX,
+	MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
+} GPIO_PULL;
+
+/* GPIO OUTPUT */
+typedef enum {
+	MT_GPIO_OUT_UNSUPPORTED = -1,
+	MT_GPIO_OUT_ZERO = 0,
+	MT_GPIO_OUT_ONE  = 1,
+
+	MT_GPIO_OUT_MAX,
+	MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
+	MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO,  /*compatible with DCT*/
+} GPIO_OUT;
+
+/* GPIO INPUT */
+typedef enum {
+	MT_GPIO_IN_UNSUPPORTED = -1,
+	MT_GPIO_IN_ZERO = 0,
+	MT_GPIO_IN_ONE  = 1,
+
+	MT_GPIO_IN_MAX,
+} GPIO_IN;
+
+#define PIN(_id, _flag, _bit, _base, _offset) {		\
+		.id = _id,				\
+		.flag = _flag,				\
+		.bit = _bit,				\
+		.base = _base,				\
+		.offset = _offset,			\
+	}
+
+struct mt_pin_info {
+	uint8_t id;
+	uint8_t flag;
+	uint8_t bit;
+	uint16_t base;
+	uint16_t offset;
+};
+
+void mt_gpio_init(void);
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin);
+#endif /* MT_GPIO_COMMON_H */
diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
index fca6913..d9a79c4 100644
--- a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
+++ b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
@@ -26,12 +26,30 @@
 	while (retry != 0) {
 		udelay(WAIT_IDLE_POLLING_DELAY_US);
 		reg_rdata = mmio_read_32((uintptr_t)wacs_register);
-		if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_IDLE) {
+		/* if last read command timeout,clear vldclr bit
+		 * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+		 * write:FSM_REQ-->idle
+		 */
+		switch (GET_WACS_FSM(reg_rdata)) {
+		case SWINF_FSM_WFVLDCLR:
+			mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_vldclr, 0x1);
+			INFO("WACS_FSM = SWINF_FSM_WFVLDCLR\n");
+			break;
+		case SWINF_FSM_WFDLE:
+			INFO("WACS_FSM = SWINF_FSM_WFDLE\n");
+			break;
+		case SWINF_FSM_REQ:
+			INFO("WACS_FSM = SWINF_FSM_REQ\n");
+			break;
+		case SWINF_FSM_IDLE:
+			goto done;
+		default:
 			break;
 		}
 		retry--;
 	};
 
+done:
 	if (retry == 0) {
 		/* timeout */
 		return E_PWR_WAIT_IDLE_TIMEOUT;
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.c b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.c
similarity index 100%
rename from plat/mediatek/mt8192/drivers/rtc/rtc.c
rename to plat/mediatek/common/drivers/rtc/rtc_mt6359p.c
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.h b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
similarity index 97%
rename from plat/mediatek/mt8192/drivers/rtc/rtc.h
rename to plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
index 419bfe4..04726e3 100644
--- a/plat/mediatek/mt8192/drivers/rtc/rtc.h
+++ b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef RTC_H
-#define RTC_H
+#ifndef RTC_MT6359P_H
+#define RTC_MT6359P_H
 
 /* RTC registers */
 enum {
@@ -194,4 +194,4 @@
 int32_t Writeif_unlock(void);
 void rtc_power_off_sequence(void);
 
-#endif /* RTC_H */
+#endif /* RTC_MT6359P_H */
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.c b/plat/mediatek/common/drivers/timer/mt_timer.c
similarity index 100%
rename from plat/mediatek/mt8192/drivers/timer/mt_timer.c
rename to plat/mediatek/common/drivers/timer/mt_timer.c
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.h b/plat/mediatek/common/drivers/timer/mt_timer.h
similarity index 100%
rename from plat/mediatek/mt8192/drivers/timer/mt_timer.h
rename to plat/mediatek/common/drivers/timer/mt_timer.h
diff --git a/plat/mediatek/mt8192/drivers/uart/uart.h b/plat/mediatek/common/drivers/uart/uart.h
similarity index 100%
rename from plat/mediatek/mt8192/drivers/uart/uart.h
rename to plat/mediatek/common/drivers/uart/uart.h
diff --git a/plat/mediatek/mt8192/plat_mt_cirq.c b/plat/mediatek/common/mtk_cirq.c
similarity index 99%
rename from plat/mediatek/mt8192/plat_mt_cirq.c
rename to plat/mediatek/common/mtk_cirq.c
index 9002b7e..de37986 100644
--- a/plat/mediatek/mt8192/plat_mt_cirq.c
+++ b/plat/mediatek/common/mtk_cirq.c
@@ -10,8 +10,7 @@
 #include <lib/mmio.h>
 
 #include <mt_gic_v3.h>
-#include <plat_mt_cirq.h>
-#include <platform_def.h>
+#include <mtk_cirq.h>
 
 static struct cirq_events cirq_all_events = {
 	.spi_start = CIRQ_SPI_START,
diff --git a/plat/mediatek/mt8192/include/plat_mt_cirq.h b/plat/mediatek/common/mtk_cirq.h
similarity index 93%
rename from plat/mediatek/mt8192/include/plat_mt_cirq.h
rename to plat/mediatek/common/mtk_cirq.h
index bb8b457..6e63bb8 100644
--- a/plat/mediatek/mt8192/include/plat_mt_cirq.h
+++ b/plat/mediatek/common/mtk_cirq.h
@@ -8,6 +8,7 @@
 #define PLAT_MT_CIRQ_H
 
 #include <stdint.h>
+#include <platform_def.h>
 
 enum {
 	IRQ_MASK_HEADER = 0xF1F1F1F1,
@@ -35,13 +36,6 @@
 /*
  * Define hardware register
  */
-
-#define  SYS_CIRQ_BASE         U(0x10204000)
-#define  CIRQ_REG_NUM          U(14)
-#define  CIRQ_IRQ_NUM          U(439)
-#define  CIRQ_SPI_START        U(64)
-#define  MD_WDT_IRQ_BIT_ID     U(110)
-
 #define  CIRQ_STA_BASE         (SYS_CIRQ_BASE + U(0x000))
 #define  CIRQ_ACK_BASE         (SYS_CIRQ_BASE + U(0x080))
 #define  CIRQ_MASK_BASE        (SYS_CIRQ_BASE + U(0x100))
diff --git a/plat/mediatek/common/mtk_plat_common.c b/plat/mediatek/common/mtk_plat_common.c
index f57e435..142b5c9 100644
--- a/plat/mediatek/common/mtk_plat_common.c
+++ b/plat/mediatek/common/mtk_plat_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -139,9 +139,9 @@
 
 int32_t plat_get_soc_version(void)
 {
-	uint32_t manfid = (JEDEC_MTK_BKID << 24U) | (JEDEC_MTK_MFID << 16U);
+	uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_MTK_BKID, JEDEC_MTK_MFID);
 
-	return (int32_t)(manfid | (SOC_CHIP_ID & 0xFFFFU));
+	return (int32_t)(manfid | (SOC_CHIP_ID & SOC_ID_IMPL_DEF_MASK));
 }
 
 int32_t plat_get_soc_revision(void)
diff --git a/plat/mediatek/common/mtk_sip_svc.h b/plat/mediatek/common/mtk_sip_svc.h
index 45ce281..74b17b6 100644
--- a/plat/mediatek/common/mtk_sip_svc.h
+++ b/plat/mediatek/common/mtk_sip_svc.h
@@ -35,6 +35,10 @@
 #define MTK_SIP_VCORE_CONTROL_ARCH32		0x82000506
 #define MTK_SIP_VCORE_CONTROL_ARCH64		0xC2000506
 
+/* APUSYS SMC call */
+#define MTK_SIP_APUSYS_CONTROL_AARCH32		0x8200051E
+#define MTK_SIP_APUSYS_CONTROL_AARCH64		0xC200051E
+
 /* Mediatek SiP Calls error code */
 enum {
 	MTK_SIP_E_SUCCESS = 0,
diff --git a/plat/mediatek/mt8183/drivers/uart/uart.h b/plat/mediatek/mt8183/drivers/uart/uart.h
deleted file mode 100644
index 062ce3a..0000000
--- a/plat/mediatek/mt8183/drivers/uart/uart.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __UART_H__
-#define __UART_H__
-
-#include <platform_def.h>
-
-/* UART HW information */
-#define HW_SUPPORT_UART_PORTS	2
-#define DRV_SUPPORT_UART_PORTS	2
-
-/* console UART clock cg */
-#define UART_CLOCK_GATE_SET		(INFRACFG_AO_BASE + 0x80)
-#define UART_CLOCK_GATE_CLR		(INFRACFG_AO_BASE + 0x84)
-#define UART_CLOCK_GATE_STA		(INFRACFG_AO_BASE + 0x90)
-#define UART0_CLOCK_GATE_BIT		(1U<<22)
-#define UART1_CLOCK_GATE_BIT		(1U<<23)
-
-/* UART registers */
-#define UART_RBR(_baseaddr)			(_baseaddr + 0x0)
-#define UART_THR(_baseaddr)			(_baseaddr + 0x0)
-#define UART_IER(_baseaddr)			(_baseaddr + 0x4)
-#define UART_IIR(_baseaddr)			(_baseaddr + 0x8)
-#define UART_FCR(_baseaddr)			(_baseaddr + 0x8)
-#define UART_LCR(_baseaddr)			(_baseaddr + 0xc)
-#define UART_MCR(_baseaddr)			(_baseaddr + 0x10)
-#define UART_LSR(_baseaddr)			(_baseaddr + 0x14)
-#define UART_MSR(_baseaddr)			(_baseaddr + 0x18)
-#define UART_SCR(_baseaddr)			(_baseaddr + 0x1c)
-#define UART_DLL(_baseaddr)			(_baseaddr + 0x0)
-#define UART_DLH(_baseaddr)			(_baseaddr + 0x4)
-#define UART_EFR(_baseaddr)			(_baseaddr + 0x8)
-#define UART_XON1(_baseaddr)			(_baseaddr + 0x10)
-#define UART_XON2(_baseaddr)			(_baseaddr + 0x14)
-#define UART_XOFF1(_baseaddr)			(_baseaddr + 0x18)
-#define UART_XOFF2(_baseaddr)			(_baseaddr + 0x1c)
-#define UART_AUTOBAUD(_baseaddr)		(_baseaddr + 0x20)
-#define UART_HIGHSPEED(_baseaddr)		(_baseaddr + 0x24)
-#define UART_SAMPLE_COUNT(_baseaddr)		(_baseaddr + 0x28)
-#define UART_SAMPLE_POINT(_baseaddr)		(_baseaddr + 0x2c)
-#define UART_AUTOBAUD_REG(_baseaddr)		(_baseaddr + 0x30)
-#define UART_RATE_FIX_REG(_baseaddr)		(_baseaddr + 0x34)
-#define UART_AUTO_BAUDSAMPLE(_baseaddr)		(_baseaddr + 0x38)
-#define UART_GUARD(_baseaddr)			(_baseaddr + 0x3c)
-#define UART_ESCAPE_DAT(_baseaddr)		(_baseaddr + 0x40)
-#define UART_ESCAPE_EN(_baseaddr)		(_baseaddr + 0x44)
-#define UART_SLEEP_EN(_baseaddr)		(_baseaddr + 0x48)
-#define UART_DMA_EN(_baseaddr)			(_baseaddr + 0x4c)
-#define UART_RXTRI_AD(_baseaddr)		(_baseaddr + 0x50)
-#define UART_FRACDIV_L(_baseaddr)		(_baseaddr + 0x54)
-#define UART_FRACDIV_M(_baseaddr)		(_baseaddr + 0x58)
-#define UART_FCR_RD(_baseaddr)			(_baseaddr + 0x5C)
-#define UART_USB_RX_SEL(_baseaddr)		(_baseaddr + 0xB0)
-#define UART_SLEEP_REQ(_baseaddr)		(_baseaddr + 0xB4)
-#define UART_SLEEP_ACK(_baseaddr)		(_baseaddr + 0xB8)
-#define UART_SPM_SEL(_baseaddr)			(_baseaddr + 0xBC)
-#define UART_LCR_DLAB				0x0080
-#define UART_LCR_MODE_B				0x00bf
-
-enum uart_port_ID {
-	UART_PORT0 = 0,
-	UART_PORT1
-};
-
-struct mt_uart_register {
-	unsigned int dll;
-	unsigned int dlh;
-	unsigned int ier;
-	unsigned int lcr;
-	unsigned int mcr;
-	unsigned int fcr;
-	unsigned int lsr;
-	unsigned int scr;
-	unsigned int efr;
-	unsigned int highspeed;
-	unsigned int sample_count;
-	unsigned int sample_point;
-	unsigned int fracdiv_l;
-	unsigned int fracdiv_m;
-	unsigned int escape_en;
-	unsigned int guard;
-	unsigned int rx_sel;
-};
-
-struct mt_uart {
-	unsigned long base;
-	struct mt_uart_register registers;
-};
-
-/* external API */
-void mt_uart_save(void);
-void mt_uart_restore(void);
-void mt_console_uart_cg(int on);
-uint32_t mt_console_uart_cg_status(void);
-
-#endif /* __UART_H__ */
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 07da1af..1615cf9 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -8,6 +8,7 @@
 MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
+                 -I${MTK_PLAT}/common/drivers/uart/                \
                  -I${MTK_PLAT_SOC}/drivers/                       \
                  -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
                  -I${MTK_PLAT_SOC}/drivers/devapc/                \
@@ -19,7 +20,6 @@
                  -I${MTK_PLAT_SOC}/drivers/spm/                   \
                  -I${MTK_PLAT_SOC}/drivers/sspm/                  \
                  -I${MTK_PLAT_SOC}/drivers/rtc/                   \
-                 -I${MTK_PLAT_SOC}/drivers/uart/                  \
                  -I${MTK_PLAT_SOC}/include/
 
 PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c       \
diff --git a/plat/mediatek/mt8192/aarch64/platform_common.c b/plat/mediatek/mt8192/aarch64/platform_common.c
index ffa10fe..fc98871 100644
--- a/plat/mediatek/mt8192/aarch64/platform_common.c
+++ b/plat/mediatek/mt8192/aarch64/platform_common.c
@@ -21,6 +21,14 @@
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
 	{ 0 }
 };
 
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index 0040747..c3cb9a5 100644
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -16,6 +16,7 @@
 #include <lib/coreboot.h>
 
 /* Platform Includes */
+#include <devapc/devapc.h>
 #include <emi_mpu/emi_mpu.h>
 #include <gpio/mtgpio.h>
 #include <mt_gic_v3.h>
@@ -94,11 +95,14 @@
 	/* MPU Init */
 	emi_mpu_init();
 
+	/* DAPC Init */
+	devapc_init();
+
 	/* Initialize the GIC driver, CPU and distributor interfaces */
 	mt_gic_driver_init();
 	mt_gic_init();
 
-	plat_mt8192_gpio_init();
+	mt_gpio_init();
 	mt_systimer_init();
 	generic_delay_timer_init();
 	spm_boot_init();
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c
new file mode 100644
index 0000000..782aa5f
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+#include <mtk_apusys.h>
+#include <plat/common/platform.h>
+
+uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+			    uint32_t *ret1)
+{
+	uint32_t request_ops;
+
+	request_ops = (uint32_t)x1;
+	INFO("[APUSYS] ops=0x%x\n", request_ops);
+
+	switch (request_ops) {
+	case MTK_SIP_APU_START_MCU:
+		/* setup addr[33:32] in reviser */
+		mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
+		mmio_write_32(REVISER_USDRFW_CTXT, 0U);
+
+		/* setup secure sideband */
+		mmio_write_32(AO_SEC_FW,
+			      (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
+			      (0U << SEC_FW_DOMAIN_SHIFT));
+
+		/* setup boot address */
+		mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
+
+		/* setup pre-define region */
+		mmio_write_32(AO_MD32_PRE_DEFINE,
+			      (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
+			      (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
+			      (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
+			      (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
+
+		/* release runstall */
+		mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
+
+		INFO("[APUSYS] reviser_ctxt=%x,%x\n",
+		     mmio_read_32(REVISER_SECUREFW_CTXT),
+		     mmio_read_32(REVISER_USDRFW_CTXT));
+		INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n",
+		     mmio_read_32(AO_SEC_FW),
+		     mmio_read_32(AO_MD32_BOOT_CTRL),
+		     mmio_read_32(AO_MD32_PRE_DEFINE),
+		     mmio_read_32(AO_MD32_SYS_CTRL));
+		break;
+	case MTK_SIP_APU_STOP_MCU:
+		/* hold runstall */
+		mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
+
+		INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
+		     mmio_read_32(AO_MD32_BOOT_CTRL),
+		     mmio_read_32(AO_MD32_SYS_CTRL));
+		break;
+	default:
+		ERROR("%s, unknown request_ops = %x\n", __func__, request_ops);
+		break;
+	}
+
+	return 0UL;
+}
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h
new file mode 100644
index 0000000..95fac4a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_H__
+#define __MTK_APUSYS_H__
+
+#include <stdint.h>
+
+/* setup the SMC command ops */
+#define MTK_SIP_APU_START_MCU	0x00U
+#define MTK_SIP_APU_STOP_MCU	0x01U
+
+/* AO Register */
+#define AO_MD32_PRE_DEFINE	(APUSYS_APU_S_S_4_BASE + 0x00)
+#define AO_MD32_BOOT_CTRL	(APUSYS_APU_S_S_4_BASE + 0x04)
+#define AO_MD32_SYS_CTRL	(APUSYS_APU_S_S_4_BASE + 0x08)
+#define AO_SEC_FW		(APUSYS_APU_S_S_4_BASE + 0x10)
+
+#define PRE_DEFINE_CACHE_TCM	0x3U
+#define PRE_DEFINE_CACHE	0x2U
+#define PRE_DEFINE_SHIFT_0G	0U
+#define PRE_DEFINE_SHIFT_1G	2U
+#define PRE_DEFINE_SHIFT_2G	4U
+#define PRE_DEFINE_SHIFT_3G	6U
+
+#define SEC_FW_NON_SECURE	1U
+#define SEC_FW_SHIFT_NS		4U
+#define SEC_FW_DOMAIN_SHIFT	0U
+
+#define SYS_CTRL_RUN		0U
+#define SYS_CTRL_STALL		1U
+
+/* Reviser Register */
+#define REVISER_SECUREFW_CTXT     (APUSYS_SCTRL_REVISER_BASE + 0x300)
+#define REVISER_USDRFW_CTXT       (APUSYS_SCTRL_REVISER_BASE + 0x304)
+
+uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+			    uint32_t *ret1);
+#endif /* __MTK_APUSYS_H__ */
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c
new file mode 100644
index 0000000..245d512
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <mtk_apusys_apc.h>
+#include <mtk_apusys_apc_def.h>
+#include <mtk_plat_common.h>
+#include <platform_def.h>
+
+static const struct APC_DOM_16 APUSYS_NOC_DAPC_AO[] = {
+/* 0~3 */
+APUSYS_APC_AO_ATTR("slv07-0",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-1",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-2",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-3",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+
+/* 16~18 */
+APUSYS_APC_AO_ATTR("slv01-0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv01-1",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv01-2",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 19~21 */
+APUSYS_APC_AO_ATTR("slv00-0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv00-1",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv00-2",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 22~26 */
+APUSYS_APC_AO_ATTR("slv02-0",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-1",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-2",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-3",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-4",
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+		NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+};
+
+static int32_t set_slave_noc_dapc(uint32_t slave,
+				  enum APUSYS_APC_DOMAIN_ID domain_id,
+				  enum APUSYS_APC_PERM_TYPE perm)
+{
+	uint32_t apc_register_index;
+	uint32_t apc_set_index;
+	uintptr_t base;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+	int32_t ret;
+
+	if (perm >= PERM_NUM) {
+		ERROR("[NOC_DAPC] perm type:0x%x is not supported!\n", perm);
+		ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED;
+		goto exit;
+	}
+
+	apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+	apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+
+	clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2));
+	set_bit = perm << (apc_set_index * 2);
+
+	if ((slave < APUSYS_NOC_DAPC_AO_SLAVE_NUM) &&
+	    (domain_id < APUSYS_NOC_DAPC_AO_DOM_NUM)) {
+		base = APUSYS_NOC_DAPC_AO_BASE +
+		       (domain_id * 0x40) + (apc_register_index * 4);
+		apuapc_writel(apuapc_readl(base) & clr_bit, base);
+		apuapc_writel(apuapc_readl(base) | set_bit, base);
+		ret = APUSYS_APC_OK;
+	} else {
+		ERROR("[NOC_DAPC] %s: %s, %s:0x%x, %s:0x%x\n",
+		      __func__, "out of boundary",
+		      "slave", slave,
+		      "domain_id", domain_id);
+		ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY;
+	}
+
+exit:
+	return ret;
+}
+
+static void dump_apusys_noc_dapc(void)
+{
+	uint32_t reg_num;
+	uint32_t d, i;
+
+	reg_num = APUSYS_NOC_DAPC_AO_SLAVE_NUM /
+		  APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+	for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) {
+		for (i = 0U; i <= reg_num; i++) {
+			INFO("[NOCDAPC] D%d_APC_%d: 0x%x\n", d, i,
+			     apuapc_readl(APUSYS_NOC_DAPC_AO_BASE +
+			     (d * 0x40) + (i * 4)));
+		}
+	}
+
+	INFO("[NOCDAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_NOC_DAPC_CON));
+}
+
+static const struct APC_DOM_16 APUSYS_AO_Devices[] = {
+
+/* 0 */
+APUSYS_APC_AO_ATTR("apusys_ao-0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-1",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-2",
+		SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-3",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-4",
+		SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-5",
+		SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-1",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-2",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_debug_apb",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+APUSYS_APC_AO_ATTR("apu_conn_config",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_sctrl_reviser",
+		SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_sema_stimer",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_emi_config",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_adl",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma_lite0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma_lite1",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_dapc_ao",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+APUSYS_APC_AO_ATTR("apu_dapc",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("infra_bcrm",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apb_dbg_ctl",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("noc_dapc",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_noc_bcrm",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_noc_config",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core0_config-0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core0_config-1",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core1_config-0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core1_config-1",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+APUSYS_APC_AO_ATTR("mdla0_apb-0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-1",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-2",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-3",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r0",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r1",
+		SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r2",
+		SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r3",
+		SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r4",
+		SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_rsi2_config",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+APUSYS_APC_AO_ATTR("apu_ssc2_config",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("vp6_core0_debug_apb",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+APUSYS_APC_AO_ATTR("vp6_core1_debug_apb",
+		NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+		FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+};
+
+static int32_t set_slave_apc(uint32_t slave,
+			     enum APUSYS_APC_DOMAIN_ID domain_id,
+			     enum APUSYS_APC_PERM_TYPE perm)
+{
+	uint32_t apc_register_index;
+	uint32_t apc_set_index;
+	uintptr_t base;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+	int32_t ret;
+
+	if (perm >= PERM_NUM) {
+		ERROR("[APUAPC] perm type:0x%x is not supported!\n", perm);
+		ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED;
+		goto exit;
+	}
+
+	apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+	apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+
+	clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2));
+	set_bit = perm << (apc_set_index * 2);
+
+	if ((slave < APUSYS_APC_SYS0_AO_SLAVE_NUM) &&
+	    (domain_id < APUSYS_APC_SYS0_AO_DOM_NUM)) {
+		base = APUSYS_APC_AO_BASE +
+		       (domain_id * 0x40) + (apc_register_index * 4);
+		apuapc_writel(apuapc_readl(base) & clr_bit, base);
+		apuapc_writel(apuapc_readl(base) | set_bit, base);
+		ret = APUSYS_APC_OK;
+	} else {
+		ERROR("[APUAPC] %s: %s, %s:0x%x, %s:0x%x\n",
+		      __func__, "out of boundary",
+		      "slave", slave,
+		      "domain_id", domain_id);
+		ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY;
+	}
+
+exit:
+	return ret;
+}
+
+static void dump_apusys_ao_apc(void)
+{
+	uint32_t reg_num;
+	uint32_t d, i;
+
+	reg_num = APUSYS_APC_SYS0_AO_SLAVE_NUM /
+		  APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+	for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) {
+		for (i = 0U; i <= reg_num; i++) {
+			INFO("[APUAPC] D%d_APC_%d: 0x%x\n", d, i,
+			     apuapc_readl(APUSYS_APC_AO_BASE +
+			     (d * 0x40) + (i * 4)));
+		}
+	}
+	INFO("[APUAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_APC_CON));
+}
+
+static int32_t set_apusys_noc_dapc(void)
+{
+	int32_t ret = 0;
+	uint32_t i;
+	uint32_t index;
+
+	for (i = 0U; i < ARRAY_SIZE(APUSYS_NOC_DAPC_AO); i++) {
+		if (i < APUSYS_NOC_DAPC_GAP_BOUNDARY) {
+			index = i;
+		} else {
+			index = i + APUSYS_NOC_DAPC_JUMP_GAP;
+		}
+		ret += set_slave_noc_dapc(index, DOMAIN_0,
+				APUSYS_NOC_DAPC_AO[i].d0_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_1,
+				APUSYS_NOC_DAPC_AO[i].d1_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_2,
+				APUSYS_NOC_DAPC_AO[i].d2_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_3,
+				APUSYS_NOC_DAPC_AO[i].d3_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_4,
+				APUSYS_NOC_DAPC_AO[i].d4_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_5,
+				APUSYS_NOC_DAPC_AO[i].d5_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_6,
+				APUSYS_NOC_DAPC_AO[i].d6_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_7,
+				APUSYS_NOC_DAPC_AO[i].d7_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_8,
+				APUSYS_NOC_DAPC_AO[i].d8_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_9,
+				APUSYS_NOC_DAPC_AO[i].d9_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_10,
+				APUSYS_NOC_DAPC_AO[i].d10_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_11,
+				APUSYS_NOC_DAPC_AO[i].d11_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_12,
+				APUSYS_NOC_DAPC_AO[i].d12_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_13,
+				APUSYS_NOC_DAPC_AO[i].d13_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_14,
+				APUSYS_NOC_DAPC_AO[i].d14_permission);
+		ret += set_slave_noc_dapc(index, DOMAIN_15,
+				APUSYS_NOC_DAPC_AO[i].d15_permission);
+	}
+
+	return ret;
+}
+
+static int32_t set_apusys_ao_apc(void)
+{
+	int32_t ret = 0;
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(APUSYS_AO_Devices); i++) {
+		ret += set_slave_apc(i, DOMAIN_0,
+				APUSYS_AO_Devices[i].d0_permission);
+		ret += set_slave_apc(i, DOMAIN_1,
+				APUSYS_AO_Devices[i].d1_permission);
+		ret += set_slave_apc(i, DOMAIN_2,
+				APUSYS_AO_Devices[i].d2_permission);
+		ret += set_slave_apc(i, DOMAIN_3,
+				APUSYS_AO_Devices[i].d3_permission);
+		ret += set_slave_apc(i, DOMAIN_4,
+				APUSYS_AO_Devices[i].d4_permission);
+		ret += set_slave_apc(i, DOMAIN_5,
+				APUSYS_AO_Devices[i].d5_permission);
+		ret += set_slave_apc(i, DOMAIN_6,
+				APUSYS_AO_Devices[i].d6_permission);
+		ret += set_slave_apc(i, DOMAIN_7,
+				APUSYS_AO_Devices[i].d7_permission);
+		ret += set_slave_apc(i, DOMAIN_8,
+				APUSYS_AO_Devices[i].d8_permission);
+		ret += set_slave_apc(i, DOMAIN_9,
+				APUSYS_AO_Devices[i].d9_permission);
+		ret += set_slave_apc(i, DOMAIN_10,
+				APUSYS_AO_Devices[i].d10_permission);
+		ret += set_slave_apc(i, DOMAIN_11,
+				APUSYS_AO_Devices[i].d11_permission);
+		ret += set_slave_apc(i, DOMAIN_12,
+				APUSYS_AO_Devices[i].d12_permission);
+		ret += set_slave_apc(i, DOMAIN_13,
+				APUSYS_AO_Devices[i].d13_permission);
+		ret += set_slave_apc(i, DOMAIN_14,
+				APUSYS_AO_Devices[i].d14_permission);
+		ret += set_slave_apc(i, DOMAIN_15,
+				APUSYS_AO_Devices[i].d15_permission);
+	}
+
+	return ret;
+}
+
+static void set_apusys_apc_lock(void)
+{
+	uint32_t set_bit = 1U << APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER;
+
+	/* Lock apu_sctrl_reviser */
+	set_bit = set_bit | (1U << APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5);
+	apuapc_writel(set_bit, APUSYS_SYS0_APC_LOCK_0);
+}
+
+void set_apusys_apc(void)
+{
+	int32_t ret = 0;
+
+	/* Check violation status */
+	INFO("[APUAPC] vio %d\n", apuapc_readl(APUSYS_APC_CON) & 0x80000000);
+
+	/* Initial Permission */
+	ret = set_apusys_ao_apc();
+	INFO("[APUAPC] %s - %s!\n", "set_apusys_ao_apc",
+	     ret ? "FAILED" : "SUCCESS");
+
+	/* Lock */
+	set_apusys_apc_lock();
+
+	/* Initial NoC Permission */
+	ret = set_apusys_noc_dapc();
+	INFO("[APUAPC] %s - %s!\n", "set_apusys_noc_dapc",
+	     ret ? "FAILED" : "SUCCESS");
+
+	/* Dump Permission */
+	dump_apusys_ao_apc();
+	dump_apusys_noc_dapc();
+
+	INFO("[APUAPC] %s done\n", __func__);
+}
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h
new file mode 100644
index 0000000..ff7a9fa
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_APC_H__
+#define __MTK_APUSYS_APC_H__
+
+void set_apusys_apc(void);
+
+#endif /* __MTK_APUSYS_APC_H__ */
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h
new file mode 100644
index 0000000..b392d6a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_APC_DEF_H__
+#define __MTK_APUSYS_APC_DEF_H__
+
+#include <lib/mmio.h>
+
+enum APUSYS_APC_ERR_STATUS {
+	APUSYS_APC_OK = 0x0,
+
+	APUSYS_APC_ERR_GENERIC = 0x1000,
+	APUSYS_APC_ERR_INVALID_CMD = 0x1001,
+	APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002,
+	APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003,
+	APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004,
+	APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005,
+	APUSYS_APC_ERR_OUT_OF_BOUNDARY = 0x1006,
+	APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED = 0x1007,
+};
+
+enum APUSYS_APC_PERM_TYPE {
+	NO_PROTECTION = 0U,
+	SEC_RW_ONLY = 1U,
+	SEC_RW_NS_R = 2U,
+	FORBIDDEN = 3U,
+	PERM_NUM = 4U,
+};
+
+enum APUSYS_APC_DOMAIN_ID {
+	DOMAIN_0 = 0U,
+	DOMAIN_1 = 1U,
+	DOMAIN_2 = 2U,
+	DOMAIN_3 = 3U,
+	DOMAIN_4 = 4U,
+	DOMAIN_5 = 5U,
+	DOMAIN_6 = 6U,
+	DOMAIN_7 = 7U,
+	DOMAIN_8 = 8U,
+	DOMAIN_9 = 9U,
+	DOMAIN_10 = 10U,
+	DOMAIN_11 = 11U,
+	DOMAIN_12 = 12U,
+	DOMAIN_13 = 13U,
+	DOMAIN_14 = 14U,
+	DOMAIN_15 = 15U,
+};
+
+struct APC_DOM_16 {
+	unsigned char d0_permission;
+	unsigned char d1_permission;
+	unsigned char d2_permission;
+	unsigned char d3_permission;
+	unsigned char d4_permission;
+	unsigned char d5_permission;
+	unsigned char d6_permission;
+	unsigned char d7_permission;
+	unsigned char d8_permission;
+	unsigned char d9_permission;
+	unsigned char d10_permission;
+	unsigned char d11_permission;
+	unsigned char d12_permission;
+	unsigned char d13_permission;
+	unsigned char d14_permission;
+	unsigned char d15_permission;
+};
+
+#define APUSYS_APC_AO_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+		PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+		PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \
+		PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \
+		PERM_ATTR14, PERM_ATTR15) \
+	{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+	(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+	(unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+	(unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
+	(unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
+	(unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
+	(unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
+	(unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
+
+#define apuapc_writel(VAL, REG)		mmio_write_32((uintptr_t)REG, VAL)
+#define apuapc_readl(REG)		mmio_read_32((uintptr_t)REG)
+
+/* APUSYS APC AO  Registers */
+#define APUSYS_APC_AO_BASE            APUSYS_APC_AO_WRAPPER_BASE
+#define APUSYS_APC_CON                (APUSYS_APC_AO_BASE + 0x00F00)
+#define APUSYS_SYS0_APC_LOCK_0        (APUSYS_APC_AO_BASE + 0x00700)
+
+/* APUSYS NOC_DPAC_AO Registers */
+#define APUSYS_NOC_DAPC_CON	      (APUSYS_NOC_DAPC_AO_BASE + 0x00F00)
+
+#define APUSYS_NOC_DAPC_GAP_BOUNDARY    4U
+#define APUSYS_NOC_DAPC_JUMP_GAP        12U
+
+#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM       16U
+#define APUSYS_APC_SYS0_AO_DOM_NUM                  16U
+#define APUSYS_APC_SYS0_AO_SLAVE_NUM                59U
+
+#define APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER  11U
+#define APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5        5U
+
+#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM       16U
+#define APUSYS_NOC_DAPC_AO_DOM_NUM                  16U
+#define APUSYS_NOC_DAPC_AO_SLAVE_NUM                27U
+
+#endif /* __MTK_APUSYS_APC_DEF_H__ */
diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.c b/plat/mediatek/mt8192/drivers/devapc/devapc.c
new file mode 100644
index 0000000..b11f272
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/devapc/devapc.c
@@ -0,0 +1,2847 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+
+#include <devapc.h>
+#include <mtk_apusys_apc.h>
+
+/* Infra_ao */
+static const struct APC_INFRA_PERI_DOM_16 INFRA_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS0_ATTR("L3C_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("PCIE_AXI_S",
+			NO_PROTECTION, NO_PROTECTION, FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 INFRA_AO_SYS1_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-13",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-14",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-15",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-20",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-21",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-22",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-23",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-24",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-25",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-26",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-27",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-28",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-29",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-30",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-31",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-32",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-33",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-34",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-35",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-36",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-37",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-38",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-39",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-100",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-101",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-102",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-103",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-104",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-105",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-106",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-107",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-108",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-109",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-110",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-111",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-112",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-113",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-114",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-115",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-116",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-117",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-118",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-119",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-120",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-121",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-122",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-123",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-124",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-125",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-126",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-127",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-128",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-129",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 70 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-130",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-131",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-132",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-133",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-134",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-135",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-136",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-137",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-138",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-139",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 80 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-140",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-141",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-142",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-143",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-200",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-201",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-202",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-203",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-204",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-205",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 90 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-206",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-207",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-300",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-301",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-302",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-303",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-304",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-305",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-306",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-307",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 100 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-400",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-401",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-402",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-403",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-404",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-405",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-406",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-407",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-408",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-409",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 110 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-410",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-411",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-412",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-413",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-414",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-415",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-416",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-417",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-418",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-419",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 120 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-420",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-421",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-422",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-423",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-424",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-425",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-426",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-427",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-428",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-429",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 130 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-430",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-431",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-432",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-433",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-434",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-435",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-436",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-437",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-438",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-439",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 140 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-440",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-441",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-442",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-443",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-444",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-445",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-446",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-447",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-448",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-449",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 150 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-450",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-451",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-452",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-453",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-454",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-455",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-456",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-457",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-458",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-459",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 160 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-460",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-461",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-462",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-463",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-464",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-465",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-466",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-467",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-468",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-469",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 170 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-470",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-471",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-472",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-473",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-474",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-475",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-476",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-477",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-478",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-479",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 180 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-480",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-481",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-482",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-483",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-484",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-485",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-486",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-487",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-488",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-489",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 190 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-490",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-491",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-492",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-493",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-494",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-495",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-496",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-497",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-498",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-499",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 200 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-500",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-501",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-502",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-503",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-504",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-505",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-506",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-507",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-508",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-509",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 210 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-510",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-511",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-512",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-513",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-514",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-515",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-516",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-517",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-518",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-519",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 220 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-520",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-521",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-522",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-523",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-524",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-525",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-526",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-527",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-528",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-529",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 230 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-530",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-531",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-532",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-533",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-534",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-535",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-536",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-537",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-538",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-539",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 240 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-540",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-541",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-542",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-543",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-544",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-545",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-546",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-547",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-548",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-549",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 250 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-550",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-551",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-552",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-553",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-554",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-555",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 INFRA_AO_SYS2_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-556",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-557",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-558",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-559",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-560",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-561",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-562",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-563",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-564",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-565",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-566",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-567",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-568",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-569",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-570",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-571",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-572",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-573",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-574",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-575",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-576",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-577",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-578",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-579",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-580",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-581",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-582",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-583",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-584",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-585",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-586",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-587",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-588",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-589",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-590",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-591",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-592",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-593",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-594",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-595",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-600",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-601",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-602",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-603",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-604",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-605",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-606",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-607",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-608",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-609",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-610",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-611",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-700",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-701",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-702",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-703",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-704",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-705",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-706",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-707",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-708",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-709",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-710",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-711",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-712",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-713",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-714",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-715",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-716",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-717",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+/* Peri_ao */
+static const struct APC_INFRA_PERI_DOM_16 PERI_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("APMIXEDSYS_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, NO_PROTECTION,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPCKGEN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, NO_PROTECTION,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRACFG_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO_SYS0_ATTR("PERICFG_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("GPIO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     NO_PROTECTION,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPRGU_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("RESERVED_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_PERI_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("BCRM_PERI_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMIC_WRAP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_AO_MM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("KP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOP_MISC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DVFSRC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("MBIST_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DPMAIF_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SYS_TIMER_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_AO_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMIF1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMICSPI_MST_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TIA_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("AUDIO_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("AUDIO_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("NOR_AXI_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PCIE_AHB_S",
+			NO_PROTECTION, NO_PROTECTION, FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 70 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 80 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 90 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF3_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF3_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF4_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF4_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRA_BUS_TRACE_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF5_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 100 */
+DAPC_PERI_AO_SYS0_ATTR("CCIF5_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_ACP_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_8 PERI_AO_SYS1_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-9",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-10",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-11",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-12",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-13",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-14",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-15",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-16",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-17",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-18",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-19",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-20",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-21",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-22",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-4",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-5",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-6",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-7",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-8",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-9",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-10",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-11",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-12",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-13",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-14",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-15",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-16",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-17",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-18",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-19",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-20",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-21",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-22",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-23",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-24",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-25",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-26",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-27",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-28",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-29",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-30",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-31",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-32",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-33",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-34",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-35",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-36",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-37",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-38",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-39",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-40",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-41",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-42",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 PERI_AO_SYS2_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS2_ATTR("CONN_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+/* Peri_ao2 */
+static const struct APC_INFRA_PERI_DOM_16 PERI_AO2_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO2_SYS0_ATTR("EFUSE_DEBUG_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("APXGPT_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SEJ_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("AES_TOP0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SECURITY_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_AO2_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_AO2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_CTRL_PERI_AO2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SPMI_MST_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_CTRL_FMEM_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_FMEM_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("PWM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-1",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-2",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-3",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     SEC_RW_NS_R,   FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB8_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB9_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB10_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB11_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB12_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB13_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB14_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB15_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB8_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB9_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB10_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB11_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB12_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB13_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB14_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB15_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB8_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 70 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB9_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB10_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB11_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB12_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB13_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB14_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB15_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 80 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB5_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB6_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB7_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EFUSE_DEBUG_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_INFRA_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF0_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 90 */
+DAPC_PERI_AO2_SYS0_ATTR("CCIF0_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF1_AP_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF1_MD_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("MBIST_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("INFRACFG_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("TRNG_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DX_CC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CQ_DMA_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SRAMROM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("INFRACFG_MEM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 100 */
+DAPC_PERI_AO2_SYS0_ATTR("RESERVED_DVFS_PROC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EMI_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EMI_MPU_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_MPU_PDN_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("APDMA_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_INFRA_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 110 */
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_PDN2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_PDN2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_FMEM_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+/* Peri_par_ao */
+static const struct APC_INFRA_PERI_DOM_16 PERI_PAR_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB4_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI0_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("BTIF_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI1_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI3_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB0_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB1_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI4_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI5_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB2_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB3_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI6_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI7_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S",
+			NO_PROTECTION, FORBIDDEN,     NO_PROTECTION, FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("NOR_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_AO_APB_S",
+			SEC_RW_ONLY,   FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEBUG_CTRL_PERI_PAR_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_AO_APB_S",
+			NO_PROTECTION, FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN,
+			FORBIDDEN,     FORBIDDEN,     FORBIDDEN,     FORBIDDEN),
+
+};
+
+static void set_module_apc(enum DEVAPC_SLAVE_TYPE slave_type,
+		uint32_t module, enum DOMAIN_ID domain_id,
+		enum DEVAPC_PERM_TYPE perm)
+{
+	uint32_t apc_register_index;
+	uint32_t apc_set_index;
+	uintptr_t base = 0, reg;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	apc_register_index = module / MOD_NO_IN_1_DEVAPC;
+	apc_set_index = module % MOD_NO_IN_1_DEVAPC;
+
+	clr_bit = (0x3U << (apc_set_index * 2));
+	set_bit = (uint32_t)perm << (apc_set_index * 2);
+
+	/* infra_ao */
+	if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS0) &&
+		(module < SLAVE_NUM_INFRA_AO_SYS0) &&
+		(domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS0)) {
+		base = DEVAPC_INFRA_AO_SYS0_D0_APC_0;
+
+	} else if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS1) &&
+		(module < SLAVE_NUM_INFRA_AO_SYS1) &&
+		(domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS1)) {
+		base = DEVAPC_INFRA_AO_SYS1_D0_APC_0;
+
+	} else if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS2) &&
+		(module < SLAVE_NUM_INFRA_AO_SYS2) &&
+		(domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS2)) {
+		base = DEVAPC_INFRA_AO_SYS2_D0_APC_0;
+	/* peri_ao */
+	} else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS0) &&
+		(module < SLAVE_NUM_PERI_AO_SYS0) &&
+		(domain_id < (uint32_t)DOM_NUM_PERI_AO_SYS0)) {
+		base = DEVAPC_PERI_AO_SYS0_D0_APC_0;
+
+	} else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS1) &&
+		(module < SLAVE_NUM_PERI_AO_SYS1) &&
+		(domain_id <= (uint32_t)DOM_NUM_PERI_AO_SYS1)) {
+		base = DEVAPC_PERI_AO_SYS1_D0_APC_0;
+
+	} else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS2) &&
+		(module < SLAVE_NUM_PERI_AO_SYS2) &&
+		(domain_id < (uint32_t)DOM_NUM_PERI_AO_SYS2)) {
+		base = DEVAPC_PERI_AO_SYS2_D0_APC_0;
+	/* peri_ao2 */
+	} else if ((slave_type == SLAVE_TYPE_PERI_AO2_SYS0) &&
+		(module < SLAVE_NUM_PERI_AO2_SYS0) &&
+		(domain_id < (uint32_t)DOM_NUM_PERI_AO2_SYS0)) {
+		base = DEVAPC_PERI_AO2_SYS0_D0_APC_0;
+
+	/* peri_par_ao */
+	} else if ((slave_type == SLAVE_TYPE_PERI_PAR_AO_SYS0) &&
+		(module < SLAVE_NUM_PERI_PAR_AO_SYS0) &&
+		(domain_id < (uint32_t)DOM_NUM_PERI_PAR_AO_SYS0)) {
+		base = DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0;
+
+	} else {
+		ERROR("[DEVAPC] %s: %s, %s:0x%x, %s:0x%x, %s:0x%x\n",
+				__func__, "out of boundary",
+				"slave_type", slave_type,
+				"module", module,
+				"domain_id", domain_id);
+	}
+
+	if (base != 0U) {
+		reg = base + domain_id * 0x40 + apc_register_index * 4;
+		mmio_clrsetbits_32(reg, clr_bit, set_bit);
+	}
+}
+
+static void dump_infra_ao_apc(void)
+{
+	int reg_num;
+	int d, i;
+
+	reg_num = (SLAVE_NUM_INFRA_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_INFRA_AO_SYS0_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	reg_num = (SLAVE_NUM_INFRA_AO_SYS1 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_INFRA_AO_SYS1; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (INFRA_AO_SYS1)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_INFRA_AO_SYS1_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	reg_num = (SLAVE_NUM_INFRA_AO_SYS2 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_INFRA_AO_SYS2; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (INFRA_AO_SYS2)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_INFRA_AO_SYS2_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	INFO("[DEVAPC] (INFRA_AO)MAS_SEC_0: 0x%x\n",
+		devapc_readl(DEVAPC_INFRA_AO_MAS_SEC_0));
+}
+
+static void dump_peri_ao_apc(void)
+{
+	int reg_num;
+	int d, i;
+
+	reg_num = (SLAVE_NUM_PERI_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_AO_SYS0; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_AO_SYS0)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_AO_SYS0_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	reg_num = (SLAVE_NUM_PERI_AO_SYS1 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_AO_SYS1; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_AO_SYS1)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_AO_SYS1_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	reg_num = (SLAVE_NUM_PERI_AO_SYS2 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_AO_SYS2; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_AO_SYS2)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_AO_SYS2_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	INFO("[DEVAPC] (PERI_AO)MAS_SEC_0: 0x%x\n",
+		devapc_readl(DEVAPC_PERI_AO_MAS_SEC_0));
+}
+
+static void dump_peri_ao2_apc(void)
+{
+	int reg_num;
+	int d, i;
+
+	reg_num = (SLAVE_NUM_PERI_AO2_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_AO2_SYS0; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_AO2_SYS0)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_AO2_SYS0_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+}
+
+static void dump_peri_par_ao_apc(void)
+{
+	int reg_num;
+	int d, i;
+
+	reg_num = (SLAVE_NUM_PERI_PAR_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+	for (d = 0; d < DOM_NUM_PERI_PAR_AO_SYS0; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO("[DEVAPC] (PERI_PAR_AO_SYS0)D%d_APC_%d: 0x%x\n",
+					d, i, devapc_readl(
+					DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0 +
+					d * 0x40 + i * 4)
+			);
+		}
+	}
+
+	INFO("[DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x%x\n",
+		devapc_readl(DEVAPC_PERI_PAR_AO_MAS_SEC_0));
+}
+
+static void set_infra_ao_apc(void)
+{
+	uint32_t infra_ao_size;
+	uint32_t i;
+
+	infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS0_Devices);
+
+	for (i = 0; i < infra_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_0,
+				INFRA_AO_SYS0_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_1,
+				INFRA_AO_SYS0_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_2,
+				INFRA_AO_SYS0_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_3,
+				INFRA_AO_SYS0_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_4,
+				INFRA_AO_SYS0_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_5,
+				INFRA_AO_SYS0_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_6,
+				INFRA_AO_SYS0_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_7,
+				INFRA_AO_SYS0_Devices[i].d7_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_8,
+				INFRA_AO_SYS0_Devices[i].d8_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_9,
+				INFRA_AO_SYS0_Devices[i].d9_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_10,
+				INFRA_AO_SYS0_Devices[i].d10_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_11,
+				INFRA_AO_SYS0_Devices[i].d11_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_12,
+				INFRA_AO_SYS0_Devices[i].d12_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_13,
+				INFRA_AO_SYS0_Devices[i].d13_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_14,
+				INFRA_AO_SYS0_Devices[i].d14_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_15,
+				INFRA_AO_SYS0_Devices[i].d15_permission);
+	}
+
+	infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS1_Devices);
+
+	for (i = 0; i < infra_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_0,
+				INFRA_AO_SYS1_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_1,
+				INFRA_AO_SYS1_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_2,
+				INFRA_AO_SYS1_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_3,
+				INFRA_AO_SYS1_Devices[i].d3_permission);
+	}
+
+	infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS2_Devices);
+
+	for (i = 0; i < infra_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_0,
+				INFRA_AO_SYS2_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_1,
+				INFRA_AO_SYS2_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_2,
+				INFRA_AO_SYS2_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_3,
+				INFRA_AO_SYS2_Devices[i].d3_permission);
+	}
+}
+
+static void set_peri_ao_apc(void)
+{
+	uint32_t peri_ao_size;
+	uint32_t i;
+
+	peri_ao_size = ARRAY_SIZE(PERI_AO_SYS0_Devices);
+
+	for (i = 0; i < peri_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_0,
+				PERI_AO_SYS0_Devices[i].d0_permission);			/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_1,
+				PERI_AO_SYS0_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_2,
+				PERI_AO_SYS0_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_3,
+				PERI_AO_SYS0_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_4,
+				PERI_AO_SYS0_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_5,
+				PERI_AO_SYS0_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_6,
+				PERI_AO_SYS0_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_7,
+				PERI_AO_SYS0_Devices[i].d7_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_8,
+				PERI_AO_SYS0_Devices[i].d8_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_9,
+				PERI_AO_SYS0_Devices[i].d9_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_10,
+				PERI_AO_SYS0_Devices[i].d10_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_11,
+				PERI_AO_SYS0_Devices[i].d11_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_12,
+				PERI_AO_SYS0_Devices[i].d12_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_13,
+				PERI_AO_SYS0_Devices[i].d13_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_14,
+				PERI_AO_SYS0_Devices[i].d14_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_15,
+				PERI_AO_SYS0_Devices[i].d15_permission);
+	}
+
+	peri_ao_size = ARRAY_SIZE(PERI_AO_SYS1_Devices);
+
+	for (i = 0; i < peri_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_0,
+				PERI_AO_SYS1_Devices[i].d0_permission);			/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_1,
+				PERI_AO_SYS1_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_2,
+				PERI_AO_SYS1_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_3,
+				PERI_AO_SYS1_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_4,
+				PERI_AO_SYS1_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_5,
+				PERI_AO_SYS1_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_6,
+				PERI_AO_SYS1_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_7,
+				PERI_AO_SYS1_Devices[i].d7_permission);
+	}
+
+	peri_ao_size = ARRAY_SIZE(PERI_AO_SYS2_Devices);
+
+	for (i = 0; i < peri_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_0,
+				PERI_AO_SYS2_Devices[i].d0_permission);			/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_1,
+				PERI_AO_SYS2_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_2,
+				PERI_AO_SYS2_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_3,
+				PERI_AO_SYS2_Devices[i].d3_permission);
+	}
+}
+
+static void set_peri_ao2_apc(void)
+{
+	uint32_t peri_ao2_size;
+	uint32_t i;
+
+	peri_ao2_size = ARRAY_SIZE(PERI_AO2_SYS0_Devices);
+
+	for (i = 0; i < peri_ao2_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_0,
+				PERI_AO2_SYS0_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_1,
+				PERI_AO2_SYS0_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_2,
+				PERI_AO2_SYS0_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_3,
+				PERI_AO2_SYS0_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_4,
+				PERI_AO2_SYS0_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_5,
+				PERI_AO2_SYS0_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_6,
+				PERI_AO2_SYS0_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_7,
+				PERI_AO2_SYS0_Devices[i].d7_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_8,
+				PERI_AO2_SYS0_Devices[i].d8_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_9,
+				PERI_AO2_SYS0_Devices[i].d9_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_10,
+				PERI_AO2_SYS0_Devices[i].d10_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_11,
+				PERI_AO2_SYS0_Devices[i].d11_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_12,
+				PERI_AO2_SYS0_Devices[i].d12_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_13,
+				PERI_AO2_SYS0_Devices[i].d13_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_14,
+				PERI_AO2_SYS0_Devices[i].d14_permission);
+		set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_15,
+				PERI_AO2_SYS0_Devices[i].d15_permission);
+	}
+}
+
+static void set_peri_par_ao_apc(void)
+{
+	uint32_t peri_par_ao_size;
+	uint32_t i;
+
+	peri_par_ao_size = ARRAY_SIZE(PERI_PAR_AO_SYS0_Devices);
+
+	for (i = 0; i < peri_par_ao_size; i++) {
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_0,
+				PERI_PAR_AO_SYS0_Devices[i].d0_permission);		/* APMCU */
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_1,
+				PERI_PAR_AO_SYS0_Devices[i].d1_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_2,
+				PERI_PAR_AO_SYS0_Devices[i].d2_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_3,
+				PERI_PAR_AO_SYS0_Devices[i].d3_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_4,
+				PERI_PAR_AO_SYS0_Devices[i].d4_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_5,
+				PERI_PAR_AO_SYS0_Devices[i].d5_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_6,
+				PERI_PAR_AO_SYS0_Devices[i].d6_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_7,
+				PERI_PAR_AO_SYS0_Devices[i].d7_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_8,
+				PERI_PAR_AO_SYS0_Devices[i].d8_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_9,
+				PERI_PAR_AO_SYS0_Devices[i].d9_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_10,
+				PERI_PAR_AO_SYS0_Devices[i].d10_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_11,
+				PERI_PAR_AO_SYS0_Devices[i].d11_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_12,
+				PERI_PAR_AO_SYS0_Devices[i].d12_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_13,
+				PERI_PAR_AO_SYS0_Devices[i].d13_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_14,
+				PERI_PAR_AO_SYS0_Devices[i].d14_permission);
+		set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_15,
+				PERI_PAR_AO_SYS0_Devices[i].d15_permission);
+	}
+}
+
+static void set_extra_apc(void)
+{
+#ifdef MTK_DEBUGSYS_LOCK
+	/* Block debugsys to avoid privilege escalation (user load only) */
+	set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, DEVAPC_DEBUGSYS_INDEX,
+			DOMAIN_0, SEC_RW_NS_R);
+#endif
+}
+
+void devapc_init(void)
+{
+	/* Initial Permission */
+	set_infra_ao_apc();
+	set_peri_ao_apc();
+	set_peri_ao2_apc();
+	set_peri_par_ao_apc();
+
+	/* Extra Permission */
+	set_extra_apc();
+
+	/* Dump Permission */
+	dump_infra_ao_apc();
+	dump_peri_ao_apc();
+	dump_peri_ao2_apc();
+	dump_peri_par_ao_apc();
+
+	/* Setup APUSYS Permission */
+	set_apusys_apc();
+
+	INFO("[DEVAPC] %s done\n", __func__);
+}
diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.h b/plat/mediatek/mt8192/drivers/devapc/devapc.h
new file mode 100644
index 0000000..9033a0f
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/devapc/devapc.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DEVAPC_H
+#define DEVAPC_H
+
+#include <stdint.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ * FUNCTION DEFINITION
+ ******************************************************************************/
+void devapc_init(void);
+
+/******************************************************************************
+ * STRUCTURE DEFINITION
+ ******************************************************************************/
+enum DEVAPC_PERM_TYPE {
+	NO_PROTECTION = 0,
+	SEC_RW_ONLY,
+	SEC_RW_NS_R,
+	FORBIDDEN,
+	PERM_NUM,
+};
+
+enum DOMAIN_ID {
+	DOMAIN_0 = 0,
+	DOMAIN_1,
+	DOMAIN_2,
+	DOMAIN_3,
+	DOMAIN_4,
+	DOMAIN_5,
+	DOMAIN_6,
+	DOMAIN_7,
+	DOMAIN_8,
+	DOMAIN_9,
+	DOMAIN_10,
+	DOMAIN_11,
+	DOMAIN_12,
+	DOMAIN_13,
+	DOMAIN_14,
+	DOMAIN_15,
+};
+
+/* Slave Type */
+enum DEVAPC_SLAVE_TYPE_SIMPLE {
+	SLAVE_TYPE_INFRA = 0,
+	SLAVE_TYPE_PERI,
+	SLAVE_TYPE_PERI2,
+	SLAVE_TYPE_PERI_PAR,
+};
+
+enum DEVAPC_SYS_INDEX {
+	DEVAPC_SYS0 = 0,
+	DEVAPC_SYS1,
+	DEVAPC_SYS2,
+};
+
+enum DEVAPC_SLAVE_TYPE {
+	SLAVE_TYPE_INFRA_AO_SYS0 = 0,
+	SLAVE_TYPE_INFRA_AO_SYS1,
+	SLAVE_TYPE_INFRA_AO_SYS2,
+	SLAVE_TYPE_PERI_AO_SYS0,
+	SLAVE_TYPE_PERI_AO_SYS1,
+	SLAVE_TYPE_PERI_AO_SYS2,
+	SLAVE_TYPE_PERI_AO2_SYS0,
+	SLAVE_TYPE_PERI_PAR_AO_SYS0,
+};
+
+/* Slave Num */
+enum DEVAPC_SLAVE_NUM {
+	SLAVE_NUM_INFRA_AO_SYS0 = 23,
+	SLAVE_NUM_INFRA_AO_SYS1 = 256,
+	SLAVE_NUM_INFRA_AO_SYS2 = 70,
+	SLAVE_NUM_PERI_AO_SYS0 = 105,
+	SLAVE_NUM_PERI_AO_SYS1 = 66,
+	SLAVE_NUM_PERI_AO_SYS2 = 1,
+	SLAVE_NUM_PERI_AO2_SYS0 = 115,
+	SLAVE_NUM_PERI_PAR_AO_SYS0 = 27,
+};
+
+enum DEVAPC_SYS_DOM_NUM {
+	DOM_NUM_INFRA_AO_SYS0 = 16,
+	DOM_NUM_INFRA_AO_SYS1 = 4,
+	DOM_NUM_INFRA_AO_SYS2 = 4,
+	DOM_NUM_PERI_AO_SYS0 = 16,
+	DOM_NUM_PERI_AO_SYS1 = 8,
+	DOM_NUM_PERI_AO_SYS2 = 4,
+	DOM_NUM_PERI_AO2_SYS0 = 16,
+	DOM_NUM_PERI_PAR_AO_SYS0 = 16,
+};
+
+enum DEVAPC_CFG_INDEX {
+	DEVAPC_DEBUGSYS_INDEX = 57,
+};
+
+struct APC_INFRA_PERI_DOM_16 {
+	unsigned char d0_permission;
+	unsigned char d1_permission;
+	unsigned char d2_permission;
+	unsigned char d3_permission;
+	unsigned char d4_permission;
+	unsigned char d5_permission;
+	unsigned char d6_permission;
+	unsigned char d7_permission;
+	unsigned char d8_permission;
+	unsigned char d9_permission;
+	unsigned char d10_permission;
+	unsigned char d11_permission;
+	unsigned char d12_permission;
+	unsigned char d13_permission;
+	unsigned char d14_permission;
+	unsigned char d15_permission;
+};
+
+struct APC_INFRA_PERI_DOM_8 {
+	unsigned char d0_permission;
+	unsigned char d1_permission;
+	unsigned char d2_permission;
+	unsigned char d3_permission;
+	unsigned char d4_permission;
+	unsigned char d5_permission;
+	unsigned char d6_permission;
+	unsigned char d7_permission;
+};
+
+struct APC_INFRA_PERI_DOM_4 {
+	unsigned char d0_permission;
+	unsigned char d1_permission;
+	unsigned char d2_permission;
+	unsigned char d3_permission;
+};
+
+#define DAPC_INFRA_AO_SYS0_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+		PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+		PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \
+		PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \
+		PERM_ATTR14, PERM_ATTR15) \
+	{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+	(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+	(unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+	(unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
+	(unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
+	(unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
+	(unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
+	(unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
+
+#define DAPC_INFRA_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+		PERM_ATTR2, PERM_ATTR3) \
+	{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+	(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3}
+
+#define DAPC_PERI_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+		PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+		PERM_ATTR6, PERM_ATTR7) \
+	{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+	(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+	(unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+	(unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7}
+
+#define DAPC_INFRA_AO_SYS2_ATTR(...)	DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO_SYS0_ATTR(...)	DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO_SYS2_ATTR(...)	DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO2_SYS0_ATTR(...)	DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+#define DAPC_PERI_PAR_AO_SYS0_ATTR(...)	DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+
+/******************************************************************************
+ * UTILITY DEFINITION
+ ******************************************************************************/
+#define devapc_writel(VAL, REG)		mmio_write_32((uintptr_t)REG, VAL)
+#define devapc_readl(REG)		mmio_read_32((uintptr_t)REG)
+
+/******************************************************************************/
+/* Device APC AO for INFRA AO */
+#define DEVAPC_INFRA_AO_SYS0_D0_APC_0		(DEVAPC_INFRA_AO_BASE + 0x0000)
+#define DEVAPC_INFRA_AO_SYS1_D0_APC_0		(DEVAPC_INFRA_AO_BASE + 0x1000)
+#define DEVAPC_INFRA_AO_SYS2_D0_APC_0		(DEVAPC_INFRA_AO_BASE + 0x2000)
+
+#define DEVAPC_INFRA_AO_MAS_SEC_0		(DEVAPC_INFRA_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+/* Device APC AO for PERI AO */
+#define DEVAPC_PERI_AO_SYS0_D0_APC_0		(DEVAPC_PERI_AO_BASE + 0x0000)
+#define DEVAPC_PERI_AO_SYS1_D0_APC_0		(DEVAPC_PERI_AO_BASE + 0x1000)
+#define DEVAPC_PERI_AO_SYS2_D0_APC_0		(DEVAPC_PERI_AO_BASE + 0x2000)
+
+#define DEVAPC_PERI_AO_MAS_SEC_0		(DEVAPC_PERI_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+/* Device APC AO for PERI AO2 */
+#define DEVAPC_PERI_AO2_SYS0_D0_APC_0		(DEVAPC_PERI_AO2_BASE + 0x0000)
+
+/******************************************************************************/
+/* Device APC AO for PERI PAR AO */
+#define DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0	(DEVAPC_PERI_PAR_AO_BASE + 0x0000)
+
+#define DEVAPC_PERI_PAR_AO_MAS_SEC_0		(DEVAPC_PERI_PAR_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+
+
+/******************************************************************************
+ * Variable DEFINITION
+ ******************************************************************************/
+#define MOD_NO_IN_1_DEVAPC              16
+
+#endif /* DEVAPC_H */
+
diff --git a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
index d9541bd..26bed29 100644
--- a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
+++ b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
@@ -117,7 +117,7 @@
 			      NO_PROT, FORBIDDEN, FORBIDDEN, NO_PROT);
 	emi_mpu_set_protection(&region_info);
 
-	/* Forbidden All */
+	/* DSP protect address */
 	region_info.start = 0x40000000ULL;	/* dram base addr */
 	region_info.end = 0x1FFFF0000ULL;
 	region_info.region = 3;
@@ -128,6 +128,17 @@
 			      FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROT);
 	emi_mpu_set_protection(&region_info);
 
+	/* Forbidden All */
+	region_info.start = 0x40000000ULL;	/* dram base addr */
+	region_info.end = 0x1FFFF0000ULL;
+	region_info.region = 4;
+	SET_ACCESS_PERMISSION(region_info.apc, 1,
+			      FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+			      FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+			      FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+			      FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROT);
+	emi_mpu_set_protection(&region_info);
+
 	dump_emi_mpu_regions();
 }
 
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
index e07b75a..c78332d 100644
--- a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
@@ -5,94 +5,17 @@
  */
 
 #include <assert.h>
-#include <common/debug.h>
-#include <drivers/delay_timer.h>
-#include <drivers/gpio.h>
-#include <lib/mmio.h>
 #include <mtgpio.h>
 #include <platform_def.h>
 
-/******************************************************************************
- *Macro Definition
- ******************************************************************************/
-#define GPIO_MODE_BITS		4
-#define MAX_GPIO_MODE_PER_REG	8
-#define MAX_GPIO_REG_BITS	32
-#define DIR_BASE		(GPIO_BASE + 0x000)
-#define DOUT_BASE		(GPIO_BASE + 0x100)
-#define DIN_BASE		(GPIO_BASE + 0x200)
-#define MODE_BASE		(GPIO_BASE + 0x300)
-#define SET			0x4
-#define CLR			0x8
-
-static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
-{
-	uint32_t pos, bit;
-
-	assert(pin < MAX_GPIO_PIN);
-	assert(dir < MT_GPIO_DIR_MAX);
-
-	pos = pin / MAX_GPIO_REG_BITS;
-	bit = pin % MAX_GPIO_REG_BITS;
-
-	if (dir == MT_GPIO_DIR_IN) {
-		mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
-	} else {
-		mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
-	}
-}
-
-static int mt_get_gpio_dir_chip(uint32_t pin)
-{
-	uint32_t pos, bit;
-	uint32_t reg;
-
-	assert(pin < MAX_GPIO_PIN);
-
-	pos = pin / MAX_GPIO_REG_BITS;
-	bit = pin % MAX_GPIO_REG_BITS;
-
-	reg = mmio_read_32(DIR_BASE + 0x10U * pos);
-	return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
-}
-
-static void mt_set_gpio_out_chip(uint32_t pin, int output)
-{
-	uint32_t pos, bit;
-
-	assert(pin < MAX_GPIO_PIN);
-	assert(output < MT_GPIO_OUT_MAX);
-
-	pos = pin / MAX_GPIO_REG_BITS;
-	bit = pin % MAX_GPIO_REG_BITS;
-
-	if (output == MT_GPIO_OUT_ZERO) {
-		mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
-	} else {
-		mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
-	}
-}
-
-static int mt_get_gpio_in_chip(uint32_t pin)
-{
-	uint32_t pos, bit;
-	uint32_t reg;
-
-	assert(pin < MAX_GPIO_PIN);
-
-	pos = pin / MAX_GPIO_REG_BITS;
-	bit = pin % MAX_GPIO_REG_BITS;
-
-	reg = mmio_read_32(DIN_BASE + 0x10U * pos);
-	return (((reg & (1U << bit)) != 0U) ? 1 : 0);
-}
-
-static uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
 {
 	uintptr_t reg_addr = 0U;
 	struct mt_pin_info gpio_info;
 
-	gpio_info = mt8192_pin_infos[pin];
+	assert(pin < MAX_GPIO_PIN);
+
+	gpio_info = mt_pin_infos[pin];
 
 	switch (gpio_info.base & 0x0f) {
 	case 0:
@@ -128,213 +51,3 @@
 
 	return reg_addr;
 }
-
-static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
-			       int select)
-{
-	uintptr_t reg1;
-	uintptr_t reg2;
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	uint32_t bit = gpio_info.bit;
-
-	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
-	reg2 = reg1 + (gpio_info.base & 0xf0);
-	if (enable == MT_GPIO_PULL_ENABLE) {
-		mmio_write_32(reg2 + SET, (1U << bit));
-		if (select == MT_GPIO_PULL_DOWN) {
-			mmio_write_32(reg1 + SET, (1U << bit));
-		} else {
-			mmio_write_32(reg1 + CLR, (1U << bit));
-		}
-	} else {
-		mmio_write_32(reg2 + CLR, (1U << bit));
-		mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
-	}
-}
-
-static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
-				 int select)
-{
-	uintptr_t reg1;
-	uintptr_t reg2;
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	uint32_t bit = gpio_info.bit;
-
-	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
-	reg2 = reg1 - (gpio_info.base & 0xf0);
-
-	if (enable == MT_GPIO_PULL_ENABLE) {
-		if (select == MT_GPIO_PULL_DOWN) {
-			mmio_write_32(reg1 + CLR, (1U << bit));
-			mmio_write_32(reg2 + SET, (1U << bit));
-		} else {
-			mmio_write_32(reg2 + CLR, (1U << bit));
-			mmio_write_32(reg1 + SET, (1U << bit));
-		}
-	} else {
-		mmio_write_32(reg1 + CLR, (1U << bit));
-		mmio_write_32(reg2 + CLR, (1U << bit));
-	}
-}
-
-static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
-		   int select)
-{
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	if (gpio_info.flag) {
-		mt_gpio_set_spec_pull_pupd(pin, enable, select);
-	} else {
-		mt_gpio_set_pull_pu_pd(pin, enable, select);
-	}
-}
-
-static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
-{
-	uintptr_t reg1;
-	uintptr_t reg2;
-	uint32_t r0;
-	uint32_t r1;
-
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	uint32_t bit = gpio_info.bit;
-
-	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
-	reg2 = reg1 + (gpio_info.base & 0xf0);
-
-	r0 = (mmio_read_32(reg2) >> bit) & 1U;
-	r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
-	if (r0 == 0U && r1 == 0U) {
-		return MT_GPIO_PULL_NONE;
-	} else {
-		if (mmio_read_32(reg1) & (1U << bit)) {
-			return MT_GPIO_PULL_DOWN;
-		} else {
-			return MT_GPIO_PULL_UP;
-		}
-	}
-}
-
-static int mt_gpio_get_pull_pu_pd(uint32_t pin)
-{
-	uintptr_t reg1;
-	uintptr_t reg2;
-	uint32_t pu;
-	uint32_t pd;
-
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	uint32_t bit = gpio_info.bit;
-
-	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
-	reg2 = reg1 - (gpio_info.base & 0xf0);
-	pu = (mmio_read_32(reg1) >> bit) & 1U;
-	pd = (mmio_read_32(reg2) >> bit) & 1U;
-	if (pu == 1U) {
-		return MT_GPIO_PULL_UP;
-	} else if (pd == 1U) {
-		return MT_GPIO_PULL_DOWN;
-	} else {
-		return MT_GPIO_PULL_NONE;
-	}
-}
-
-static int mt_gpio_get_pull_chip(uint32_t pin)
-{
-	struct mt_pin_info gpio_info;
-
-	gpio_info = mt8192_pin_infos[pin];
-	if (gpio_info.flag) {
-		return mt_gpio_get_spec_pull_pupd(pin);
-	} else {
-		return mt_gpio_get_pull_pu_pd(pin);
-	}
-}
-
-static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
-{
-	assert(pin < MAX_GPIO_PIN);
-
-	if (sel == MT_GPIO_PULL_NONE) {
-		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
-	} else if (sel == MT_GPIO_PULL_UP) {
-		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
-	} else if (sel == MT_GPIO_PULL_DOWN) {
-		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
-	}
-}
-
-/* get pull-up or pull-down, regardless of resistor value */
-static int mt_get_gpio_pull_select_chip(uint32_t pin)
-{
-	assert(pin < MAX_GPIO_PIN);
-
-	return mt_gpio_get_pull_chip(pin);
-}
-
-static void mt_set_gpio_dir(int gpio, int direction)
-{
-	mt_set_gpio_dir_chip((uint32_t)gpio, direction);
-}
-
-static int mt_get_gpio_dir(int gpio)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	return mt_get_gpio_dir_chip(pin);
-}
-
-static void mt_set_gpio_pull(int gpio, int pull)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	mt_set_gpio_pull_select_chip(pin, pull);
-}
-
-static int mt_get_gpio_pull(int gpio)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	return mt_get_gpio_pull_select_chip(pin);
-}
-
-static void mt_set_gpio_out(int gpio, int value)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	mt_set_gpio_out_chip(pin, value);
-}
-
-static int mt_get_gpio_in(int gpio)
-{
-	uint32_t pin;
-
-	pin = (uint32_t)gpio;
-	return mt_get_gpio_in_chip(pin);
-}
-
-const gpio_ops_t mtgpio_ops = {
-	 .get_direction = mt_get_gpio_dir,
-	 .set_direction = mt_set_gpio_dir,
-	 .get_value = mt_get_gpio_in,
-	 .set_value = mt_set_gpio_out,
-	 .set_pull = mt_set_gpio_pull,
-	 .get_pull = mt_get_gpio_pull,
-};
-
-void plat_mt8192_gpio_init(void)
-{
-	gpio_init(&mtgpio_ops);
-}
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
index ca0c964..d3aa24d 100644
--- a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
@@ -7,17 +7,7 @@
 #ifndef MT_GPIO_H
 #define MT_GPIO_H
 
-#include <stdbool.h>
-#include <stdint.h>
-
-#include <plat/common/common_def.h>
-
-/*  Error Code No. */
-#define RSUCCESS        0
-#define ERACCESS        1
-#define ERINVAL         2
-#define ERWRAPPER       3
-#define MAX_GPIO_PIN    MT_GPIO_BASE_MAX
+#include <mtgpio_common.h>
 
 /* Enumeration for GPIO pin */
 typedef enum GPIO_PIN {
@@ -54,110 +44,7 @@
 	MT_GPIO_BASE_MAX
 } GPIO_PIN;
 
-/* GPIO MODE CONTROL VALUE*/
-typedef enum {
-	GPIO_MODE_UNSUPPORTED = -1,
-	GPIO_MODE_GPIO  = 0,
-	GPIO_MODE_00    = 0,
-	GPIO_MODE_01,
-	GPIO_MODE_02,
-	GPIO_MODE_03,
-	GPIO_MODE_04,
-	GPIO_MODE_05,
-	GPIO_MODE_06,
-	GPIO_MODE_07,
-
-	GPIO_MODE_MAX,
-	GPIO_MODE_DEFAULT = GPIO_MODE_00,
-} GPIO_MODE;
-
-/* GPIO DIRECTION */
-typedef enum {
-	MT_GPIO_DIR_UNSUPPORTED = -1,
-	MT_GPIO_DIR_OUT    = 0,
-	MT_GPIO_DIR_IN     = 1,
-	MT_GPIO_DIR_MAX,
-	MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
-} GPIO_DIR;
-
-/* GPIO PULL ENABLE*/
-typedef enum {
-	MT_GPIO_PULL_EN_UNSUPPORTED = -1,
-	MT_GPIO_PULL_DISABLE   = 0,
-	MT_GPIO_PULL_ENABLE    = 1,
-	MT_GPIO_PULL_ENABLE_R0 = 2,
-	MT_GPIO_PULL_ENABLE_R1 = 3,
-	MT_GPIO_PULL_ENABLE_R0R1 = 4,
-
-	MT_GPIO_PULL_EN_MAX,
-	MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
-} GPIO_PULL_EN;
-
-/* GPIO PULL-UP/PULL-DOWN*/
-typedef enum {
-	MT_GPIO_PULL_UNSUPPORTED = -1,
-	MT_GPIO_PULL_NONE        = 0,
-	MT_GPIO_PULL_UP          = 1,
-	MT_GPIO_PULL_DOWN        = 2,
-	MT_GPIO_PULL_MAX,
-	MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
-} GPIO_PULL;
-
-/* GPIO OUTPUT */
-typedef enum {
-	MT_GPIO_OUT_UNSUPPORTED = -1,
-	MT_GPIO_OUT_ZERO = 0,
-	MT_GPIO_OUT_ONE  = 1,
-
-	MT_GPIO_OUT_MAX,
-	MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
-	MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO,  /*compatible with DCT*/
-} GPIO_OUT;
-
-/* GPIO INPUT */
-typedef enum {
-	MT_GPIO_IN_UNSUPPORTED = -1,
-	MT_GPIO_IN_ZERO = 0,
-	MT_GPIO_IN_ONE  = 1,
-
-	MT_GPIO_IN_MAX,
-} GPIO_IN;
-
-typedef struct {
-	uint32_t val;
-	uint32_t set;
-	uint32_t rst;
-	uint32_t _align1;
-} VAL_REGS;
-
-typedef struct {
-	VAL_REGS dir[7];
-	uint8_t rsv00[144];
-	VAL_REGS dout[7];
-	uint8_t rsv01[144];
-	VAL_REGS din[7];
-	uint8_t rsv02[144];
-	VAL_REGS mode[28];
-} GPIO_REGS;
-
-
-#define PIN(_id, _flag, _bit, _base, _offset) {		\
-		.id = _id,				\
-		.flag = _flag,				\
-		.bit = _bit,				\
-		.base = _base,				\
-		.offset = _offset,			\
-	}
-
-struct mt_pin_info {
-	uint8_t id;
-	uint8_t flag;
-	uint8_t bit;
-	uint16_t base;
-	uint16_t offset;
-};
-
-static const struct mt_pin_info mt8192_pin_infos[] = {
+static const struct mt_pin_info mt_pin_infos[] = {
 	PIN(0, 0, 9, 0x23, 0xb0),
 	PIN(1, 0, 10, 0x23, 0xb0),
 	PIN(2, 0, 11, 0x23, 0xb0),
@@ -379,6 +266,4 @@
 	PIN(218, 0, 1, 0x14, 0x50),
 	PIN(219, 0, 2, 0x14, 0x50),
 };
-
-void plat_mt8192_gpio_init(void);
 #endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
index 809518f..e74d3e7 100644
--- a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
@@ -6,8 +6,8 @@
 
 #include <mt_lp_rm.h>
 #include <mt_lp_irqremain.h>
+#include <mtk_cirq.h>
 #include <plat_mtk_lpm.h>
-#include <plat_mt_cirq.h>
 
 #define EDMA0_IRQ_ID		U(448)
 #define MDLA_IRQ_ID		U(446)
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
index 92fd25f..f66b8ec 100644
--- a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -24,7 +24,7 @@
 
 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
 #include <mt_gic_v3.h>
-#include <plat_mt_cirq.h>
+#include <mtk_cirq.h>
 #endif
 
 #define CONSTRAINT_BUS26M_ALLOW			\
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
index 307862d..2d67fdf 100644
--- a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
@@ -143,6 +143,11 @@
 		blocked |= SPM_COND_CHECK_BLOCKED_PLL;
 	}
 
+	if (is_system_suspend && (blocked != 0U)) {
+		INFO("suspend: %s total blocked = 0x%08x\n",
+		     dest->name, blocked);
+	}
+
 	return blocked;
 }
 
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
index ba13fe3..91ebdd9 100644
--- a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
@@ -23,20 +23,11 @@
 	PLAT_SPM_COND_MAX,
 };
 
-enum PLAT_SPM_COND_PLL {
-	PLAT_SPM_COND_PLL_UNIVPLL = 0,
-	PLAT_SPM_COND_PLL_MFGPLL,
-	PLAT_SPM_COND_PLL_MSDCPLL,
-	PLAT_SPM_COND_PLL_TVDPLL,
-	PLAT_SPM_COND_PLL_MMPLL,
-	PLAT_SPM_COND_PLL_MAX,
-};
-
-#define PLL_BIT_MFGPLL	(PLAT_SPM_COND_PLL_MFGPLL)
-#define PLL_BIT_MMPLL	(PLAT_SPM_COND_PLL_MMPLL)
-#define PLL_BIT_UNIVPLL	(PLAT_SPM_COND_PLL_UNIVPLL)
-#define PLL_BIT_MSDCPLL	(PLAT_SPM_COND_PLL_MSDCPLL)
-#define PLL_BIT_TVDPLL	(PLAT_SPM_COND_PLL_TVDPLL)
+#define PLL_BIT_UNIVPLL	BIT(0)
+#define PLL_BIT_MFGPLL	BIT(1)
+#define PLL_BIT_MSDCPLL	BIT(2)
+#define PLL_BIT_TVDPLL	BIT(3)
+#define PLL_BIT_MMPLL	BIT(4)
 
 /* Definition about SPM_COND_CHECK_BLOCKED
  * bit [00 ~ 15]: cg blocking index
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index 540463d..ec377b5 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -26,26 +26,40 @@
 #define MTK_MCDI_SRAM_BASE      0x11B000
 #define MTK_MCDI_SRAM_MAP_SIZE  0x1000
 
-#define TOPCKGEN_BASE    (IO_PHYS + 0x00000000)
-#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
-#define GPIO_BASE        (IO_PHYS + 0x00005000)
-#define SPM_BASE         (IO_PHYS + 0x00006000)
-#define APMIXEDSYS       (IO_PHYS + 0x0000C000)
-#define DVFSRC_BASE      (IO_PHYS + 0x00012000)
-#define PMIC_WRAP_BASE   (IO_PHYS + 0x00026000)
-#define EMI_BASE         (IO_PHYS + 0x00219000)
-#define EMI_MPU_BASE     (IO_PHYS + 0x00226000)
-#define SSPM_MBOX_BASE   (IO_PHYS + 0x00480000)
-#define IOCFG_RM_BASE    (IO_PHYS + 0x01C20000)
-#define IOCFG_BM_BASE    (IO_PHYS + 0x01D10000)
-#define IOCFG_BL_BASE    (IO_PHYS + 0x01D30000)
-#define IOCFG_BR_BASE    (IO_PHYS + 0x01D40000)
-#define IOCFG_LM_BASE    (IO_PHYS + 0x01E20000)
-#define IOCFG_LB_BASE    (IO_PHYS + 0x01E70000)
-#define IOCFG_RT_BASE    (IO_PHYS + 0x01EA0000)
-#define IOCFG_LT_BASE    (IO_PHYS + 0x01F20000)
-#define IOCFG_TL_BASE    (IO_PHYS + 0x01F30000)
-#define MMSYS_BASE       (IO_PHYS + 0x04000000)
+#define APUSYS_BASE                   0x19000000
+#define APUSYS_SCTRL_REVISER_BASE     0x19021000
+#define APUSYS_SCTRL_REVISER_SIZE     0x1000
+#define APUSYS_APU_S_S_4_BASE         0x190F2000
+#define APUSYS_APU_S_S_4_SIZE         0x1000
+#define APUSYS_APC_AO_WRAPPER_BASE    0x190F8000
+#define APUSYS_APC_AO_WRAPPER_SIZE    0x1000
+#define APUSYS_NOC_DAPC_AO_BASE       0x190FC000
+#define APUSYS_NOC_DAPC_AO_SIZE       0x1000
+
+#define TOPCKGEN_BASE            (IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE         (IO_PHYS + 0x00001000)
+#define GPIO_BASE                (IO_PHYS + 0x00005000)
+#define SPM_BASE                 (IO_PHYS + 0x00006000)
+#define APMIXEDSYS               (IO_PHYS + 0x0000C000)
+#define DVFSRC_BASE              (IO_PHYS + 0x00012000)
+#define PMIC_WRAP_BASE           (IO_PHYS + 0x00026000)
+#define DEVAPC_INFRA_AO_BASE     (IO_PHYS + 0x00030000)
+#define DEVAPC_PERI_AO_BASE      (IO_PHYS + 0x00034000)
+#define DEVAPC_PERI_AO2_BASE     (IO_PHYS + 0x00038000)
+#define DEVAPC_PERI_PAR_AO_BASE  (IO_PHYS + 0x0003C000)
+#define EMI_BASE                 (IO_PHYS + 0x00219000)
+#define EMI_MPU_BASE             (IO_PHYS + 0x00226000)
+#define SSPM_MBOX_BASE           (IO_PHYS + 0x00480000)
+#define IOCFG_RM_BASE            (IO_PHYS + 0x01C20000)
+#define IOCFG_BM_BASE            (IO_PHYS + 0x01D10000)
+#define IOCFG_BL_BASE            (IO_PHYS + 0x01D30000)
+#define IOCFG_BR_BASE            (IO_PHYS + 0x01D40000)
+#define IOCFG_LM_BASE            (IO_PHYS + 0x01E20000)
+#define IOCFG_LB_BASE            (IO_PHYS + 0x01E70000)
+#define IOCFG_RT_BASE            (IO_PHYS + 0x01EA0000)
+#define IOCFG_LT_BASE            (IO_PHYS + 0x01F20000)
+#define IOCFG_TL_BASE            (IO_PHYS + 0x01F30000)
+#define MMSYS_BASE               (IO_PHYS + 0x04000000)
 /*******************************************************************************
  * UART related constants
  ******************************************************************************/
@@ -61,13 +75,19 @@
 #define SYS_COUNTER_FREQ_IN_MHZ      13
 
 /*******************************************************************************
- * GIC-400 & interrupt handling related constants
+ * GIC-600 & interrupt handling related constants
  ******************************************************************************/
 
 /* Base MTK_platform compatible GIC memory map */
 #define BASE_GICD_BASE        MT_GIC_BASE
 #define MT_GIC_RDIST_BASE     (MT_GIC_BASE + 0x40000)
 
+#define SYS_CIRQ_BASE         (IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM          14
+#define CIRQ_IRQ_NUM          439
+#define CIRQ_SPI_START        64
+#define MD_WDT_IRQ_BIT_ID     110
+
 /*******************************************************************************
  * Platform binary types for linking
  ******************************************************************************/
diff --git a/plat/mediatek/mt8192/include/rtc.h b/plat/mediatek/mt8192/include/rtc.h
new file mode 100644
index 0000000..a9c7bc8
--- /dev/null
+++ b/plat/mediatek/mt8192/include/rtc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+#include <rtc_mt6359p.h>
+
+#endif  /* RTC_H */
diff --git a/plat/mediatek/mt8192/plat_sip_calls.c b/plat/mediatek/mt8192/plat_sip_calls.c
index 360ad0f..f567f02 100644
--- a/plat/mediatek/mt8192/plat_sip_calls.c
+++ b/plat/mediatek/mt8192/plat_sip_calls.c
@@ -6,6 +6,7 @@
 
 #include <common/debug.h>
 #include <common/runtime_svc.h>
+#include <mtk_apusys.h>
 #include <mtk_sip_svc.h>
 #include <mt_spm_vcorefs.h>
 #include "plat_sip_calls.h"
@@ -20,6 +21,7 @@
 				u_register_t flags)
 {
 	uint64_t ret;
+	uint32_t rnd_val0 = 0U;
 
 	switch (smc_fid) {
 	case MTK_SIP_VCORE_CONTROL_ARCH32:
@@ -27,6 +29,11 @@
 		ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
 		SMC_RET2(handle, ret, x4);
 		break;
+	case MTK_SIP_APUSYS_CONTROL_AARCH32:
+	case MTK_SIP_APUSYS_CONTROL_AARCH64:
+		ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0);
+		SMC_RET2(handle, ret, rnd_val0);
+		break;
 	default:
 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
 		break;
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index 0b35d06..7761a55 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -8,19 +8,23 @@
 MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
+                 -I${MTK_PLAT}/common/drivers/gic600/             \
+                 -I${MTK_PLAT}/common/drivers/gpio/               \
+                 -I${MTK_PLAT}/common/drivers/rtc/                \
+                 -I${MTK_PLAT}/common/drivers/timer/              \
+                 -I${MTK_PLAT}/common/drivers/uart/               \
                  -I${MTK_PLAT}/common/lpm/                        \
                  -I${MTK_PLAT_SOC}/include/                       \
                  -I${MTK_PLAT_SOC}/drivers/                       \
+                 -I${MTK_PLAT_SOC}/drivers/apusys/                \
                  -I${MTK_PLAT_SOC}/drivers/dcm                    \
+                 -I${MTK_PLAT_SOC}/drivers/devapc                 \
                  -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
                  -I${MTK_PLAT_SOC}/drivers/gpio/                  \
                  -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
                  -I${MTK_PLAT_SOC}/drivers/pmic/                  \
                  -I${MTK_PLAT_SOC}/drivers/ptp3/                  \
-                 -I${MTK_PLAT_SOC}/drivers/rtc/                   \
-                 -I${MTK_PLAT_SOC}/drivers/spmc/                  \
-                 -I${MTK_PLAT_SOC}/drivers/timer/                 \
-                 -I${MTK_PLAT_SOC}/drivers/uart/
+                 -I${MTK_PLAT_SOC}/drivers/spmc/
 
 GICV3_SUPPORT_GIC600        :=      1
 include drivers/arm/gic/v3/gicv3.mk
@@ -40,10 +44,15 @@
                    lib/cpus/aarch64/cortex_a55.S                         \
                    lib/cpus/aarch64/cortex_a76.S                         \
                    plat/common/plat_gicv3.c                              \
+                   ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c         \
+                   ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c       \
                    ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
                    ${MTK_PLAT}/common/drivers/rtc/rtc_common.c           \
+                   ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c          \
+                   ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
                    ${MTK_PLAT}/common/drivers/uart/uart.c                \
                    ${MTK_PLAT}/common/lpm/mt_lp_rm.c                     \
+                   ${MTK_PLAT}/common/mtk_cirq.c                         \
                    ${MTK_PLAT}/common/mtk_plat_common.c                  \
                    ${MTK_PLAT}/common/mtk_sip_svc.c                      \
                    ${MTK_PLAT}/common/params_setup.c                     \
@@ -51,14 +60,14 @@
                    ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                    ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
                    ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
-                   ${MTK_PLAT_SOC}/drivers/rtc/rtc.c                     \
                    ${MTK_PLAT_SOC}/plat_pm.c                             \
                    ${MTK_PLAT_SOC}/plat_topology.c                       \
-                   ${MTK_PLAT_SOC}/plat_mt_gic.c                         \
-                   ${MTK_PLAT_SOC}/plat_mt_cirq.c                        \
                    ${MTK_PLAT_SOC}/plat_sip_calls.c                      \
+                   ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c           \
+                   ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys_apc.c       \
                    ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c                 \
                    ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c           \
+                   ${MTK_PLAT_SOC}/drivers/devapc/devapc.c               \
                    ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c             \
                    ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
                    ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c              \
@@ -66,8 +75,7 @@
                    ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c        \
                    ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c                \
                    ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c          \
-                   ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
-                   ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c
+                   ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c
 
 # Build SPM drivers
 include ${MTK_PLAT_SOC}/drivers/spm/build.mk
diff --git a/plat/mediatek/mt8195/aarch64/plat_helpers.S b/plat/mediatek/mt8195/aarch64/plat_helpers.S
new file mode 100644
index 0000000..a973f4d
--- /dev/null
+++ b/plat/mediatek/mt8195/aarch64/plat_helpers.S
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl plat_is_my_cpu_primary
+	.globl plat_my_core_pos
+	.globl plat_mediatek_calc_core_pos
+
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+	cmp	x0, #PLAT_PRIMARY_CPU
+	cset	x0, eq
+	ret
+endfunc plat_is_my_cpu_primary
+
+	/* -----------------------------------------------------
+	 *  unsigned int plat_my_core_pos(void)
+	 *  This function uses the plat_mediatek_calc_core_pos()
+	 *  definition to get the index of the calling CPU.
+	 * -----------------------------------------------------
+	 */
+func plat_my_core_pos
+	mrs	x0, mpidr_el1
+	b	plat_mediatek_calc_core_pos
+endfunc plat_my_core_pos
+
+	/* -----------------------------------------------------
+	 * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+	 *
+	 * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and
+	 * AFF0 is thread id. There is only one cluster in ARMv8.2
+	 * and one thread in current implementation.
+	 *
+	 * With this function: CorePos = CoreID (AFF1)
+	 * we do it with x0 = (x0 >> 8) & 0xff
+	 * -----------------------------------------------------
+	 */
+func plat_mediatek_calc_core_pos
+	mov	x1, #MPIDR_AFFLVL_MASK
+	and	x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
+	ret
+endfunc plat_mediatek_calc_core_pos
diff --git a/plat/mediatek/mt8195/aarch64/platform_common.c b/plat/mediatek/mt8195/aarch64/platform_common.c
new file mode 100644
index 0000000..4792746
--- /dev/null
+++ b/plat/mediatek/mt8195/aarch64/platform_common.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include <platform_def.h>
+
+/* Table of regions to map using the MMU.  */
+const mmap_region_t plat_mmap[] = {
+	/* for TF text, RO, RW */
+	MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	{ 0 }
+};
+
+/*******************************************************************************
+ * Macro generating the code for the function setting up the pagetables as per
+ * the platform memory map & initialize the mmu, for the given exception level
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+			    uintptr_t total_size,
+			    uintptr_t ro_start,
+			    uintptr_t ro_limit)
+{
+	mmap_add_region(total_base, total_base, total_size,
+			MT_RW_DATA | MT_SECURE);
+	mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
+			MT_CODE | MT_SECURE);
+	mmap_add(plat_mmap);
+	init_xlat_tables();
+	enable_mmu_el3(0);
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	return SYS_COUNTER_FREQ_IN_TICKS;
+}
diff --git a/plat/mediatek/mt8195/bl31_plat_setup.c b/plat/mediatek/mt8195/bl31_plat_setup.c
new file mode 100644
index 0000000..8745454
--- /dev/null
+++ b/plat/mediatek/mt8195/bl31_plat_setup.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* System Includes */
+#include <assert.h>
+
+/* Project Includes */
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/ti/uart/uart_16550.h>
+#include <lib/coreboot.h>
+
+/* Platform Includes */
+#include <mt_gic_v3.h>
+#include <mt_spm.h>
+#include <mt_timer.h>
+#include <mtk_dcm.h>
+#include <mtgpio.h>
+#include <plat_params.h>
+#include <plat_private.h>
+
+static entry_point_info_t bl32_ep_info;
+static entry_point_info_t bl33_ep_info;
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image for
+ * the security state specified. BL33 corresponds to the non-secure image type
+ * while BL32 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+	entry_point_info_t *next_image_info;
+
+	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
+
+	/* None of the images on this platform can have 0x0 as the entrypoint */
+	if (next_image_info->pc) {
+		return next_image_info;
+	} else {
+		return NULL;
+	}
+}
+
+/*******************************************************************************
+ * Perform any BL31 early platform setup. Here is an opportunity to copy
+ * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
+ * are lost (potentially). This needs to be done before the MMU is initialized
+ * so that the memory layout can be used while creating page tables.
+ * BL2 has flushed this information to memory, so we are guaranteed to pick up
+ * good data.
+ ******************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
+{
+	static console_t console;
+
+	params_early_setup(arg1);
+
+#if COREBOOT
+	if (coreboot_serial.type) {
+		console_16550_register(coreboot_serial.baseaddr,
+				       coreboot_serial.input_hertz,
+				       coreboot_serial.baud,
+				       &console);
+	}
+#else
+	console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
+#endif
+
+	NOTICE("MT8195 bl31_setup\n");
+
+	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
+}
+
+
+/*******************************************************************************
+ * Perform any BL31 platform setup code
+ ******************************************************************************/
+void bl31_platform_setup(void)
+{
+	/* Set dcm on */
+	if (!dcm_set_default()) {
+		ERROR("Failed to set default dcm on!!\n");
+	}
+
+	/* Initialize the GIC driver, CPU and distributor interfaces */
+	mt_gic_driver_init();
+	mt_gic_init();
+
+	mt_gpio_init();
+	mt_systimer_init();
+	generic_delay_timer_init();
+	spm_boot_init();
+}
+
+/*******************************************************************************
+ * Perform the very early platform specific architectural setup here. At the
+ * moment this is only intializes the mmu in a quick and dirty way.
+ ******************************************************************************/
+void bl31_plat_arch_setup(void)
+{
+	plat_configure_mmu_el3(BL31_START,
+			       BL31_END - BL31_START,
+			       BL_CODE_BASE,
+			       BL_CODE_END);
+}
diff --git a/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.c b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.c
new file mode 100644
index 0000000..aed0833
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_dcm.h>
+#include <mtk_dcm_utils.h>
+
+static void dcm_armcore(bool mode)
+{
+	dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
+	dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
+	dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
+}
+
+static void dcm_mcusys(bool on)
+{
+	dcm_mp_cpusys_top_adb_dcm(on);
+	dcm_mp_cpusys_top_apb_dcm(on);
+	dcm_mp_cpusys_top_cpubiu_dcm(on);
+	dcm_mp_cpusys_top_misc_dcm(on);
+	dcm_mp_cpusys_top_mp0_qdcm(on);
+	dcm_cpccfg_reg_emi_wfifo(on);
+	dcm_mp_cpusys_top_last_cor_idle_dcm(on);
+}
+
+static void dcm_stall(bool on)
+{
+	dcm_mp_cpusys_top_core_stall_dcm(on);
+	dcm_mp_cpusys_top_fcm_stall_dcm(on);
+}
+
+static bool check_dcm_state(void)
+{
+	bool ret = true;
+
+	ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
+	ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
+	ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
+
+	ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
+	ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
+	ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
+	ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
+	ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
+	ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
+	ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
+
+	ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
+	ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
+
+	return ret;
+}
+
+bool dcm_set_default(void)
+{
+	dcm_armcore(true);
+	dcm_mcusys(true);
+	dcm_stall(true);
+
+	return check_dcm_state();
+}
diff --git a/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.h b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.h
new file mode 100644
index 0000000..cb65b85
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_DCM_H
+#define MTK_DCM_H
+
+#include <stdbool.h>
+
+bool dcm_set_default(void);
+
+#endif /* #ifndef MTK_DCM_H */
diff --git a/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.c b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.c
new file mode 100644
index 0000000..a1a3720
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.c
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mtk_dcm_utils.h>
+
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
+			BIT(16) | \
+			BIT(17) | \
+			BIT(18) | \
+			BIT(21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
+			BIT(16) | \
+			BIT(17) | \
+			BIT(18))
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \
+			BIT(16) | \
+			BIT(17) | \
+			BIT(18) | \
+			BIT(21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \
+			BIT(16) | \
+			BIT(17) | \
+			BIT(18))
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
+			(0x0 << 16) | \
+			(0x0 << 17) | \
+			(0x0 << 18) | \
+			(0x0 << 21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
+			(0x0 << 16) | \
+			(0x0 << 17) | \
+			(0x0 << 18))
+
+bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
+		MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
+		MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
+		MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_adb_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
+			MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
+			MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
+			MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
+			MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
+			MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
+			MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
+			MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
+			MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
+			MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
+			MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
+#define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
+#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))
+
+bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
+		MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
+		MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
+		MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_apb_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+			MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_APB_DCM_REG0_ON);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
+			MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
+			MP_CPUSYS_TOP_APB_DCM_REG1_ON);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
+			MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
+			MP_CPUSYS_TOP_APB_DCM_REG2_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+			MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
+			MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
+			MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
+			MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
+			MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11) | \
+			BIT(24) | \
+			BIT(25))
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | \
+			BIT(24) | \
+			BIT(25))
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11) | \
+			(0x0 << 24) | \
+			(0x0 << 25))
+
+bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
+		MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
+			MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
+			MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))
+
+bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
+		MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_core_stall_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
+			MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
+			MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))
+
+bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCSIC_DCM0) &
+		MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_cpubiu_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0,
+			MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0,
+			MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(24) | \
+			BIT(25))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(24) | \
+			BIT(25))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 24) | \
+			(0x0 << 25))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) &
+		MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0,
+			MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0,
+			MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(24) | \
+			BIT(25))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(24) | \
+			BIT(25))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 24) | \
+			(0x0 << 25))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) &
+		MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1,
+			MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1,
+			MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))
+
+bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
+		MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_fcm_stall_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
+			MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
+			MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31))
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31))
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31))
+
+bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
+		MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
+			MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
+			MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \
+			BIT(4))
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \
+			BIT(4))
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
+			(0x0 << 4))
+
+bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
+		MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_misc_dcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+			MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+			MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
+			MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
+	}
+}
+
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \
+			BIT(1) | \
+			BIT(2) | \
+			BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \
+			BIT(1) | \
+			BIT(2) | \
+			BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
+			(0x0 << 1) | \
+			(0x0 << 2) | \
+			(0x0 << 3))
+
+bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
+		MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
+	ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
+		MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
+		(unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
+
+	return ret;
+}
+
+void dcm_mp_cpusys_top_mp0_qdcm(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+			MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
+			MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
+			MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
+			MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+			MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
+			MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
+		mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
+			MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
+			MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
+	}
+}
+
+#define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \
+			BIT(1) | \
+			BIT(2) | \
+			BIT(3))
+#define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \
+			BIT(1) | \
+			BIT(2) | \
+			BIT(3))
+#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
+			(0x0 << 1) | \
+			(0x0 << 2) | \
+			(0x0 << 3))
+
+bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
+{
+	bool ret = true;
+
+	ret &= ((mmio_read_32(CPCCFG_REG_EMI_WFIFO) &
+		CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
+		(unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);
+
+	return ret;
+}
+
+void dcm_cpccfg_reg_emi_wfifo(bool on)
+{
+	if (on) {
+		/* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
+		mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO,
+			CPCCFG_REG_EMI_WFIFO_REG0_MASK,
+			CPCCFG_REG_EMI_WFIFO_REG0_ON);
+	} else {
+		/* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
+		mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO,
+			CPCCFG_REG_EMI_WFIFO_REG0_MASK,
+			CPCCFG_REG_EMI_WFIFO_REG0_OFF);
+	}
+}
diff --git a/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.h b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.h
new file mode 100644
index 0000000..e5743af
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_DCM_UTILS_H
+#define MTK_DCM_UTILS_H
+
+#include <stdbool.h>
+
+#include <mtk_dcm.h>
+#include <platform_def.h>
+
+/* Base */
+#define MP_CPUSYS_TOP_BASE	(MCUCFG_BASE + 0x8000)
+#define CPCCFG_REG_BASE		(MCUCFG_BASE + 0xA800)
+
+/* Register Definition */
+#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
+#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
+#define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
+#define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
+#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
+#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
+#define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
+#define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
+#define CPCCFG_REG_EMI_WFIFO (CPCCFG_REG_BASE + 0x100)
+#define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
+#define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c)
+
+/* MP_CPUSYS_TOP */
+bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
+void dcm_mp_cpusys_top_adb_dcm(bool on);
+bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
+void dcm_mp_cpusys_top_apb_dcm(bool on);
+bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
+void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on);
+bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
+void dcm_mp_cpusys_top_core_stall_dcm(bool on);
+bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpubiu_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on);
+bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
+void dcm_mp_cpusys_top_fcm_stall_dcm(bool on);
+bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
+void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on);
+bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
+void dcm_mp_cpusys_top_misc_dcm(bool on);
+bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
+void dcm_mp_cpusys_top_mp0_qdcm(bool on);
+/* CPCCFG_REG */
+bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
+void dcm_cpccfg_reg_emi_wfifo(bool on);
+
+#endif
diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.c b/plat/mediatek/mt8195/drivers/dp/mt_dp.c
new file mode 100644
index 0000000..7ab2194
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dp/mt_dp.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_dp.h>
+#include <mtk_sip_svc.h>
+#include <platform_def.h>
+
+static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset,
+				uint32_t value, uint32_t mask)
+{
+	uint32_t reg = (is_edp != 0U) ? eDP_SEC_BASE : DP_SEC_BASE;
+
+	mmio_clrsetbits_32(reg + offset, mask, value);
+
+	return mmio_read_32(reg + offset);
+}
+
+int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val)
+{
+	int32_t ret = 0L;
+	uint32_t is_edp = 0UL;
+	uint32_t regval = 0UL;
+	uint32_t regmsk = 0UL;
+	uint32_t fldmask = 0UL;
+
+	if ((cmd > DP_ATF_CMD_COUNT) || (val == NULL)) {
+		INFO("dp_secure_handler error cmd 0x%llx\n", cmd);
+		return MTK_SIP_E_INVALID_PARAM;
+	}
+
+	switch (cmd) {
+	case DP_ATF_DP_VIDEO_UNMUTE:
+		INFO("[%s] DP_ATF_DP_VIDEO_UNMUTE\n", __func__);
+		is_edp = DP_ATF_TYPE_DP;
+		ret = MTK_SIP_E_SUCCESS;
+		break;
+	case DP_ATF_EDP_VIDEO_UNMUTE:
+		INFO("[%s] DP_ATF_EDP_VIDEO_UNMUTE\n", __func__);
+		is_edp = DP_ATF_TYPE_EDP;
+		ret = MTK_SIP_E_SUCCESS;
+		break;
+	default:
+		ret = MTK_SIP_E_INVALID_PARAM;
+		break;
+	}
+
+	if (ret == MTK_SIP_E_SUCCESS) {
+		regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK |
+				VIDEO_MUTE_SW_SECURE_FLDMASK);
+		if (para > 0U) {
+			fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK;
+		} else {
+			fldmask = 0;
+		}
+
+		regval = (VIDEO_MUTE_SEL_SECURE_FLDMASK | fldmask);
+		*val = dp_write_sec_reg(is_edp, DP_TX_SECURE_REG11,
+					regval, regmsk);
+	}
+
+	return ret;
+}
diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.h b/plat/mediatek/mt8195/drivers/dp/mt_dp.h
new file mode 100644
index 0000000..8157598
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dp/mt_dp.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_DP_H
+#define MT_DP_H
+
+#define DP_TX_SECURE_REG11		(0x2c)
+
+#define VIDEO_MUTE_SEL_SECURE_FLDMASK	(0x10)
+#define VIDEO_MUTE_SW_SECURE_FLDMASK	(0x8)
+
+enum DP_ATF_HW_TYPE {
+	DP_ATF_TYPE_DP = 0,
+	DP_ATF_TYPE_EDP = 1
+};
+
+enum DP_ATF_CMD {
+	DP_ATF_DP_VIDEO_UNMUTE = 0x20,
+	DP_ATF_EDP_VIDEO_UNMUTE,
+	DP_ATF_CMD_COUNT
+};
+
+int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val);
+
+#endif
diff --git a/plat/mediatek/mt8195/drivers/gpio/mtgpio.c b/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..daab84c
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+	uintptr_t reg_addr = 0U;
+	struct mt_pin_info gpio_info;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	gpio_info = mt_pin_infos[pin];
+
+	switch (gpio_info.base & 0x0f) {
+	case 0:
+		reg_addr = IOCFG_BM_BASE;
+		break;
+	case 1:
+		reg_addr = IOCFG_BL_BASE;
+		break;
+	case 2:
+		reg_addr = IOCFG_BR_BASE;
+		break;
+	case 3:
+		reg_addr = IOCFG_LM_BASE;
+		break;
+	case 4:
+		reg_addr = IOCFG_RB_BASE;
+		break;
+	case 5:
+		reg_addr = IOCFG_TL_BASE;
+		break;
+	default:
+		break;
+	}
+
+	return reg_addr;
+}
diff --git a/plat/mediatek/mt8195/drivers/gpio/mtgpio.h b/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..88b4706
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <mtgpio_common.h>
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+	GPIO_UNSUPPORTED = -1,
+
+	GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
+	GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
+	GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
+	GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
+	GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
+	GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
+	GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
+	GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
+	GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
+	GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
+	GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
+	GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
+	GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
+	GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
+	GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
+	GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
+	GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135,
+	GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143,
+	MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+static const struct mt_pin_info mt_pin_infos[] = {
+	PIN(0, 1, 0, 0x23, 0x60),
+	PIN(1, 1, 1, 0x23, 0x60),
+	PIN(2, 1, 2, 0x23, 0x60),
+	PIN(3, 1, 3, 0x23, 0x60),
+	PIN(4, 1, 4, 0x23, 0x60),
+	PIN(5, 1, 5, 0x23, 0x60),
+	PIN(6, 0, 6, 0x23, 0x70),
+	PIN(7, 0, 7, 0x23, 0x70),
+	PIN(8, 0, 13, 0x23, 0x70),
+	PIN(9, 0, 8, 0x23, 0x70),
+	PIN(10, 0, 14, 0x23, 0x70),
+	PIN(11, 0, 9, 0x23, 0x70),
+	PIN(12, 0, 15, 0x23, 0x70),
+	PIN(13, 0, 10, 0x23, 0x70),
+	PIN(14, 0, 16, 0x23, 0x70),
+	PIN(15, 0, 11, 0x23, 0x70),
+	PIN(16, 0, 17, 0x23, 0x70),
+	PIN(17, 0, 12, 0x23, 0x70),
+	PIN(18, 0, 5, 0x10, 0x60),
+	PIN(19, 0, 12, 0x10, 0x60),
+	PIN(20, 0, 11, 0x10, 0x60),
+	PIN(21, 0, 10, 0x10, 0x60),
+	PIN(22, 0, 0, 0x10, 0x60),
+	PIN(23, 0, 1, 0x10, 0x60),
+	PIN(24, 0, 2, 0x10, 0x60),
+	PIN(25, 0, 4, 0x10, 0x60),
+	PIN(26, 0, 3, 0x10, 0x60),
+	PIN(27, 0, 6, 0x10, 0x60),
+	PIN(28, 0, 7, 0x10, 0x60),
+	PIN(29, 0, 8, 0x10, 0x60),
+	PIN(30, 0, 9, 0x10, 0x60),
+	PIN(31, 0, 13, 0x21, 0xa0),
+	PIN(32, 0, 12, 0x21, 0xa0),
+	PIN(33, 0, 11, 0x21, 0xa0),
+	PIN(34, 0, 14, 0x21, 0xa0),
+	PIN(35, 0, 15, 0x21, 0xa0),
+	PIN(36, 0, 3, 0x21, 0xb0),
+	PIN(37, 0, 6, 0x21, 0xb0),
+	PIN(38, 0, 4, 0x21, 0xb0),
+	PIN(39, 0, 5, 0x21, 0xb0),
+	PIN(40, 0, 8, 0x21, 0xb0),
+	PIN(41, 0, 7, 0x21, 0xb0),
+	PIN(42, 0, 10, 0x21, 0xb0),
+	PIN(43, 0, 9, 0x21, 0xb0),
+	PIN(44, 0, 20, 0x21, 0xb0),
+	PIN(45, 0, 21, 0x21, 0xb0),
+	PIN(46, 0, 18, 0x21, 0xa0),
+	PIN(47, 0, 16, 0x21, 0xa0),
+	PIN(48, 0, 19, 0x21, 0xa0),
+	PIN(49, 0, 17, 0x21, 0xa0),
+	PIN(50, 0, 25, 0x21, 0xa0),
+	PIN(51, 0, 20, 0x21, 0xa0),
+	PIN(52, 0, 26, 0x21, 0xa0),
+	PIN(53, 0, 21, 0x21, 0xa0),
+	PIN(54, 0, 22, 0x21, 0xa0),
+	PIN(55, 0, 23, 0x21, 0xa0),
+	PIN(56, 0, 24, 0x21, 0xa0),
+	PIN(57, 0, 29, 0x21, 0xa0),
+	PIN(58, 0, 27, 0x21, 0xa0),
+	PIN(59, 0, 30, 0x21, 0xa0),
+	PIN(60, 0, 28, 0x21, 0xa0),
+	PIN(61, 0, 8, 0x21, 0xa0),
+	PIN(62, 0, 7, 0x21, 0xa0),
+	PIN(63, 0, 10, 0x21, 0xa0),
+	PIN(64, 0, 9, 0x21, 0xa0),
+	PIN(65, 0, 1, 0x21, 0xb0),
+	PIN(66, 0, 31, 0x21, 0xa0),
+	PIN(67, 0, 0, 0x21, 0xb0),
+	PIN(68, 0, 2, 0x21, 0xb0),
+	PIN(69, 0, 0, 0x21, 0xa0),
+	PIN(70, 0, 6, 0x21, 0xa0),
+	PIN(71, 0, 4, 0x21, 0xa0),
+	PIN(72, 0, 5, 0x21, 0xa0),
+	PIN(73, 0, 1, 0x21, 0xa0),
+	PIN(74, 0, 2, 0x21, 0xa0),
+	PIN(75, 0, 3, 0x21, 0xa0),
+	PIN(76, 0, 11, 0x21, 0xb0),
+	PIN(77, 1, 1, 0x22, 0x60),
+	PIN(78, 1, 2, 0x22, 0x60),
+	PIN(79, 1, 9, 0x22, 0x60),
+	PIN(80, 1, 10, 0x22, 0x60),
+	PIN(81, 1, 11, 0x22, 0x60),
+	PIN(82, 1, 12, 0x22, 0x60),
+	PIN(83, 1, 13, 0x22, 0x60),
+	PIN(84, 1, 14, 0x22, 0x60),
+	PIN(85, 1, 15, 0x22, 0x60),
+	PIN(86, 1, 16, 0x22, 0x60),
+	PIN(87, 1, 3, 0x22, 0x60),
+	PIN(88, 1, 4, 0x22, 0x60),
+	PIN(89, 1, 5, 0x22, 0x60),
+	PIN(90, 1, 6, 0x22, 0x60),
+	PIN(91, 1, 7, 0x22, 0x60),
+	PIN(92, 1, 8, 0x22, 0x60),
+	PIN(93, 1, 18, 0x22, 0x60),
+	PIN(94, 1, 19, 0x22, 0x60),
+	PIN(95, 1, 17, 0x22, 0x60),
+	PIN(96, 1, 0, 0x22, 0x60),
+	PIN(97, 0, 20, 0x22, 0x70),
+	PIN(98, 0, 28, 0x22, 0x70),
+	PIN(99, 0, 27, 0x22, 0x70),
+	PIN(100, 0, 30, 0x22, 0x70),
+	PIN(101, 0, 29, 0x22, 0x70),
+	PIN(102, 0, 0, 0x22, 0x70),
+	PIN(103, 0, 31, 0x22, 0x70),
+	PIN(104, 1, 25, 0x22, 0x60),
+	PIN(105, 1, 26, 0x22, 0x60),
+	PIN(106, 1, 23, 0x22, 0x60),
+	PIN(107, 1, 24, 0x22, 0x60),
+	PIN(108, 0, 22, 0x22, 0x70),
+	PIN(109, 0, 21, 0x22, 0x70),
+	PIN(110, 1, 1, 0x14, 0x20),
+	PIN(111, 1, 0, 0x14, 0x20),
+	PIN(112, 1, 2, 0x14, 0x20),
+	PIN(113, 1, 3, 0x14, 0x20),
+	PIN(114, 1, 4, 0x14, 0x20),
+	PIN(115, 1, 5, 0x14, 0x20),
+	PIN(116, 1, 9, 0x25, 0x50),
+	PIN(117, 1, 8, 0x25, 0x50),
+	PIN(118, 1, 7, 0x25, 0x50),
+	PIN(119, 1, 6, 0x25, 0x50),
+	PIN(120, 1, 11, 0x25, 0x50),
+	PIN(121, 1, 1, 0x25, 0x50),
+	PIN(122, 1, 0, 0x25, 0x50),
+	PIN(123, 1, 5, 0x25, 0x50),
+	PIN(124, 1, 4, 0x25, 0x50),
+	PIN(125, 1, 3, 0x25, 0x50),
+	PIN(126, 1, 2, 0x25, 0x50),
+	PIN(127, 1, 10, 0x25, 0x50),
+	PIN(128, 0, 3, 0x22, 0x70),
+	PIN(129, 0, 1, 0x22, 0x70),
+	PIN(130, 0, 4, 0x22, 0x70),
+	PIN(131, 0, 2, 0x22, 0x70),
+	PIN(132, 0, 13, 0x25, 0x60),
+	PIN(133, 0, 12, 0x25, 0x60),
+	PIN(134, 0, 15, 0x25, 0x60),
+	PIN(135, 0, 14, 0x25, 0x60),
+	PIN(136, 0, 13, 0x21, 0xb0),
+	PIN(137, 0, 12, 0x21, 0xb0),
+	PIN(138, 0, 15, 0x21, 0xb0),
+	PIN(139, 0, 14, 0x21, 0xb0),
+	PIN(140, 0, 17, 0x21, 0xb0),
+	PIN(141, 0, 16, 0x21, 0xb0),
+	PIN(142, 0, 19, 0x21, 0xb0),
+	PIN(143, 0, 18, 0x21, 0xb0),
+};
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c
new file mode 100644
index 0000000..5a80d95
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+#include <lib/spinlock.h>
+
+#include <mt_cpu_pm_cpc.h>
+#include <mt_lp_irqremain.h>
+#include <mt_lp_rm.h>
+#include <mt_mcdi.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1);
+
+static int plat_mt_lp_cpu_rc;
+
+static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state)
+{
+	return 0;
+}
+
+static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state)
+{
+	mtk_cpc_core_on_hint_clr(cpu);
+
+	if (IS_SYSTEM_SUSPEND_STATE(state)) {
+		mtk_cpc_time_sync();
+	}
+
+	return 0;
+}
+
+static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+	return 0;
+}
+
+static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+	/* clear DBGPRCR.CORENPDRQ to allow CPU power down  */
+	write_dbgprcr_el1(0ULL);
+
+	return 0;
+}
+
+static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+	return 0;
+}
+
+static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+	return 0;
+}
+
+static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+	if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
+		return -1;
+	}
+
+	mtk_cpc_mcusys_off_reflect();
+
+	return 0;
+}
+
+static int pwr_mcusys_pwron_finished(unsigned int cpu,
+					const psci_power_state_t *state)
+{
+	int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
+	if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
+		return -1;
+	}
+
+	mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
+	mt_lp_irqremain_release();
+
+	return 0;
+}
+
+static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+	int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
+	if (!IS_MCUSYS_OFF_STATE(state)) {
+		goto mt_pwr_mcusysoff_break;
+	}
+
+	if (mcdi_try_init() != 0) {
+		goto mt_pwr_mcusysoff_break;
+	}
+
+	if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
+		goto mt_pwr_mcusysoff_break;
+	}
+
+	plat_mt_lp_cpu_rc =
+		mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
+
+	if (plat_mt_lp_cpu_rc < 0) {
+		goto mt_pwr_mcusysoff_reflect;
+	}
+
+	mt_lp_irqremain_aquire();
+
+	return 0;
+
+mt_pwr_mcusysoff_reflect:
+	mtk_cpc_mcusys_off_reflect();
+
+mt_pwr_mcusysoff_break:
+
+	plat_mt_lp_cpu_rc = -1;
+
+	return -1;
+}
+
+static const struct mt_lpm_tz plat_pm = {
+	.pwr_prompt			= pwr_state_prompt,
+	.pwr_reflect			= pwr_state_reflect,
+	.pwr_cpu_on			= pwr_cpu_pwron,
+	.pwr_cpu_dwn			= pwr_cpu_pwrdwn,
+	.pwr_cluster_on			= pwr_cluster_pwron,
+	.pwr_cluster_dwn		= pwr_cluster_pwrdwn,
+	.pwr_mcusys_dwn			= pwr_mcusys_pwrdwn,
+	.pwr_mcusys_on			= pwr_mcusys_pwron,
+	.pwr_mcusys_on_finished		= pwr_mcusys_pwron_finished
+};
+
+const struct mt_lpm_tz *mt_plat_cpu_pm_init(void)
+{
+	mtk_cpc_init();
+
+	if (mcdi_try_init() == 0) {
+		INFO("MCDI init done.\n");
+	}
+
+	mt_lp_irqremain_init();
+
+	return &plat_pm;
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c
new file mode 100644
index 0000000..f8c51a1
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <drivers/delay_timer.h>
+
+#include <mt_cpu_pm_cpc.h>
+#include <mt_timer.h>
+
+struct mtk_cpc_dev {
+	int auto_off;
+	unsigned int auto_thres_tick;
+};
+
+static struct mtk_cpc_dev cpc;
+
+static int mtk_cpc_last_core_prot(uint32_t prot_req,
+				uint32_t resp_reg, uint32_t resp_ofs)
+{
+	uint32_t sta, retry;
+
+	retry = 0U;
+
+	while (retry++ < RETRY_CNT_MAX) {
+
+		mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req);
+
+		udelay(1U);
+
+		sta = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK;
+
+		if (sta == PROT_SUCCESS) {
+			return CPC_SUCCESS;
+		} else if (sta == PROT_GIVEUP) {
+			return CPC_ERR_FAIL;
+		}
+	}
+
+	return CPC_ERR_TIMEOUT;
+}
+
+int mtk_cpu_pm_mcusys_prot_aquire(void)
+{
+	return mtk_cpc_last_core_prot(
+			MCUSYS_PROT_SET,
+			CPC_MCUSYS_LAST_CORE_RESP,
+			MCUSYS_RESP_OFS);
+}
+
+void mtk_cpu_pm_mcusys_prot_release(void)
+{
+	mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR);
+}
+
+int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster)
+{
+	return mtk_cpc_last_core_prot(
+			CPUSYS_PROT_SET,
+			CPC_MCUSYS_MP_LAST_CORE_RESP,
+			CPUSYS_RESP_OFS);
+}
+
+void mtk_cpu_pm_cluster_prot_release(unsigned int cluster)
+{
+	mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR);
+}
+
+static void mtk_cpc_cluster_cnt_backup(void)
+{
+	uint32_t backup_cnt;
+	uint32_t curr_cnt;
+	uint32_t cnt_mask = GENMASK(14, 0);
+	uint32_t clr_mask = GENMASK(1, 0);
+
+	/* Single Cluster */
+	backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP);
+	curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER);
+
+	/* Get off count if dormant count is 0 */
+	if ((curr_cnt & cnt_mask) == 0U) {
+		curr_cnt = (curr_cnt >> 16) & cnt_mask;
+	} else {
+		curr_cnt = curr_cnt & cnt_mask;
+	}
+
+	mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt);
+	mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask);
+}
+
+static inline void mtk_cpc_mcusys_off_en(void)
+{
+	mmio_write_32(CPC_MCUSYS_PWR_CTRL, 1U);
+}
+
+static inline void mtk_cpc_mcusys_off_dis(void)
+{
+	mmio_write_32(CPC_MCUSYS_PWR_CTRL, 0U);
+}
+
+void mtk_cpc_mcusys_off_reflect(void)
+{
+	mtk_cpc_mcusys_off_dis();
+	mtk_cpu_pm_mcusys_prot_release();
+}
+
+int mtk_cpc_mcusys_off_prepare(void)
+{
+	if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) {
+		return CPC_ERR_FAIL;
+	}
+
+	mtk_cpc_cluster_cnt_backup();
+	mtk_cpc_mcusys_off_en();
+
+	return CPC_SUCCESS;
+}
+
+void mtk_cpc_core_on_hint_set(unsigned int cpu)
+{
+	mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu));
+}
+
+void mtk_cpc_core_on_hint_clr(unsigned int cpu)
+{
+	mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu));
+}
+
+static void mtk_cpc_dump_timestamp(void)
+{
+	uint32_t id;
+
+	for (id = 0U; id < CPC_TRACE_ID_NUM; id++) {
+		mmio_write_32(CPC_MCUSYS_TRACE_SEL, id);
+
+		memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id),
+				(const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA,
+				CPC_TRACE_SIZE);
+	}
+}
+
+void mtk_cpc_time_sync(void)
+{
+	uint64_t kt;
+	uint32_t systime_l, systime_h;
+
+	kt = sched_clock();
+	systime_l = mmio_read_32(CNTSYS_L_REG);
+	systime_h = mmio_read_32(CNTSYS_H_REG);
+
+	/* sync kernel timer to cpc */
+	mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt);
+	mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32));
+	/* sync system timer to cpc */
+	mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l);
+	mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h);
+}
+
+static void mtk_cpc_config(uint32_t cfg, uint32_t data)
+{
+	uint32_t val;
+	uint32_t reg = 0U;
+
+	switch (cfg) {
+	case CPC_SMC_CONFIG_PROF:
+		reg = CPC_MCUSYS_CPC_DBG_SETTING;
+		val = mmio_read_32(reg);
+		val = (data != 0U) ? (val | CPC_PROF_EN) : (val & ~CPC_PROF_EN);
+		break;
+	case CPC_SMC_CONFIG_AUTO_OFF:
+		reg = CPC_MCUSYS_CPC_FLOW_CTRL_CFG;
+		val = mmio_read_32(reg);
+		if (data != 0U) {
+			val |= CPC_AUTO_OFF_EN;
+			cpc.auto_off = 1;
+		} else {
+			val &= ~CPC_AUTO_OFF_EN;
+			cpc.auto_off = 0;
+		}
+		break;
+	case CPC_SMC_CONFIG_AUTO_OFF_THRES:
+		reg = CPC_MCUSYS_CPC_OFF_THRES;
+		cpc.auto_thres_tick = us_to_ticks(data);
+		val = cpc.auto_thres_tick;
+		break;
+	case CPC_SMC_CONFIG_CNT_CLR:
+		reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR;
+		val = GENMASK(1, 0);	/* clr_mask */
+		break;
+	case CPC_SMC_CONFIG_TIME_SYNC:
+		mtk_cpc_time_sync();
+		break;
+	default:
+		break;
+	}
+
+	if (reg != 0U) {
+		mmio_write_32(reg, val);
+	}
+}
+
+static uint32_t mtk_cpc_read_config(uint32_t cfg)
+{
+	uint32_t res = 0U;
+
+	switch (cfg) {
+	case CPC_SMC_CONFIG_PROF:
+		res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ?
+			1U : 0U;
+		break;
+	case CPC_SMC_CONFIG_AUTO_OFF:
+		res = cpc.auto_off;
+		break;
+	case CPC_SMC_CONFIG_AUTO_OFF_THRES:
+		res = ticks_to_us(cpc.auto_thres_tick);
+		break;
+	case CPC_SMC_CONFIG_CNT_CLR:
+		break;
+	default:
+		break;
+	}
+
+	return res;
+}
+
+uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2)
+{
+	uint64_t res = 0ULL;
+
+	switch (act) {
+	case CPC_SMC_EVENT_DUMP_TRACE_DATA:
+		mtk_cpc_dump_timestamp();
+		break;
+	case CPC_SMC_EVENT_GIC_DPG_SET:
+		/* isolated_status = x2; */
+		break;
+	case CPC_SMC_EVENT_CPC_CONFIG:
+		mtk_cpc_config((uint32_t)arg1, (uint32_t)arg2);
+		break;
+	case CPC_SMC_EVENT_READ_CONFIG:
+		res = mtk_cpc_read_config((uint32_t)arg1);
+		break;
+	default:
+		break;
+	}
+
+	return res;
+}
+
+void mtk_cpc_init(void)
+{
+	mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING,
+			mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING)
+			| CPC_DBG_EN
+			| CPC_CALC_EN);
+
+	cpc.auto_off = 1;
+	cpc.auto_thres_tick = us_to_ticks(8000);
+
+	mmio_write_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
+			mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG)
+			| CPC_OFF_PRE_EN
+			| (cpc.auto_off ? CPC_AUTO_OFF_EN : 0U));
+
+	mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick);
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h
new file mode 100644
index 0000000..19dd6a2
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_CPU_PM_CPC_H
+#define MT_CPU_PM_CPC_H
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mcucfg.h>
+#include <platform_def.h>
+
+#define NEED_CPUSYS_PROT_WORKAROUND	1
+
+/* system sram registers */
+#define CPUIDLE_SRAM_REG(r)	(uint32_t)(MTK_MCDI_SRAM_BASE + (r))
+
+/* db dump */
+#define CPC_TRACE_SIZE		U(0x20)
+#define CPC_TRACE_ID_NUM	U(10)
+#define CPC_TRACE_SRAM(id)	(CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE)
+
+/* buckup off count */
+#define CPC_CLUSTER_CNT_BACKUP	CPUIDLE_SRAM_REG(0x1F0)
+#define CPC_MCUSYS_CNT		CPUIDLE_SRAM_REG(0x1F4)
+
+/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG(0xA814): debug setting */
+#define CPC_PWR_ON_SEQ_DIS	BIT(1)
+#define CPC_PWR_ON_PRIORITY	BIT(2)
+#define CPC_AUTO_OFF_EN		BIT(5)
+#define CPC_DORMANT_WAIT_EN	BIT(14)
+#define CPC_CTRL_EN		BIT(16)
+#define CPC_OFF_PRE_EN		BIT(29)
+
+/* CPC_MCUSYS_LAST_CORE_REQ(0xA818) : last core protection */
+#define CPUSYS_PROT_SET		BIT(0)
+#define MCUSYS_PROT_SET		BIT(8)
+#define CPUSYS_PROT_CLR		BIT(8)
+#define MCUSYS_PROT_CLR		BIT(9)
+
+#define CPC_PROT_RESP_MASK	U(0x3)
+#define CPUSYS_RESP_OFS		U(16)
+#define MCUSYS_RESP_OFS		U(30)
+
+#define cpusys_resp(r)		(((r) >> CPUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
+#define mcusys_resp(r)		(((r) >> MCUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
+
+#define RETRY_CNT_MAX		U(1000)
+
+#define PROT_RETRY		U(0)
+#define PROT_SUCCESS		U(1)
+#define PROT_GIVEUP		U(2)
+
+/* CPC_MCUSYS_CPC_DBG_SETTING(0xAB00): debug setting */
+#define CPC_PROF_EN		BIT(0)
+#define CPC_DBG_EN		BIT(1)
+#define CPC_FREEZE		BIT(2)
+#define CPC_CALC_EN		BIT(3)
+
+enum {
+	CPC_SUCCESS = 0,
+
+	CPC_ERR_FAIL,
+	CPC_ERR_TIMEOUT,
+
+	NF_CPC_ERR
+};
+
+enum {
+	CPC_SMC_EVENT_DUMP_TRACE_DATA,
+	CPC_SMC_EVENT_GIC_DPG_SET,
+	CPC_SMC_EVENT_CPC_CONFIG,
+	CPC_SMC_EVENT_READ_CONFIG,
+
+	NF_CPC_SMC_EVENT
+};
+
+enum {
+	CPC_SMC_CONFIG_PROF,
+	CPC_SMC_CONFIG_AUTO_OFF,
+	CPC_SMC_CONFIG_AUTO_OFF_THRES,
+	CPC_SMC_CONFIG_CNT_CLR,
+	CPC_SMC_CONFIG_TIME_SYNC,
+
+	NF_CPC_SMC_CONFIG
+};
+
+#define us_to_ticks(us)		((us) * 13)
+#define ticks_to_us(tick)	((tick) / 13)
+
+int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster);
+void mtk_cpu_pm_cluster_prot_release(unsigned int cluster);
+
+void mtk_cpc_mcusys_off_reflect(void);
+int mtk_cpc_mcusys_off_prepare(void);
+
+void mtk_cpc_core_on_hint_set(unsigned int cpu);
+void mtk_cpc_core_on_hint_clr(unsigned int cpu);
+void mtk_cpc_time_sync(void);
+
+uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2);
+void mtk_cpc_init(void);
+
+#endif /* MT_CPU_PM_CPC_H */
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c
new file mode 100644
index 0000000..4147184
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mt_lp_rm.h>
+#include <mt_lp_irqremain.h>
+#include <mtk_cirq.h>
+#include <plat_mtk_lpm.h>
+
+
+#define KEYPAD_IRQ_ID		U(138)
+
+#define KEYPAD_WAKESRC		0x4
+
+static struct mt_irqremain remain_irqs;
+
+int mt_lp_irqremain_submit(void)
+{
+	if (remain_irqs.count == 0) {
+		return -1;
+	}
+
+	set_wakeup_sources(remain_irqs.irqs, remain_irqs.count);
+	mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs);
+
+	return 0;
+}
+
+int mt_lp_irqremain_aquire(void)
+{
+	if (remain_irqs.count == 0) {
+		return -1;
+	}
+
+	mt_cirq_sw_reset();
+	mt_cirq_clone_gic();
+	mt_cirq_enable();
+
+	return 0;
+}
+
+int mt_lp_irqremain_release(void)
+{
+	if (remain_irqs.count == 0) {
+		return -1;
+	}
+
+	mt_cirq_flush();
+	mt_cirq_disable();
+
+	return 0;
+}
+
+void mt_lp_irqremain_init(void)
+{
+	uint32_t idx;
+
+	remain_irqs.count = 0;
+
+	/*edge keypad*/
+	idx = remain_irqs.count;
+	remain_irqs.irqs[idx] = KEYPAD_IRQ_ID;
+	remain_irqs.wakeupsrc_cat[idx] = 0;
+	remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC;
+	remain_irqs.count++;
+
+	mt_lp_irqremain_submit();
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h
new file mode 100644
index 0000000..b86e17e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_IRQREMAIN_H
+#define MT_LP_IRQREMAIN_H
+
+extern int mt_lp_irqremain_submit(void);
+extern int mt_lp_irqremain_aquire(void);
+extern int mt_lp_irqremain_release(void);
+extern void mt_lp_irqremain_init(void);
+#endif /* MT_LP_IRQREMAIN_H */
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c
new file mode 100644
index 0000000..c14e83b
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+#include <common/debug.h>
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mt_mcdi.h>
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY	U(0)
+#define APMCU_MCUPM_MBOX_RESERVED_1	U(1)
+#define APMCU_MCUPM_MBOX_RESERVED_2	U(2)
+#define APMCU_MCUPM_MBOX_RESERVED_3	U(3)
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN	U(4)
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE	U(5)
+#define APMCU_MCUPM_MBOX_BUCK_MODE	U(6)
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE	U(7)
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA	U(8)
+#define APMCU_MCUPM_MBOX_RESERVED_9	U(9)
+#define APMCU_MCUPM_MBOX_RESERVED_10	U(10)
+#define APMCU_MCUPM_MBOX_RESERVED_11	U(11)
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU	U(12)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN */
+#define MCUPM_MCUSYS_CTRL		BIT(0)
+#define MCUPM_BUCK_CTRL			BIT(1)
+#define MCUPM_ARMPLL_CTRL		BIT(2)
+#define MCUPM_CM_CTRL			BIT(3)
+#define MCUPM_PWR_CTRL_MASK		GENMASK(3, 0)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE */
+#define MCUPM_BUCK_NORMAL_MODE		U(0) /* default */
+#define MCUPM_BUCK_LP_MODE		U(1)
+#define MCUPM_BUCK_OFF_MODE		U(2)
+#define NF_MCUPM_BUCK_MODE		U(3)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE */
+#define MCUPM_ARMPLL_ON			U(0) /* default */
+#define MCUPM_ARMPLL_GATING		U(1)
+#define MCUPM_ARMPLL_OFF		U(2)
+#define NF_MCUPM_ARMPLL_MODE		U(3)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA */
+#define MCUPM_TASK_UNINIT		U(0)
+#define MCUPM_TASK_INIT			U(1)
+#define MCUPM_TASK_INIT_FINISH		U(2)
+#define MCUPM_TASK_WAIT			U(3)
+#define MCUPM_TASK_RUN			U(4)
+#define MCUPM_TASK_PAUSE		U(5)
+
+#define SSPM_MBOX_3_BASE		U(0x0c55fce0)
+
+#define MCDI_NOT_INIT			0
+#define MCDI_INIT_1			1
+#define MCDI_INIT_2			2
+#define MCDI_INIT_DONE			3
+
+static int mcdi_init_status __section("tzfw_coherent_mem");
+
+static inline uint32_t mcdi_mbox_read(uint32_t id)
+{
+	return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2));
+}
+
+static inline void mcdi_mbox_write(uint32_t id, uint32_t val)
+{
+	mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val);
+}
+
+static void mtk_mcupm_pwr_ctrl_setting(uint32_t dev)
+{
+	mcdi_mbox_write(APMCU_MCUPM_MBOX_PWR_CTRL_EN, dev);
+}
+
+static void mtk_set_mcupm_pll_mode(uint32_t mode)
+{
+	if (mode < NF_MCUPM_ARMPLL_MODE) {
+		mcdi_mbox_write(APMCU_MCUPM_MBOX_ARMPLL_MODE, mode);
+	}
+}
+
+static void mtk_set_mcupm_buck_mode(uint32_t mode)
+{
+	if (mode < NF_MCUPM_BUCK_MODE) {
+		mcdi_mbox_write(APMCU_MCUPM_MBOX_BUCK_MODE, mode);
+	}
+}
+
+static int mtk_mcupm_is_ready(void)
+{
+	unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
+
+	return (sta == MCUPM_TASK_WAIT) || (sta == MCUPM_TASK_INIT_FINISH);
+}
+
+static int mcdi_init_1(void)
+{
+	unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
+
+	if (sta != MCUPM_TASK_INIT) {
+		return -1;
+	}
+
+	mtk_set_mcupm_pll_mode(MCUPM_ARMPLL_OFF);
+	mtk_set_mcupm_buck_mode(MCUPM_BUCK_OFF_MODE);
+
+	mtk_mcupm_pwr_ctrl_setting(
+			 MCUPM_MCUSYS_CTRL |
+			 MCUPM_BUCK_CTRL |
+			 MCUPM_ARMPLL_CTRL);
+
+	mcdi_mbox_write(APMCU_MCUPM_MBOX_AP_READY, 1);
+
+	return 0;
+}
+
+static int mcdi_init_2(void)
+{
+	return mtk_mcupm_is_ready() ? 0 : -1;
+}
+
+int mcdi_try_init(void)
+{
+	if (mcdi_init_status == MCDI_INIT_DONE) {
+		return 0;
+	}
+
+	if (mcdi_init_status == MCDI_NOT_INIT) {
+		mcdi_init_status = MCDI_INIT_1;
+	}
+
+	if (mcdi_init_status == MCDI_INIT_1 && mcdi_init_1() == 0) {
+		mcdi_init_status = MCDI_INIT_2;
+	}
+
+	if (mcdi_init_status == MCDI_INIT_2 && mcdi_init_2() == 0) {
+		mcdi_init_status = MCDI_INIT_DONE;
+	}
+
+	INFO("mcdi ready for mcusys-off-idle and system suspend\n");
+
+	return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status;
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h
new file mode 100644
index 0000000..f3545aa
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_MCDI_H
+#define MT_MCDI_H
+
+int mcdi_try_init(void);
+
+#endif /* MT_MCDI_H */
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.c b/plat/mediatek/mt8195/drivers/pmic/pmic.c
new file mode 100644
index 0000000..cca4413
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <pmic.h>
+#include <pmic_wrap_init.h>
+
+void pmic_power_off(void)
+{
+	pwrap_write(PMIC_PWRHOLD, 0x0);
+}
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.h b/plat/mediatek/mt8195/drivers/pmic/pmic.h
new file mode 100644
index 0000000..aac22af
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_H
+#define PMIC_H
+
+#define PMIC_PWRHOLD 0xa08
+
+/* external API */
+void pmic_power_off(void);
+
+#endif /* PMIC_H */
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
new file mode 100644
index 0000000..39e78f5
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <stdint.h>
+
+#include "platform_def.h"
+
+/* external API */
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+
+static struct mt8195_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+/* PMIC_WRAP registers */
+struct mt8195_pmic_wrap_regs {
+	uint32_t init_done;
+	uint32_t reserved[543];
+	uint32_t wacs2_cmd;
+	uint32_t wacs2_wdata;
+	uint32_t reserved1[3];
+	uint32_t wacs2_rdata;
+	uint32_t reserved2[3];
+	uint32_t wacs2_vldclr;
+	uint32_t wacs2_sta;
+};
+
+#define GET_WACS_FSM(x)	((x >> 1) & 0x7)
+
+/* macro for SWINF_FSM */
+#define SWINF_FSM_IDLE		(0x00)
+#define SWINF_FSM_REQ		(0x02)
+#define SWINF_FSM_WFDLE		(0x04)
+#define SWINF_FSM_WFVLDCLR	(0x06)
+#define SWINF_INIT_DONE		(0x01)
+
+/* timeout setting */
+#define PWRAP_READ_US	1000
+#define PWRAP_WAIT_IDLE_US	1000
+
+/* error information flag */
+enum pwrap_errno {
+	E_PWR_INVALID_ARG             = 1,
+	E_PWR_INVALID_RW              = 2,
+	E_PWR_INVALID_ADDR            = 3,
+	E_PWR_INVALID_WDAT            = 4,
+	E_PWR_INVALID_OP_MANUAL       = 5,
+	E_PWR_NOT_IDLE_STATE          = 6,
+	E_PWR_NOT_INIT_DONE           = 7,
+	E_PWR_NOT_INIT_DONE_READ      = 8,
+	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
+	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
+	E_PWR_INIT_SIDLY_FAIL         = 11,
+	E_PWR_RESET_TIMEOUT           = 12,
+	E_PWR_TIMEOUT                 = 13,
+	E_PWR_INIT_RESET_SPI          = 20,
+	E_PWR_INIT_SIDLY              = 21,
+	E_PWR_INIT_REG_CLOCK          = 22,
+	E_PWR_INIT_ENABLE_PMIC        = 23,
+	E_PWR_INIT_DIO                = 24,
+	E_PWR_INIT_CIPHER             = 25,
+	E_PWR_INIT_WRITE_TEST         = 26,
+	E_PWR_INIT_ENABLE_CRC         = 27,
+	E_PWR_INIT_ENABLE_DEWRAP      = 28,
+	E_PWR_INIT_ENABLE_EVENT       = 29,
+	E_PWR_READ_TEST_FAIL          = 30,
+	E_PWR_WRITE_TEST_FAIL         = 31,
+	E_PWR_SWITCH_DIO              = 32
+};
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h
new file mode 100644
index 0000000..341cf86
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_PTP3_COMMON_H
+#define MTK_PTP3_COMMON_H
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+/************************************************
+ * CPU info
+ ************************************************/
+#define NR_PTP3_CFG_CPU			U(8)
+#define PTP3_CFG_CPU_START_ID_L		U(0)
+#define PTP3_CFG_CPU_START_ID_B		U(4)
+#define PTP3_CFG_CPU_END_ID		U(7)
+
+#define NR_PTP3_CFG1_DATA		U(2)
+#define PTP3_CFG1_MASK			0x3000
+
+#define NR_PTP3_CFG2_DATA		U(5)
+
+#define PTP3_CFG3_MASK1			0x1180
+#define PTP3_CFG3_MASK2			0x35C0
+#define PTP3_CFG3_MASK3			0x3DC0
+
+/************************************************
+ * register read/write
+ ************************************************/
+#define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val)
+#define ptp3_clrsetbits(addr, clear, set) \
+	mmio_clrsetbits_32((uintptr_t)addr, clear, set)
+
+/************************************************
+ * config enum
+ ************************************************/
+enum PTP3_CFG {
+	PTP3_CFG_ADDR,
+	PTP3_CFG_VALUE,
+	NR_PTP3_CFG,
+};
+
+/************************************
+ * prototype
+ ************************************/
+extern void ptp3_core_init(unsigned int core);
+extern void ptp3_core_unInit(unsigned int core);
+
+#endif /* MTK_PTP3_COMMON_H */
diff --git a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c
new file mode 100644
index 0000000..540cb33
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved. \
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <mtk_ptp3_common.h>
+
+#define PTP3_CORE_OFT(core)	(0x800 * (core))
+
+/************************************************
+ * Central control
+ ************************************************/
+static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = {
+	{0x0C53A2A0, 0x1000},
+	{0x0C53A2A4, 0x1000}
+};
+
+static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = {
+	{0x0C530404, 0x3A1000},
+	{0x0C530428, 0x13E0408},
+	{0x0C530434, 0xB22800},
+	{0x0C53043C, 0x750},
+	{0x0C530440, 0x0222c4cc}
+};
+
+static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80};
+static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00};
+
+static void ptp3_init(unsigned int core)
+{
+	unsigned int i, addr, value;
+
+	if (core < PTP3_CFG_CPU_START_ID_B) {
+		ptp3_clrsetbits(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
+				ptp3_cfg1[0][PTP3_CFG_VALUE]);
+	} else {
+		ptp3_clrsetbits(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
+				ptp3_cfg1[1][PTP3_CFG_VALUE]);
+	}
+
+	if (core < PTP3_CFG_CPU_START_ID_B) {
+		for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
+			addr = ptp3_cfg2[i][PTP3_CFG_ADDR] +
+			       PTP3_CORE_OFT(core);
+			value = ptp3_cfg2[i][PTP3_CFG_VALUE];
+
+			ptp3_write(addr, value);
+		}
+	} else {
+		for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
+			addr = ptp3_cfg2[i][PTP3_CFG_ADDR] +
+			       PTP3_CORE_OFT(core);
+
+			if (i == 2) {
+				value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0;
+			} else {
+				value = ptp3_cfg2[i][PTP3_CFG_VALUE];
+			}
+			ptp3_write(addr, value);
+		}
+	}
+
+	if (core < PTP3_CFG_CPU_START_ID_B) {
+		addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
+		value = ptp3_cfg3[PTP3_CFG_VALUE];
+
+		ptp3_write(addr, value & PTP3_CFG3_MASK1);
+		ptp3_write(addr, value & PTP3_CFG3_MASK2);
+		ptp3_write(addr, value & PTP3_CFG3_MASK3);
+	} else {
+		addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
+		value = ptp3_cfg3_ext[PTP3_CFG_VALUE];
+
+		ptp3_write(addr, value & PTP3_CFG3_MASK1);
+		ptp3_write(addr, value & PTP3_CFG3_MASK2);
+		ptp3_write(addr, value & PTP3_CFG3_MASK3);
+	}
+}
+
+void pdp_proc_ARM_write(unsigned int pdp_n)
+{
+	unsigned long v = 0;
+
+	dsb();
+	__asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
+	v |= (UL(0x0) << 52);
+	v |= (UL(0x1) << 53);
+	v |= (UL(0x0) << 54);
+	v |= (UL(0x0) << 48);
+	v |= (UL(0x1) << 49);
+	__asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
+	dsb();
+}
+
+void pdp_init(unsigned int pdp_cpu, unsigned int en)
+{
+	if ((pdp_cpu >= PTP3_CFG_CPU_START_ID_B) &&
+	    (pdp_cpu < NR_PTP3_CFG_CPU)) {
+		pdp_proc_ARM_write(pdp_cpu);
+	}
+}
+
+static void dt_proc_ARM_write(unsigned int dt_n)
+{
+	unsigned long v = 0;
+
+	dsb();
+	__asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
+	v |= (UL(0x0) << 33);
+	v |= (UL(0x0) << 32);
+	__asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
+	dsb();
+}
+
+void dt_init(unsigned int dt_cpu, unsigned int en)
+{
+	if ((dt_cpu >= PTP3_CFG_CPU_START_ID_B) &&
+	    (dt_cpu < NR_PTP3_CFG_CPU)) {
+		dt_proc_ARM_write(dt_cpu);
+	}
+}
+void ptp3_core_init(unsigned int core)
+{
+	/* init for ptp3 */
+	ptp3_init(core);
+	/* init for pdp */
+	pdp_init(core, 1);
+	/* init for dt */
+	dt_init(core, 1);
+}
+
+void ptp3_core_unInit(unsigned int core)
+{
+	/* TBD */
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/build.mk b/plat/mediatek/mt8195/drivers/spm/build.mk
new file mode 100644
index 0000000..d1ee092
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/build.mk
@@ -0,0 +1,67 @@
+#
+# Copyright (c) 2021, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Enable or disable spm feature
+MT_SPM_FEATURE_SUPPORT = yes
+
+# Enable or disable cirq restore
+MT_SPM_CIRQ_FEATURE_SUPPORT = yes
+
+# sspm notifier support
+MT_SPM_SSPM_NOTIFIER_SUPPORT = yes
+
+CUR_SPM_FOLDER = ${MTK_PLAT_SOC}/drivers/spm
+
+# spm common files
+PLAT_SPM_SOURCE_FILES_COMMON +=			\
+	${CUR_SPM_FOLDER}/mt_spm.c		\
+	${CUR_SPM_FOLDER}/mt_spm_conservation.c	\
+	${CUR_SPM_FOLDER}/mt_spm_internal.c	\
+	${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c
+
+# spm platform dependcy files
+PLAT_SPM_SOURCE_FILES +=					\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_bus26m.c	\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_cpu_buck_ldo.c	\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_dram.c		\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c	\
+	${CUR_SPM_FOLDER}/mt_spm_cond.c				\
+	${CUR_SPM_FOLDER}/mt_spm_suspend.c			\
+	${CUR_SPM_FOLDER}/mt_spm_idle.c
+
+ifeq (${MT_SPM_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${PLAT_SPM_SOURCE_FILES_COMMON}
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES +=	\
+	${PLAT_SPM_SOURCE_FILES_COMMON} \
+	${PLAT_SPM_SOURCE_FILES}
+endif
+
+ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_CIRQ_UNSUPPORT
+endif
+
+ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES +=	\
+	${CUR_SPM_FOLDER}/notifier/mt_spm_sspm_notifier.c
+endif
+
+$(info --------------------------------------)
+$(info SPM build flags: ${PLAT_SPM_DEBUG_CFLAGS})
+$(info SPM build files: ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES})
+$(info --------------------------------------)
+
+# Common makefile for platform.mk
+PLAT_INCLUDES +=				\
+	${PLAT_SPM_DEBUG_CFLAGS}		\
+	-I${CUR_SPM_FOLDER}/			\
+	-I${CUR_SPM_FOLDER}/constraints/	\
+	-I${CUR_SPM_FOLDER}/notifier/
+
+PLAT_BL_COMMON_SOURCES += ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES}
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..d2ad282
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mt_gic_v3.h>
+#include <mtk_cirq.h>
+#endif
+
+#define CONSTRAINT_BUS26M_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_VCORE_LP |	\
+	 MT_RM_CONSTRAINT_ALLOW_LVTS_STATE |	\
+	 MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_ENABLE_TIA_WORKAROUND |	\
+	 SPM_FLAG_ENABLE_LVTS_WORKAROUND |	\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH |	\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1		0U
+
+#define CONSTRAINT_BUS26M_RESOURCE_REQ		0U
+
+static unsigned int bus26m_ext_opand;
+static struct mt_irqremain *refer2remain_irq;
+static struct mt_spm_cond_tables cond_bus26m = {
+	.name = "bus26m",
+	.table_cg = {
+		0xFFFFD408,	/* MTCMOS1 */
+		0x2284C802,	/* INFRA0  */
+		0x27AF8000,	/* INFRA1  */
+		0x86040650,	/* INFRA2  */
+		0x30038020,	/* INFRA3  */
+		0x80000000,	/* INFRA4  */
+		0x00080ABB,	/* PERI0   */
+		0x00004000,	/* VPPSYS0_0  */
+		0x08803000,	/* VPPSYS0_1  */
+		0x00000000,	/* VPPSYS0_2  */
+		0x80005555,	/* VPPSYS1_0  */
+		0x00009008,	/* VPPSYS1_1  */
+		0x60060000,	/* VDOSYS0_0  */
+		0x00000000,	/* VDOSYS0_1  */
+		0x201E01F8,	/* VDOSYS1_0  */
+		0x00800000,	/* VDOSYS1_1  */
+		0x00000000,	/* VDOSYS1_2  */
+		0x00000080,	/* I2C */
+	},
+	.table_pll = (PLL_BIT_UNIVPLL |
+		      PLL_BIT_MFGPLL |
+		      PLL_BIT_MSDCPLL |
+		      PLL_BIT_TVDPLL |
+		      PLL_BIT_MMPLL),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_BUS26M,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_bus26m_res,
+};
+
+/*
+ * Cirq will take the place of gic when gic is off.
+ * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
+ * Therefore, we need to set irq pending for specific wakeup source.
+ */
+#ifdef ATF_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+				   unsigned int irq_index,
+				   struct wake_status *wakeup)
+{
+	INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
+	     wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
+	     wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
+	     wakeup->tr.comm.b_sw_flag1);
+
+	INFO("irq:%u(0x%08x) set pending\n",
+	     irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+	unsigned int idx;
+	int res = 0;
+	struct wake_status *wakeup = NULL;
+	struct mt_irqremain *irqs = refer2remain_irq;
+
+	res = spm_conservation_get_result(&wakeup);
+
+	if ((res != 0) && (irqs == NULL)) {
+		return;
+	}
+
+	for (idx = 0U; idx < irqs->count; ++idx) {
+		if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+		    ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+			if ((irqs->wakeupsrc_cat[idx] &
+			     MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+				mt_spm_irq_remain_dump(irqs, idx, wakeup);
+			}
+
+			mt_irq_set_pending(irqs->irqs[idx]);
+		}
+	}
+}
+#endif
+
+static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp,
+			       unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	if (type == PLAT_RC_UPDATE_CONDITION) {
+		tlb = (const struct mt_spm_cond_tables *)val;
+		tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+		status.cond_block =
+			mt_spm_cond_check(state_id, tlb, tlb_check,
+					  ((status.valid &
+					    MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+					  &cond_bus26m_res : NULL);
+	} else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
+		refer2remain_irq = (struct mt_irqremain *)val;
+	} else {
+		res = MT_RM_STATUS_BAD;
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				      bus26m_ext_opand),
+				     CONSTRAINT_BUS26M_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT,
+					  spm_bus26m_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
+		mt_spm_suspend_resume(state_id, ext_op, NULL);
+		bus26m_ext_opand = 0U;
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+		status.enter_cnt++;
+	}
+
+	do_irqs_delivery();
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..cf71350
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1		0U
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ	\
+	(MT_SPM_DRAM_S1 |			\
+	 MT_SPM_DRAM_S0 |			\
+	 MT_SPM_SYSPLL |			\
+	 MT_SPM_INFRA |				\
+	 MT_SPM_26M |				\
+	 MT_SPM_XO_FPM)
+
+
+static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
+static unsigned int cpubuckldo_enter_cnt;
+
+static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
+				     unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+	(void)state_id;
+
+	return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				     MT_SPM_EX_OP_SET_WDT,
+				     CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, 0U,
+					  spm_cpu_bcuk_ldo_conduct);
+	}
+
+	cpubuckldo_enter_cnt++;
+
+	return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, 0U, NULL);
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_dram.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..bd24ddd
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#define CONSTRAINT_DRAM_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_DRAM_S0	|	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH |	\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1		0U
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ		\
+	(MT_SPM_SYSPLL |			\
+	 MT_SPM_INFRA |				\
+	 MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+	.name = "dram",
+	.table_cg = {
+		0xFFFDD008,	/* MTCMOS1 */
+		0x20040802,	/* INFRA0  */
+		0x27AF8000,	/* INFRA1  */
+		0x86040640,	/* INFRA2  */
+		0x00000000,	/* INFRA3  */
+		0x80000000,	/* INFRA4  */
+		0x00000000,	/* PERI0   */
+		0x00004000,	/* VPPSYS0_0  */
+		0x08803000,	/* VPPSYS0_1  */
+		0x00000000,	/* VPPSYS0_2  */
+		0x80005555,	/* VPPSYS1_0  */
+		0x00009008,	/* VPPSYS1_1  */
+		0x60060000,	/* VDOSYS0_0  */
+		0x00000000,	/* VDOSYS0_1  */
+		0x201E01F8,	/* VDOSYS1_0  */
+		0x00800000,	/* VDOSYS1_1  */
+		0x00000000,	/* VDOSYS1_2  */
+		0x00000080,	/* I2C */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_DRAM,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH |
+		  MT_SPM_RC_VALID_XSOC_BBLPM),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_dram_res,
+};
+
+static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
+			     unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	if (type == PLAT_RC_UPDATE_CONDITION) {
+		tlb = (const struct mt_spm_cond_tables *)val;
+		tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+		status.cond_block =
+			mt_spm_cond_check(state_id, tlb, tlb_check,
+					  ((status.valid &
+					    MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+					  &cond_dram_res : NULL);
+	} else {
+		res = MT_RM_STATUS_BAD;
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#else
+	(void)allows;
+#endif
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				      MT_SPM_EX_OP_HW_S1_DETECT),
+				     CONSTRAINT_DRAM_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_WDT |
+				       MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+		status.enter_cnt++;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_internal.h b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..9e74ace
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#include <stdbool.h>
+
+#define SPM_FLAG_SRAM_SLEEP_CTRL			\
+	(SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |	\
+	 SPM_FLAG_DISABLE_SYSRAM_SLEEP)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+#endif /* MT_SPM_RC_INTERNAL_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_syspll.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..662f85e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH |	\
+	 SPM_FLAG_ENABLE_6315_CTRL |		\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
+	 SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1		0U
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ		(MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_syspll = {
+	.name = "syspll",
+	.table_cg = {
+		0xFFFFD008,	/* MTCMOS1 */
+		0x20844802,	/* INFRA0  */
+		0x27AF8000,	/* INFRA1  */
+		0x86040640,	/* INFRA2  */
+		0x30038020,	/* INFRA3  */
+		0x80000000,	/* INFRA4  */
+		0x00080A8B,	/* PERI0   */
+		0x00004000,	/* VPPSYS0_0  */
+		0x08803000,	/* VPPSYS0_1  */
+		0x00000000,	/* VPPSYS0_2  */
+		0x80005555,	/* VPPSYS1_0  */
+		0x00009008,	/* VPPSYS1_1  */
+		0x60060000,	/* VDOSYS0_0  */
+		0x00000000,	/* VDOSYS0_1  */
+		0x201E01F8,	/* VDOSYS1_0  */
+		0x00800000,	/* VDOSYS1_1  */
+		0x00000000,	/* VDOSYS1_2  */
+		0x00000080,	/* I2C */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_SYSPLL,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH |
+		  MT_SPM_RC_VALID_XSOC_BBLPM),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_syspll_res,
+};
+
+static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
+			       unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	if (type == PLAT_RC_UPDATE_CONDITION) {
+		tlb = (const struct mt_spm_cond_tables *)val;
+		tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
+
+		status.cond_block =
+			mt_spm_cond_check(state_id, tlb, tlb_check,
+					  ((status.valid &
+					    MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+					  &cond_syspll_res : NULL);
+	} else {
+		res = MT_RM_STATUS_BAD;
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#else
+	(void)allows;
+#endif
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE),
+				     CONSTRAINT_SYSPLL_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				       MT_SPM_EX_OP_SET_WDT |
+				       MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+		status.enter_cnt++;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm.c b/plat/mediatek/mt8195/drivers/spm/mt_spm.c
new file mode 100644
index 0000000..f708bf5
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <string.h>
+#include <common/debug.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <mtk_plat_common.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+#include <sleep_def.h>
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DEFINE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock_init() bakery_lock_init(&spm_lock)
+#else
+spinlock_t spm_lock;
+#define plat_spm_lock_init()
+#endif
+
+/* CLK_SCP_CFG_0 */
+#define CLK_SCP_CFG_0		(TOPCKGEN_BASE + 0x264)
+#define SPM_CK_CONTROL_EN	0x7FF
+
+struct mt_resource_constraint plat_constraint_bus26m = {
+	.is_valid = spm_is_valid_rc_bus26m,
+	.update = spm_update_rc_bus26m,
+	.allow = spm_allow_rc_bus26m,
+	.run = spm_run_rc_bus26m,
+	.reset = spm_reset_rc_bus26m,
+};
+
+struct mt_resource_constraint plat_constraint_syspll = {
+	.is_valid = spm_is_valid_rc_syspll,
+	.update = spm_update_rc_syspll,
+	.allow = spm_allow_rc_syspll,
+	.run = spm_run_rc_syspll,
+	.reset = spm_reset_rc_syspll,
+};
+
+struct mt_resource_constraint plat_constraint_dram = {
+	.is_valid = spm_is_valid_rc_dram,
+	.update = spm_update_rc_dram,
+	.allow = spm_allow_rc_dram,
+	.run = spm_run_rc_dram,
+	.reset = spm_reset_rc_dram,
+};
+
+struct mt_resource_constraint plat_constraint_cpu = {
+	.is_valid = spm_is_valid_rc_cpu_buck_ldo,
+	.update = NULL,
+	.allow = spm_allow_rc_cpu_buck_ldo,
+	.run = spm_run_rc_cpu_buck_ldo,
+	.reset = spm_reset_rc_cpu_buck_ldo,
+};
+
+struct mt_resource_constraint *plat_constraints[] = {
+	&plat_constraint_bus26m,
+	&plat_constraint_syspll,
+	&plat_constraint_dram,
+	&plat_constraint_cpu,
+	NULL,
+};
+
+struct mt_resource_manager plat_mt8195_rm = {
+	.update = mt_spm_cond_update,
+	.consts = plat_constraints,
+};
+
+void spm_boot_init(void)
+{
+	NOTICE("MT8195 %s\n", __func__);
+	/* switch ck_off/axi_26m control to SPM */
+	mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
+
+	plat_spm_lock_init();
+	mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+	mt_lp_rm_register(&plat_mt8195_rm);
+	mt_spm_idle_generic_init();
+	mt_spm_suspend_init();
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm.h b/plat/mediatek/mt8195/drivers/spm/mt_spm.h
new file mode 100644
index 0000000..bc57b61
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_H
+#define MT_SPM_H
+
+#include <lib/bakery_lock.h>
+#include <lib/spinlock.h>
+
+#include <plat_mtk_lpm.h>
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. So, there is no doubt to use the spin_lock here
+ */
+#if !HW_ASSISTED_COHERENCY
+#define MT_SPM_USING_BAKERY_LOCK
+#endif
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DECLARE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock() bakery_lock_get(&spm_lock)
+#define plat_spm_unlock() bakery_lock_release(&spm_lock)
+#else
+extern spinlock_t spm_lock;
+#define plat_spm_lock() spin_lock(&spm_lock)
+#define plat_spm_unlock() spin_unlock(&spm_lock)
+#endif
+
+#define MT_SPM_USING_SRCLKEN_RC
+
+/* spm extern operand definition */
+#define MT_SPM_EX_OP_CLR_26M_RECORD			(1U << 0)
+#define MT_SPM_EX_OP_SET_WDT				(1U << 1)
+#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ		(1U << 2)
+#define MT_SPM_EX_OP_SET_SUSPEND_MODE			(1U << 3)
+#define MT_SPM_EX_OP_SET_IS_ADSP			(1U << 4)
+#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM			(1U << 5)
+#define MT_SPM_EX_OP_HW_S1_DETECT			(1U << 6)
+
+typedef enum {
+	WR_NONE = 0,
+	WR_UART_BUSY = 1,
+	WR_ABORT = 2,
+	WR_PCM_TIMER = 3,
+	WR_WAKE_SRC = 4,
+	WR_DVFSRC = 5,
+	WR_TWAM = 6,
+	WR_PMSR = 7,
+	WR_SPM_ACK_CHK = 8,
+	WR_UNKNOWN = 9,
+} wake_reason_t;
+
+static inline void spm_lock_get(void)
+{
+	plat_spm_lock();
+}
+
+static inline void spm_lock_release(void)
+{
+	plat_spm_unlock();
+}
+
+extern void spm_boot_init(void);
+#endif /* MT_SPM_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
new file mode 100644
index 0000000..c80faf5
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+#define MT_LP_TZ_INFRA_REG(ofs)		(INFRACFG_AO_BASE + ofs)
+#define MT_LP_TZ_SPM_REG(ofs)		(SPM_BASE + ofs)
+#define MT_LP_TZ_TOPCK_REG(ofs)		(TOPCKGEN_BASE + ofs)
+#define MT_LP_TZ_APMIXEDSYS(ofs)	(APMIXEDSYS + ofs)
+#define MT_LP_TZ_VPPSYS0_REG(ofs)	(VPPSYS0_BASE + ofs)
+#define MT_LP_TZ_VPPSYS1_REG(ofs)	(VPPSYS1_BASE + ofs)
+#define MT_LP_TZ_VDOSYS0_REG(ofs)	(VDOSYS0_BASE + ofs)
+#define MT_LP_TZ_VDOSYS1_REG(ofs)	(VDOSYS1_BASE + ofs)
+#define MT_LP_TZ_PERI_AO_REG(ofs)	(PERICFG_AO_BASE + ofs)
+
+#define SPM_PWR_STATUS			MT_LP_TZ_SPM_REG(0x016C)
+#define SPM_PWR_STATUS_2ND		MT_LP_TZ_SPM_REG(0x0170)
+#define INFRA_SW_CG0			MT_LP_TZ_INFRA_REG(0x0094)
+#define INFRA_SW_CG1			MT_LP_TZ_INFRA_REG(0x0090)
+#define INFRA_SW_CG2			MT_LP_TZ_INFRA_REG(0x00AC)
+#define INFRA_SW_CG3			MT_LP_TZ_INFRA_REG(0x00C8)
+#define INFRA_SW_CG4			MT_LP_TZ_INFRA_REG(0x00E8)
+#define TOP_SW_I2C_CG			MT_LP_TZ_TOPCK_REG(0x00BC)
+#define PERI_SW_CG0			MT_LP_TZ_PERI_AO_REG(0x0018)
+#define VPPSYS0_SW_CG0			MT_LP_TZ_VPPSYS0_REG(0x0020)
+#define VPPSYS0_SW_CG1			MT_LP_TZ_VPPSYS0_REG(0x002C)
+#define VPPSYS0_SW_CG2			MT_LP_TZ_VPPSYS0_REG(0x0038)
+#define VPPSYS1_SW_CG0			MT_LP_TZ_VPPSYS1_REG(0x0100)
+#define VPPSYS1_SW_CG1			MT_LP_TZ_VPPSYS1_REG(0x0110)
+#define VDOSYS0_SW_CG0			MT_LP_TZ_VDOSYS0_REG(0x0100)
+#define VDOSYS0_SW_CG1			MT_LP_TZ_VDOSYS0_REG(0x0110)
+#define VDOSYS1_SW_CG0			MT_LP_TZ_VDOSYS1_REG(0x0100)
+#define VDOSYS1_SW_CG1			MT_LP_TZ_VDOSYS1_REG(0x0120)
+#define VDOSYS1_SW_CG2			MT_LP_TZ_VDOSYS1_REG(0x0130)
+
+/***********************************************************
+ * Check clkmux registers
+ ***********************************************************/
+#define CLK_CFG(id)	MT_LP_TZ_TOPCK_REG(0x98 + id * 0x10)
+#define PDN_CHECK	BIT(7)
+#define CLK_CHECK	BIT(31)
+
+enum {
+	CLKMUX_DISP = 0,
+	NF_CLKMUX,
+};
+
+static bool is_clkmux_pdn(unsigned int clkmux_id)
+{
+	unsigned int reg, val, idx;
+
+	if ((clkmux_id & CLK_CHECK) != 0U) {
+		clkmux_id = (clkmux_id & ~CLK_CHECK);
+		reg = clkmux_id / 4U;
+		val = mmio_read_32(CLK_CFG(reg));
+		idx = clkmux_id % 4U;
+		val = (val >> (idx * 8U)) & PDN_CHECK;
+		return (val != 0U);
+	}
+
+	return false;
+}
+
+static struct mt_spm_cond_tables spm_cond_t;
+
+struct idle_cond_info {
+	unsigned int subsys_mask;
+	uintptr_t addr;
+	bool bBitflip;
+	unsigned int clkmux_id;
+};
+
+#define IDLE_CG(mask, addr, bitflip, clkmux)	\
+	{mask, (uintptr_t)addr, bitflip, clkmux}
+
+static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
+	IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
+	IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0U),
+	IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0U),
+	IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0U),
+	IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0U),
+	IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0U),
+	IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0U),
+	IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00000800, VPPSYS0_SW_CG2, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00001000, VPPSYS1_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00001000, VPPSYS1_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00002000, VDOSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00002000, VDOSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00004000, VDOSYS1_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00004000, VDOSYS1_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00004000, VDOSYS1_SW_CG2, true, (CLK_CHECK|CLKMUX_DISP)),
+	IDLE_CG(0x00000080, TOP_SW_I2C_CG, true, (CLK_CHECK|CLKMUX_DISP)),
+};
+
+/***********************************************************
+ * Check pll idle condition
+ ***********************************************************/
+#define PLL_MFGPLL	MT_LP_TZ_APMIXEDSYS(0x340)
+#define PLL_MMPLL	MT_LP_TZ_APMIXEDSYS(0x0E0)
+#define PLL_UNIVPLL	MT_LP_TZ_APMIXEDSYS(0x1F0)
+#define PLL_MSDCPLL	MT_LP_TZ_APMIXEDSYS(0x710)
+#define PLL_TVDPLL	MT_LP_TZ_APMIXEDSYS(0x380)
+
+unsigned int mt_spm_cond_check(int state_id,
+			       const struct mt_spm_cond_tables *src,
+			       const struct mt_spm_cond_tables *dest,
+			       struct mt_spm_cond_tables *res)
+{
+	unsigned int blocked = 0U, i;
+	bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
+
+	if ((src == NULL) || (dest == NULL)) {
+		return SPM_COND_CHECK_FAIL;
+	}
+
+	for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+		if (res != NULL) {
+			res->table_cg[i] =
+				(src->table_cg[i] & dest->table_cg[i]);
+
+			if (is_system_suspend && (res->table_cg[i] != 0U)) {
+				INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
+				     dest->name, i, idle_cg_info[i].addr,
+				     res->table_cg[i]);
+			}
+
+			if (res->table_cg[i] != 0U) {
+				blocked |= (1U << i);
+			}
+		} else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
+			blocked |= (1U << i);
+			break;
+		}
+	}
+
+	if (res != NULL) {
+		res->table_pll = (src->table_pll & dest->table_pll);
+
+		if (res->table_pll != 0U) {
+			blocked |=
+				(res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
+				 SPM_COND_CHECK_BLOCKED_PLL;
+		}
+	} else if ((src->table_pll & dest->table_pll) != 0U) {
+		blocked |= SPM_COND_CHECK_BLOCKED_PLL;
+	}
+
+	if (is_system_suspend && (blocked != 0U)) {
+		INFO("suspend: %s blocked=0x%08x\n", dest->name, blocked);
+	}
+
+	return blocked;
+}
+
+#define IS_MT_SPM_PWR_OFF(mask)					\
+	(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) &&	\
+	 ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
+
+int mt_spm_cond_update(struct mt_resource_constraint **con,
+		       int stateid, void *priv)
+{
+	int res;
+	uint32_t i;
+	struct mt_resource_constraint *const *rc;
+
+	/* read all cg state */
+	for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+		spm_cond_t.table_cg[i] = 0U;
+
+		/* check mtcmos, if off set idle_value and clk to 0 disable */
+		if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
+			continue;
+		}
+
+		/* check clkmux */
+		if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
+			continue;
+		}
+
+		spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
+					 ~mmio_read_32(idle_cg_info[i].addr) :
+					 mmio_read_32(idle_cg_info[i].addr);
+	}
+
+	spm_cond_t.table_pll = 0U;
+	if ((mmio_read_32(PLL_MFGPLL) & 0x200) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MFGPLL;
+	}
+
+	if ((mmio_read_32(PLL_MMPLL) & 0x200) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MMPLL;
+	}
+
+	if ((mmio_read_32(PLL_UNIVPLL) & 0x200) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_UNIVPLL;
+	}
+
+	if ((mmio_read_32(PLL_MSDCPLL) & 0x200) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MSDCPLL;
+	}
+
+	if ((mmio_read_32(PLL_TVDPLL) & 0x200) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_TVDPLL;
+	}
+
+	spm_cond_t.priv = priv;
+	for (rc = con; *rc != NULL; rc++) {
+		if (((*rc)->update) == NULL) {
+			continue;
+		}
+
+		res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION,
+				    (void const *)&spm_cond_t);
+		if (res != MT_RM_STATUS_OK) {
+			break;
+		}
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
new file mode 100644
index 0000000..e471b55
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONDIT_H
+#define MT_SPM_CONDIT_H
+
+#include <mt_lp_rm.h>
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS1 = 0,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_INFRA_4,
+	PLAT_SPM_COND_CG_PERI_SW_0,
+	PLAT_SPM_COND_CG_VPPSYS0_SW_CG_0,
+	PLAT_SPM_COND_CG_VPPSYS0_SW_CG_1,
+	PLAT_SPM_COND_CG_VPPSYS0_SW_CG_2,
+	PLAT_SPM_COND_CG_VPPSYS1_SW_CG_0,
+	PLAT_SPM_COND_CG_VPPSYS1_SW_CG_1,
+	PLAT_SPM_COND_CG_VDOSYS0_SW_CG_0,
+	PLAT_SPM_COND_CG_VDOSYS0_SW_CG_1,
+	PLAT_SPM_COND_CG_VDOSYS1_SW_CG_0,
+	PLAT_SPM_COND_CG_VDOSYS1_SW_CG_1,
+	PLAT_SPM_COND_CG_VDOSYS1_SW_CG_2,
+	PLAT_SPM_COND_CG_I2C_SW_CG,
+	PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_COND_PLL {
+	PLAT_SPM_COND_PLL_UNIVPLL = 0,
+	PLAT_SPM_COND_PLL_MFGPLL,
+	PLAT_SPM_COND_PLL_MSDCPLL,
+	PLAT_SPM_COND_PLL_TVDPLL,
+	PLAT_SPM_COND_PLL_MMPLL,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#define PLL_BIT_MFGPLL	BIT(PLAT_SPM_COND_PLL_MFGPLL)
+#define PLL_BIT_MMPLL	BIT(PLAT_SPM_COND_PLL_MMPLL)
+#define PLL_BIT_UNIVPLL	BIT(PLAT_SPM_COND_PLL_UNIVPLL)
+#define PLL_BIT_MSDCPLL	BIT(PLAT_SPM_COND_PLL_MSDCPLL)
+#define PLL_BIT_TVDPLL	BIT(PLAT_SPM_COND_PLL_TVDPLL)
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 17]: cg blocking index
+ * bit [18 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]	: idle condition check fail
+ */
+#define SPM_COND_BLOCKED_CG_IDX		U(0)
+#define SPM_COND_BLOCKED_PLL_IDX	U(18)
+#define SPM_COND_CHECK_BLOCKED_PLL	BIT(30)
+#define SPM_COND_CHECK_FAIL		BIT(31)
+
+struct mt_spm_cond_tables {
+	char *name;
+	unsigned int table_cg[PLAT_SPM_COND_MAX];
+	unsigned int table_pll;
+	void *priv;
+};
+
+extern unsigned int mt_spm_cond_check(int state_id,
+				      const struct mt_spm_cond_tables *src,
+				      const struct mt_spm_cond_tables *dest,
+				      struct mt_spm_cond_tables *res);
+extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+			      int stateid, void *priv);
+#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.c
new file mode 100644
index 0000000..7f33408
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+struct wake_status spm_wakesta; /* record last wakesta */
+
+static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
+				struct spm_lp_scen *spm_lp,
+				unsigned int resource_req)
+{
+	int ret = 0;
+	struct pwr_ctrl *pwrctrl;
+	uint32_t cpu = plat_my_core_pos();
+
+	pwrctrl = spm_lp->pwrctrl;
+
+	__spm_set_cpu_status(cpu);
+	__spm_set_power_control(pwrctrl);
+	__spm_set_wakeup_event(pwrctrl);
+	__spm_set_pcm_flags(pwrctrl);
+	__spm_src_req_update(pwrctrl, resource_req);
+
+	if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+		__spm_set_pcm_wdt(1);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+		__spm_xo_soc_bblpm(1);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+		spm_hw_s1_state_monitor_resume();
+	}
+
+	/* Disable auto resume by PCM in system suspend stage */
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		__spm_disable_pcm_timer();
+		__spm_set_pcm_wdt(0);
+	}
+
+	__spm_send_cpu_wakeup_event();
+
+	INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
+	     cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
+	     mmio_read_32(PCM_TIMER_VAL) / 32768);
+	INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
+	     pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
+	     mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
+	     mmio_read_32(PWR_STATUS_2ND));
+	INFO("cpu_pwr = 0x%x 0x%x\n", mmio_read_32(CPU_PWR_STATUS),
+	     mmio_read_32(CPU_PWR_STATUS_2ND));
+
+	return ret;
+}
+
+static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
+				struct spm_lp_scen *spm_lp,
+				struct wake_status **status)
+{
+	unsigned int ext_status = 0U;
+
+	/* system watchdog will be resumed at kernel stage */
+	if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+		__spm_set_pcm_wdt(0);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+		__spm_xo_soc_bblpm(0);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+		spm_hw_s1_state_monitor_pause(&ext_status);
+	}
+
+	__spm_ext_int_wakeup_req_clr();
+	__spm_get_wakeup_status(&spm_wakesta, ext_status);
+
+	if (status != NULL) {
+		*status = &spm_wakesta;
+	}
+
+	__spm_clean_after_wakeup();
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		__spm_output_wake_reason(state_id, &spm_wakesta);
+	}
+}
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+		     struct spm_lp_scen *spm_lp, unsigned int resource_req)
+{
+	if (spm_lp == NULL) {
+		return -1;
+	}
+
+	spm_lock_get();
+	go_to_spm_before_wfi(state_id, ext_opand, spm_lp, resource_req);
+	spm_lock_release();
+
+	return 0;
+}
+
+void spm_conservation_finish(int state_id, unsigned int ext_opand,
+			     struct spm_lp_scen *spm_lp,
+			     struct wake_status **status)
+{
+	spm_lock_get();
+	go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
+	spm_lock_release();
+}
+
+int spm_conservation_get_result(struct wake_status **res)
+{
+	if (res == NULL) {
+		return -1;
+	}
+
+	*res = &spm_wakesta;
+
+	return 0;
+}
+
+#define GPIO_BANK	(GPIO_BASE + 0x6F0)
+#define TRAP_UFS_FIRST	BIT(11) /* bit 11, 0: UFS, 1: eMMC */
+
+void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl)
+{
+	if (pwrctrl == NULL) {
+		return;
+	}
+
+	/* For ufs, emmc storage type */
+	if ((mmio_read_32(GPIO_BANK) & TRAP_UFS_FIRST) != 0U) {
+		/* If eMMC is used, mask UFS req */
+		pwrctrl->reg_ufs_srcclkena_mask_b = 0;
+		pwrctrl->reg_ufs_infra_req_mask_b = 0;
+		pwrctrl->reg_ufs_apsrc_req_mask_b = 0;
+		pwrctrl->reg_ufs_vrf18_req_mask_b = 0;
+		pwrctrl->reg_ufs_ddr_en_mask_b = 0;
+	}
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.h
new file mode 100644
index 0000000..aa627e7
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSERVATION_H
+#define MT_SPM_CONSERVATION_H
+
+#include <mt_spm_internal.h>
+
+extern int spm_conservation(int state_id, unsigned int ext_opand,
+			    struct spm_lp_scen *spm_lp,
+			    unsigned int resource_req);
+extern void spm_conservation_finish(int state_id, unsigned int ext_opand,
+				    struct spm_lp_scen *spm_lp,
+				    struct wake_status **status);
+extern int spm_conservation_get_result(struct wake_status **res);
+extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl);
+#endif /* MT_SPM_CONSERVATION_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h
new file mode 100644
index 0000000..944c227
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF	(1U << 0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0		(1U << 1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1		(1U << 2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP		(1U << 3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN	(1U << 4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF	(1U << 5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND	(1U << 6)
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM		(1U << 7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS		(1U << 8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE	(1U << 9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE	(1U << 10)
+
+#define MT_SPM_RC_INVALID		0x0
+#define MT_SPM_RC_VALID_SW		(1U << 0)
+#define MT_SPM_RC_VALID_FW		(1U << 1)
+#define MT_SPM_RC_VALID_RESIDNECY	(1U << 2)
+#define MT_SPM_RC_VALID_COND_CHECK	(1U << 3)
+#define MT_SPM_RC_VALID_COND_LATCH	(1U << 4)
+#define MT_SPM_RC_VALID_UFS_H8		(1U << 5)
+#define MT_SPM_RC_VALID_FLIGHTMODE	(1U << 6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM	(1U << 7)
+#define MT_SPM_RC_VALID_TRACE_EVENT	(1U << 8)
+
+#define MT_SPM_RC_VALID	(MT_SPM_RC_VALID_SW)
+
+#define IS_MT_RM_RC_READY(status)	\
+	((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+#define MT_SPM_RC_BBLPM_MODE		\
+	(MT_SPM_RC_VALID_UFS_H8 |	\
+	 MT_SPM_RC_VALID_FLIGHTMODE |	\
+	 MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st)	\
+	((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+struct constraint_status {
+	uint16_t id;
+	uint16_t valid;
+	uint32_t cond_block;
+	uint32_t enter_cnt;
+	struct mt_spm_cond_tables *cond_res;
+};
+
+enum MT_SPM_RM_RC_TYPE {
+	MT_RM_CONSTRAINT_ID_BUS26M,
+	MT_RM_CONSTRAINT_ID_SYSPLL,
+	MT_RM_CONSTRAINT_ID_DRAM,
+	MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
+	MT_RM_CONSTRAINT_ID_ALL,
+};
+#endif /* MT_SPM_CONSTRAINT_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c
new file mode 100644
index 0000000..4bafe95
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <plat_pm.h>
+
+#define __WAKE_SRC_FOR_IDLE_COMMON__	\
+	(R12_PCM_TIMER |		\
+	 R12_KP_IRQ_B |			\
+	 R12_APWDT_EVENT_B |		\
+	 R12_APXGPT1_EVENT_B |		\
+	 R12_CONN2AP_SPM_WAKEUP_B |	\
+	 R12_EINT_EVENT_B |		\
+	 R12_CONN_WDT_IRQ_B |		\
+	 R12_CCIF0_EVENT_B |		\
+	 R12_SSPM2SPM_WAKEUP_B |	\
+	 R12_SCP2SPM_WAKEUP_B |		\
+	 R12_ADSP2SPM_WAKEUP_B |	\
+	 R12_USBX_CDSC_B |		\
+	 R12_USBX_POWERDWN_B |		\
+	 R12_SYS_TIMER_EVENT_B |	\
+	 R12_EINT_EVENT_SECURE_B |	\
+	 R12_AFE_IRQ_MCU_B |		\
+	 R12_SYS_CIRQ_IRQ_B |		\
+	 R12_MD2AP_PEER_EVENT_B |	\
+	 R12_MD1_WDT_B |		\
+	 R12_CLDMA_EVENT_B |		\
+	 R12_REG_CPU_WAKEUP |		\
+	 R12_APUSYS_WAKE_HOST_B)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
+#else
+#define WAKE_SRC_FOR_IDLE		\
+	(__WAKE_SRC_FOR_IDLE_COMMON__ |	\
+	  R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl idle_spm_pwr = {
+	.wake_src = WAKE_SRC_FOR_IDLE,
+
+	/* SPM_AP_STANDBY_CON */
+	/* [0] */
+	.reg_wfi_op = 0,
+	/* [1] */
+	.reg_wfi_type = 0,
+	/* [2] */
+	.reg_mp0_cputop_idle_mask = 0,
+	/* [3] */
+	.reg_mp1_cputop_idle_mask = 0,
+	/* [4] */
+	.reg_mcusys_idle_mask = 0,
+	/* [25] */
+	.reg_md_apsrc_1_sel = 0,
+	/* [26] */
+	.reg_md_apsrc_0_sel = 0,
+	/* [29] */
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC_REQ */
+	/* [0] */
+	.reg_spm_apsrc_req = 0,
+	/* [1] */
+	.reg_spm_f26m_req = 1,
+	/* [3] */
+	.reg_spm_infra_req = 1,
+	/* [4] */
+	.reg_spm_vrf18_req = 0,
+	/* [7] FIXME: default disable HW Auto S1 */
+	.reg_spm_ddr_en_req = 1,
+	/* [8] */
+	.reg_spm_dvfs_req = 0,
+	/* [9] */
+	.reg_spm_sw_mailbox_req = 0,
+	/* [10] */
+	.reg_spm_sspm_mailbox_req = 0,
+	/* [11] */
+	.reg_spm_adsp_mailbox_req = 0,
+	/* [12] */
+	.reg_spm_scp_mailbox_req = 0,
+
+
+	/* SPM_SRC_MASK */
+	/* [0] */
+	.reg_sspm_srcclkena_0_mask_b = 1,
+	/* [1] */
+	.reg_sspm_infra_req_0_mask_b = 1,
+	/* [2] */
+	.reg_sspm_apsrc_req_0_mask_b = 1,
+	/* [3] */
+	.reg_sspm_vrf18_req_0_mask_b = 1,
+	/* [4] */
+	.reg_sspm_ddr_en_0_mask_b = 1,
+	/* [5] */
+	.reg_scp_srcclkena_mask_b = 1,
+	/* [6] */
+	.reg_scp_infra_req_mask_b = 1,
+	/* [7] */
+	.reg_scp_apsrc_req_mask_b = 1,
+	/* [8] */
+	.reg_scp_vrf18_req_mask_b = 1,
+	/* [9] */
+	.reg_scp_ddr_en_mask_b = 1,
+	/* [10] */
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	/* [11] */
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	/* [12] */
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	/* [13] */
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	/* [14] */
+	.reg_audio_dsp_ddr_en_mask_b = 1,
+	/* [15] */
+	.reg_apu_srcclkena_mask_b = 1,
+	/* [16] */
+	.reg_apu_infra_req_mask_b = 1,
+	/* [17] */
+	.reg_apu_apsrc_req_mask_b = 1,
+	/* [18] */
+	.reg_apu_vrf18_req_mask_b = 1,
+	/* [19] */
+	.reg_apu_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_cpueb_srcclkena_mask_b = 1,
+	/* [21] */
+	.reg_cpueb_infra_req_mask_b = 1,
+	/* [22] */
+	.reg_cpueb_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_cpueb_vrf18_req_mask_b = 1,
+	/* [24] */
+	.reg_cpueb_ddr_en_mask_b = 1,
+	/* [25] */
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	/* [26] */
+	.reg_bak_psri_infra_req_mask_b = 0,
+	/* [27] */
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	/* [28] */
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	/* [29] */
+	.reg_bak_psri_ddr_en_mask_b = 0,
+
+	/* SPM_SRC2_MASK */
+	/* [0] */
+	.reg_msdc0_srcclkena_mask_b = 1,
+	/* [1] */
+	.reg_msdc0_infra_req_mask_b = 1,
+	/* [2] */
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	/* [3] */
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	/* [4] */
+	.reg_msdc0_ddr_en_mask_b = 1,
+	/* [5] */
+	.reg_msdc1_srcclkena_mask_b = 1,
+	/* [6] */
+	.reg_msdc1_infra_req_mask_b = 1,
+	/* [7] */
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	/* [8] */
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	/* [9] */
+	.reg_msdc1_ddr_en_mask_b = 1,
+	/* [10] */
+	.reg_msdc2_srcclkena_mask_b = 1,
+	/* [11] */
+	.reg_msdc2_infra_req_mask_b = 1,
+	/* [12] */
+	.reg_msdc2_apsrc_req_mask_b = 1,
+	/* [13] */
+	.reg_msdc2_vrf18_req_mask_b = 1,
+	/* [14] */
+	.reg_msdc2_ddr_en_mask_b = 1,
+	/* [15] */
+	.reg_ufs_srcclkena_mask_b = 1,
+	/* [16] */
+	.reg_ufs_infra_req_mask_b = 1,
+	/* [17] */
+	.reg_ufs_apsrc_req_mask_b = 1,
+	/* [18] */
+	.reg_ufs_vrf18_req_mask_b = 1,
+	/* [19] */
+	.reg_ufs_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_usb_srcclkena_mask_b = 1,
+	/* [21] */
+	.reg_usb_infra_req_mask_b = 1,
+	/* [22] */
+	.reg_usb_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_usb_vrf18_req_mask_b = 1,
+	/* [24] */
+	.reg_usb_ddr_en_mask_b = 1,
+	/* [25] */
+	.reg_pextp_p0_srcclkena_mask_b = 1,
+	/* [26] */
+	.reg_pextp_p0_infra_req_mask_b = 1,
+	/* [27] */
+	.reg_pextp_p0_apsrc_req_mask_b = 1,
+	/* [28] */
+	.reg_pextp_p0_vrf18_req_mask_b = 1,
+	/* [29] */
+	.reg_pextp_p0_ddr_en_mask_b = 1,
+
+	/* SPM_SRC3_MASK */
+	/* [0] */
+	.reg_pextp_p1_srcclkena_mask_b = 1,
+	/* [1] */
+	.reg_pextp_p1_infra_req_mask_b = 1,
+	/* [2] */
+	.reg_pextp_p1_apsrc_req_mask_b = 1,
+	/* [3] */
+	.reg_pextp_p1_vrf18_req_mask_b = 1,
+	/* [4] */
+	.reg_pextp_p1_ddr_en_mask_b = 1,
+	/* [5] */
+	.reg_gce0_infra_req_mask_b = 1,
+	/* [6] */
+	.reg_gce0_apsrc_req_mask_b = 1,
+	/* [7] */
+	.reg_gce0_vrf18_req_mask_b = 1,
+	/* [8] */
+	.reg_gce0_ddr_en_mask_b = 1,
+	/* [9] */
+	.reg_gce1_infra_req_mask_b = 1,
+	/* [10] */
+	.reg_gce1_apsrc_req_mask_b = 1,
+	/* [11] */
+	.reg_gce1_vrf18_req_mask_b = 1,
+	/* [12] */
+	.reg_gce1_ddr_en_mask_b = 1,
+	/* [13] */
+	.reg_spm_srcclkena_reserved_mask_b = 1,
+	/* [14] */
+	.reg_spm_infra_req_reserved_mask_b = 1,
+	/* [15] */
+	.reg_spm_apsrc_req_reserved_mask_b = 1,
+	/* [16] */
+	.reg_spm_vrf18_req_reserved_mask_b = 1,
+	/* [17] */
+	.reg_spm_ddr_en_reserved_mask_b = 1,
+	/* [18] */
+	.reg_disp0_apsrc_req_mask_b = 1,
+	/* [19] */
+	.reg_disp0_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_disp1_apsrc_req_mask_b = 1,
+	/* [21] */
+	.reg_disp1_ddr_en_mask_b = 1,
+	/* [22] */
+	.reg_disp2_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_disp2_ddr_en_mask_b = 1,
+	/* [24] */
+	.reg_disp3_apsrc_req_mask_b = 1,
+	/* [25] */
+	.reg_disp3_ddr_en_mask_b = 1,
+	/* [26] */
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	/* [27] */
+	.reg_infrasys_ddr_en_mask_b = 1,
+
+	/* [28] */
+	.reg_cg_check_srcclkena_mask_b = 1,
+	/* [29] */
+	.reg_cg_check_apsrc_req_mask_b = 1,
+	/* [30] */
+	.reg_cg_check_vrf18_req_mask_b = 1,
+	/* [31] */
+	.reg_cg_check_ddr_en_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	/* [8:0] */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x17,
+	/* [17:9] */
+	.reg_mcusys_merge_ddr_en_mask_b = 0x17,
+	/* [19:18] */
+	.reg_dramc_md32_infra_req_mask_b = 0,
+	/* [21:20] */
+	.reg_dramc_md32_vrf18_req_mask_b = 0,
+	/* [23:22] */
+	.reg_dramc_md32_ddr_en_mask_b = 0,
+	/* [24] */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK2 */
+	/* [3:0] */
+	.reg_sc_sw2spm_wakeup_mask_b = 0,
+	/* [4] */
+	.reg_sc_adsp2spm_wakeup_mask_b = 0,
+	/* [8:5] */
+	.reg_sc_sspm2spm_wakeup_mask_b = 0,
+	/* [9] */
+	.reg_sc_scp2spm_wakeup_mask_b = 0,
+	/* [10] */
+	.reg_csyspwrup_ack_mask = 0,
+	/* [11] */
+	.reg_csyspwrup_req_mask = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	/* [31:0] */
+	.reg_wakeup_event_mask = 0xC1282203,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	/* [31:0] */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+struct spm_lp_scen idle_spm_lp = {
+	.pwrctrl = &idle_spm_pwr,
+};
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
+			      spm_idle_conduct fn)
+{
+	unsigned int src_req = 0;
+
+	if (fn != NULL) {
+		fn(&idle_spm_lp, &src_req);
+	}
+
+	return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
+}
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+				struct wake_status **status)
+{
+	spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
+}
+
+void mt_spm_idle_generic_init(void)
+{
+	spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h
new file mode 100644
index 0000000..7f6fb0c
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_IDLE_H
+#define MT_SPM_IDLE_H
+
+typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp,
+				 unsigned int *resource_req);
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
+			      spm_idle_conduct fn);
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+				struct wake_status **status);
+void mt_spm_idle_generic_init(void);
+#endif /* MT_SPM_IDLE_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c
new file mode 100644
index 0000000..2f460e6
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c
@@ -0,0 +1,543 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <assert.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <platform_def.h>
+#include <plat_pm.h>
+
+/**************************************
+ * Define and Declare
+ **************************************/
+#define ROOT_CORE_ADDR_OFFSET			0x20000000
+#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK	0xefffffff
+#define	SPM_INIT_DONE_US			20
+
+static unsigned int mt_spm_bblpm_cnt;
+
+const char *wakeup_src_str[32] = {
+	[0] = "R12_PCM_TIMER",
+	[1] = "R12_RESERVED_DEBUG_B",
+	[2] = "R12_KP_IRQ_B",
+	[3] = "R12_APWDT_EVENT_B",
+	[4] = "R12_APXGPT1_EVENT_B",
+	[5] = "R12_MSDC_WAKEUP_B",
+	[6] = "R12_EINT_EVENT_B",
+	[7] = "R12_IRRX_WAKEUP_B",
+	[8] = "R12_SBD_INTR_WAKEUP_B",
+	[9] = "R12_RESERVE0",
+	[10] = "R12_SC_SSPM2SPM_WAKEUP_B",
+	[11] = "R12_SC_SCP2SPM_WAKEUP_B",
+	[12] = "R12_SC_ADSP2SPM_WAKEUP_B",
+	[13] = "R12_WDT_WAKEUP_B",
+	[14] = "R12_USB_U2_B",
+	[15] = "R12_USB_TOP_B",
+	[16] = "R12_SYS_TIMER_EVENT_B",
+	[17] = "R12_EINT_EVENT_SECURE_B",
+	[18] = "R12_ECE_INT_HDMI_B",
+	[19] = "R12_RESERVE1",
+	[20] = "R12_AFE_IRQ_MCU_B",
+	[21] = "R12_THERM_CTRL_EVENT_B",
+	[22] = "R12_SCP_CIRQ_IRQ_B",
+	[23] = "R12_NNA2INFRA_WAKEUP_B",
+	[24] = "R12_CSYSPWREQ_B",
+	[25] = "R12_RESERVE2",
+	[26] = "R12_PCIE_WAKEUPEVENT_B",
+	[27] = "R12_SEJ_EVENT_B",
+	[28] = "R12_SPM_CPU_WAKEUPEVENT_B",
+	[29] = "R12_APUSYS",
+	[30] = "R12_RESERVE3",
+	[31] = "R12_RESERVE4",
+};
+
+/**************************************
+ * Function and API
+ **************************************/
+
+wake_reason_t __spm_output_wake_reason(int state_id,
+				       const struct wake_status *wakesta)
+{
+	uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
+	wake_reason_t wr = WR_UNKNOWN;
+
+	if (wakesta == NULL) {
+		return WR_UNKNOWN;
+	}
+
+	if (wakesta->abort != 0U) {
+		ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
+		      wakesta->abort, wakesta->timer_out);
+	} else {
+		for (i = 0U; i < 32U; i++) {
+			if ((wakesta->r12 & (1U << i)) != 0U) {
+				INFO("wake up by %s, timer_out = %u\n",
+				     wakeup_src_str[i], wakesta->timer_out);
+				wr = WR_WAKE_SRC;
+				break;
+			}
+		}
+	}
+
+	INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
+	     wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
+	     wakesta->debug_flag1);
+	INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
+	     wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
+	     wakesta->md32pcm_event_sta, wakesta->idle_sta,
+	     wakesta->cg_check_sta);
+	INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
+	     wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
+	     wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
+	INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
+	     wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
+	INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
+	     wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
+	INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
+	     wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
+	     wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
+	INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
+	     wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
+	     mmio_read_32(SYS_TIMER_VALUE_H));
+
+	if (wakesta->timer_out != 0U) {
+		bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
+		spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
+		INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
+	}
+
+	return wr;
+}
+
+void __spm_set_cpu_status(unsigned int cpu)
+{
+	uint32_t root_core_addr;
+
+	if (cpu < 8U) {
+		mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu));
+		root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
+		root_core_addr += ROOT_CORE_ADDR_OFFSET;
+		mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
+		/* Notify MCUPM that preferred cpu wakeup */
+		mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
+	} else {
+		ERROR("%s: error cpu number %d\n", __func__, cpu);
+	}
+}
+
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+			  unsigned int resource_usage)
+{
+	uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
+			    1 : pwrctrl->reg_spm_apsrc_req;
+	uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
+			     1 : pwrctrl->reg_spm_ddr_en_req;
+	uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
+			    1 : pwrctrl->reg_spm_vrf18_req;
+	uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
+			    1 : pwrctrl->reg_spm_infra_req;
+	uint8_t f26m_req  = ((resource_usage &
+			      (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
+			    1 : pwrctrl->reg_spm_f26m_req;
+
+	mmio_write_32(SPM_SRC_REQ,
+		      ((apsrc_req & 0x1) << 0) |
+		      ((f26m_req & 0x1) << 1) |
+		      ((infra_req & 0x1) << 3) |
+		      ((vrf18_req & 0x1) << 4) |
+		      ((ddr_en_req & 0x1) << 7) |
+		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+}
+
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	mmio_write_32(SPM_AP_STANDBY_CON,
+		((pwrctrl->reg_wfi_op & 0x1) << 0) |
+		((pwrctrl->reg_wfi_type & 0x1) << 1) |
+		((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+		((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+		((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+		((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+		((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+		((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+	/* SPM_SRC_REQ */
+	mmio_write_32(SPM_SRC_REQ,
+		((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+		((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+		((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+		((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+		((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+		((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+	/* SPM_SRC_MASK */
+	mmio_write_32(SPM_SRC_MASK,
+		((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29));
+
+	/* SPM_SRC2_MASK */
+	mmio_write_32(SPM_SRC2_MASK,
+		((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
+
+	/* SPM_SRC3_MASK */
+	mmio_write_32(SPM_SRC3_MASK,
+		((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
+
+	/* Mask MCUSYS request since SOC HW would check it */
+	mmio_write_32(SPM_SRC4_MASK, 0x1fc0000);
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+		((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+		((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* Auto-gen End */
+}
+
+void __spm_disable_pcm_timer(void)
+{
+	mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+}
+
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+	uint32_t val, mask;
+
+	/* toggle event counter clear */
+	mmio_setbits_32(PCM_CON1,
+			SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+
+	/* toggle for reset SYS TIMER start point */
+	mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+
+	if (pwrctrl->timer_val_cust == 0U) {
+		val = pwrctrl->timer_val;
+	} else {
+		val = pwrctrl->timer_val_cust;
+	}
+
+	mmio_write_32(PCM_TIMER_VAL, val);
+	mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
+
+	/* unmask AP wakeup source */
+	if (pwrctrl->wake_src_cust == 0U) {
+		mask = pwrctrl->wake_src;
+	} else {
+		mask = pwrctrl->wake_src_cust;
+	}
+
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+	/* unmask SPM ISR (keep TWAM setting) */
+	mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
+
+	/* toggle event counter clear */
+	mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB,
+			   SPM_REGWR_CFG_KEY);
+	/* toggle for reset SYS TIMER start point */
+	mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+}
+
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+	/* set PCM flags and data */
+	if (pwrctrl->pcm_flags_cust_clr != 0U) {
+		pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+	}
+
+	if (pwrctrl->pcm_flags_cust_set != 0U) {
+		pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+	}
+
+	if (pwrctrl->pcm_flags1_cust_clr != 0U) {
+		pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+	}
+
+	if (pwrctrl->pcm_flags1_cust_set != 0U) {
+		pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+	}
+
+	mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
+	mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
+	mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
+	mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
+}
+
+void __spm_get_wakeup_status(struct wake_status *wakesta,
+			     unsigned int ext_status)
+{
+	wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+	wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+	wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
+	wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+	wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+	wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+	wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+	wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+	wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+	wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+	if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
+		wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
+						SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
+		mmio_write_32(PCM_WDT_LATCH_SPARE_0,
+			      wakesta->tr.comm.debug_flag);
+	}
+
+	wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+	wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+	/* record below spm info for debug */
+	wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+	wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
+	wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+	wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+	wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
+	wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
+	wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
+
+	/* backup of SPM_WAKEUP_MISC */
+	wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
+
+	/* get sleep time, backup of PCM_TIMER_OUT */
+	wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+
+	/* get other SYS and co-clock status */
+	wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
+	wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+	wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+	wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+	wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+	wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+	wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+	/* get HW CG check status */
+	wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
+
+	/* get debug flag for PCM execution check */
+	wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+	wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+	/* get backup SW flag status */
+	wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+	wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+	wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
+	wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
+	wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
+	wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
+	wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
+
+	/* get ISR status */
+	wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+
+	/* get SW flag status */
+	wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
+	wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+
+	/* get CLK SETTLE */
+	wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
+
+	/* check abort */
+	wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) |
+			 (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1);
+}
+
+void __spm_clean_after_wakeup(void)
+{
+	mmio_write_32(SPM_BK_WAKE_EVENT,
+		      mmio_read_32(SPM_WAKEUP_STA) |
+		      mmio_read_32(SPM_BK_WAKE_EVENT));
+	mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
+
+	/*
+	 * clean wakeup event raw status (for edge trigger event)
+	 * bit[28] for cpu wake up event
+	 */
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
+
+	/* clean ISR status (except TWAM) */
+	mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
+	mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+	mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void __spm_set_pcm_wdt(int en)
+{
+	mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
+			   SPM_REGWR_CFG_KEY);
+
+	if (en == 1) {
+		mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
+				   SPM_REGWR_CFG_KEY);
+
+		if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
+			mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+		}
+
+		mmio_write_32(PCM_WDT_VAL,
+			      mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+		mmio_setbits_32(PCM_CON1,
+				SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
+	}
+}
+
+void __spm_send_cpu_wakeup_event(void)
+{
+	/* SPM will clear SPM_CPU_WAKEUP_EVENT */
+	mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+}
+
+void __spm_ext_int_wakeup_req_clr(void)
+{
+	mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
+
+	/* Clear spm2mcupm wakeup interrupt status */
+	mmio_write_32(SPM2CPUEB_CON, 0);
+}
+
+void __spm_xo_soc_bblpm(int en)
+{
+	if (en == 1) {
+		mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+				   RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC);
+		assert(mt_spm_bblpm_cnt == 0);
+		mt_spm_bblpm_cnt += 1;
+	} else {
+		mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+				   RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM);
+		mt_spm_bblpm_cnt -= 1;
+	}
+}
+
+void __spm_hw_s1_state_monitor(int en, unsigned int *status)
+{
+	unsigned int reg;
+
+	reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+
+	if (en == 1) {
+		reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
+		mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+		reg |= SPM_ACK_CHK_3_CON_EN;
+		mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+	} else {
+		if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
+		    (status != NULL)) {
+			*status |= SPM_INTERNAL_STATUS_HW_S1;
+		}
+
+		mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
+				   SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
+				   SPM_ACK_CHK_3_CON_CLR_ALL);
+	}
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h
new file mode 100644
index 0000000..5ac7c91
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h
@@ -0,0 +1,583 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_INTERNAL_H
+#define MT_SPM_INTERNAL_H
+
+#include "mt_spm.h"
+
+/**************************************
+ * Config and Parameter
+ **************************************/
+#define POWER_ON_VAL0_DEF	0x0000F100
+#define POWER_ON_VAL1_DEF	0x80015860
+#define PCM_WDT_TIMEOUT		(30 * 32768)	/* 30s */
+#define PCM_TIMER_MAX		(0xffffffff - PCM_WDT_TIMEOUT)
+
+/**************************************
+ * Define and Declare
+ **************************************/
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0		(1U << 0)
+#define PCM_PWRIO_EN_R7		(1U << 7)
+#define PCM_RF_SYNC_R0		(1U << 16)
+#define PCM_RF_SYNC_R6		(1U << 22)
+#define PCM_RF_SYNC_R7		(1U << 23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0		(1U << 0)
+#define PCM_SW_INT1		(1U << 1)
+#define PCM_SW_INT2		(1U << 2)
+#define PCM_SW_INT3		(1U << 3)
+#define PCM_SW_INT4		(1U << 4)
+#define PCM_SW_INT5		(1U << 5)
+#define PCM_SW_INT6		(1U << 6)
+#define PCM_SW_INT7		(1U << 7)
+#define PCM_SW_INT8		(1U << 8)
+#define PCM_SW_INT9		(1U << 9)
+#define PCM_SW_INT_ALL		(PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+				 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+				 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+				 PCM_SW_INT0)
+
+/* SPM_AP_STANDBY_CON */
+#define WFI_OP_AND		1
+#define WFI_OP_OR		0
+
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM		(1U << 2)
+#define ISRM_PCM_RETURN		(1U << 3)
+#define ISRM_RET_IRQ0		(1U << 8)
+#define ISRM_RET_IRQ1		(1U << 9)
+#define ISRM_RET_IRQ2		(1U << 10)
+#define ISRM_RET_IRQ3		(1U << 11)
+#define ISRM_RET_IRQ4		(1U << 12)
+#define ISRM_RET_IRQ5		(1U << 13)
+#define ISRM_RET_IRQ6		(1U << 14)
+#define ISRM_RET_IRQ7		(1U << 15)
+#define ISRM_RET_IRQ8		(1U << 16)
+#define ISRM_RET_IRQ9		(1U << 17)
+#define ISRM_RET_IRQ_AUX	((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+				 (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+				 (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+				 (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+				 (ISRM_RET_IRQ1))
+#define ISRM_ALL_EXC_TWAM	(ISRM_RET_IRQ_AUX)
+#define ISRM_ALL		(ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM		(1U << 2)
+#define ISRS_PCM_RETURN		(1U << 3)
+#define ISRC_TWAM		ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM	ISRS_PCM_RETURN
+#define ISRC_ALL		(ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP             0x3FF
+#define WAKE_MISC_DVFSRC_IRQ	         DVFSRC_IRQ_LSB
+#define WAKE_MISC_REG_CPU_WAKEUP         SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
+#define WAKE_MISC_PCM_TIMER_EVENT        PCM_TIMER_EVENT_LSB
+#define WAKE_MISC_PMIC_OUT_B		 ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B             TWAM_IRQ_B_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET0        PMSR_IRQ_B_SET0_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET1        PMSR_IRQ_B_SET1_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET2        PMSR_IRQ_B_SET2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   SPM_ACK_CHK_WAKEUP_0_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 SPM_ACK_CHK_WAKEUP_1_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 SPM_ACK_CHK_WAKEUP_2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 SPM_ACK_CHK_WAKEUP_3_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
+#define WAKE_MISC_PMIC_IRQ_ACK           PMIC_IRQ_ACK_LSB
+#define WAKE_MISC_PMIC_SCP_IRQ           PMIC_SCP_IRQ_LSB
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK				\
+	(SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC |	\
+	 SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1					\
+	(SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT |			\
+	 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT |	\
+	 SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+#define MCUPM_MBOX_WAKEUP_CPU		0x0C55FD10
+
+struct pwr_ctrl {
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint8_t wdt_disable;
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_md_apsrc_1_sel;
+	uint8_t reg_md_apsrc_0_sel;
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_vrf18_req;
+	uint8_t reg_spm_ddr_en_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	uint8_t reg_sspm_srcclkena_0_mask_b;
+	uint8_t reg_sspm_infra_req_0_mask_b;
+	uint8_t reg_sspm_apsrc_req_0_mask_b;
+	uint8_t reg_sspm_vrf18_req_0_mask_b;
+	uint8_t reg_sspm_ddr_en_0_mask_b;
+	uint8_t reg_scp_srcclkena_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_scp_ddr_en_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_ddr_en_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_apu_ddr_en_mask_b;
+	uint8_t reg_cpueb_srcclkena_mask_b;
+	uint8_t reg_cpueb_infra_req_mask_b;
+	uint8_t reg_cpueb_apsrc_req_mask_b;
+	uint8_t reg_cpueb_vrf18_req_mask_b;
+	uint8_t reg_cpueb_ddr_en_mask_b;
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	uint8_t reg_bak_psri_ddr_en_mask_b;
+
+	/* SPM_SRC2_MASK */
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc0_ddr_en_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc1_ddr_en_mask_b;
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	uint8_t reg_msdc2_infra_req_mask_b;
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	uint8_t reg_msdc2_ddr_en_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	uint8_t reg_ufs_ddr_en_mask_b;
+	uint8_t reg_usb_srcclkena_mask_b;
+	uint8_t reg_usb_infra_req_mask_b;
+	uint8_t reg_usb_apsrc_req_mask_b;
+	uint8_t reg_usb_vrf18_req_mask_b;
+	uint8_t reg_usb_ddr_en_mask_b;
+	uint8_t reg_pextp_p0_srcclkena_mask_b;
+	uint8_t reg_pextp_p0_infra_req_mask_b;
+	uint8_t reg_pextp_p0_apsrc_req_mask_b;
+	uint8_t reg_pextp_p0_vrf18_req_mask_b;
+	uint8_t reg_pextp_p0_ddr_en_mask_b;
+
+	/* SPM_SRC3_MASK */
+	uint8_t reg_pextp_p1_srcclkena_mask_b;
+	uint8_t reg_pextp_p1_infra_req_mask_b;
+	uint8_t reg_pextp_p1_apsrc_req_mask_b;
+	uint8_t reg_pextp_p1_vrf18_req_mask_b;
+	uint8_t reg_pextp_p1_ddr_en_mask_b;
+	uint8_t reg_gce0_infra_req_mask_b;
+	uint8_t reg_gce0_apsrc_req_mask_b;
+	uint8_t reg_gce0_vrf18_req_mask_b;
+	uint8_t reg_gce0_ddr_en_mask_b;
+	uint8_t reg_gce1_infra_req_mask_b;
+	uint8_t reg_gce1_apsrc_req_mask_b;
+	uint8_t reg_gce1_vrf18_req_mask_b;
+	uint8_t reg_gce1_ddr_en_mask_b;
+	uint8_t reg_spm_srcclkena_reserved_mask_b;
+	uint8_t reg_spm_infra_req_reserved_mask_b;
+	uint8_t reg_spm_apsrc_req_reserved_mask_b;
+	uint8_t reg_spm_vrf18_req_reserved_mask_b;
+	uint8_t reg_spm_ddr_en_reserved_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddr_en_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddr_en_mask_b;
+	uint8_t reg_disp2_apsrc_req_mask_b;
+	uint8_t reg_disp2_ddr_en_mask_b;
+	uint8_t reg_disp3_apsrc_req_mask_b;
+	uint8_t reg_disp3_ddr_en_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddr_en_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_cg_check_ddr_en_mask_b;
+
+	/* SPM_SRC4_MASK */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddr_en_mask_b;
+	uint8_t reg_dramc_md32_infra_req_mask_b;
+	uint8_t reg_dramc_md32_vrf18_req_mask_b;
+	uint8_t reg_dramc_md32_ddr_en_mask_b;
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK2 */
+	uint8_t reg_sc_sw2spm_wakeup_mask_b;
+	uint8_t reg_sc_adsp2spm_wakeup_mask_b;
+	uint8_t reg_sc_sspm2spm_wakeup_mask_b;
+	uint8_t reg_sc_scp2spm_wakeup_mask_b;
+	uint8_t reg_csyspwrup_ack_mask;
+	uint8_t reg_csyspwrup_req_mask;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_CLK_CON */
+	PW_REG_SRCCLKEN0_CTL,
+	PW_REG_SRCCLKEN1_CTL,
+	PW_REG_SPM_LOCK_INFRA_DCM,
+	PW_REG_SRCCLKEN_MASK,
+	PW_REG_MD1_C32RM_EN,
+	PW_REG_MD2_C32RM_EN,
+	PW_REG_CLKSQ0_SEL_CTRL,
+	PW_REG_CLKSQ1_SEL_CTRL,
+	PW_REG_SRCCLKEN0_EN,
+	PW_REG_SRCCLKEN1_EN,
+	PW_REG_SYSCLK0_SRC_MASK_B,
+	PW_REG_SYSCLK1_SRC_MASK_B,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDR_EN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_MD_SRCCLKENA_0_MASK_B,
+	PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
+	PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
+	PW_REG_MD_APSRC_REQ_0_MASK_B,
+	PW_REG_MD_VRF18_REQ_0_MASK_B,
+	PW_REG_MD_DDR_EN_0_MASK_B,
+	PW_REG_MD_SRCCLKENA_1_MASK_B,
+	PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
+	PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
+	PW_REG_MD_APSRC_REQ_1_MASK_B,
+	PW_REG_MD_VRF18_REQ_1_MASK_B,
+	PW_REG_MD_DDR_EN_1_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDR_EN_MASK_B,
+	PW_REG_CONN_VFE28_MASK_B,
+	PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDR_EN_MASK_B,
+	PW_REG_MD32_SRCCLKENA_MASK_B,
+	PW_REG_MD32_INFRA_REQ_MASK_B,
+	PW_REG_MD32_APSRC_REQ_MASK_B,
+	PW_REG_MD32_VRF18_REQ_MASK_B,
+	PW_REG_MD32_DDR_EN_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDR_EN_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDR_EN_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDR_EN_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDR_EN_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDR_EN_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDR_EN_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDR_EN_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_INT0_MASK_B,
+	PW_REG_SW2SPM_INT1_MASK_B,
+	PW_REG_SW2SPM_INT2_MASK_B,
+	PW_REG_SW2SPM_INT3_MASK_B,
+	PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRREQ_MASK,
+	PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+	PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUPM_DDR_EN_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDR_EN_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDR_EN_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_CCIF_EVENT_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDR_EN_MASK_B,
+	PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
+	PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_REG_DRAMC0_MD32_WAKEUP_MASK,
+	PW_REG_DRAMC1_MD32_WAKEUP_MASK,
+
+	/* SPM_SRC5_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	PW_MAX_COUNT,
+};
+
+#define SPM_INTERNAL_STATUS_HW_S1	(1U << 0)
+#define SPM_ACK_CHK_3_SEL_HW_S1		0x00350098
+#define SPM_ACK_CHK_3_HW_S1_CNT		1
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG	0x800
+#define SPM_ACK_CHK_3_CON_EN		0x110
+#define SPM_ACK_CHK_3_CON_CLR_ALL	0x2
+#define SPM_ACK_CHK_3_CON_RESULT	0x8000
+
+struct wake_status_trace_comm {
+	uint32_t debug_flag;			/* PCM_WDT_LATCH_SPARE_0 */
+	uint32_t debug_flag1;			/* PCM_WDT_LATCH_SPARE_1 */
+	uint32_t timer_out;			/* SPM_BK_PCM_TIMER */
+	uint32_t b_sw_flag0;			/* SPM_SW_RSV_7 */
+	uint32_t b_sw_flag1;			/* SPM_SW_RSV_8 */
+	uint32_t r12;				/* SPM_SW_RSV_0 */
+	uint32_t r13;				/* PCM_REG13_DATA */
+	uint32_t req_sta0;			/* SRC_REQ_STA_0 */
+	uint32_t req_sta1;			/* SRC_REQ_STA_1 */
+	uint32_t req_sta2;			/* SRC_REQ_STA_2 */
+	uint32_t req_sta3;			/* SRC_REQ_STA_3 */
+	uint32_t req_sta4;			/* SRC_REQ_STA_4 */
+	uint32_t raw_sta;			/* SPM_WAKEUP_STA */
+	uint32_t times_h;			/* timestamp high bits */
+	uint32_t times_l;			/* timestamp low bits */
+	uint32_t resumetime;			/* timestamp low bits */
+};
+
+struct wake_status_trace {
+	struct wake_status_trace_comm comm;
+};
+
+struct wake_status {
+	struct wake_status_trace tr;
+	uint32_t r12;				/* SPM_BK_WAKE_EVENT */
+	uint32_t r12_ext;			/* SPM_WAKEUP_STA */
+	uint32_t raw_sta;			/* SPM_WAKEUP_STA */
+	uint32_t raw_ext_sta;			/* SPM_WAKEUP_EXT_STA */
+	uint32_t md32pcm_wakeup_sta;		/* MD32PCM_WAKEUP_STA */
+	uint32_t md32pcm_event_sta;		/* MD32PCM_EVENT_STA */
+	uint32_t src_req;			/* SPM_SRC_REQ */
+	uint32_t wake_misc;			/* SPM_BK_WAKE_MISC */
+	uint32_t timer_out;			/* SPM_BK_PCM_TIMER */
+	uint32_t r13;				/* PCM_REG13_DATA */
+	uint32_t idle_sta;			/* SUBSYS_IDLE_STA */
+	uint32_t req_sta0;			/* SRC_REQ_STA_0 */
+	uint32_t req_sta1;			/* SRC_REQ_STA_1 */
+	uint32_t req_sta2;			/* SRC_REQ_STA_2 */
+	uint32_t req_sta3;			/* SRC_REQ_STA_3 */
+	uint32_t req_sta4;			/* SRC_REQ_STA_4 */
+	uint32_t cg_check_sta;			/* SPM_CG_CHECK_STA */
+	uint32_t debug_flag;			/* PCM_WDT_LATCH_SPARE_0 */
+	uint32_t debug_flag1;			/* PCM_WDT_LATCH_SPARE_1 */
+	uint32_t b_sw_flag0;			/* SPM_SW_RSV_7 */
+	uint32_t b_sw_flag1;			/* SPM_SW_RSV_8 */
+	uint32_t rt_req_sta0;			/* SPM_SW_RSV_2 */
+	uint32_t rt_req_sta1;			/* SPM_SW_RSV_3 */
+	uint32_t rt_req_sta2;			/* SPM_SW_RSV_4 */
+	uint32_t rt_req_sta3;			/* SPM_SW_RSV_5 */
+	uint32_t rt_req_sta4;			/* SPM_SW_RSV_6 */
+	uint32_t isr;				/* SPM_IRQ_STA */
+	uint32_t sw_flag0;			/* SPM_SW_FLAG_0 */
+	uint32_t sw_flag1;			/* SPM_SW_FLAG_1 */
+	uint32_t clk_settle;			/* SPM_CLK_SETTLE */
+	uint32_t abort;
+};
+
+struct spm_lp_scen {
+	struct pcm_desc *pcmdesc;
+	struct pwr_ctrl *pwrctrl;
+};
+
+extern struct spm_lp_scen __spm_vcorefs;
+extern void __spm_set_cpu_status(unsigned int cpu);
+extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
+extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
+extern void __spm_init_pcm_register(void);
+extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+				 unsigned int resource_usage);
+extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+extern void __spm_disable_pcm_timer(void);
+extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
+extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
+extern void __spm_send_cpu_wakeup_event(void);
+extern void __spm_get_wakeup_status(struct wake_status *wakesta,
+				    unsigned int ext_status);
+extern void __spm_clean_after_wakeup(void);
+extern wake_reason_t
+__spm_output_wake_reason(int state_id, const struct wake_status *wakesta);
+extern void
+__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
+				    const struct pwr_ctrl *src_pwr_ctrl);
+extern void __spm_set_pcm_wdt(int en);
+extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
+extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
+extern void __spm_ext_int_wakeup_req_clr(void);
+extern void __spm_xo_soc_bblpm(int en);
+
+static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
+					 uint32_t flags)
+{
+	if (pwrctrl->pcm_flags_cust == 0U) {
+		pwrctrl->pcm_flags = flags;
+	} else {
+		pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
+	}
+}
+
+static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
+					  uint32_t flags)
+{
+	if (pwrctrl->pcm_flags1_cust == 0U) {
+		pwrctrl->pcm_flags1 = flags;
+	} else {
+		pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
+	}
+}
+
+extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
+
+static inline void spm_hw_s1_state_monitor_resume(void)
+{
+	__spm_hw_s1_state_monitor(1, NULL);
+}
+
+static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
+{
+	__spm_hw_s1_state_monitor(0, status);
+}
+#endif /* MT_SPM_INTERNAL_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c
new file mode 100644
index 0000000..9da644c
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+/* PMIC_WRAP MT6359 */
+#define VCORE_BASE_UV		40000
+#define VOLT_TO_PMIC_VAL(volt)	(((volt) - VCORE_BASE_UV + 625 - 1) / 625)
+#define PMIC_VAL_TO_VOLT(pmic)	(((pmic) * 625) + VCORE_BASE_UV)
+
+#define NR_PMIC_WRAP_CMD	(NR_IDX_ALL)
+#define SPM_DATA_SHIFT		16
+
+#define BUCK_VGPU11_ELR0	0x15B4
+#define TOP_SPI_CON0		0x0456
+#define BUCK_TOP_CON1		0x1443
+#define TOP_CON			0x0013
+#define TOP_DIG_WPK		0x03a9
+#define TOP_CON_LOCK		0x03a8
+#define TOP_CLK_CON0		0x0134
+
+struct pmic_wrap_cmd {
+	unsigned long cmd_addr;
+	unsigned long cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+	enum pmic_wrap_phase_id phase;
+	struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+	struct {
+		struct {
+			unsigned long cmd_addr;
+			unsigned long cmd_wdata;
+		} _[NR_PMIC_WRAP_CMD];
+		const int nr_idx;
+	} set[NR_PMIC_WRAP_PHASE];
+};
+
+static struct pmic_wrap_setting pw = {
+	.phase = NR_PMIC_WRAP_PHASE,    /* invalid setting for init */
+	.addr = { {0UL, 0UL} },
+	.set[PMIC_WRAP_PHASE_ALLINONE] = {
+		._[CMD_0]	= {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(75000),},
+		._[CMD_1]	= {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
+		._[CMD_2]	= {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
+		._[CMD_3]	= {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(55000),},
+		._[CMD_4]	= {TOP_SPI_CON0, 0x1,},
+		._[CMD_5]	= {TOP_SPI_CON0, 0x0,},
+		._[CMD_6]	= {BUCK_TOP_CON1, 0x0,},
+		._[CMD_7]	= {BUCK_TOP_CON1, 0xf,},
+		._[CMD_8]	= {TOP_CON, 0x3,},
+		._[CMD_9]	= {TOP_CON, 0x0,},
+		._[CMD_10]	= {TOP_DIG_WPK, 0x63,},
+		._[CMD_11]	= {TOP_CON_LOCK, 0x15,},
+		._[CMD_12]	= {TOP_DIG_WPK, 0x0,},
+		._[CMD_13]	= {TOP_CON_LOCK, 0x0,},
+		._[CMD_14]	= {TOP_CLK_CON0, 0x40,},
+		._[CMD_15]	= {TOP_CLK_CON0, 0x0,},
+		.nr_idx = NR_IDX_ALL,
+	},
+};
+
+void _mt_spm_pmic_table_init(void)
+{
+	struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+		{(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
+		{(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
+		{(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
+		{(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
+		{(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
+		{(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
+		{(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
+		{(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
+		{(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
+		{(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
+		{(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
+		{(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
+		{(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
+		{(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
+		{(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
+		{(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
+	};
+
+	memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+	uint32_t idx, addr, data;
+
+	if (phase >= NR_PMIC_WRAP_PHASE) {
+		return;
+	}
+
+	if (pw.phase == phase) {
+		return;
+	}
+
+	if (pw.addr[0].cmd_addr == 0UL) {
+		_mt_spm_pmic_table_init();
+	}
+
+	pw.phase = phase;
+	mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+	for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
+		addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+		data = pw.set[phase]._[idx].cmd_wdata;
+		mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
+	}
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
+			      uint32_t cmd_wdata)
+{
+	uint32_t addr;
+
+	if (phase >= NR_PMIC_WRAP_PHASE) {
+		return;
+	}
+
+	if (idx >= pw.set[phase].nr_idx) {
+		return;
+	}
+
+	pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
+	mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+	if (pw.phase == phase) {
+		addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+		mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
+	}
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
+{
+	if (phase >= NR_PMIC_WRAP_PHASE) {
+		return 0UL;
+	}
+
+	if (idx >= pw.set[phase].nr_idx) {
+		return 0UL;
+	}
+
+	return pw.set[phase]._[idx].cmd_wdata;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h
new file mode 100644
index 0000000..53fdda2
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+#ifndef MT_SPM_PMIC_WRAP_H
+#define MT_SPM_PMIC_WRAP_H
+
+enum pmic_wrap_phase_id {
+	PMIC_WRAP_PHASE_ALLINONE,
+	NR_PMIC_WRAP_PHASE,
+};
+
+/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
+enum {
+	CMD_0,        /* 0x0 */
+	CMD_1,        /* 0x1 */
+	CMD_2,        /* 0x2 */
+	CMD_3,        /* 0x3 */
+	CMD_4,        /* 0x4 */
+	CMD_5,        /* 0x5 */
+	CMD_6,        /* 0x6 */
+	CMD_7,        /* 0x7 */
+	CMD_8,        /* 0x8 */
+	CMD_9,        /* 0x9 */
+	CMD_10,        /* 0xA */
+	CMD_11,        /* 0xB */
+	CMD_12,        /* 0xC */
+	CMD_13,        /* 0xD */
+	CMD_14,        /* 0xE */
+	CMD_15,        /* 0xF */
+	NR_IDX_ALL,
+};
+
+/* APIs */
+extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
+				     uint32_t idx, uint32_t cmd_wdata);
+extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
+					 uint32_t idx);
+#endif /* MT_SPM_PMIC_WRAP_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h
new file mode 100644
index 0000000..d8b9b29
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h
@@ -0,0 +1,2859 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+
+#ifndef MT_SPM_REG
+#define MT_SPM_REG
+
+#include "sleep_def.h"
+#include <platform_def.h>
+#include "pcm_def.h"
+
+/**************************************
+ * Define and Declare
+ **************************************/
+
+/*******Register_SPM_CFG*************************************************/
+#define POWERON_CONFIG_EN              (SPM_BASE + 0x000)
+#define SPM_POWER_ON_VAL0              (SPM_BASE + 0x004)
+#define SPM_POWER_ON_VAL1              (SPM_BASE + 0x008)
+#define SPM_CLK_CON                    (SPM_BASE + 0x00C)
+#define SPM_CLK_SETTLE                 (SPM_BASE + 0x010)
+#define SPM_AP_STANDBY_CON             (SPM_BASE + 0x014)
+#define PCM_CON0                       (SPM_BASE + 0x018)
+#define PCM_CON1                       (SPM_BASE + 0x01C)
+#define SPM_POWER_ON_VAL2              (SPM_BASE + 0x020)
+#define SPM_POWER_ON_VAL3              (SPM_BASE + 0x024)
+#define PCM_REG_DATA_INI               (SPM_BASE + 0x028)
+#define PCM_PWR_IO_EN                  (SPM_BASE + 0x02C)
+#define PCM_TIMER_VAL                  (SPM_BASE + 0x030)
+#define PCM_WDT_VAL                    (SPM_BASE + 0x034)
+#define SPM_SW_RST_CON                 (SPM_BASE + 0x040)
+#define SPM_SW_RST_CON_SET             (SPM_BASE + 0x044)
+#define SPM_SW_RST_CON_CLR             (SPM_BASE + 0x048)
+#define VS1_PSR_MASK_B                 (SPM_BASE + 0x04C)
+#define SPM_ARBITER_EN                 (SPM_BASE + 0x050)
+#define SCPSYS_CLK_CON                 (SPM_BASE + 0x054)
+#define SPM_SRAM_RSV_CON               (SPM_BASE + 0x058)
+#define SPM_SWINT                      (SPM_BASE + 0x05C)
+#define SPM_SWINT_SET                  (SPM_BASE + 0x060)
+#define SPM_SWINT_CLR                  (SPM_BASE + 0x064)
+#define SPM_SCP_MAILBOX                (SPM_BASE + 0x068)
+#define SCP_SPM_MAILBOX                (SPM_BASE + 0x06C)
+#define SPM_SCP_IRQ                    (SPM_BASE + 0x070)
+#define SPM_CPU_WAKEUP_EVENT           (SPM_BASE + 0x074)
+#define SPM_IRQ_MASK                   (SPM_BASE + 0x078)
+#define SPM_SRC_REQ                    (SPM_BASE + 0x080)
+#define SPM_SRC_MASK                   (SPM_BASE + 0x084)
+#define SPM_SRC2_MASK                  (SPM_BASE + 0x088)
+#define SPM_SRC3_MASK                  (SPM_BASE + 0x090)
+#define SPM_SRC4_MASK                  (SPM_BASE + 0x094)
+#define SPM_WAKEUP_EVENT_MASK2         (SPM_BASE + 0x098)
+#define SPM_WAKEUP_EVENT_MASK          (SPM_BASE + 0x09C)
+#define SPM_WAKEUP_EVENT_SENS          (SPM_BASE + 0x0A0)
+#define SPM_WAKEUP_EVENT_CLEAR         (SPM_BASE + 0x0A4)
+#define SPM_WAKEUP_EVENT_EXT_MASK      (SPM_BASE + 0x0A8)
+#define SCP_CLK_CON                    (SPM_BASE + 0x0AC)
+#define PCM_DEBUG_CON                  (SPM_BASE + 0x0B0)
+#define DDREN_DBC_CON                  (SPM_BASE + 0x0B4)
+#define SPM_RESOURCE_ACK_CON0          (SPM_BASE + 0x0B8)
+#define SPM_RESOURCE_ACK_CON1          (SPM_BASE + 0x0BC)
+#define SPM_RESOURCE_ACK_CON2          (SPM_BASE + 0x0C0)
+#define SPM_RESOURCE_ACK_CON3          (SPM_BASE + 0x0C4)
+#define SPM_RESOURCE_ACK_CON4          (SPM_BASE + 0x0C8)
+#define SPM_SRAM_CON                   (SPM_BASE + 0x0CC)
+/*******Register_SPM_STA*************************************************/
+#define PCM_REG0_DATA                  (SPM_BASE + 0x100)
+#define PCM_REG2_DATA                  (SPM_BASE + 0x104)
+#define PCM_REG6_DATA                  (SPM_BASE + 0x108)
+#define PCM_REG7_DATA                  (SPM_BASE + 0x10C)
+#define PCM_REG13_DATA                 (SPM_BASE + 0x110)
+#define SRC_REQ_STA_0                  (SPM_BASE + 0x114)
+#define SRC_REQ_STA_1                  (SPM_BASE + 0x118)
+#define SRC_REQ_STA_2                  (SPM_BASE + 0x120)
+#define SRC_REQ_STA_3                  (SPM_BASE + 0x124)
+#define SRC_REQ_STA_4                  (SPM_BASE + 0x128)
+#define PCM_TIMER_OUT                  (SPM_BASE + 0x130)
+#define PCM_WDT_OUT                    (SPM_BASE + 0x134)
+#define SPM_IRQ_STA                    (SPM_BASE + 0x138)
+#define MD32PCM_WAKEUP_STA             (SPM_BASE + 0x13C)
+#define MD32PCM_EVENT_STA              (SPM_BASE + 0x140)
+#define SPM_WAKEUP_STA                 (SPM_BASE + 0x144)
+#define SPM_WAKEUP_EXT_STA             (SPM_BASE + 0x148)
+#define SPM_WAKEUP_MISC                (SPM_BASE + 0x14C)
+#define MM_DVFS_HALT                   (SPM_BASE + 0x150)
+#define SUBSYS_IDLE_STA                (SPM_BASE + 0x164)
+#define PCM_STA                        (SPM_BASE + 0x168)
+#define PWR_STATUS                     (SPM_BASE + 0x16C)
+#define PWR_STATUS_2ND                 (SPM_BASE + 0x170)
+#define CPU_PWR_STATUS                 (SPM_BASE + 0x174)
+#define CPU_PWR_STATUS_2ND             (SPM_BASE + 0x178)
+#define SPM_VTCXO_EVENT_COUNT_STA      (SPM_BASE + 0x17C)
+#define SPM_INFRA_EVENT_COUNT_STA      (SPM_BASE + 0x180)
+#define SPM_VRF18_EVENT_COUNT_STA      (SPM_BASE + 0x184)
+#define SPM_APSRC_EVENT_COUNT_STA      (SPM_BASE + 0x188)
+#define SPM_DDREN_EVENT_COUNT_STA      (SPM_BASE + 0x18C)
+#define MD32PCM_STA                    (SPM_BASE + 0x190)
+#define MD32PCM_PC                     (SPM_BASE + 0x194)
+#define OTHER_PWR_STATUS               (SPM_BASE + 0x198)
+#define DVFSRC_EVENT_STA               (SPM_BASE + 0x19C)
+#define BUS_PROTECT_RDY                (SPM_BASE + 0x1A0)
+#define BUS_PROTECT1_RDY               (SPM_BASE + 0x1A4)
+#define BUS_PROTECT2_RDY               (SPM_BASE + 0x1A8)
+#define BUS_PROTECT3_RDY               (SPM_BASE + 0x1AC)
+#define BUS_PROTECT4_RDY               (SPM_BASE + 0x1B0)
+#define BUS_PROTECT5_RDY               (SPM_BASE + 0x1B4)
+#define BUS_PROTECT6_RDY               (SPM_BASE + 0x1B8)
+#define BUS_PROTECT7_RDY               (SPM_BASE + 0x1BC)
+#define BUS_PROTECT8_RDY               (SPM_BASE + 0x1C0)
+#define BUS_PROTECT9_RDY               (SPM_BASE + 0x1C4)
+#define SPM_TWAM_LAST_STA0             (SPM_BASE + 0x1D0)
+#define SPM_TWAM_LAST_STA1             (SPM_BASE + 0x1D4)
+#define SPM_TWAM_LAST_STA2             (SPM_BASE + 0x1D8)
+#define SPM_TWAM_LAST_STA3             (SPM_BASE + 0x1DC)
+#define SPM_TWAM_CURR_STA0             (SPM_BASE + 0x1E0)
+#define SPM_TWAM_CURR_STA1             (SPM_BASE + 0x1E4)
+#define SPM_TWAM_CURR_STA2             (SPM_BASE + 0x1E8)
+#define SPM_TWAM_CURR_STA3             (SPM_BASE + 0x1EC)
+#define SPM_TWAM_TIMER_OUT             (SPM_BASE + 0x1F0)
+#define SPM_CG_CHECK_STA               (SPM_BASE + 0x1F4)
+#define SPM_DVFS_STA                   (SPM_BASE + 0x1F8)
+#define SPM_DVFS_OPP_STA               (SPM_BASE + 0x1FC)
+/*******Register_CPU_MT*************************************************/
+#define CPUEB_PWR_CON                  (SPM_BASE + 0x200)
+#define SPM_MCUSYS_PWR_CON             (SPM_BASE + 0x204)
+#define SPM_CPUTOP_PWR_CON             (SPM_BASE + 0x208)
+#define SPM_CPU0_PWR_CON               (SPM_BASE + 0x20C)
+#define SPM_CPU1_PWR_CON               (SPM_BASE + 0x210)
+#define SPM_CPU2_PWR_CON               (SPM_BASE + 0x214)
+#define SPM_CPU3_PWR_CON               (SPM_BASE + 0x218)
+#define SPM_CPU4_PWR_CON               (SPM_BASE + 0x21C)
+#define SPM_CPU5_PWR_CON               (SPM_BASE + 0x220)
+#define SPM_CPU6_PWR_CON               (SPM_BASE + 0x224)
+#define SPM_CPU7_PWR_CON               (SPM_BASE + 0x228)
+#define ARMPLL_CLK_CON                 (SPM_BASE + 0x22C)
+#define MCUSYS_IDLE_STA                (SPM_BASE + 0x230)
+#define GIC_WAKEUP_STA                 (SPM_BASE + 0x234)
+#define CPU_SPARE_CON                  (SPM_BASE + 0x238)
+#define CPU_SPARE_CON_SET              (SPM_BASE + 0x23C)
+#define CPU_SPARE_CON_CLR              (SPM_BASE + 0x240)
+#define ARMPLL_CLK_SEL                 (SPM_BASE + 0x244)
+#define EXT_INT_WAKEUP_REQ             (SPM_BASE + 0x248)
+#define EXT_INT_WAKEUP_REQ_SET         (SPM_BASE + 0x24C)
+#define EXT_INT_WAKEUP_REQ_CLR         (SPM_BASE + 0x250)
+#define CPU0_IRQ_MASK                  (SPM_BASE + 0x260)
+#define CPU_IRQ_MASK_SET               (SPM_BASE + 0x264)
+#define CPU_IRQ_MASK_CLR               (SPM_BASE + 0x268)
+#define CPU_WFI_EN                     (SPM_BASE + 0x280)
+#define CPU_WFI_EN_SET                 (SPM_BASE + 0x284)
+#define CPU_WFI_EN_CLR                 (SPM_BASE + 0x288)
+#define SYSRAM_CON                     (SPM_BASE + 0x290)
+#define SYSROM_CON                     (SPM_BASE + 0x294)
+#define ROOT_CPUTOP_ADDR               (SPM_BASE + 0x2A0)
+#define ROOT_CORE_ADDR                 (SPM_BASE + 0x2A4)
+#define SPM2SW_MAILBOX_0               (SPM_BASE + 0x2D0)
+#define SPM2SW_MAILBOX_1               (SPM_BASE + 0x2D4)
+#define SPM2SW_MAILBOX_2               (SPM_BASE + 0x2D8)
+#define SPM2SW_MAILBOX_3               (SPM_BASE + 0x2DC)
+#define SW2SPM_INT                     (SPM_BASE + 0x2E0)
+#define SW2SPM_INT_SET                 (SPM_BASE + 0x2E4)
+#define SW2SPM_INT_CLR                 (SPM_BASE + 0x2E8)
+#define SW2SPM_MAILBOX_0               (SPM_BASE + 0x2EC)
+#define SW2SPM_MAILBOX_1               (SPM_BASE + 0x2F0)
+#define SW2SPM_MAILBOX_2               (SPM_BASE + 0x2F4)
+#define SW2SPM_MAILBOX_3               (SPM_BASE + 0x2F8)
+#define SW2SPM_CFG                     (SPM_BASE + 0x2FC)
+/*******Register_NONCPU_MT*************************************************/
+#define MFG0_PWR_CON                   (SPM_BASE + 0x300)
+#define MFG1_PWR_CON                   (SPM_BASE + 0x304)
+#define MFG2_PWR_CON                   (SPM_BASE + 0x308)
+#define MFG3_PWR_CON                   (SPM_BASE + 0x30C)
+#define MFG4_PWR_CON                   (SPM_BASE + 0x310)
+#define MFG5_PWR_CON                   (SPM_BASE + 0x314)
+#define MFG6_PWR_CON                   (SPM_BASE + 0x318)
+#define IFR_PWR_CON                    (SPM_BASE + 0x31C)
+#define IFR_SUB_PWR_CON                (SPM_BASE + 0x320)
+#define PERI_PWR_CON                   (SPM_BASE + 0x324)
+#define PEXTP_MAC_TOP_P0_PWR_CON       (SPM_BASE + 0x328)
+#define PEXTP_MAC_TOP_P1_PWR_CON       (SPM_BASE + 0x32C)
+#define PCIE_PHY_PWR_CON               (SPM_BASE + 0x330)
+#define SSUSB_PCIE_PHY_PWR_CON         (SPM_BASE + 0x334)
+#define SSUSB_TOP_P1_PWR_CON           (SPM_BASE + 0x338)
+#define SSUSB_TOP_P2_PWR_CON           (SPM_BASE + 0x33C)
+#define SSUSB_TOP_P3_PWR_CON           (SPM_BASE + 0x340)
+#define ETHER_PWR_CON                  (SPM_BASE + 0x344)
+#define DPY0_PWR_CON                   (SPM_BASE + 0x348)
+#define DPY1_PWR_CON                   (SPM_BASE + 0x34C)
+#define DPM0_PWR_CON                   (SPM_BASE + 0x350)
+#define DPM1_PWR_CON                   (SPM_BASE + 0x354)
+#define AUDIO_PWR_CON                  (SPM_BASE + 0x358)
+#define AUDIO_ASRC_PWR_CON             (SPM_BASE + 0x35C)
+#define ADSP_PWR_CON                   (SPM_BASE + 0x360)
+#define VPPSYS0_PWR_CON                (SPM_BASE + 0x364)
+#define VPPSYS1_PWR_CON                (SPM_BASE + 0x368)
+#define VDOSYS0_PWR_CON                (SPM_BASE + 0x36C)
+#define VDOSYS1_PWR_CON                (SPM_BASE + 0x370)
+#define WPESYS_PWR_CON                 (SPM_BASE + 0x374)
+#define DP_TX_PWR_CON                  (SPM_BASE + 0x378)
+#define EDP_TX_PWR_CON                 (SPM_BASE + 0x37C)
+#define HDMI_TX_PWR_CON                (SPM_BASE + 0x380)
+#define HDMI_RX_PWR_CON                (SPM_BASE + 0x384)
+#define VDE0_PWR_CON                   (SPM_BASE + 0x388)
+#define VDE1_PWR_CON                   (SPM_BASE + 0x38C)
+#define VDE2_PWR_CON                   (SPM_BASE + 0x390)
+#define VEN_PWR_CON                    (SPM_BASE + 0x394)
+#define VEN_CORE1_PWR_CON              (SPM_BASE + 0x398)
+#define CAM_PWR_CON                    (SPM_BASE + 0x39C)
+#define CAM_RAWA_PWR_CON               (SPM_BASE + 0x3A0)
+#define CAM_RAWB_PWR_CON               (SPM_BASE + 0x3A4)
+#define CAM_RAWC_PWR_CON               (SPM_BASE + 0x3A8)
+#define IMG_M_PWR_CON                  (SPM_BASE + 0x3AC)
+#define IMG_D_PWR_CON                  (SPM_BASE + 0x3B0)
+#define IPE_PWR_CON                    (SPM_BASE + 0x3B4)
+#define NNA0_PWR_CON                   (SPM_BASE + 0x3B8)
+#define NNA1_PWR_CON                   (SPM_BASE + 0x3BC)
+#define IPNNA_PWR_CON                  (SPM_BASE + 0x3C0)
+#define CSI_RX_TOP_PWR_CON             (SPM_BASE + 0x3C4)
+#define SSPM_SRAM_CON                  (SPM_BASE + 0x3C4)
+#define SCP_SRAM_CON                   (SPM_BASE + 0x3D0)
+#define UFS_SRAM_CON                   (SPM_BASE + 0x3D4)
+#define DEVAPC_IFR_SRAM_CON            (SPM_BASE + 0x3D8)
+#define DEVAPC_SUBIFR_SRAM_CON         (SPM_BASE + 0x3DC)
+#define DEVAPC_ACP_SRAM_CON            (SPM_BASE + 0x3E0)
+#define USB_SRAM_CON                   (SPM_BASE + 0x3E4)
+#define DUMMY_SRAM_CO                  (SPM_BASE + 0x3E8)
+#define EXT_BUCK_ISO                   (SPM_BASE + 0x3EC)
+#define MSDC_SRAM_CON                  (SPM_BASE + 0x3F0)
+#define DEBUGTOP_SRAM                  (SPM_BASE + 0x3F4)
+#define DPMAIF_SRAM_C                  (SPM_BASE + 0x3F8)
+#define GCPU_SRAM_CON                  (SPM_BASE + 0x3FC)
+/*******Register_DIRC_IF*************************************************/
+#define SPM_MEM_CK_SEL                 (SPM_BASE + 0x400)
+#define SPM_BUS_PROTECT_MASK_B         (SPM_BASE + 0x404)
+#define SPM_BUS_PROTECT1_MASK_B        (SPM_BASE + 0x408)
+#define SPM_BUS_PROTECT2_MASK_B        (SPM_BASE + 0x40C)
+#define SPM_BUS_PROTECT3_MASK_B        (SPM_BASE + 0x410)
+#define SPM_BUS_PROTECT4_MASK_B        (SPM_BASE + 0x414)
+#define SPM_BUS_PROTECT5_MASK_B        (SPM_BASE + 0x418)
+#define SPM_BUS_PROTECT6_MASK_B        (SPM_BASE + 0x41C)
+#define SPM_BUS_PROTECT7_MASK_B        (SPM_BASE + 0x420)
+#define SPM_BUS_PROTECT8_MASK_B        (SPM_BASE + 0x424)
+#define SPM_BUS_PROTECT9_MASK_B        (SPM_BASE + 0x428)
+#define SPM_EMI_BW_MODE                (SPM_BASE + 0x42C)
+#define SPM2MM_CON                     (SPM_BASE + 0x434)
+#define SPM2CPUEB_CON                  (SPM_BASE + 0x438)
+#define AP_MDSRC_REQ                   (SPM_BASE + 0x43C)
+#define SPM2EMI_ENTER_ULPM             (SPM_BASE + 0x440)
+#define SPM_PLL_CON                    (SPM_BASE + 0x444)
+#define RC_SPM_CTRL                    (SPM_BASE + 0x448)
+#define SPM_DRAM_MCU_SW_CON_0          (SPM_BASE + 0x44C)
+#define SPM_DRAM_MCU_SW_CON_1          (SPM_BASE + 0x450)
+#define SPM_DRAM_MCU_SW_CON_2          (SPM_BASE + 0x454)
+#define SPM_DRAM_MCU_SW_CON_3          (SPM_BASE + 0x458)
+#define SPM_DRAM_MCU_SW_CON_4          (SPM_BASE + 0x45C)
+#define SPM_DRAM_MCU_STA_0             (SPM_BASE + 0x460)
+#define SPM_DRAM_MCU_STA_1             (SPM_BASE + 0x464)
+#define SPM_DRAM_MCU_STA_2             (SPM_BASE + 0x468)
+#define SPM_DRAM_MCU_SW_SEL_0          (SPM_BASE + 0x46C)
+#define RELAY_DVFS_LEVEL               (SPM_BASE + 0x470)
+#define DRAMC_DPY_CLK_SW_CON_0         (SPM_BASE + 0x474)
+#define DRAMC_DPY_CLK_SW_CON_1         (SPM_BASE + 0x478)
+#define DRAMC_DPY_CLK_SW_CON_2         (SPM_BASE + 0x47C)
+#define DRAMC_DPY_CLK_SW_CON_3         (SPM_BASE + 0x480)
+#define DRAMC_DPY_CLK_SW_SEL_0         (SPM_BASE + 0x484)
+#define DRAMC_DPY_CLK_SW_SEL_1         (SPM_BASE + 0x488)
+#define DRAMC_DPY_CLK_SW_SEL_2         (SPM_BASE + 0x48C)
+#define DRAMC_DPY_CLK_SW_SEL_3         (SPM_BASE + 0x490)
+#define DRAMC_DPY_CLK_SPM_CON          (SPM_BASE + 0x494)
+#define SPM_DVFS_LEVEL                 (SPM_BASE + 0x498)
+#define SPM_CIRQ_CON                   (SPM_BASE + 0x49C)
+#define SPM_DVFS_MISC                  (SPM_BASE + 0x4A0)
+#define RG_MODULE_SW_CG_0_MASK_REQ_0   (SPM_BASE + 0x4A4)
+#define RG_MODULE_SW_CG_0_MASK_REQ_1   (SPM_BASE + 0x4A8)
+#define RG_MODULE_SW_CG_0_MASK_REQ_2   (SPM_BASE + 0x4AC)
+#define RG_MODULE_SW_CG_1_MASK_REQ_0   (SPM_BASE + 0x4B0)
+#define RG_MODULE_SW_CG_1_MASK_REQ_1   (SPM_BASE + 0x4B4)
+#define RG_MODULE_SW_CG_1_MASK_REQ_2   (SPM_BASE + 0x4B8)
+#define RG_MODULE_SW_CG_2_MASK_REQ_0   (SPM_BASE + 0x4BC)
+#define RG_MODULE_SW_CG_2_MASK_REQ_1   (SPM_BASE + 0x4C0)
+#define RG_MODULE_SW_CG_2_MASK_REQ_2   (SPM_BASE + 0x4C4)
+#define RG_MODULE_SW_CG_3_MASK_REQ_0   (SPM_BASE + 0x4C8)
+#define RG_MODULE_SW_CG_3_MASK_REQ_1   (SPM_BASE + 0x4CC)
+#define RG_MODULE_SW_CG_3_MASK_REQ_2   (SPM_BASE + 0x4D0)
+#define PWR_STATUS_MASK_REQ_0          (SPM_BASE + 0x4D4)
+#define PWR_STATUS_MASK_REQ_1          (SPM_BASE + 0x4D8)
+#define PWR_STATUS_MASK_REQ_2          (SPM_BASE + 0x4DC)
+#define SPM_CG_CHECK_CON               (SPM_BASE + 0x4E0)
+#define SPM_SRC_RDY_STA                (SPM_BASE + 0x4E4)
+#define SPM_DVS_DFS_LEVEL              (SPM_BASE + 0x4E8)
+#define SPM_FORCE_DVFS                 (SPM_BASE + 0x4EC)
+#define DRAMC_MCU_SRAM_CON             (SPM_BASE + 0x4F0)
+#define DRAMC_MCU2_SRAM_CON            (SPM_BASE + 0x4F4)
+#define DPY_SHU_SRAM_CON               (SPM_BASE + 0x4F8)
+#define DPY_SHU2_SRAM_CON              (SPM_BASE + 0x4FC)
+/*******The Others*************************************************/
+#define SRCLKEN_RC_CFG                 (SPM_BASE + 0x500)
+#define RC_CENTRAL_CFG1                (SPM_BASE + 0x504)
+#define RC_CENTRAL_CFG2                (SPM_BASE + 0x508)
+#define RC_CMD_ARB_CFG                 (SPM_BASE + 0x50C)
+#define RC_PMIC_RCEN_ADDR              (SPM_BASE + 0x510)
+#define RC_PMIC_RCEN_SET_CLR_ADDR      (SPM_BASE + 0x514)
+#define RC_DCXO_FPM_CFG                (SPM_BASE + 0x518)
+#define RC_CENTRAL_CFG3                (SPM_BASE + 0x51C)
+#define RC_M00_SRCLKEN_CFG             (SPM_BASE + 0x520)
+#define RC_M01_SRCLKEN_CFG             (SPM_BASE + 0x524)
+#define RC_M02_SRCLKEN_CFG             (SPM_BASE + 0x528)
+#define RC_M03_SRCLKEN_CFG             (SPM_BASE + 0x52C)
+#define RC_M04_SRCLKEN_CFG             (SPM_BASE + 0x530)
+#define RC_M05_SRCLKEN_CFG             (SPM_BASE + 0x534)
+#define RC_M06_SRCLKEN_CFG             (SPM_BASE + 0x538)
+#define RC_M07_SRCLKEN_CFG             (SPM_BASE + 0x53C)
+#define RC_M08_SRCLKEN_CFG             (SPM_BASE + 0x540)
+#define RC_M09_SRCLKEN_CFG             (SPM_BASE + 0x544)
+#define RC_M10_SRCLKEN_CFG             (SPM_BASE + 0x548)
+#define RC_M11_SRCLKEN_CFG             (SPM_BASE + 0x54C)
+#define RC_M12_SRCLKEN_CFG             (SPM_BASE + 0x550)
+#define RC_SRCLKEN_SW_CON_CFG          (SPM_BASE + 0x554)
+#define RC_CENTRAL_CFG4                (SPM_BASE + 0x558)
+#define RC_PROTOCOL_CHK_CFG            (SPM_BASE + 0x560)
+#define RC_DEBUG_CFG                   (SPM_BASE + 0x564)
+#define RC_MISC_0                      (SPM_BASE + 0x5B4)
+
+#define SUBSYS_INTF_CFG                (SPM_BASE + 0x5BC)
+#define PCM_WDT_LATCH_25               (SPM_BASE + 0x5C0)
+#define PCM_WDT_LATCH_26               (SPM_BASE + 0x5C4)
+#define PCM_WDT_LATCH_27               (SPM_BASE + 0x5C8)
+#define PCM_WDT_LATCH_28               (SPM_BASE + 0x5CC)
+#define PCM_WDT_LATCH_29               (SPM_BASE + 0x5D0)
+#define PCM_WDT_LATCH_30               (SPM_BASE + 0x5D4)
+#define PCM_WDT_LATCH_31               (SPM_BASE + 0x5D8)
+#define PCM_WDT_LATCH_32               (SPM_BASE + 0x5DC)
+#define PCM_WDT_LATCH_33               (SPM_BASE + 0x5E0)
+#define PCM_WDT_LATCH_34               (SPM_BASE + 0x5E4)
+#define PCM_WDT_LATCH_35               (SPM_BASE + 0x5EC)
+#define PCM_WDT_LATCH_36               (SPM_BASE + 0x5F0)
+#define PCM_WDT_LATCH_37               (SPM_BASE + 0x5F4)
+#define PCM_WDT_LATCH_38               (SPM_BASE + 0x5F8)
+#define PCM_WDT_LATCH_39               (SPM_BASE + 0x5FC)
+/*******Register_RSV*************************************************/
+#define SPM_SW_FLAG_0                  (SPM_BASE + 0x600)
+#define SPM_SW_DEBUG_0                 (SPM_BASE + 0x604)
+#define SPM_SW_FLAG_1                  (SPM_BASE + 0x608)
+#define SPM_SW_DEBUG_1                 (SPM_BASE + 0x60C)
+#define SPM_SW_RSV_0                   (SPM_BASE + 0x610)
+#define SPM_SW_RSV_1                   (SPM_BASE + 0x614)
+#define SPM_SW_RSV_2                   (SPM_BASE + 0x618)
+#define SPM_SW_RSV_3                   (SPM_BASE + 0x61C)
+#define SPM_SW_RSV_4                   (SPM_BASE + 0x620)
+#define SPM_SW_RSV_5                   (SPM_BASE + 0x624)
+#define SPM_SW_RSV_6                   (SPM_BASE + 0x628)
+#define SPM_SW_RSV_7                   (SPM_BASE + 0x62C)
+#define SPM_SW_RSV_8                   (SPM_BASE + 0x630)
+#define SPM_BK_WAKE_EVENT              (SPM_BASE + 0x634)
+#define SPM_BK_VTCXO_DUR               (SPM_BASE + 0x638)
+#define SPM_BK_WAKE_MISC               (SPM_BASE + 0x63C)
+#define SPM_BK_PCM_TIMER               (SPM_BASE + 0x640)
+#define ULPOSC_CON                     (SPM_BASE + 0x644)
+#define SPM_RSV_CON_0                  (SPM_BASE + 0x650)
+#define SPM_RSV_CON_1                  (SPM_BASE + 0x654)
+#define SPM_RSV_STA_0                  (SPM_BASE + 0x658)
+#define SPM_RSV_STA_1                  (SPM_BASE + 0x65C)
+#define SPM_SPARE_CON                  (SPM_BASE + 0x660)
+#define SPM_SPARE_CON_SET              (SPM_BASE + 0x664)
+#define SPM_SPARE_CON_CLR              (SPM_BASE + 0x668)
+#define SPM_CROSS_WAKE_M00_REQ         (SPM_BASE + 0x66C)
+#define SPM_CROSS_WAKE_M01_REQ         (SPM_BASE + 0x670)
+#define SPM_CROSS_WAKE_M02_REQ         (SPM_BASE + 0x674)
+#define SPM_CROSS_WAKE_M03_REQ         (SPM_BASE + 0x678)
+#define SCP_VCORE_LEVEL                (SPM_BASE + 0x67C)
+#define SC_MM_CK_SEL_CON               (SPM_BASE + 0x680)
+#define SPARE_ACK_MASK                 (SPM_BASE + 0x684)
+#define SPM_DV_CON_0                   (SPM_BASE + 0x68C)
+#define SPM_DV_CON_1                   (SPM_BASE + 0x690)
+#define SPM_DV_STA                     (SPM_BASE + 0x694)
+#define CONN_XOWCN_DEBUG_EN            (SPM_BASE + 0x698)
+#define SPM_SEMA_M0                    (SPM_BASE + 0x69C)
+#define SPM_SEMA_M1                    (SPM_BASE + 0x6A0)
+#define SPM_SEMA_M2                    (SPM_BASE + 0x6A4)
+#define SPM_SEMA_M3                    (SPM_BASE + 0x6A8)
+#define SPM_SEMA_M4                    (SPM_BASE + 0x6AC)
+#define SPM_SEMA_M5                    (SPM_BASE + 0x6B0)
+#define SPM_SEMA_M6                    (SPM_BASE + 0x6B4)
+#define SPM_SEMA_M7                    (SPM_BASE + 0x6B8)
+#define SPM2ADSP_MAILBOX               (SPM_BASE + 0x6BC)
+#define ADSP2SPM_MAILBOX               (SPM_BASE + 0x6C0)
+#define SPM_ADSP_IRQ                   (SPM_BASE + 0x6C4)
+#define SPM_MD32_IRQ                   (SPM_BASE + 0x6C8)
+#define SPM2PMCU_MAILBOX_0             (SPM_BASE + 0x6CC)
+#define SPM2PMCU_MAILBOX_1             (SPM_BASE + 0x6D0)
+#define SPM2PMCU_MAILBOX_2             (SPM_BASE + 0x6D4)
+#define SPM2PMCU_MAILBOX_3             (SPM_BASE + 0x6D8)
+#define PMCU2SPM_MAILBOX_0             (SPM_BASE + 0x6DC)
+#define PMCU2SPM_MAILBOX_1             (SPM_BASE + 0x6E0)
+#define PMCU2SPM_MAILBOX_2             (SPM_BASE + 0x6E4)
+#define PMCU2SPM_MAILBOX_3             (SPM_BASE + 0x6E8)
+#define UFS_PSRI_SW                    (SPM_BASE + 0x6EC)
+#define UFS_PSRI_SW_SET                (SPM_BASE + 0x6F0)
+#define UFS_PSRI_SW_CLR                (SPM_BASE + 0x6F4)
+#define SPM_AP_SEMA                    (SPM_BASE + 0x6F8)
+#define SPM_SPM_SEMA                   (SPM_BASE + 0x6FC)
+/*******Register_DVFS_TAB*************************************************/
+#define SPM_DVFS_CON                   (SPM_BASE + 0x700)
+#define SPM_DVFS_CON_STA               (SPM_BASE + 0x704)
+#define SPM_PMIC_SPMI_CON              (SPM_BASE + 0x708)
+#define SPM_DVFS_CMD0                  (SPM_BASE + 0x710)
+#define SPM_DVFS_CMD1                  (SPM_BASE + 0x714)
+#define SPM_DVFS_CMD2                  (SPM_BASE + 0x718)
+#define SPM_DVFS_CMD3                  (SPM_BASE + 0x71C)
+#define SPM_DVFS_CMD4                  (SPM_BASE + 0x720)
+#define SPM_DVFS_CMD5                  (SPM_BASE + 0x724)
+#define SPM_DVFS_CMD6                  (SPM_BASE + 0x728)
+#define SPM_DVFS_CMD7                  (SPM_BASE + 0x72C)
+#define SPM_DVFS_CMD8                  (SPM_BASE + 0x730)
+#define SPM_DVFS_CMD9                  (SPM_BASE + 0x734)
+#define SPM_DVFS_CMD10                 (SPM_BASE + 0x738)
+#define SPM_DVFS_CMD11                 (SPM_BASE + 0x73C)
+#define SPM_DVFS_CMD12                 (SPM_BASE + 0x740)
+#define SPM_DVFS_CMD13                 (SPM_BASE + 0x744)
+#define SPM_DVFS_CMD14                 (SPM_BASE + 0x748)
+#define SPM_DVFS_CMD15                 (SPM_BASE + 0x74C)
+#define SPM_DVFS_CMD16                 (SPM_BASE + 0x750)
+#define SPM_DVFS_CMD17                 (SPM_BASE + 0x754)
+#define SPM_DVFS_CMD18                 (SPM_BASE + 0x758)
+#define SPM_DVFS_CMD19                 (SPM_BASE + 0x75C)
+#define SPM_DVFS_CMD20                 (SPM_BASE + 0x760)
+#define SPM_DVFS_CMD21                 (SPM_BASE + 0x764)
+#define SPM_DVFS_CMD22                 (SPM_BASE + 0x768)
+#define SPM_DVFS_CMD23                 (SPM_BASE + 0x76C)
+#define SYS_TIMER_VALUE_L              (SPM_BASE + 0x770)
+#define SYS_TIMER_VALUE_H              (SPM_BASE + 0x774)
+#define SYS_TIMER_START_L              (SPM_BASE + 0x778)
+#define SYS_TIMER_START_H              (SPM_BASE + 0x77C)
+#define SYS_TIMER_LATCH_L_00           (SPM_BASE + 0x780)
+#define SYS_TIMER_LATCH_H_00           (SPM_BASE + 0x784)
+#define SYS_TIMER_LATCH_L_01           (SPM_BASE + 0x788)
+#define SYS_TIMER_LATCH_H_01           (SPM_BASE + 0x78C)
+#define SYS_TIMER_LATCH_L_02           (SPM_BASE + 0x790)
+#define SYS_TIMER_LATCH_H_02           (SPM_BASE + 0x794)
+#define SYS_TIMER_LATCH_L_03           (SPM_BASE + 0x798)
+#define SYS_TIMER_LATCH_H_03           (SPM_BASE + 0x79C)
+#define SYS_TIMER_LATCH_L_04           (SPM_BASE + 0x7A0)
+#define SYS_TIMER_LATCH_H_04           (SPM_BASE + 0x7A4)
+#define SYS_TIMER_LATCH_L_05           (SPM_BASE + 0x7A8)
+#define SYS_TIMER_LATCH_H_05           (SPM_BASE + 0x7AC)
+#define SYS_TIMER_LATCH_L_06           (SPM_BASE + 0x7B0)
+#define SYS_TIMER_LATCH_H_06           (SPM_BASE + 0x7B4)
+#define SYS_TIMER_LATCH_L_07           (SPM_BASE + 0x7B8)
+#define SYS_TIMER_LATCH_H_07           (SPM_BASE + 0x7BC)
+#define SYS_TIMER_LATCH_L_08           (SPM_BASE + 0x7C0)
+#define SYS_TIMER_LATCH_H_08           (SPM_BASE + 0x7C4)
+#define SYS_TIMER_LATCH_L_09           (SPM_BASE + 0x7C8)
+#define SYS_TIMER_LATCH_H_09           (SPM_BASE + 0x7CC)
+#define SYS_TIMER_LATCH_L_10           (SPM_BASE + 0x7D0)
+#define SYS_TIMER_LATCH_H_10           (SPM_BASE + 0x7D4)
+#define SYS_TIMER_LATCH_L_11           (SPM_BASE + 0x7D8)
+#define SYS_TIMER_LATCH_H_11           (SPM_BASE + 0x7DC)
+#define SYS_TIMER_LATCH_L_12           (SPM_BASE + 0x7E0)
+#define SYS_TIMER_LATCH_H_12           (SPM_BASE + 0x7E4)
+#define SYS_TIMER_LATCH_L_13           (SPM_BASE + 0x7E8)
+#define SYS_TIMER_LATCH_H_13           (SPM_BASE + 0x7EC)
+#define SYS_TIMER_LATCH_L_14           (SPM_BASE + 0x7F0)
+#define SYS_TIMER_LATCH_H_14           (SPM_BASE + 0x7F4)
+#define SYS_TIMER_LATCH_L_15           (SPM_BASE + 0x7F8)
+#define SYS_TIMER_LATCH_H_15           (SPM_BASE + 0x7FC)
+/*******Register_LAT_STA*************************************************/
+#define PCM_WDT_LATCH_0                (SPM_BASE + 0x800)
+#define PCM_WDT_LATCH_1                (SPM_BASE + 0x804)
+#define PCM_WDT_LATCH_2                (SPM_BASE + 0x808)
+#define PCM_WDT_LATCH_3                (SPM_BASE + 0x80C)
+#define PCM_WDT_LATCH_4                (SPM_BASE + 0x810)
+#define PCM_WDT_LATCH_5                (SPM_BASE + 0x814)
+#define PCM_WDT_LATCH_6                (SPM_BASE + 0x818)
+#define PCM_WDT_LATCH_7                (SPM_BASE + 0x81C)
+#define PCM_WDT_LATCH_8                (SPM_BASE + 0x820)
+#define PCM_WDT_LATCH_9                (SPM_BASE + 0x824)
+#define PCM_WDT_LATCH_10               (SPM_BASE + 0x828)
+#define PCM_WDT_LATCH_11               (SPM_BASE + 0x82C)
+#define PCM_WDT_LATCH_12               (SPM_BASE + 0x830)
+#define PCM_WDT_LATCH_13               (SPM_BASE + 0x834)
+#define PCM_WDT_LATCH_14               (SPM_BASE + 0x838)
+#define PCM_WDT_LATCH_15               (SPM_BASE + 0x83C)
+#define PCM_WDT_LATCH_16               (SPM_BASE + 0x840)
+#define PCM_WDT_LATCH_17               (SPM_BASE + 0x844)
+#define PCM_WDT_LATCH_18               (SPM_BASE + 0x848)
+#define PCM_WDT_LATCH_SPARE_0          (SPM_BASE + 0x84C)
+#define PCM_WDT_LATCH_SPARE_1          (SPM_BASE + 0x850)
+#define PCM_WDT_LATCH_SPARE_2          (SPM_BASE + 0x854)
+#define PCM_WDT_LATCH_CONN_0           (SPM_BASE + 0x870)
+#define PCM_WDT_LATCH_CONN_1           (SPM_BASE + 0x874)
+#define PCM_WDT_LATCH_CONN_2           (SPM_BASE + 0x878)
+#define DRAMC_GATING_ERR_LATCH_CH0_0   (SPM_BASE + 0x8A0)
+#define DRAMC_GATING_ERR_LATCH_CH0_1   (SPM_BASE + 0x8A4)
+#define DRAMC_GATING_ERR_LATCH_CH0_2   (SPM_BASE + 0x8A8)
+#define DRAMC_GATING_ERR_LATCH_CH0_3   (SPM_BASE + 0x8AC)
+#define DRAMC_GATING_ERR_LATCH_CH0_4   (SPM_BASE + 0x8B0)
+#define DRAMC_GATING_ERR_LATCH_CH0_5   (SPM_BASE + 0x8B4)
+#define DRAMC_GATING_ERR_LATCH_CH0_6   (SPM_BASE + 0x8B8)
+#define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4)
+/*******Register_SPM_ACK_CHK*************************************************/
+#define SPM_ACK_CHK_CON_0              (SPM_BASE + 0x900)
+#define SPM_ACK_CHK_PC_0               (SPM_BASE + 0x904)
+#define SPM_ACK_CHK_SEL_0              (SPM_BASE + 0x908)
+#define SPM_ACK_CHK_TIMER_0            (SPM_BASE + 0x90C)
+#define SPM_ACK_CHK_STA_0              (SPM_BASE + 0x910)
+#define SPM_ACK_CHK_SWINT_0            (SPM_BASE + 0x914)
+#define SPM_ACK_CHK_CON_1              (SPM_BASE + 0x920)
+#define SPM_ACK_CHK_PC_1               (SPM_BASE + 0x924)
+#define SPM_ACK_CHK_SEL_1              (SPM_BASE + 0x928)
+#define SPM_ACK_CHK_TIMER_1            (SPM_BASE + 0x92C)
+#define SPM_ACK_CHK_STA_1              (SPM_BASE + 0x930)
+#define SPM_ACK_CHK_SWINT_1            (SPM_BASE + 0x934)
+#define SPM_ACK_CHK_CON_2              (SPM_BASE + 0x940)
+#define SPM_ACK_CHK_PC_2               (SPM_BASE + 0x944)
+#define SPM_ACK_CHK_SEL_2              (SPM_BASE + 0x948)
+#define SPM_ACK_CHK_TIMER_2            (SPM_BASE + 0x94C)
+#define SPM_ACK_CHK_STA_2              (SPM_BASE + 0x950)
+#define SPM_ACK_CHK_SWINT_2            (SPM_BASE + 0x954)
+#define SPM_ACK_CHK_CON_3              (SPM_BASE + 0x960)
+#define SPM_ACK_CHK_PC_3               (SPM_BASE + 0x964)
+#define SPM_ACK_CHK_SEL_3              (SPM_BASE + 0x968)
+#define SPM_ACK_CHK_TIMER_3            (SPM_BASE + 0x96C)
+#define SPM_ACK_CHK_STA_3              (SPM_BASE + 0x970)
+#define SPM_ACK_CHK_SWINT_3            (SPM_BASE + 0x974)
+#define SPM_COUNTER_0                  (SPM_BASE + 0x978)
+#define SPM_COUNTER_1                  (SPM_BASE + 0x97C)
+#define SPM_COUNTER_2                  (SPM_BASE + 0x980)
+#define SYS_TIMER_CON                  (SPM_BASE + 0x98C)
+#define SPM_TWAM_CON                   (SPM_BASE + 0x990)
+#define SPM_TWAM_WINDOW_LEN            (SPM_BASE + 0x994)
+#define SPM_TWAM_IDLE_SEL              (SPM_BASE + 0x998)
+#define SPM_TWAM_EVENT_CLEAR           (SPM_BASE + 0x99C)
+/*******The OTHERS*************************************************/
+#define RC_FSM_STA_0                   (SPM_BASE + 0xE00)
+#define RC_CMD_STA_0                   (SPM_BASE + 0xE04)
+#define RC_CMD_STA_1                   (SPM_BASE + 0xE08)
+#define RC_SPI_STA_0                   (SPM_BASE + 0xE0C)
+#define RC_PI_PO_STA_0                 (SPM_BASE + 0xE10)
+#define RC_M00_REQ_STA_0               (SPM_BASE + 0xE14)
+#define RC_M01_REQ_STA_0               (SPM_BASE + 0xE1C)
+#define RC_M02_REQ_STA_0               (SPM_BASE + 0xE20)
+#define RC_M03_REQ_STA_0               (SPM_BASE + 0xE24)
+#define RC_M04_REQ_STA_0               (SPM_BASE + 0xE28)
+#define RC_M05_REQ_STA_0               (SPM_BASE + 0xE2C)
+#define RC_M06_REQ_STA_0               (SPM_BASE + 0xE30)
+#define RC_M07_REQ_STA_0               (SPM_BASE + 0xE34)
+#define RC_M08_REQ_STA_0               (SPM_BASE + 0xE38)
+#define RC_M09_REQ_STA_0               (SPM_BASE + 0xE3C)
+#define RC_M10_REQ_STA_0               (SPM_BASE + 0xE40)
+#define RC_M11_REQ_STA_0               (SPM_BASE + 0xE44)
+#define RC_M12_REQ_STA_0               (SPM_BASE + 0xE48)
+#define RC_DEBUG_STA_0                 (SPM_BASE + 0xE4C)
+#define RC_DEBUG_TRACE_0_LSB           (SPM_BASE + 0xE50)
+#define RC_DEBUG_TRACE_0_MSB           (SPM_BASE + 0xE54)
+#define RC_DEBUG_TRACE_1_LSB           (SPM_BASE + 0xE5C)
+#define RC_DEBUG_TRACE_1_MSB           (SPM_BASE + 0xE60)
+#define RC_DEBUG_TRACE_2_LSB           (SPM_BASE + 0xE64)
+#define RC_DEBUG_TRACE_2_MSB           (SPM_BASE + 0xE6C)
+#define RC_DEBUG_TRACE_3_LSB           (SPM_BASE + 0xE70)
+#define RC_DEBUG_TRACE_3_MSB           (SPM_BASE + 0xE74)
+#define RC_DEBUG_TRACE_4_LSB           (SPM_BASE + 0xE78)
+#define RC_DEBUG_TRACE_4_MSB           (SPM_BASE + 0xE7C)
+#define RC_DEBUG_TRACE_5_LSB           (SPM_BASE + 0xE80)
+#define RC_DEBUG_TRACE_5_MSB           (SPM_BASE + 0xE84)
+#define RC_DEBUG_TRACE_6_LSB           (SPM_BASE + 0xE88)
+#define RC_DEBUG_TRACE_6_MSB           (SPM_BASE + 0xE8C)
+#define RC_DEBUG_TRACE_7_LSB           (SPM_BASE + 0xE90)
+#define RC_DEBUG_TRACE_7_MSB           (SPM_BASE + 0xE94)
+#define RC_SYS_TIMER_LATCH_0_LSB       (SPM_BASE + 0xE98)
+#define RC_SYS_TIMER_LATCH_0_MSB       (SPM_BASE + 0xE9C)
+#define RC_SYS_TIMER_LATCH_1_LSB       (SPM_BASE + 0xEA0)
+#define RC_SYS_TIMER_LATCH_1_MSB       (SPM_BASE + 0xEA4)
+#define RC_SYS_TIMER_LATCH_2_LSB       (SPM_BASE + 0xEA8)
+#define RC_SYS_TIMER_LATCH_2_MSB       (SPM_BASE + 0xEAC)
+#define RC_SYS_TIMER_LATCH_3_LSB       (SPM_BASE + 0xEB0)
+#define RC_SYS_TIMER_LATCH_3_MSB       (SPM_BASE + 0xEB4)
+#define RC_SYS_TIMER_LATCH_4_LSB       (SPM_BASE + 0xEB8)
+#define RC_SYS_TIMER_LATCH_4_MSB       (SPM_BASE + 0xEBC)
+#define RC_SYS_TIMER_LATCH_5_LSB       (SPM_BASE + 0xEC0)
+#define RC_SYS_TIMER_LATCH_5_MSB       (SPM_BASE + 0xEC4)
+#define RC_SYS_TIMER_LATCH_6_LSB       (SPM_BASE + 0xEC8)
+#define RC_SYS_TIMER_LATCH_6_MSB       (SPM_BASE + 0xECC)
+#define RC_SYS_TIMER_LATCH_7_LSB       (SPM_BASE + 0xED0)
+#define RC_SYS_TIMER_LATCH_7_MSB       (SPM_BASE + 0xED4)
+#define PCM_WDT_LATCH_19               (SPM_BASE + 0xED8)
+#define PCM_WDT_LATCH_20               (SPM_BASE + 0xEDC)
+#define PCM_WDT_LATCH_21               (SPM_BASE + 0xEE0)
+#define PCM_WDT_LATCH_22               (SPM_BASE + 0xEE4)
+#define PCM_WDT_LATCH_23               (SPM_BASE + 0xEE8)
+#define PCM_WDT_LATCH_24               (SPM_BASE + 0xEEC)
+/*******Register_PMSR*************************************************/
+#define PMSR_LAST_DAT                  (SPM_BASE + 0xF00)
+#define PMSR_LAST_CNT                  (SPM_BASE + 0xF04)
+#define PMSR_LAST_ACK                  (SPM_BASE + 0xF08)
+#define SPM_PMSR_SEL_CON0              (SPM_BASE + 0xF10)
+#define SPM_PMSR_SEL_CON1              (SPM_BASE + 0xF14)
+#define SPM_PMSR_SEL_CON2              (SPM_BASE + 0xF18)
+#define SPM_PMSR_SEL_CON3              (SPM_BASE + 0xF1C)
+#define SPM_PMSR_SEL_CON4              (SPM_BASE + 0xF20)
+#define SPM_PMSR_SEL_CON5              (SPM_BASE + 0xF24)
+#define SPM_PMSR_SEL_CON6              (SPM_BASE + 0xF28)
+#define SPM_PMSR_SEL_CON7              (SPM_BASE + 0xF2C)
+#define SPM_PMSR_SEL_CON8              (SPM_BASE + 0xF30)
+#define SPM_PMSR_SEL_CON9              (SPM_BASE + 0xF34)
+#define SPM_PMSR_SEL_CON10             (SPM_BASE + 0xF3C)
+#define SPM_PMSR_SEL_CON11             (SPM_BASE + 0xF40)
+#define SPM_PMSR_TIEMR_STA0            (SPM_BASE + 0xFB8)
+#define SPM_PMSR_TIEMR_STA1            (SPM_BASE + 0xFBC)
+#define SPM_PMSR_TIEMR_STA2            (SPM_BASE + 0xFC0)
+#define SPM_PMSR_GENERAL_CON0          (SPM_BASE + 0xFC4)
+#define SPM_PMSR_GENERAL_CON1          (SPM_BASE + 0xFC8)
+#define SPM_PMSR_GENERAL_CON2          (SPM_BASE + 0xFCC)
+#define SPM_PMSR_GENERAL_CON3          (SPM_BASE + 0xFD0)
+#define SPM_PMSR_GENERAL_CON4          (SPM_BASE + 0xFD4)
+#define SPM_PMSR_GENERAL_CON5          (SPM_BASE + 0xFD8)
+#define SPM_PMSR_SW_RESET              (SPM_BASE + 0xFDC)
+#define SPM_PMSR_MON_CON0              (SPM_BASE + 0xFE0)
+#define SPM_PMSR_MON_CON1              (SPM_BASE + 0xFE4)
+#define SPM_PMSR_MON_CON2              (SPM_BASE + 0xFE8)
+#define SPM_PMSR_LEN_CON0              (SPM_BASE + 0xFEC)
+#define SPM_PMSR_LEN_CON1              (SPM_BASE + 0xFF0)
+#define SPM_PMSR_LEN_CON2              (SPM_BASE + 0xFF4)
+/*******Register End*************************************************/
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB                      (1U << 0)       /* 1b */
+#define PROJECT_CODE_LSB                    (1U << 16)      /* 16b */
+/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
+#define POWER_ON_VAL0_LSB                   (1U << 0)       /* 32b */
+/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
+#define POWER_ON_VAL1_LSB                   (1U << 0)       /* 32b */
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define REG_SRCCLKEN0_CTL_LSB               (1U << 0)       /* 2b */
+#define REG_SRCCLKEN1_CTL_LSB               (1U << 2)       /* 2b */
+#define SYS_SETTLE_SEL_LSB                  (1U << 4)       /* 1b */
+#define REG_SPM_LOCK_INFRA_DCM_LSB          (1U << 5)       /* 1b */
+#define REG_SRCCLKEN_MASK_LSB               (1U << 6)       /* 3b */
+#define REG_MD1_C32RM_EN_LSB                (1U << 9)       /* 1b */
+#define REG_MD2_C32RM_EN_LSB                (1U << 10)      /* 1b */
+#define REG_CLKSQ0_SEL_CTRL_LSB             (1U << 11)      /* 1b */
+#define REG_CLKSQ1_SEL_CTRL_LSB             (1U << 12)      /* 1b */
+#define REG_SRCCLKEN0_EN_LSB                (1U << 13)      /* 1b */
+#define REG_SRCCLKEN1_EN_LSB                (1U << 14)      /* 1b */
+#define SCP_DCM_EN_LSB                      (1U << 15)      /* 1b */
+#define REG_SYSCLK0_SRC_MASK_B_LSB          (1U << 16)      /* 8b */
+#define REG_SYSCLK1_SRC_MASK_B_LSB          (1U << 24)      /* 8b */
+/* SPM_CLK_SETTLE (0x10006000+0x010) */
+#define SYSCLK_SETTLE_LSB                   (1U << 0)       /* 28b */
+/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
+#define REG_WFI_OP_LSB                      (1U << 0)       /* 1b */
+#define REG_WFI_TYPE_LSB                    (1U << 1)       /* 1b */
+#define REG_MP0_CPUTOP_IDLE_MASK_LSB        (1U << 2)       /* 1b */
+#define REG_MP1_CPUTOP_IDLE_MASK_LSB        (1U << 3)       /* 1b */
+#define REG_MCUSYS_IDLE_MASK_LSB            (1U << 4)       /* 1b */
+#define REG_MD_APSRC_1_SEL_LSB              (1U << 25)      /* 1b */
+#define REG_MD_APSRC_0_SEL_LSB              (1U << 26)      /* 1b */
+#define REG_CONN_APSRC_SEL_LSB              (1U << 29)      /* 1b */
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_CK_EN_LSB                       (1U << 2)       /* 1b */
+#define RG_EN_IM_SLEEP_DVS_LSB              (1U << 3)       /* 1b */
+#define PCM_CK_FROM_CKSYS_LSB               (1U << 4)       /* 1b */
+#define PCM_SW_RESET_LSB                    (1U << 15)      /* 1b */
+#define PCM_CON0_PROJECT_CODE_LSB           (1U << 16)      /* 16b */
+/* PCM_CON1 (0x10006000+0x01C) */
+#define RG_IM_SLAVE_LSB                     (1U << 0)       /* 1b */
+#define RG_IM_SLEEP_LSB                     (1U << 1)       /* 1b */
+#define REG_SPM_SRAM_CTRL_MUX_LSB           (1U << 2)       /* 1b */
+#define RG_AHBMIF_APBEN_LSB                 (1U << 3)       /* 1b */
+#define RG_IM_PDN_LSB                       (1U << 4)       /* 1b */
+#define RG_PCM_TIMER_EN_LSB                 (1U << 5)       /* 1b */
+#define SPM_EVENT_COUNTER_CLR_LSB           (1U << 6)       /* 1b */
+#define RG_DIS_MIF_PROT_LSB                 (1U << 7)       /* 1b */
+#define RG_PCM_WDT_EN_LSB                   (1U << 8)       /* 1b */
+#define RG_PCM_WDT_WAKE_LSB                 (1U << 9)       /* 1b */
+#define REG_SPM_SRAM_SLEEP_B_LSB            (1U << 10)      /* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB           (1U << 11)      /* 1b */
+#define REG_EVENT_LOCK_EN_LSB               (1U << 12)      /* 1b */
+#define REG_SRCCLKEN_FAST_RESP_LSB          (1U << 13)      /* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB        (1U << 14)      /* 1b */
+#define RG_PCM_IRQ_MSK_LSB                  (1U << 15)      /* 1b */
+#define PCM_CON1_PROJECT_CODE_LSB           (1U << 16)      /* 16b */
+/* SPM_POWER_ON_VAL2 (0x10006000+0x020) */
+#define POWER_ON_VAL2_LSB                   (1U << 0)       /* 32b */
+/* SPM_POWER_ON_VAL3 (0x10006000+0x024) */
+#define POWER_ON_VAL3_LSB                   (1U << 0)       /* 32b */
+/* PCM_REG_DATA_INI (0x10006000+0x028) */
+#define PCM_REG_DATA_INI_LSB                (1U << 0)       /* 32b */
+/* PCM_PWR_IO_EN (0x10006000+0x02C) */
+#define PCM_PWR_IO_EN_LSB                   (1U << 0)       /* 8b */
+#define RG_RF_SYNC_EN_LSB                   (1U << 16)      /* 8b */
+/* PCM_TIMER_VAL (0x10006000+0x030) */
+#define REG_PCM_TIMER_VAL_LSB               (1U << 0)       /* 32b */
+/* PCM_WDT_VAL (0x10006000+0x034) */
+#define RG_PCM_WDT_VAL_LSB                  (1U << 0)       /* 32b */
+/* SPM_SW_RST_CON (0x10006000+0x040) */
+#define SPM_SW_RST_CON_LSB                  (1U << 0)       /* 16b */
+#define SPM_SW_RST_CON_PROJECT_CODE_LSB     (1U << 16)      /* 16b */
+/* SPM_SW_RST_CON_SET (0x10006000+0x044) */
+#define SPM_SW_RST_CON_SET_LSB              (1U << 0)       /* 16b */
+#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16)      /* 16b */
+/* SPM_SW_RST_CON_CLR (0x10006000+0x048) */
+#define SPM_SW_RST_CON_CLR_LSB              (1U << 0)       /* 16b */
+#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16)      /* 16b */
+/* VS1_PSR_MASK_B (0x10006000+0x04C) */
+#define VS1_OPP0_PSR_MASK_B_LSB             (1U << 0)       /* 8b */
+#define VS1_OPP1_PSR_MASK_B_LSB             (1U << 8)       /* 8b */
+/* VS2_PSR_MASK_B (0x10006000+0x050) */
+#define VS2_OPP0_PSR_MASK_B_LSB             (1U << 0)       /* 8b */
+#define VS2_OPP1_PSR_MASK_B_LSB             (1U << 8)       /* 8b */
+#define VS2_OPP2_PSR_MASK_B_LSB             (1U << 16)      /* 8b */
+/* MD32_CLK_CON (0x10006000+0x084) */
+#define REG_MD32_26M_CK_SEL_LSB             (1U << 0)       /* 1b */
+#define REG_MD32_DCM_EN_LSB                 (1U << 1)       /* 1b */
+/* SPM_SRAM_RSV_CON (0x10006000+0x088) */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB         (1U << 0)       /* 1b */
+/* SPM_SWINT (0x10006000+0x08C) */
+#define SPM_SWINT_LSB                       (1U << 0)       /* 32b */
+/* SPM_SWINT_SET (0x10006000+0x090) */
+#define SPM_SWINT_SET_LSB                   (1U << 0)       /* 32b */
+/* SPM_SWINT_CLR (0x10006000+0x094) */
+#define SPM_SWINT_CLR_LSB                   (1U << 0)       /* 32b */
+/* SPM_SCP_MAILBOX (0x10006000+0x098) */
+#define SPM_SCP_MAILBOX_LSB                 (1U << 0)       /* 32b */
+/* SCP_SPM_MAILBOX (0x10006000+0x09C) */
+#define SCP_SPM_MAILBOX_LSB                 (1U << 0)       /* 32b */
+/* SPM_TWAM_CON (0x10006000+0x0A0) */
+#define REG_TWAM_ENABLE_LSB                 (1U << 0)       /* 1b */
+#define REG_TWAM_SPEED_MODE_EN_LSB          (1U << 1)       /* 1b */
+#define REG_TWAM_SW_RST_LSB                 (1U << 2)       /* 1b */
+#define REG_TWAM_IRQ_MASK_LSB               (1U << 3)       /* 1b */
+#define REG_TWAM_MON_TYPE_0_LSB             (1U << 4)       /* 2b */
+#define REG_TWAM_MON_TYPE_1_LSB             (1U << 6)       /* 2b */
+#define REG_TWAM_MON_TYPE_2_LSB             (1U << 8)       /* 2b */
+#define REG_TWAM_MON_TYPE_3_LSB             (1U << 10)      /* 2b */
+/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */
+#define REG_TWAM_WINDOW_LEN_LSB             (1U << 0)       /* 32b */
+/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */
+#define REG_TWAM_SIG_SEL_0_LSB              (1U << 0)       /* 7b */
+#define REG_TWAM_SIG_SEL_1_LSB              (1U << 8)       /* 7b */
+#define REG_TWAM_SIG_SEL_2_LSB              (1U << 16)      /* 7b */
+#define REG_TWAM_SIG_SEL_3_LSB              (1U << 24)      /* 7b */
+/* SPM_SCP_IRQ (0x10006000+0x0AC) */
+#define SC_SPM2SCP_WAKEUP_LSB               (1U << 0)       /* 1b */
+#define SC_SCP2SPM_WAKEUP_LSB               (1U << 4)       /* 1b */
+/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
+#define REG_CPU_WAKEUP_LSB                  (1U << 0)       /* 1b */
+/* SPM_IRQ_MASK (0x10006000+0x0B4) */
+#define REG_SPM_IRQ_MASK_LSB                (1U << 0)       /* 32b */
+/* DDR_EN_DBC (0x10006000+0x0B4) */
+#define REG_ALL_DDR_EN_DBC_EN_LSB           (1U << 16)       /* 1b */
+/* SPM_SRC_REQ (0x10006000+0x0B8) */
+#define REG_SPM_APSRC_REQ_LSB               (1U << 0)       /* 1b */
+#define REG_SPM_F26M_REQ_LSB                (1U << 1)       /* 1b */
+#define REG_SPM_INFRA_REQ_LSB               (1U << 3)       /* 1b */
+#define REG_SPM_VRF18_REQ_LSB               (1U << 4)       /* 1b */
+#define REG_SPM_DDR_EN_REQ_LSB              (1U << 7)       /* 1b */
+#define REG_SPM_DVFS_REQ_LSB                (1U << 8)       /* 1b */
+#define REG_SPM_SW_MAILBOX_REQ_LSB          (1U << 9)       /* 1b */
+#define REG_SPM_SSPM_MAILBOX_REQ_LSB        (1U << 10)      /* 1b */
+#define REG_SPM_ADSP_MAILBOX_REQ_LSB        (1U << 11)      /* 1b */
+#define REG_SPM_SCP_MAILBOX_REQ_LSB         (1U << 12)      /* 1b */
+/* SPM_SRC_MASK (0x10006000+0x0BC) */
+#define REG_MD_SRCCLKENA_0_MASK_B_LSB       (1U << 0)       /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1)       /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2)       /* 1b */
+#define REG_MD_APSRC_REQ_0_MASK_B_LSB       (1U << 3)       /* 1b */
+#define REG_MD_VRF18_REQ_0_MASK_B_LSB       (1U << 4)       /* 1b */
+#define REG_MD_DDR_EN_0_MASK_B_LSB          (1U << 5)       /* 1b */
+#define REG_MD_SRCCLKENA_1_MASK_B_LSB       (1U << 6)       /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7)       /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8)       /* 1b */
+#define REG_MD_APSRC_REQ_1_MASK_B_LSB       (1U << 9)       /* 1b */
+#define REG_MD_VRF18_REQ_1_MASK_B_LSB       (1U << 10)      /* 1b */
+#define REG_MD_DDR_EN_1_MASK_B_LSB          (1U << 11)      /* 1b */
+#define REG_CONN_SRCCLKENA_MASK_B_LSB       (1U << 12)      /* 1b */
+#define REG_CONN_SRCCLKENB_MASK_B_LSB       (1U << 13)      /* 1b */
+#define REG_CONN_INFRA_REQ_MASK_B_LSB       (1U << 14)      /* 1b */
+#define REG_CONN_APSRC_REQ_MASK_B_LSB       (1U << 15)      /* 1b */
+#define REG_CONN_VRF18_REQ_MASK_B_LSB       (1U << 16)      /* 1b */
+#define REG_CONN_DDR_EN_MASK_B_LSB          (1U << 17)      /* 1b */
+#define REG_CONN_VFE28_MASK_B_LSB           (1U << 18)      /* 1b */
+#define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19)      /* 1b */
+#define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20)      /* 1b */
+#define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21)      /* 1b */
+#define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22)      /* 1b */
+#define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23)      /* 1b */
+#define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24)      /* 1b */
+#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB   (1U << 25)      /* 1b */
+#define REG_INFRASYS_DDR_EN_MASK_B_LSB      (1U << 26)      /* 1b */
+#define REG_MD32_SRCCLKENA_MASK_B_LSB       (1U << 27)      /* 1b */
+#define REG_MD32_INFRA_REQ_MASK_B_LSB       (1U << 28)      /* 1b */
+#define REG_MD32_APSRC_REQ_MASK_B_LSB       (1U << 29)      /* 1b */
+#define REG_MD32_VRF18_REQ_MASK_B_LSB       (1U << 30)      /* 1b */
+#define REG_MD32_DDR_EN_MASK_B_LSB          (1U << 31)      /* 1b */
+/* SPM_SRC2_MASK (0x10006000+0x0C0) */
+#define REG_SCP_SRCCLKENA_MASK_B_LSB        (1U << 0)       /* 1b */
+#define REG_SCP_INFRA_REQ_MASK_B_LSB        (1U << 1)       /* 1b */
+#define REG_SCP_APSRC_REQ_MASK_B_LSB        (1U << 2)       /* 1b */
+#define REG_SCP_VRF18_REQ_MASK_B_LSB        (1U << 3)       /* 1b */
+#define REG_SCP_DDR_EN_MASK_B_LSB           (1U << 4)       /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB  (1U << 5)       /* 1b */
+#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB  (1U << 6)       /* 1b */
+#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB  (1U << 7)       /* 1b */
+#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB  (1U << 8)       /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB     (1U << 9)       /* 1b */
+#define REG_UFS_SRCCLKENA_MASK_B_LSB        (1U << 10)      /* 1b */
+#define REG_UFS_INFRA_REQ_MASK_B_LSB        (1U << 11)      /* 1b */
+#define REG_UFS_APSRC_REQ_MASK_B_LSB        (1U << 12)      /* 1b */
+#define REG_UFS_VRF18_REQ_MASK_B_LSB        (1U << 13)      /* 1b */
+#define REG_UFS_DDR_EN_MASK_B_LSB           (1U << 14)      /* 1b */
+#define REG_DISP0_APSRC_REQ_MASK_B_LSB      (1U << 15)      /* 1b */
+#define REG_DISP0_DDR_EN_MASK_B_LSB         (1U << 16)      /* 1b */
+#define REG_DISP1_APSRC_REQ_MASK_B_LSB      (1U << 17)      /* 1b */
+#define REG_DISP1_DDR_EN_MASK_B_LSB         (1U << 18)      /* 1b */
+#define REG_GCE_INFRA_REQ_MASK_B_LSB        (1U << 19)      /* 1b */
+#define REG_GCE_APSRC_REQ_MASK_B_LSB        (1U << 20)      /* 1b */
+#define REG_GCE_VRF18_REQ_MASK_B_LSB        (1U << 21)      /* 1b */
+#define REG_GCE_DDR_EN_MASK_B_LSB           (1U << 22)      /* 1b */
+#define REG_APU_SRCCLKENA_MASK_B_LSB        (1U << 23)      /* 1b */
+#define REG_APU_INFRA_REQ_MASK_B_LSB        (1U << 24)      /* 1b */
+#define REG_APU_APSRC_REQ_MASK_B_LSB        (1U << 25)      /* 1b */
+#define REG_APU_VRF18_REQ_MASK_B_LSB        (1U << 26)      /* 1b */
+#define REG_APU_DDR_EN_MASK_B_LSB           (1U << 27)      /* 1b */
+#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB   (1U << 28)      /* 1b */
+#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB   (1U << 29)      /* 1b */
+#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB   (1U << 30)      /* 1b */
+#define REG_CG_CHECK_DDR_EN_MASK_B_LSB      (1U << 31)      /* 1b */
+/* SPM_SRC3_MASK (0x10006000+0x0C4) */
+#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0)       /* 1b */
+#define REG_SW2SPM_INT0_MASK_B_LSB          (1U << 1)       /* 1b */
+#define REG_SW2SPM_INT1_MASK_B_LSB          (1U << 2)       /* 1b */
+#define REG_SW2SPM_INT2_MASK_B_LSB          (1U << 3)       /* 1b */
+#define REG_SW2SPM_INT3_MASK_B_LSB          (1U << 4)       /* 1b */
+#define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB   (1U << 5)       /* 1b */
+#define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB   (1U << 6)       /* 4b */
+#define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB    (1U << 10)      /* 1b */
+#define REG_CSYSPWRREQ_MASK_LSB             (1U << 11)      /* 1b */
+#define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12)      /* 1b */
+#define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13)      /* 1b */
+#define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14)      /* 1b */
+#define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15)      /* 1b */
+#define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB  (1U << 16)      /* 1b */
+#define REG_MCUPM_SRCCLKENA_MASK_B_LSB      (1U << 17)      /* 1b */
+#define REG_MCUPM_INFRA_REQ_MASK_B_LSB      (1U << 18)      /* 1b */
+#define REG_MCUPM_APSRC_REQ_MASK_B_LSB      (1U << 19)      /* 1b */
+#define REG_MCUPM_VRF18_REQ_MASK_B_LSB      (1U << 20)      /* 1b */
+#define REG_MCUPM_DDR_EN_MASK_B_LSB         (1U << 21)      /* 1b */
+#define REG_MSDC0_SRCCLKENA_MASK_B_LSB      (1U << 22)      /* 1b */
+#define REG_MSDC0_INFRA_REQ_MASK_B_LSB      (1U << 23)      /* 1b */
+#define REG_MSDC0_APSRC_REQ_MASK_B_LSB      (1U << 24)      /* 1b */
+#define REG_MSDC0_VRF18_REQ_MASK_B_LSB      (1U << 25)      /* 1b */
+#define REG_MSDC0_DDR_EN_MASK_B_LSB         (1U << 26)      /* 1b */
+#define REG_MSDC1_SRCCLKENA_MASK_B_LSB      (1U << 27)      /* 1b */
+#define REG_MSDC1_INFRA_REQ_MASK_B_LSB      (1U << 28)      /* 1b */
+#define REG_MSDC1_APSRC_REQ_MASK_B_LSB      (1U << 29)      /* 1b */
+#define REG_MSDC1_VRF18_REQ_MASK_B_LSB      (1U << 30)      /* 1b */
+#define REG_MSDC1_DDR_EN_MASK_B_LSB         (1U << 31)      /* 1b */
+/* SPM_SRC4_MASK (0x10006000+0x0C8) */
+#define CCIF_EVENT_MASK_B_LSB               (1U << 0)       /* 16b */
+#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB   (1U << 16)      /* 1b */
+#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB   (1U << 17)      /* 1b */
+#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB   (1U << 18)      /* 1b */
+#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB   (1U << 19)      /* 1b */
+#define REG_BAK_PSRI_DDR_EN_MASK_B_LSB      (1U << 20)      /* 1b */
+#define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21)      /* 1b */
+#define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22)      /* 1b */
+#define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23)      /* 1b */
+#define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24)      /* 1b */
+#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25)      /* 1b */
+#define REG_DRAMC0_MD32_WAKEUP_MASK_LSB     (1U << 26)      /* 1b */
+#define REG_DRAMC1_MD32_WAKEUP_MASK_LSB     (1U << 27)      /* 1b */
+/* SPM_SRC5_MASK (0x10006000+0x0CC) */
+#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0)       /* 9b */
+#define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB  (1U << 9)       /* 9b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
+#define REG_WAKEUP_EVENT_MASK_LSB           (1U << 0)       /* 32b */
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */
+#define REG_EXT_WAKEUP_EVENT_MASK_LSB       (1U << 0)       /* 32b */
+/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */
+#define SPM_TWAM_EVENT_CLEAR_LSB            (1U << 0)       /* 1b */
+/* SCP_CLK_CON (0x10006000+0x0DC) */
+#define REG_SCP_26M_CK_SEL_LSB              (1U << 0)       /* 1b */
+#define REG_SCP_DCM_EN_LSB                  (1U << 1)       /* 1b */
+#define SCP_SECURE_V_REQ_MASK_LSB           (1U << 2)       /* 1b */
+#define SCP_SLP_REQ_LSB                     (1U << 3)       /* 1b */
+#define SCP_SLP_ACK_LSB                     (1U << 4)       /* 1b */
+/* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */
+#define REG_MD_SRCCLKENA_ACK_0_MASK_LSB     (1U << 0)       /* 1b */
+#define REG_MD_INFRA_ACK_0_MASK_LSB         (1U << 1)       /* 1b */
+#define REG_MD_APSRC_ACK_0_MASK_LSB         (1U << 2)       /* 1b */
+#define REG_MD_VRF18_ACK_0_MASK_LSB         (1U << 3)       /* 1b */
+#define REG_MD_DDR_EN_ACK_0_MASK_LSB        (1U << 4)       /* 1b */
+#define REG_MD_SRCCLKENA_ACK_1_MASK_LSB     (1U << 5)       /* 1b */
+#define REG_MD_INFRA_ACK_1_MASK_LSB         (1U << 6)       /* 1b */
+#define REG_MD_APSRC_ACK_1_MASK_LSB         (1U << 7)       /* 1b */
+#define REG_MD_VRF18_ACK_1_MASK_LSB         (1U << 8)       /* 1b */
+#define REG_MD_DDR_EN_ACK_1_MASK_LSB        (1U << 9)       /* 1b */
+#define REG_CONN_SRCCLKENA_ACK_MASK_LSB     (1U << 10)      /* 1b */
+#define REG_CONN_INFRA_ACK_MASK_LSB         (1U << 11)      /* 1b */
+#define REG_CONN_APSRC_ACK_MASK_LSB         (1U << 12)      /* 1b */
+#define REG_CONN_VRF18_ACK_MASK_LSB         (1U << 13)      /* 1b */
+#define REG_CONN_DDR_EN_ACK_MASK_LSB        (1U << 14)      /* 1b */
+#define REG_MD32_SRCCLKENA_ACK_MASK_LSB     (1U << 15)      /* 1b */
+#define REG_MD32_INFRA_ACK_MASK_LSB         (1U << 16)      /* 1b */
+#define REG_MD32_APSRC_ACK_MASK_LSB         (1U << 17)      /* 1b */
+#define REG_MD32_VRF18_ACK_MASK_LSB         (1U << 18)      /* 1b */
+#define REG_MD32_DDR_EN_ACK_MASK_LSB        (1U << 19)      /* 1b */
+#define REG_SCP_SRCCLKENA_ACK_MASK_LSB      (1U << 20)      /* 1b */
+#define REG_SCP_INFRA_ACK_MASK_LSB          (1U << 21)      /* 1b */
+#define REG_SCP_APSRC_ACK_MASK_LSB          (1U << 22)      /* 1b */
+#define REG_SCP_VRF18_ACK_MASK_LSB          (1U << 23)      /* 1b */
+#define REG_SCP_DDR_EN_ACK_MASK_LSB         (1U << 24)      /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25)      /* 1b */
+#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB    (1U << 26)      /* 1b */
+#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB    (1U << 27)      /* 1b */
+#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB    (1U << 28)      /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB   (1U << 29)      /* 1b */
+#define REG_DISP0_DDR_EN_ACK_MASK_LSB       (1U << 30)      /* 1b */
+#define REG_DISP1_APSRC_ACK_MASK_LSB        (1U << 31)      /* 1b */
+/* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */
+#define REG_UFS_SRCCLKENA_ACK_MASK_LSB      (1U << 0)       /* 1b */
+#define REG_UFS_INFRA_ACK_MASK_LSB          (1U << 1)       /* 1b */
+#define REG_UFS_APSRC_ACK_MASK_LSB          (1U << 2)       /* 1b */
+#define REG_UFS_VRF18_ACK_MASK_LSB          (1U << 3)       /* 1b */
+#define REG_UFS_DDR_EN_ACK_MASK_LSB         (1U << 4)       /* 1b */
+#define REG_APU_SRCCLKENA_ACK_MASK_LSB      (1U << 5)       /* 1b */
+#define REG_APU_INFRA_ACK_MASK_LSB          (1U << 6)       /* 1b */
+#define REG_APU_APSRC_ACK_MASK_LSB          (1U << 7)       /* 1b */
+#define REG_APU_VRF18_ACK_MASK_LSB          (1U << 8)       /* 1b */
+#define REG_APU_DDR_EN_ACK_MASK_LSB         (1U << 9)       /* 1b */
+#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB    (1U << 10)      /* 1b */
+#define REG_MCUPM_INFRA_ACK_MASK_LSB        (1U << 11)      /* 1b */
+#define REG_MCUPM_APSRC_ACK_MASK_LSB        (1U << 12)      /* 1b */
+#define REG_MCUPM_VRF18_ACK_MASK_LSB        (1U << 13)      /* 1b */
+#define REG_MCUPM_DDR_EN_ACK_MASK_LSB       (1U << 14)      /* 1b */
+#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB    (1U << 15)      /* 1b */
+#define REG_MSDC0_INFRA_ACK_MASK_LSB        (1U << 16)      /* 1b */
+#define REG_MSDC0_APSRC_ACK_MASK_LSB        (1U << 17)      /* 1b */
+#define REG_MSDC0_VRF18_ACK_MASK_LSB        (1U << 18)      /* 1b */
+#define REG_MSDC0_DDR_EN_ACK_MASK_LSB       (1U << 19)      /* 1b */
+#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB    (1U << 20)      /* 1b */
+#define REG_MSDC1_INFRA_ACK_MASK_LSB        (1U << 21)      /* 1b */
+#define REG_MSDC1_APSRC_ACK_MASK_LSB        (1U << 22)      /* 1b */
+#define REG_MSDC1_VRF18_ACK_MASK_LSB        (1U << 23)      /* 1b */
+#define REG_MSDC1_DDR_EN_ACK_MASK_LSB       (1U << 24)      /* 1b */
+#define REG_DISP0_APSRC_ACK_MASK_LSB        (1U << 25)      /* 1b */
+#define REG_DISP1_DDR_EN_ACK_MASK_LSB       (1U << 26)      /* 1b */
+#define REG_GCE_INFRA_ACK_MASK_LSB          (1U << 27)      /* 1b */
+#define REG_GCE_APSRC_ACK_MASK_LSB          (1U << 28)      /* 1b */
+#define REG_GCE_VRF18_ACK_MASK_LSB          (1U << 29)      /* 1b */
+#define REG_GCE_DDR_EN_ACK_MASK_LSB         (1U << 30)      /* 1b */
+/* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */
+#define SPM_F26M_ACK_WAIT_CYCLE_LSB         (1U << 0)       /* 8b */
+#define SPM_INFRA_ACK_WAIT_CYCLE_LSB        (1U << 8)       /* 8b */
+#define SPM_APSRC_ACK_WAIT_CYCLE_LSB        (1U << 16)      /* 8b */
+#define SPM_VRF18_ACK_WAIT_CYCLE_LSB        (1U << 24)      /* 8b */
+/* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */
+#define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB       (1U << 0)       /* 8b */
+#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8)       /* 1b */
+#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB     (1U << 9)       /* 1b */
+#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB     (1U << 10)      /* 1b */
+#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB     (1U << 11)      /* 1b */
+#define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB    (1U << 12)      /* 1b */
+/* PCM_REG0_DATA (0x10006000+0x100) */
+#define PCM_REG0_RF_LSB                     (1U << 0)       /* 32b */
+/* PCM_REG2_DATA (0x10006000+0x104) */
+#define PCM_REG2_RF_LSB                     (1U << 0)       /* 32b */
+/* PCM_REG6_DATA (0x10006000+0x108) */
+#define PCM_REG6_RF_LSB                     (1U << 0)       /* 32b */
+/* PCM_REG7_DATA (0x10006000+0x10C) */
+#define PCM_REG7_RF_LSB                     (1U << 0)       /* 32b */
+/* PCM_REG13_DATA (0x10006000+0x110) */
+#define PCM_REG13_RF_LSB                    (1U << 0)       /* 32b */
+/* SRC_REQ_STA_0 (0x10006000+0x114) */
+#define MD_SRCCLKENA_0_LSB                  (1U << 0)       /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_0_LSB        (1U << 1)       /* 1b */
+#define MD_APSRC2INFRA_REQ_0_LSB            (1U << 2)       /* 1b */
+#define MD_APSRC_REQ_0_LSB                  (1U << 3)       /* 1b */
+#define MD_VRF18_REQ_0_LSB                  (1U << 4)       /* 1b */
+#define MD_DDR_EN_0_LSB                     (1U << 5)       /* 1b */
+#define MD_SRCCLKENA_1_LSB                  (1U << 6)       /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_1_LSB        (1U << 7)       /* 1b */
+#define MD_APSRC2INFRA_REQ_1_LSB            (1U << 8)       /* 1b */
+#define MD_APSRC_REQ_1_LSB                  (1U << 9)       /* 1b */
+#define MD_VRF18_REQ_1_LSB                  (1U << 10)      /* 1b */
+#define MD_DDR_EN_1_LSB                     (1U << 11)      /* 1b */
+#define CONN_SRCCLKENA_LSB                  (1U << 12)      /* 1b */
+#define CONN_SRCCLKENB_LSB                  (1U << 13)      /* 1b */
+#define CONN_INFRA_REQ_LSB                  (1U << 14)      /* 1b */
+#define CONN_APSRC_REQ_LSB                  (1U << 15)      /* 1b */
+#define CONN_VRF18_REQ_LSB                  (1U << 16)      /* 1b */
+#define CONN_DDR_EN_LSB                     (1U << 17)      /* 1b */
+#define SRCCLKENI_LSB                       (1U << 18)      /* 3b */
+#define MD32_SRCCLKENA_LSB                  (1U << 21)      /* 1b */
+#define MD32_INFRA_REQ_LSB                  (1U << 22)      /* 1b */
+#define MD32_APSRC_REQ_LSB                  (1U << 23)      /* 1b */
+#define MD32_VRF18_REQ_LSB                  (1U << 24)      /* 1b */
+#define MD32_DDR_EN_LSB                     (1U << 25)      /* 1b */
+#define DISP0_APSRC_REQ_LSB                 (1U << 26)      /* 1b */
+#define DISP0_DDR_EN_LSB                    (1U << 27)      /* 1b */
+#define DISP1_APSRC_REQ_LSB                 (1U << 28)      /* 1b */
+#define DISP1_DDR_EN_LSB                    (1U << 29)      /* 1b */
+#define DVFSRC_EVENT_TRIGGER_LSB            (1U << 30)      /* 1b */
+/* SRC_REQ_STA_1 (0x10006000+0x118) */
+#define SCP_SRCCLKENA_LSB                   (1U << 0)       /* 1b */
+#define SCP_INFRA_REQ_LSB                   (1U << 1)       /* 1b */
+#define SCP_APSRC_REQ_LSB                   (1U << 2)       /* 1b */
+#define SCP_VRF18_REQ_LSB                   (1U << 3)       /* 1b */
+#define SCP_DDR_EN_LSB                      (1U << 4)       /* 1b */
+#define AUDIO_DSP_SRCCLKENA_LSB             (1U << 5)       /* 1b */
+#define AUDIO_DSP_INFRA_REQ_LSB             (1U << 6)       /* 1b */
+#define AUDIO_DSP_APSRC_REQ_LSB             (1U << 7)       /* 1b */
+#define AUDIO_DSP_VRF18_REQ_LSB             (1U << 8)       /* 1b */
+#define AUDIO_DSP_DDR_EN_LSB                (1U << 9)       /* 1b */
+#define UFS_SRCCLKENA_LSB                   (1U << 10)      /* 1b */
+#define UFS_INFRA_REQ_LSB                   (1U << 11)      /* 1b */
+#define UFS_APSRC_REQ_LSB                   (1U << 12)      /* 1b */
+#define UFS_VRF18_REQ_LSB                   (1U << 13)      /* 1b */
+#define UFS_DDR_EN_LSB                      (1U << 14)      /* 1b */
+#define GCE_INFRA_REQ_LSB                   (1U << 15)      /* 1b */
+#define GCE_APSRC_REQ_LSB                   (1U << 16)      /* 1b */
+#define GCE_VRF18_REQ_LSB                   (1U << 17)      /* 1b */
+#define GCE_DDR_EN_LSB                      (1U << 18)      /* 1b */
+#define INFRASYS_APSRC_REQ_LSB              (1U << 19)      /* 1b */
+#define INFRASYS_DDR_EN_LSB                 (1U << 20)      /* 1b */
+#define MSDC0_SRCCLKENA_LSB                 (1U << 21)      /* 1b */
+#define MSDC0_INFRA_REQ_LSB                 (1U << 22)      /* 1b */
+#define MSDC0_APSRC_REQ_LSB                 (1U << 23)      /* 1b */
+#define MSDC0_VRF18_REQ_LSB                 (1U << 24)      /* 1b */
+#define MSDC0_DDR_EN_LSB                    (1U << 25)      /* 1b */
+#define MSDC1_SRCCLKENA_LSB                 (1U << 26)      /* 1b */
+#define MSDC1_INFRA_REQ_LSB                 (1U << 27)      /* 1b */
+#define MSDC1_APSRC_REQ_LSB                 (1U << 28)      /* 1b */
+#define MSDC1_VRF18_REQ_LSB                 (1U << 29)      /* 1b */
+#define MSDC1_DDR_EN_LSB                    (1U << 30)      /* 1b */
+/* SRC_REQ_STA_2 (0x10006000+0x11C) */
+#define MCUSYS_MERGE_DDR_EN_LSB             (1U << 0)       /* 9b */
+#define EMI_SELF_REFRESH_CH_LSB             (1U << 9)       /* 2b */
+#define SW2SPM_INT_LSB                      (1U << 11)      /* 4b */
+#define SC_ADSP2SPM_WAKEUP_LSB              (1U << 15)      /* 1b */
+#define SC_SSPM2SPM_WAKEUP_LSB              (1U << 16)      /* 4b */
+#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20)      /* 1b */
+#define SPM_SRCCLKENA_RESERVED_LSB          (1U << 21)      /* 1b */
+#define SPM_INFRA_REQ_RESERVED_LSB          (1U << 22)      /* 1b */
+#define SPM_APSRC_REQ_RESERVED_LSB          (1U << 23)      /* 1b */
+#define SPM_VRF18_REQ_RESERVED_LSB          (1U << 24)      /* 1b */
+#define SPM_DDR_EN_RESERVED_LSB             (1U << 25)      /* 1b */
+#define MCUPM_SRCCLKENA_LSB                 (1U << 26)      /* 1b */
+#define MCUPM_INFRA_REQ_LSB                 (1U << 27)      /* 1b */
+#define MCUPM_APSRC_REQ_LSB                 (1U << 28)      /* 1b */
+#define MCUPM_VRF18_REQ_LSB                 (1U << 29)      /* 1b */
+#define MCUPM_DDR_EN_LSB                    (1U << 30)      /* 1b */
+/* PCM_TIMER_OUT (0x10006000+0x120) */
+#define PCM_TIMER_LSB                       (1U << 0)       /* 32b */
+/* PCM_WDT_OUT (0x10006000+0x124) */
+#define PCM_WDT_TIMER_VAL_OUT_LSB           (1U << 0)       /* 32b */
+/* SPM_IRQ_STA (0x10006000+0x128) */
+#define TWAM_IRQ_LSB                        (1U << 2)       /* 1b */
+#define PCM_IRQ_LSB                         (1U << 3)       /* 1b */
+/* SRC_REQ_STA_4 (0x10006000+0x12C) */
+#define APU_SRCCLKENA_LSB                   (1U << 0)       /* 1b */
+#define APU_INFRA_REQ_LSB                   (1U << 1)       /* 1b */
+#define APU_APSRC_REQ_LSB                   (1U << 2)       /* 1b */
+#define APU_VRF18_REQ_LSB                   (1U << 3)       /* 1b */
+#define APU_DDR_EN_LSB                      (1U << 4)       /* 1b */
+#define BAK_PSRI_SRCCLKENA_LSB              (1U << 5)       /* 1b */
+#define BAK_PSRI_INFRA_REQ_LSB              (1U << 6)       /* 1b */
+#define BAK_PSRI_APSRC_REQ_LSB              (1U << 7)       /* 1b */
+#define BAK_PSRI_VRF18_REQ_LSB              (1U << 8)       /* 1b */
+#define BAK_PSRI_DDR_EN_LSB                 (1U << 9)       /* 1b */
+/* MD32PCM_WAKEUP_STA (0x10006000+0x130) */
+#define MD32PCM_WAKEUP_STA_LSB              (1U << 0)       /* 32b */
+/* MD32PCM_EVENT_STA (0x10006000+0x134) */
+#define MD32PCM_EVENT_STA_LSB               (1U << 0)       /* 32b */
+/* SPM_WAKEUP_STA (0x10006000+0x138) */
+#define F32K_WAKEUP_EVENT_L_LSB             (1U << 0)       /* 16b */
+#define ASYN_WAKEUP_EVENT_L_LSB             (1U << 16)      /* 16b */
+/* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */
+#define EXT_WAKEUP_EVENT_LSB                (1U << 0)       /* 32b */
+/* SPM_WAKEUP_MISC (0x10006000+0x140) */
+#define GIC_WAKEUP_LSB                      (1U << 0)       /* 10b */
+#define DVFSRC_IRQ_LSB                      (1U << 16)      /* 1b */
+#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB  (1U << 17)      /* 1b */
+#define PCM_TIMER_EVENT_LSB                 (1U << 18)      /* 1b */
+#define PMIC_EINT_OUT_B_LSB                 (1U << 19)      /* 2b */
+#define TWAM_IRQ_B_LSB                      (1U << 21)      /* 1b */
+#define PMSR_IRQ_B_SET0_LSB                 (1U << 22)      /* 1b */
+#define PMSR_IRQ_B_SET1_LSB                 (1U << 23)      /* 1b */
+#define PMSR_IRQ_B_SET2_LSB                 (1U << 24)      /* 1b */
+#define SPM_ACK_CHK_WAKEUP_0_LSB            (1U << 25)      /* 1b */
+#define SPM_ACK_CHK_WAKEUP_1_LSB            (1U << 26)      /* 1b */
+#define SPM_ACK_CHK_WAKEUP_2_LSB            (1U << 27)      /* 1b */
+#define SPM_ACK_CHK_WAKEUP_3_LSB            (1U << 28)      /* 1b */
+#define SPM_ACK_CHK_WAKEUP_ALL_LSB          (1U << 29)      /* 1b */
+#define PMIC_IRQ_ACK_LSB                    (1U << 30)      /* 1b */
+#define PMIC_SCP_IRQ_LSB                    (1U << 31)      /* 1b */
+/* MM_DVFS_HALT (0x10006000+0x144) */
+#define MM_DVFS_HALT_LSB                    (1U << 0)       /* 5b */
+/* BUS_PROTECT_RDY (0x10006000+0x150) */
+#define PROTECT_READY_LSB                   (1U << 0)       /* 32b */
+/* BUS_PROTECT1_RDY (0x10006000+0x154) */
+#define PROTECT1_READY_LSB                  (1U << 0)       /* 32b */
+/* BUS_PROTECT2_RDY (0x10006000+0x158) */
+#define PROTECT2_READY_LSB                  (1U << 0)       /* 32b */
+/* BUS_PROTECT3_RDY (0x10006000+0x15C) */
+#define PROTECT3_READY_LSB                  (1U << 0)       /* 32b */
+/* SUBSYS_IDLE_STA (0x10006000+0x160) */
+#define SUBSYS_IDLE_SIGNALS_LSB             (1U << 0)       /* 32b */
+/* PCM_STA (0x10006000+0x164) */
+#define PCM_CK_SEL_O_LSB                    (1U << 0)       /* 4b */
+#define EXT_SRC_STA_LSB                     (1U << 4)       /* 3b */
+/* SRC_REQ_STA_3 (0x10006000+0x168) */
+#define CCIF_EVENT_RAW_STATUS_LSB           (1U << 0)       /* 16b */
+#define F26M_STATE_LSB                      (1U << 16)      /* 1b */
+#define INFRA_STATE_LSB                     (1U << 17)      /* 1b */
+#define APSRC_STATE_LSB                     (1U << 18)      /* 1b */
+#define VRF18_STATE_LSB                     (1U << 19)      /* 1b */
+#define DDR_EN_STATE_LSB                    (1U << 20)      /* 1b */
+#define DVFS_STATE_LSB                      (1U << 21)      /* 1b */
+#define SW_MAILBOX_STATE_LSB                (1U << 22)      /* 1b */
+#define SSPM_MAILBOX_STATE_LSB              (1U << 23)      /* 1b */
+#define ADSP_MAILBOX_STATE_LSB              (1U << 24)      /* 1b */
+#define SCP_MAILBOX_STATE_LSB               (1U << 25)      /* 1b */
+/* PWR_STATUS (0x10006000+0x16C) */
+#define PWR_STATUS_LSB                      (1U << 0)       /* 32b */
+/* PWR_STATUS_2ND (0x10006000+0x170) */
+#define PWR_STATUS_2ND_LSB                  (1U << 0)       /* 32b */
+/* CPU_PWR_STATUS (0x10006000+0x174) */
+#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB        (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB        (1U << 1)       /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB        (1U << 2)       /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB        (1U << 3)       /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB        (1U << 4)       /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB        (1U << 5)       /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB        (1U << 6)       /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB        (1U << 7)       /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB      (1U << 8)       /* 1b */
+#define MCUSYS_SPMC_PWR_ON_ACK_LSB          (1U << 9)       /* 1b */
+/* OTHER_PWR_STATUS (0x10006000+0x178) */
+#define OTHER_PWR_STATUS_LSB                (1U << 0)       /* 32b */
+/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */
+#define SPM_VTCXO_SLEEP_COUNT_LSB           (1U << 0)       /* 16b */
+#define SPM_VTCXO_WAKE_COUNT_LSB            (1U << 16)      /* 16b */
+/* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */
+#define SPM_INFRA_SLEEP_COUNT_LSB           (1U << 0)       /* 16b */
+#define SPM_INFRA_WAKE_COUNT_LSB            (1U << 16)      /* 16b */
+/* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */
+#define SPM_VRF18_SLEEP_COUNT_LSB           (1U << 0)       /* 16b */
+#define SPM_VRF18_WAKE_COUNT_LSB            (1U << 16)      /* 16b */
+/* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */
+#define SPM_APSRC_SLEEP_COUNT_LSB           (1U << 0)       /* 16b */
+#define SPM_APSRC_WAKE_COUNT_LSB            (1U << 16)      /* 16b */
+/* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */
+#define SPM_DDREN_SLEEP_COUNT_LSB           (1U << 0)       /* 16b */
+#define SPM_DDREN_WAKE_COUNT_LSB            (1U << 16)      /* 16b */
+/* MD32PCM_STA (0x10006000+0x190) */
+#define MD32PCM_HALT_LSB                    (1U << 0)       /* 1b */
+#define MD32PCM_GATED_LSB                   (1U << 1)       /* 1b */
+/* MD32PCM_PC (0x10006000+0x194) */
+#define MON_PC_LSB                          (1U << 0)       /* 32b */
+/* DVFSRC_EVENT_STA (0x10006000+0x1A4) */
+#define DVFSRC_EVENT_LSB                    (1U << 0)       /* 32b */
+/* BUS_PROTECT4_RDY (0x10006000+0x1A8) */
+#define PROTECT4_READY_LSB                  (1U << 0)       /* 32b */
+/* BUS_PROTECT5_RDY (0x10006000+0x1AC) */
+#define PROTECT5_READY_LSB                  (1U << 0)       /* 32b */
+/* BUS_PROTECT6_RDY (0x10006000+0x1B0) */
+#define PROTECT6_READY_LSB                  (1U << 0)       /* 32b */
+/* BUS_PROTECT7_RDY (0x10006000+0x1B4) */
+#define PROTECT7_READY_LSB                  (1U << 0)       /* 32b */
+/* BUS_PROTECT8_RDY (0x10006000+0x1B8) */
+#define PROTECT8_READY_LSB                  (1U << 0)       /* 32b */
+/* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */
+#define LAST_IDLE_CNT_0_LSB                 (1U << 0)       /* 32b */
+/* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */
+#define LAST_IDLE_CNT_1_LSB                 (1U << 0)       /* 32b */
+/* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */
+#define LAST_IDLE_CNT_2_LSB                 (1U << 0)       /* 32b */
+/* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */
+#define LAST_IDLE_CNT_3_LSB                 (1U << 0)       /* 32b */
+/* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */
+#define CURRENT_IDLE_CNT_0_LSB              (1U << 0)       /* 32b */
+/* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */
+#define CURRENT_IDLE_CNT_1_LSB              (1U << 0)       /* 32b */
+/* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */
+#define CURRENT_IDLE_CNT_2_LSB              (1U << 0)       /* 32b */
+/* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */
+#define CURRENT_IDLE_CNT_3_LSB              (1U << 0)       /* 32b */
+/* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */
+#define TWAM_TIMER_LSB                      (1U << 0)       /* 32b */
+/* SPM_CG_CHECK_STA (0x10006000+0x1F4) */
+#define SPM_CG_CHECK_SLEEP_REQ_0_LSB        (1U << 0)       /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_1_LSB        (1U << 1)       /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_2_LSB        (1U << 2)       /* 1b */
+/* SPM_DVFS_STA (0x10006000+0x1F8) */
+#define TARGET_DVFS_LEVEL_LSB               (1U << 0)       /* 32b */
+/* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */
+#define TARGET_DVFS_OPP_LSB                 (1U << 0)       /* 5b */
+#define CURRENT_DVFS_OPP_LSB                (1U << 5)       /* 5b */
+#define RELAY_DVFS_OPP_LSB                  (1U << 10)      /* 5b */
+/* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */
+#define MCUSYS_SPMC_PWR_RST_B_LSB           (1U << 0)       /* 1b */
+#define MCUSYS_SPMC_PWR_ON_LSB              (1U << 2)       /* 1b */
+#define MCUSYS_SPMC_PWR_CLK_DIS_LSB         (1U << 4)       /* 1b */
+#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB   (1U << 5)       /* 1b */
+#define MCUSYS_SPMC_DORMANT_EN_LSB          (1U << 6)       /* 1b */
+#define MCUSYS_VPROC_EXT_OFF_LSB            (1U << 7)       /* 1b */
+#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31)      /* 1b */
+/* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */
+#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB       (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPUTOP_LSB          (1U << 2)       /* 1b */
+#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB     (1U << 4)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5)       /* 1b */
+#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB      (1U << 6)       /* 1b */
+#define MP0_VPROC_EXT_OFF_LSB               (1U << 7)       /* 1b */
+#define MP0_VSRAM_EXT_OFF_LSB               (1U << 8)       /* 1b */
+#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31)      /* 1b */
+/* SPM_CPU0_PWR_CON (0x10006000+0x208) */
+#define MP0_SPMC_PWR_RST_B_CPU0_LSB         (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPU0_LSB            (1U << 2)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5)       /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU0_LSB          (1U << 7)       /* 1b */
+#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31)      /* 1b */
+/* SPM_CPU1_PWR_CON (0x10006000+0x20C) */
+#define MP0_SPMC_PWR_RST_B_CPU1_LSB         (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPU1_LSB            (1U << 2)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5)       /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU1_LSB          (1U << 7)       /* 1b */
+#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31)      /* 1b */
+/* SPM_CPU2_PWR_CON (0x10006000+0x210) */
+#define MP0_SPMC_PWR_RST_B_CPU2_LSB         (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPU2_LSB            (1U << 2)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5)       /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU2_LSB          (1U << 7)       /* 1b */
+#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31)      /* 1b */
+/* SPM_CPU3_PWR_CON (0x10006000+0x214) */
+#define MP0_SPMC_PWR_RST_B_CPU3_LSB         (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPU3_LSB            (1U << 2)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5)       /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU3_LSB          (1U << 7)       /* 1b */
+#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31)      /* 1b */
+/* SPM_CPU4_PWR_CON (0x10006000+0x218) */
+#define MP0_SPMC_PWR_RST_B_CPU4_LSB         (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPU4_LSB            (1U << 2)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5)       /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU4_LSB          (1U << 7)       /* 1b */
+#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31)      /* 1b */
+/* SPM_CPU5_PWR_CON (0x10006000+0x21C) */
+#define MP0_SPMC_PWR_RST_B_CPU5_LSB         (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPU5_LSB            (1U << 2)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5)       /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU5_LSB          (1U << 7)       /* 1b */
+#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31)      /* 1b */
+/* SPM_CPU6_PWR_CON (0x10006000+0x220) */
+#define MP0_SPMC_PWR_RST_B_CPU6_LSB         (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPU6_LSB            (1U << 2)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5)       /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU6_LSB          (1U << 7)       /* 1b */
+#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31)      /* 1b */
+/* SPM_CPU7_PWR_CON (0x10006000+0x224) */
+#define MP0_SPMC_PWR_RST_B_CPU7_LSB         (1U << 0)       /* 1b */
+#define MP0_SPMC_PWR_ON_CPU7_LSB            (1U << 2)       /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5)       /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU7_LSB          (1U << 7)       /* 1b */
+#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31)      /* 1b */
+/* ARMPLL_CLK_CON (0x10006000+0x22C) */
+#define SC_ARM_FHC_PAUSE_LSB                (1U << 0)       /* 6b */
+#define SC_ARM_CK_OFF_LSB                   (1U << 6)       /* 6b */
+#define SC_ARMPLL_OFF_LSB                   (1U << 12)      /* 1b */
+#define SC_ARMBPLL_OFF_LSB                  (1U << 13)      /* 1b */
+#define SC_ARMBPLL1_OFF_LSB                 (1U << 14)      /* 1b */
+#define SC_ARMBPLL2_OFF_LSB                 (1U << 15)      /* 1b */
+#define SC_ARMBPLL3_OFF_LSB                 (1U << 16)      /* 1b */
+#define SC_CCIPLL_CKOFF_LSB                 (1U << 17)      /* 1b */
+#define SC_ARMDDS_OFF_LSB                   (1U << 18)      /* 1b */
+#define SC_ARMBPLL_S_OFF_LSB                (1U << 19)      /* 1b */
+#define SC_ARMBPLL1_S_OFF_LSB               (1U << 20)      /* 1b */
+#define SC_ARMBPLL2_S_OFF_LSB               (1U << 21)      /* 1b */
+#define SC_ARMBPLL3_S_OFF_LSB               (1U << 22)      /* 1b */
+#define SC_CCIPLL_PWROFF_LSB                (1U << 23)      /* 1b */
+#define SC_ARMPLLOUT_OFF_LSB                (1U << 24)      /* 1b */
+#define SC_ARMBPLLOUT_OFF_LSB               (1U << 25)      /* 1b */
+#define SC_ARMBPLLOUT1_OFF_LSB              (1U << 26)      /* 1b */
+#define SC_ARMBPLLOUT2_OFF_LSB              (1U << 27)      /* 1b */
+#define SC_ARMBPLLOUT3_OFF_LSB              (1U << 28)      /* 1b */
+#define SC_CCIPLL_OUT_OFF_LSB               (1U << 29)      /* 1b */
+/* MCUSYS_IDLE_STA (0x10006000+0x230) */
+#define ARMBUS_IDLE_TO_26M_LSB              (1U << 0)       /* 1b */
+#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB     (1U << 1)       /* 1b */
+#define MCUSYS_DDR_EN_0_LSB                 (1U << 2)       /* 1b */
+#define MCUSYS_DDR_EN_1_LSB                 (1U << 3)       /* 1b */
+#define MCUSYS_DDR_EN_2_LSB                 (1U << 4)       /* 1b */
+#define MCUSYS_DDR_EN_3_LSB                 (1U << 5)       /* 1b */
+#define MCUSYS_DDR_EN_4_LSB                 (1U << 6)       /* 1b */
+#define MCUSYS_DDR_EN_5_LSB                 (1U << 7)       /* 1b */
+#define MCUSYS_DDR_EN_6_LSB                 (1U << 8)       /* 1b */
+#define MCUSYS_DDR_EN_7_LSB                 (1U << 9)       /* 1b */
+#define MP0_CPU_IDLE_TO_PWR_OFF_LSB         (1U << 16)      /* 8b */
+#define WFI_AF_SEL_LSB                      (1U << 24)      /* 8b */
+/* GIC_WAKEUP_STA (0x10006000+0x234) */
+#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB       (1U << 10)      /* 10b */
+/* CPU_SPARE_CON (0x10006000+0x238) */
+#define CPU_SPARE_CON_LSB                   (1U << 0)       /* 32b */
+/* CPU_SPARE_CON_SET (0x10006000+0x23C) */
+#define CPU_SPARE_CON_SET_LSB               (1U << 0)       /* 32b */
+/* CPU_SPARE_CON_CLR (0x10006000+0x240) */
+#define CPU_SPARE_CON_CLR_LSB               (1U << 0)       /* 32b */
+/* ARMPLL_CLK_SEL (0x10006000+0x244) */
+#define ARMPLL_CLK_SEL_LSB                  (1U << 0)       /* 15b */
+/* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */
+#define EXT_INT_WAKEUP_REQ_LSB              (1U << 0)       /* 10b */
+/* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */
+#define EXT_INT_WAKEUP_REQ_SET_LSB          (1U << 0)       /* 10b */
+/* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */
+#define EXT_INT_WAKEUP_REQ_CLR_LSB          (1U << 0)       /* 10b */
+/* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */
+#define MP0_CPU0_IRQ_MASK_LSB               (1U << 0)       /* 1b */
+#define MP0_CPU0_AUX_LSB                    (1U << 8)       /* 11b */
+/* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */
+#define MP0_CPU1_IRQ_MASK_LSB               (1U << 0)       /* 1b */
+#define MP0_CPU1_AUX_LSB                    (1U << 8)       /* 11b */
+/* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */
+#define MP0_CPU2_IRQ_MASK_LSB               (1U << 0)       /* 1b */
+#define MP0_CPU2_AUX_LSB                    (1U << 8)       /* 11b */
+/* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */
+#define MP0_CPU3_IRQ_MASK_LSB               (1U << 0)       /* 1b */
+#define MP0_CPU3_AUX_LSB                    (1U << 8)       /* 11b */
+/* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */
+#define MP1_CPU0_IRQ_MASK_LSB               (1U << 0)       /* 1b */
+#define MP1_CPU0_AUX_LSB                    (1U << 8)       /* 11b */
+/* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */
+#define MP1_CPU1_IRQ_MASK_LSB               (1U << 0)       /* 1b */
+#define MP1_CPU1_AUX_LSB                    (1U << 8)       /* 11b */
+/* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */
+#define MP1_CPU2_IRQ_MASK_LSB               (1U << 0)       /* 1b */
+#define MP1_CPU2_AUX_LSB                    (1U << 8)       /* 11b */
+/* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */
+#define MP1_CPU3_IRQ_MASK_LSB               (1U << 0)       /* 1b */
+#define MP1_CPU3_AUX_LSB                    (1U << 8)       /* 11b */
+/* MP0_CPU0_WFI_EN (0x10006000+0x280) */
+#define MP0_CPU0_WFI_EN_LSB                 (1U << 0)       /* 1b */
+/* MP0_CPU1_WFI_EN (0x10006000+0x284) */
+#define MP0_CPU1_WFI_EN_LSB                 (1U << 0)       /* 1b */
+/* MP0_CPU2_WFI_EN (0x10006000+0x288) */
+#define MP0_CPU2_WFI_EN_LSB                 (1U << 0)       /* 1b */
+/* MP0_CPU3_WFI_EN (0x10006000+0x28C) */
+#define MP0_CPU3_WFI_EN_LSB                 (1U << 0)       /* 1b */
+/* MP0_CPU4_WFI_EN (0x10006000+0x290) */
+#define MP0_CPU4_WFI_EN_LSB                 (1U << 0)       /* 1b */
+/* MP0_CPU5_WFI_EN (0x10006000+0x294) */
+#define MP0_CPU5_WFI_EN_LSB                 (1U << 0)       /* 1b */
+/* MP0_CPU6_WFI_EN (0x10006000+0x298) */
+#define MP0_CPU6_WFI_EN_LSB                 (1U << 0)       /* 1b */
+/* MP0_CPU7_WFI_EN (0x10006000+0x29C) */
+#define MP0_CPU7_WFI_EN_LSB                 (1U << 0)       /* 1b */
+/* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */
+#define ROOT_CPUTOP_ADDR_LSB                (1U << 0)       /* 32b */
+/* ROOT_CORE_ADDR (0x10006000+0x2A4) */
+#define ROOT_CORE_ADDR_LSB                  (1U << 0)       /* 32b */
+/* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */
+#define SPM2SW_MAILBOX_0_LSB                (1U << 0)       /* 32b */
+/* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */
+#define SPM2SW_MAILBOX_1_LSB                (1U << 0)       /* 32b */
+/* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */
+#define SPM2SW_MAILBOX_2_LSB                (1U << 0)       /* 32b */
+/* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */
+#define SPM2SW_MAILBOX_3_LSB                (1U << 0)       /* 32b */
+/* SW2SPM_INT (0x10006000+0x2E0) */
+#define SW2SPM_INT_SW2SPM_INT_LSB           (1U << 0)       /* 4b */
+/* SW2SPM_INT_SET (0x10006000+0x2E4) */
+#define SW2SPM_INT_SET_LSB                  (1U << 0)       /* 4b */
+/* SW2SPM_INT_CLR (0x10006000+0x2E8) */
+#define SW2SPM_INT_CLR_LSB                  (1U << 0)       /* 4b */
+/* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */
+#define SW2SPM_MAILBOX_0_LSB                (1U << 0)       /* 32b */
+/* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */
+#define SW2SPM_MAILBOX_1_LSB                (1U << 0)       /* 32b */
+/* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */
+#define SW2SPM_MAILBOX_2_LSB                (1U << 0)       /* 32b */
+/* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */
+#define SW2SPM_MAILBOX_3_LSB                (1U << 0)       /* 32b */
+/* SW2SPM_CFG (0x10006000+0x2FC) */
+#define SWU2SPM_INT_MASK_B_LSB              (1U << 0)       /* 4b */
+/* MD1_PWR_CON (0x10006000+0x300) */
+#define MD1_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define MD1_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define MD1_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define MD1_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define MD1_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define MD1_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_MD1_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* CONN_PWR_CON (0x10006000+0x304) */
+#define CONN_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define CONN_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define CONN_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define CONN_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define CONN_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+/* MFG0_PWR_CON (0x10006000+0x308) */
+#define MFG0_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define MFG0_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define MFG0_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define MFG0_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define MFG0_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define MFG0_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_MFG0_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* MFG1_PWR_CON (0x10006000+0x30C) */
+#define MFG1_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define MFG1_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define MFG1_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define MFG1_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define MFG1_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define MFG1_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_MFG1_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* MFG2_PWR_CON (0x10006000+0x310) */
+#define MFG2_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define MFG2_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define MFG2_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define MFG2_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define MFG2_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define MFG2_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_MFG2_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* MFG3_PWR_CON (0x10006000+0x314) */
+#define MFG3_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define MFG3_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define MFG3_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define MFG3_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define MFG3_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define MFG3_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_MFG3_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* MFG4_PWR_CON (0x10006000+0x318) */
+#define MFG4_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define MFG4_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define MFG4_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define MFG4_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define MFG4_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define MFG4_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_MFG4_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* MFG5_PWR_CON (0x10006000+0x31C) */
+#define MFG5_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define MFG5_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define MFG5_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define MFG5_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define MFG5_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define MFG5_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_MFG5_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* MFG6_PWR_CON (0x10006000+0x320) */
+#define MFG6_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define MFG6_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define MFG6_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define MFG6_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define MFG6_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define MFG6_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_MFG6_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* IFR_PWR_CON (0x10006000+0x324) */
+#define IFR_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define IFR_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define IFR_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define IFR_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define IFR_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define IFR_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_IFR_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* IFR_SUB_PWR_CON (0x10006000+0x328) */
+#define IFR_SUB_PWR_RST_B_LSB               (1U << 0)       /* 1b */
+#define IFR_SUB_PWR_ISO_LSB                 (1U << 1)       /* 1b */
+#define IFR_SUB_PWR_ON_LSB                  (1U << 2)       /* 1b */
+#define IFR_SUB_PWR_ON_2ND_LSB              (1U << 3)       /* 1b */
+#define IFR_SUB_PWR_CLK_DIS_LSB             (1U << 4)       /* 1b */
+#define IFR_SUB_SRAM_PDN_LSB                (1U << 8)       /* 1b */
+#define SC_IFR_SUB_SRAM_PDN_ACK_LSB         (1U << 12)      /* 1b */
+/* DPY_PWR_CON (0x10006000+0x32C) */
+#define DPY_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define DPY_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define DPY_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define DPY_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define DPY_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define DPY_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_DPY_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* ISP_PWR_CON (0x10006000+0x330) */
+#define ISP_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define ISP_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define ISP_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define ISP_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define ISP_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define ISP_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_ISP_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* ISP2_PWR_CON (0x10006000+0x334) */
+#define ISP2_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define ISP2_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define ISP2_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define ISP2_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define ISP2_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define ISP2_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_ISP2_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* IPE_PWR_CON (0x10006000+0x338) */
+#define IPE_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define IPE_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define IPE_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define IPE_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define IPE_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define IPE_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_IPE_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* VDE_PWR_CON (0x10006000+0x33C) */
+#define VDE_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define VDE_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define VDE_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define VDE_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define VDE_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define VDE_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_VDE_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* VDE2_PWR_CON (0x10006000+0x340) */
+#define VDE2_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define VDE2_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define VDE2_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define VDE2_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define VDE2_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define VDE2_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_VDE2_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* VEN_PWR_CON (0x10006000+0x344) */
+#define VEN_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define VEN_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define VEN_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define VEN_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define VEN_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define VEN_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_VEN_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* VEN_CORE1_PWR_CON (0x10006000+0x348) */
+#define VEN_CORE1_PWR_RST_B_LSB             (1U << 0)       /* 1b */
+#define VEN_CORE1_PWR_ISO_LSB               (1U << 1)       /* 1b */
+#define VEN_CORE1_PWR_ON_LSB                (1U << 2)       /* 1b */
+#define VEN_CORE1_PWR_ON_2ND_LSB            (1U << 3)       /* 1b */
+#define VEN_CORE1_PWR_CLK_DIS_LSB           (1U << 4)       /* 1b */
+#define VEN_CORE1_SRAM_PDN_LSB              (1U << 8)       /* 1b */
+#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB       (1U << 12)      /* 1b */
+/* MDP_PWR_CON (0x10006000+0x34C) */
+#define MDP_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define MDP_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define MDP_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define MDP_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define MDP_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define MDP_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_MDP_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* DIS_PWR_CON (0x10006000+0x350) */
+#define DIS_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define DIS_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define DIS_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define DIS_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define DIS_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define DIS_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_DIS_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* AUDIO_PWR_CON (0x10006000+0x354) */
+#define AUDIO_PWR_RST_B_LSB                 (1U << 0)       /* 1b */
+#define AUDIO_PWR_ISO_LSB                   (1U << 1)       /* 1b */
+#define AUDIO_PWR_ON_LSB                    (1U << 2)       /* 1b */
+#define AUDIO_PWR_ON_2ND_LSB                (1U << 3)       /* 1b */
+#define AUDIO_PWR_CLK_DIS_LSB               (1U << 4)       /* 1b */
+#define AUDIO_SRAM_PDN_LSB                  (1U << 8)       /* 1b */
+#define SC_AUDIO_SRAM_PDN_ACK_LSB           (1U << 12)      /* 1b */
+/* ADSP_PWR_CON (0x10006000+0x358) */
+#define ADSP_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define ADSP_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define ADSP_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define ADSP_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define ADSP_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define ADSP_SRAM_CKISO_LSB                 (1U << 5)       /* 1b */
+#define ADSP_SRAM_ISOINT_B_LSB              (1U << 6)       /* 1b */
+#define ADSP_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define ADSP_SRAM_SLEEP_B_LSB               (1U << 9)       /* 1b */
+#define SC_ADSP_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB        (1U << 13)      /* 1b */
+/* CAM_PWR_CON (0x10006000+0x35C) */
+#define CAM_PWR_RST_B_LSB                   (1U << 0)       /* 1b */
+#define CAM_PWR_ISO_LSB                     (1U << 1)       /* 1b */
+#define CAM_PWR_ON_LSB                      (1U << 2)       /* 1b */
+#define CAM_PWR_ON_2ND_LSB                  (1U << 3)       /* 1b */
+#define CAM_PWR_CLK_DIS_LSB                 (1U << 4)       /* 1b */
+#define CAM_SRAM_PDN_LSB                    (1U << 8)       /* 1b */
+#define SC_CAM_SRAM_PDN_ACK_LSB             (1U << 12)      /* 1b */
+/* CAM_RAWA_PWR_CON (0x10006000+0x360) */
+#define CAM_RAWA_PWR_RST_B_LSB              (1U << 0)       /* 1b */
+#define CAM_RAWA_PWR_ISO_LSB                (1U << 1)       /* 1b */
+#define CAM_RAWA_PWR_ON_LSB                 (1U << 2)       /* 1b */
+#define CAM_RAWA_PWR_ON_2ND_LSB             (1U << 3)       /* 1b */
+#define CAM_RAWA_PWR_CLK_DIS_LSB            (1U << 4)       /* 1b */
+#define CAM_RAWA_SRAM_PDN_LSB               (1U << 8)       /* 1b */
+#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB        (1U << 12)      /* 1b */
+/* CAM_RAWB_PWR_CON (0x10006000+0x364) */
+#define CAM_RAWB_PWR_RST_B_LSB              (1U << 0)       /* 1b */
+#define CAM_RAWB_PWR_ISO_LSB                (1U << 1)       /* 1b */
+#define CAM_RAWB_PWR_ON_LSB                 (1U << 2)       /* 1b */
+#define CAM_RAWB_PWR_ON_2ND_LSB             (1U << 3)       /* 1b */
+#define CAM_RAWB_PWR_CLK_DIS_LSB            (1U << 4)       /* 1b */
+#define CAM_RAWB_SRAM_PDN_LSB               (1U << 8)       /* 1b */
+#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB        (1U << 12)      /* 1b */
+/* CAM_RAWC_PWR_CON (0x10006000+0x368) */
+#define CAM_RAWC_PWR_RST_B_LSB              (1U << 0)       /* 1b */
+#define CAM_RAWC_PWR_ISO_LSB                (1U << 1)       /* 1b */
+#define CAM_RAWC_PWR_ON_LSB                 (1U << 2)       /* 1b */
+#define CAM_RAWC_PWR_ON_2ND_LSB             (1U << 3)       /* 1b */
+#define CAM_RAWC_PWR_CLK_DIS_LSB            (1U << 4)       /* 1b */
+#define CAM_RAWC_SRAM_PDN_LSB               (1U << 8)       /* 1b */
+#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB        (1U << 12)      /* 1b */
+/* SYSRAM_CON (0x10006000+0x36C) */
+#define SYSRAM_SRAM_CKISO_LSB               (1U << 0)       /* 1b */
+#define SYSRAM_SRAM_ISOINT_B_LSB            (1U << 1)       /* 1b */
+#define SYSRAM_SRAM_SLEEP_B_LSB             (1U << 4)       /* 4b */
+#define SYSRAM_SRAM_PDN_LSB                 (1U << 16)      /* 4b */
+/* SYSROM_CON (0x10006000+0x370) */
+#define SYSROM_SRAM_PDN_LSB                 (1U << 0)       /* 6b */
+/* SSPM_SRAM_CON (0x10006000+0x374) */
+#define SSPM_SRAM_CKISO_LSB                 (1U << 0)       /* 1b */
+#define SSPM_SRAM_ISOINT_B_LSB              (1U << 1)       /* 1b */
+#define SSPM_SRAM_SLEEP_B_LSB               (1U << 4)       /* 1b */
+#define SSPM_SRAM_PDN_LSB                   (1U << 16)      /* 1b */
+/* SCP_SRAM_CON (0x10006000+0x378) */
+#define SCP_SRAM_CKISO_LSB                  (1U << 0)       /* 1b */
+#define SCP_SRAM_ISOINT_B_LSB               (1U << 1)       /* 1b */
+#define SCP_SRAM_SLEEP_B_LSB                (1U << 4)       /* 1b */
+#define SCP_SRAM_PDN_LSB                    (1U << 16)      /* 1b */
+/* DPY_SHU_SRAM_CON (0x10006000+0x37C) */
+#define DPY_SHU_SRAM_CKISO_LSB              (1U << 0)       /* 1b */
+#define DPY_SHU_SRAM_ISOINT_B_LSB           (1U << 1)       /* 1b */
+#define DPY_SHU_SRAM_SLEEP_B_LSB            (1U << 4)       /* 2b */
+#define DPY_SHU_SRAM_PDN_LSB                (1U << 16)      /* 2b */
+/* UFS_SRAM_CON (0x10006000+0x380) */
+#define UFS_SRAM_CKISO_LSB                  (1U << 0)       /* 1b */
+#define UFS_SRAM_ISOINT_B_LSB               (1U << 1)       /* 1b */
+#define UFS_SRAM_SLEEP_B_LSB                (1U << 4)       /* 5b */
+#define UFS_SRAM_PDN_LSB                    (1U << 16)      /* 5b */
+/* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */
+#define DEVAPC_IFR_SRAM_CKISO_LSB           (1U << 0)       /* 1b */
+#define DEVAPC_IFR_SRAM_ISOINT_B_LSB        (1U << 1)       /* 1b */
+#define DEVAPC_IFR_SRAM_SLEEP_B_LSB         (1U << 4)       /* 6b */
+#define DEVAPC_IFR_SRAM_PDN_LSB             (1U << 16)      /* 6b */
+/* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */
+#define DEVAPC_SUBIFR_SRAM_CKISO_LSB        (1U << 0)       /* 1b */
+#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB     (1U << 1)       /* 1b */
+#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB      (1U << 4)       /* 6b */
+#define DEVAPC_SUBIFR_SRAM_PDN_LSB          (1U << 16)      /* 6b */
+/* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */
+#define DEVAPC_ACP_SRAM_CKISO_LSB           (1U << 0)       /* 1b */
+#define DEVAPC_ACP_SRAM_ISOINT_B_LSB        (1U << 1)       /* 1b */
+#define DEVAPC_ACP_SRAM_SLEEP_B_LSB         (1U << 4)       /* 6b */
+#define DEVAPC_ACP_SRAM_PDN_LSB             (1U << 16)      /* 6b */
+/* USB_SRAM_CON (0x10006000+0x390) */
+#define USB_SRAM_PDN_LSB                    (1U << 0)       /* 7b */
+/* DUMMY_SRAM_CON (0x10006000+0x394) */
+#define DUMMY_SRAM_CKISO_LSB                (1U << 0)       /* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB             (1U << 1)       /* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB              (1U << 4)       /* 8b */
+#define DUMMY_SRAM_PDN_LSB                  (1U << 16)      /* 8b */
+/* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */
+#define VMODEM_EXT_BUCK_ISO_LSB             (1U << 0)       /* 1b */
+#define VMD_EXT_BUCK_ISO_LSB                (1U << 1)       /* 1b */
+/* EXT_BUCK_ISO (0x10006000+0x39C) */
+#define VIMVO_EXT_BUCK_ISO_LSB              (1U << 0)       /* 1b */
+#define GPU_EXT_BUCK_ISO_LSB                (1U << 1)       /* 1b */
+#define IPU_EXT_BUCK_ISO_LSB                (1U << 5)       /* 3b */
+/* DXCC_SRAM_CON (0x10006000+0x3A0) */
+#define DXCC_SRAM_CKISO_LSB                 (1U << 0)       /* 1b */
+#define DXCC_SRAM_ISOINT_B_LSB              (1U << 1)       /* 1b */
+#define DXCC_SRAM_SLEEP_B_LSB               (1U << 4)       /* 1b */
+#define DXCC_SRAM_PDN_LSB                   (1U << 16)      /* 1b */
+/* MSDC_SRAM_CON (0x10006000+0x3A4) */
+#define MSDC_SRAM_CKISO_LSB                 (1U << 0)       /* 1b */
+#define MSDC_SRAM_ISOINT_B_LSB              (1U << 1)       /* 1b */
+#define MSDC_SRAM_SLEEP_B_LSB               (1U << 4)       /* 5b */
+#define MSDC_SRAM_PDN_LSB                   (1U << 16)      /* 5b */
+/* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */
+#define DEBUGTOP_SRAM_PDN_LSB               (1U << 0)       /* 1b */
+/* DP_TX_PWR_CON (0x10006000+0x3AC) */
+#define DP_TX_PWR_RST_B_LSB                 (1U << 0)       /* 1b */
+#define DP_TX_PWR_ISO_LSB                   (1U << 1)       /* 1b */
+#define DP_TX_PWR_ON_LSB                    (1U << 2)       /* 1b */
+#define DP_TX_PWR_ON_2ND_LSB                (1U << 3)       /* 1b */
+#define DP_TX_PWR_CLK_DIS_LSB               (1U << 4)       /* 1b */
+#define DP_TX_SRAM_PDN_LSB                  (1U << 8)       /* 1b */
+#define SC_DP_TX_SRAM_PDN_ACK_LSB           (1U << 12)      /* 1b */
+/* DPMAIF_SRAM_CON (0x10006000+0x3B0) */
+#define DPMAIF_SRAM_CKISO_LSB               (1U << 0)       /* 1b */
+#define DPMAIF_SRAM_ISOINT_B_LSB            (1U << 1)       /* 1b */
+#define DPMAIF_SRAM_SLEEP_B_LSB             (1U << 4)       /* 1b */
+#define DPMAIF_SRAM_PDN_LSB                 (1U << 16)      /* 1b */
+/* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */
+#define DPY_SHU2_SRAM_CKISO_LSB             (1U << 0)       /* 1b */
+#define DPY_SHU2_SRAM_ISOINT_B_LSB          (1U << 1)       /* 1b */
+#define DPY_SHU2_SRAM_SLEEP_B_LSB           (1U << 4)       /* 2b */
+#define DPY_SHU2_SRAM_PDN_LSB               (1U << 16)      /* 2b */
+/* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */
+#define DRAMC_MCU2_SRAM_CKISO_LSB           (1U << 0)       /* 1b */
+#define DRAMC_MCU2_SRAM_ISOINT_B_LSB        (1U << 1)       /* 1b */
+#define DRAMC_MCU2_SRAM_SLEEP_B_LSB         (1U << 4)       /* 1b */
+#define DRAMC_MCU2_SRAM_PDN_LSB             (1U << 16)      /* 1b */
+/* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */
+#define DRAMC_MCU_SRAM_CKISO_LSB            (1U << 0)       /* 1b */
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB         (1U << 1)       /* 1b */
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB          (1U << 4)       /* 1b */
+#define DRAMC_MCU_SRAM_PDN_LSB              (1U << 16)      /* 1b */
+/* MCUPM_SRAM_CON (0x10006000+0x3C0) */
+#define MCUPM_SRAM_CKISO_LSB                (1U << 0)       /* 1b */
+#define MCUPM_SRAM_ISOINT_B_LSB             (1U << 1)       /* 1b */
+#define MCUPM_SRAM_SLEEP_B_LSB              (1U << 4)       /* 8b */
+#define MCUPM_SRAM_PDN_LSB                  (1U << 16)      /* 8b */
+/* DPY2_PWR_CON (0x10006000+0x3C4) */
+#define DPY2_PWR_RST_B_LSB                  (1U << 0)       /* 1b */
+#define DPY2_PWR_ISO_LSB                    (1U << 1)       /* 1b */
+#define DPY2_PWR_ON_LSB                     (1U << 2)       /* 1b */
+#define DPY2_PWR_ON_2ND_LSB                 (1U << 3)       /* 1b */
+#define DPY2_PWR_CLK_DIS_LSB                (1U << 4)       /* 1b */
+#define DPY2_SRAM_PDN_LSB                   (1U << 8)       /* 1b */
+#define SC_DPY2_SRAM_PDN_ACK_LSB            (1U << 12)      /* 1b */
+/* SPM_MEM_CK_SEL (0x10006000+0x400) */
+#define SC_MEM_CK_SEL_LSB                   (1U << 0)       /* 1b */
+#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB     (1U << 1)       /* 1b */
+/* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */
+#define SPM_BUS_PROTECT_MASK_B_LSB          (1U << 0)       /* 32b */
+/* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */
+#define SPM_BUS_PROTECT1_MASK_B_LSB         (1U << 0)       /* 32b */
+/* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */
+#define SPM_BUS_PROTECT2_MASK_B_LSB         (1U << 0)       /* 32b */
+/* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */
+#define SPM_BUS_PROTECT3_MASK_B_LSB         (1U << 0)       /* 32b */
+/* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */
+#define SPM_BUS_PROTECT4_MASK_B_LSB         (1U << 0)       /* 32b */
+/* SPM_EMI_BW_MODE (0x10006000+0x418) */
+#define EMI_BW_MODE_LSB                     (1U << 0)       /* 1b */
+#define EMI_BOOST_MODE_LSB                  (1U << 1)       /* 1b */
+#define EMI_BW_MODE_2_LSB                   (1U << 2)       /* 1b */
+#define EMI_BOOST_MODE_2_LSB                (1U << 3)       /* 1b */
+/* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */
+#define AP2MD_PEER_WAKEUP_LSB               (1U << 0)       /* 1b */
+/* ULPOSC_CON (0x10006000+0x420) */
+#define ULPOSC_EN_LSB                       (1U << 0)       /* 1b */
+#define ULPOSC_RST_LSB                      (1U << 1)       /* 1b */
+#define ULPOSC_CG_EN_LSB                    (1U << 2)       /* 1b */
+#define ULPOSC_CLK_SEL_LSB                  (1U << 3)       /* 1b */
+/* SPM2MM_CON (0x10006000+0x424) */
+#define SPM2MM_FORCE_ULTRA_LSB              (1U << 0)       /* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB             (1U << 1)       /* 1b */
+#define SPM2MM_ULTRAREQ_LSB                 (1U << 2)       /* 1b */
+#define SPM2MD_ULTRAREQ_LSB                 (1U << 3)       /* 1b */
+#define SPM2ISP_ULTRAREQ_LSB                (1U << 4)       /* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB      (1U << 16)      /* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB     (1U << 17)      /* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB            (1U << 18)      /* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB             (1U << 19)      /* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB             (1U << 20)      /* 1b */
+/* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */
+#define SPM_BUS_PROTECT5_MASK_B_LSB         (1U << 0)       /* 32b */
+/* SPM2MCUPM_CON (0x10006000+0x42C) */
+#define SPM2MCUPM_SW_RST_B_LSB              (1U << 0)       /* 1b */
+#define SPM2MCUPM_SW_INT_LSB                (1U << 1)       /* 1b */
+/* AP_MDSRC_REQ (0x10006000+0x430) */
+#define AP_MDSMSRC_REQ_LSB                  (1U << 0)       /* 1b */
+#define AP_L1SMSRC_REQ_LSB                  (1U << 1)       /* 1b */
+#define AP_MD2SRC_REQ_LSB                   (1U << 2)       /* 1b */
+#define AP_MDSMSRC_ACK_LSB                  (1U << 4)       /* 1b */
+#define AP_L1SMSRC_ACK_LSB                  (1U << 5)       /* 1b */
+#define AP_MD2SRC_ACK_LSB                   (1U << 6)       /* 1b */
+/* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */
+#define SPM2EMI_ENTER_ULPM_LSB              (1U << 0)       /* 1b */
+/* SPM2MD_DVFS_CON (0x10006000+0x438) */
+#define SPM2MD_DVFS_CON_LSB                 (1U << 0)       /* 32b */
+/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
+#define MD2SPM_DVFS_CON_LSB                 (1U << 0)       /* 32b */
+/* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */
+#define SPM_BUS_PROTECT6_MASK_B_LSB         (1U << 0)       /* 32b */
+/* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */
+#define SPM_BUS_PROTECT7_MASK_B_LSB         (1U << 0)       /* 32b */
+/* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */
+#define SPM_BUS_PROTECT8_MASK_B_LSB         (1U << 0)       /* 32b */
+/* SPM_PLL_CON (0x10006000+0x44C) */
+#define SC_MAINPLLOUT_OFF_LSB               (1U << 0)       /* 1b */
+#define SC_UNIPLLOUT_OFF_LSB                (1U << 1)       /* 1b */
+#define SC_MAINPLL_OFF_LSB                  (1U << 4)       /* 1b */
+#define SC_UNIPLL_OFF_LSB                   (1U << 5)       /* 1b */
+#define SC_MAINPLL_S_OFF_LSB                (1U << 8)       /* 1b */
+#define SC_UNIPLL_S_OFF_LSB                 (1U << 9)       /* 1b */
+#define SC_SMI_CK_OFF_LSB                   (1U << 16)      /* 1b */
+#define SC_MD32K_CK_OFF_LSB                 (1U << 17)      /* 1b */
+#define SC_CKSQ1_OFF_LSB                    (1U << 18)      /* 1b */
+#define SC_AXI_MEM_CK_OFF_LSB               (1U << 19)      /* 1b */
+/* CPU_DVFS_REQ (0x10006000+0x450) */
+#define CPU_DVFS_REQ_LSB                    (1U << 0)       /* 32b */
+/* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */
+#define SW_DDR_PST_REQ_LSB                  (1U << 0)       /* 2b */
+#define SW_DDR_PST_ABORT_REQ_LSB            (1U << 2)       /* 2b */
+/* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */
+#define SW_DDR_PST_CH0_LSB                  (1U << 0)       /* 32b */
+/* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */
+#define SW_DDR_PST_CH1_LSB                  (1U << 0)       /* 32b */
+/* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */
+#define SW_DDR_RESERVED_CH0_LSB             (1U << 0)       /* 32b */
+/* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */
+#define SW_DDR_RESERVED_CH1_LSB             (1U << 0)       /* 32b */
+/* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */
+#define SC_DDR_PST_ACK_LSB                  (1U << 0)       /* 2b */
+#define SC_DDR_PST_ABORT_ACK_LSB            (1U << 2)       /* 2b */
+/* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */
+#define SC_DDR_CUR_PST_STA_CH0_LSB          (1U << 0)       /* 32b */
+/* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */
+#define SC_DDR_CUR_PST_STA_CH1_LSB          (1U << 0)       /* 32b */
+/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */
+#define SW_DDR_PST_REQ_SEL_LSB              (1U << 0)       /* 2b */
+#define SW_DDR_PST_SEL_LSB                  (1U << 2)       /* 2b */
+#define SW_DDR_PST_ABORT_REQ_SEL_LSB        (1U << 4)       /* 2b */
+#define SW_DDR_RESERVED_SEL_LSB             (1U << 6)       /* 2b */
+#define SW_DDR_PST_ACK_SEL_LSB              (1U << 8)       /* 2b */
+#define SW_DDR_PST_ABORT_ACK_SEL_LSB        (1U << 10)      /* 2b */
+/* RELAY_DVFS_LEVEL (0x10006000+0x478) */
+#define RELAY_DVFS_LEVEL_LSB                (1U << 0)       /* 32b */
+/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */
+#define SW_PHYPLL_EN_LSB                    (1U << 0)       /* 2b */
+#define SW_DPY_VREF_EN_LSB                  (1U << 2)       /* 2b */
+#define SW_DPY_DLL_CK_EN_LSB                (1U << 4)       /* 2b */
+#define SW_DPY_DLL_EN_LSB                   (1U << 6)       /* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB               (1U << 8)       /* 2b */
+#define SW_MEM_CK_OFF_LSB                   (1U << 10)      /* 2b */
+#define SW_DMSUS_OFF_LSB                    (1U << 12)      /* 2b */
+#define SW_DPY_MODE_SW_LSB                  (1U << 14)      /* 2b */
+#define SW_EMI_CLK_OFF_LSB                  (1U << 16)      /* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB              (1U << 18)      /* 2b */
+#define SW_DR_GATE_RETRY_EN_LSB             (1U << 20)      /* 2b */
+#define SW_DPHY_PRECAL_UP_LSB               (1U << 24)      /* 2b */
+#define SW_DPY_BCLK_ENABLE_LSB              (1U << 26)      /* 2b */
+#define SW_TX_TRACKING_DIS_LSB              (1U << 28)      /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_LSB       (1U << 30)      /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */
+#define SW_SHU_RESTORE_LSB                  (1U << 0)       /* 2b */
+#define SW_DMYRD_MOD_LSB                    (1U << 2)       /* 2b */
+#define SW_DMYRD_INTV_LSB                   (1U << 4)       /* 2b */
+#define SW_DMYRD_EN_LSB                     (1U << 6)       /* 2b */
+#define SW_DRS_DIS_REQ_LSB                  (1U << 8)       /* 2b */
+#define SW_DR_SRAM_LOAD_LSB                 (1U << 10)      /* 2b */
+#define SW_DR_SRAM_RESTORE_LSB              (1U << 12)      /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB      (1U << 14)      /* 2b */
+#define SW_TX_TRACK_RETRY_EN_LSB            (1U << 16)      /* 2b */
+#define SW_DPY_MIDPI_EN_LSB                 (1U << 18)      /* 2b */
+#define SW_DPY_PI_RESETB_EN_LSB             (1U << 20)      /* 2b */
+#define SW_DPY_MCK8X_EN_LSB                 (1U << 22)      /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB        (1U << 24)      /* 4b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB        (1U << 28)      /* 4b */
+/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */
+#define SW_DR_SHU_LEVEL_LSB                 (1U << 0)       /* 2b */
+#define SW_DR_SHU_EN_LSB                    (1U << 2)       /* 1b */
+#define SW_DR_SHORT_QUEUE_LSB               (1U << 3)       /* 1b */
+#define SW_PHYPLL_MODE_SW_LSB               (1U << 4)       /* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB              (1U << 5)       /* 1b */
+#define SW_PHYPLL_SHU_EN_LSB                (1U << 6)       /* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB               (1U << 7)       /* 1b */
+#define SW_DR_RESERVED_0_LSB                (1U << 24)      /* 2b */
+#define SW_DR_RESERVED_1_LSB                (1U << 26)      /* 2b */
+#define SW_DR_RESERVED_2_LSB                (1U << 28)      /* 2b */
+#define SW_DR_RESERVED_3_LSB                (1U << 30)      /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */
+#define SC_DR_SHU_EN_ACK_LSB                (1U << 0)       /* 4b */
+#define SC_EMI_CLK_OFF_ACK_LSB              (1U << 4)       /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB           (1U << 8)       /* 4b */
+#define SC_DRAMC_DFS_STA_LSB                (1U << 12)      /* 4b */
+#define SC_DRS_DIS_ACK_LSB                  (1U << 16)      /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_LSB             (1U << 20)      /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_LSB         (1U << 24)      /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_LSB          (1U << 28)      /* 4b */
+/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */
+#define SW_PHYPLL_EN_SEL_LSB                (1U << 0)       /* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB              (1U << 2)       /* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB            (1U << 4)       /* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB               (1U << 6)       /* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB           (1U << 8)       /* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB               (1U << 10)      /* 2b */
+#define SW_DMSUS_OFF_SEL_LSB                (1U << 12)      /* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB              (1U << 14)      /* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB              (1U << 16)      /* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB          (1U << 18)      /* 2b */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB         (1U << 20)      /* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB           (1U << 24)      /* 2b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB          (1U << 26)      /* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB          (1U << 28)      /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB   (1U << 30)      /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */
+#define SW_SHU_RESTORE_SEL_LSB              (1U << 0)       /* 2b */
+#define SW_DMYRD_MOD_SEL_LSB                (1U << 2)       /* 2b */
+#define SW_DMYRD_INTV_SEL_LSB               (1U << 4)       /* 2b */
+#define SW_DMYRD_EN_SEL_LSB                 (1U << 6)       /* 2b */
+#define SW_DRS_DIS_REQ_SEL_LSB              (1U << 8)       /* 2b */
+#define SW_DR_SRAM_LOAD_SEL_LSB             (1U << 10)      /* 2b */
+#define SW_DR_SRAM_RESTORE_SEL_LSB          (1U << 12)      /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB  (1U << 14)      /* 2b */
+#define SW_TX_TRACK_RETRY_EN_SEL_LSB        (1U << 16)      /* 2b */
+#define SW_DPY_MIDPI_EN_SEL_LSB             (1U << 18)      /* 2b */
+#define SW_DPY_PI_RESETB_EN_SEL_LSB         (1U << 20)      /* 2b */
+#define SW_DPY_MCK8X_EN_SEL_LSB             (1U << 22)      /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB        (1U << 24)      /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */
+#define SW_DR_SHU_LEVEL_SEL_LSB             (1U << 0)       /* 1b */
+#define SW_DR_SHU_EN_SEL_LSB                (1U << 2)       /* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB           (1U << 3)       /* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB           (1U << 4)       /* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB          (1U << 5)       /* 1b */
+#define SW_PHYPLL_SHU_EN_SEL_LSB            (1U << 6)       /* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB           (1U << 7)       /* 1b */
+#define SW_DR_RESERVED_0_SEL_LSB            (1U << 24)      /* 2b */
+#define SW_DR_RESERVED_1_SEL_LSB            (1U << 26)      /* 2b */
+#define SW_DR_RESERVED_2_SEL_LSB            (1U << 28)      /* 2b */
+#define SW_DR_RESERVED_3_SEL_LSB            (1U << 30)      /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */
+#define SC_DR_SHU_EN_ACK_SEL_LSB            (1U << 0)       /* 4b */
+#define SC_EMI_CLK_OFF_ACK_SEL_LSB          (1U << 4)       /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB       (1U << 8)       /* 4b */
+#define SC_DRAMC_DFS_STA_SEL_LSB            (1U << 12)      /* 4b */
+#define SC_DRS_DIS_ACK_SEL_LSB              (1U << 16)      /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_SEL_LSB         (1U << 20)      /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB     (1U << 24)      /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB      (1U << 28)      /* 4b */
+/* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */
+#define SC_DMYRD_EN_MOD_SEL_PCM_LSB         (1U << 0)       /* 1b */
+#define SC_DMYRD_INTV_SEL_PCM_LSB           (1U << 1)       /* 1b */
+#define SC_DMYRD_EN_PCM_LSB                 (1U << 2)       /* 1b */
+#define SC_DRS_DIS_REQ_PCM_LSB              (1U << 3)       /* 1b */
+#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB        (1U << 4)       /* 4b */
+#define SC_DR_GATE_RETRY_EN_PCM_LSB         (1U << 8)       /* 1b */
+#define SC_DR_SHORT_QUEUE_PCM_LSB           (1U << 9)       /* 1b */
+#define SC_DPY_MIDPI_EN_PCM_LSB             (1U << 10)      /* 1b */
+#define SC_DPY_PI_RESETB_EN_PCM_LSB         (1U << 11)      /* 1b */
+#define SC_DPY_MCK8X_EN_PCM_LSB             (1U << 12)      /* 1b */
+#define SC_DR_RESERVED_0_PCM_LSB            (1U << 13)      /* 1b */
+#define SC_DR_RESERVED_1_PCM_LSB            (1U << 14)      /* 1b */
+#define SC_DR_RESERVED_2_PCM_LSB            (1U << 15)      /* 1b */
+#define SC_DR_RESERVED_3_PCM_LSB            (1U << 16)      /* 1b */
+#define SC_DMDRAMCSHU_ACK_ALL_LSB           (1U << 24)      /* 1b */
+#define SC_EMI_CLK_OFF_ACK_ALL_LSB          (1U << 25)      /* 1b */
+#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB       (1U << 26)      /* 1b */
+#define SC_DRAMC_DFS_STA_ALL_LSB            (1U << 27)      /* 1b */
+#define SC_DRS_DIS_ACK_ALL_LSB              (1U << 28)      /* 1b */
+#define SC_DR_SRAM_LOAD_ACK_ALL_LSB         (1U << 29)      /* 1b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB     (1U << 30)      /* 1b */
+#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB      (1U << 31)      /* 1b */
+/* SPM_DVFS_LEVEL (0x10006000+0x4A4) */
+#define SPM_DVFS_LEVEL_LSB                  (1U << 0)       /* 32b */
+/* SPM_CIRQ_CON (0x10006000+0x4A8) */
+#define CIRQ_CLK_SEL_LSB                    (1U << 0)       /* 1b */
+/* SPM_DVFS_MISC (0x10006000+0x4AC) */
+#define MSDC_DVFS_REQUEST_LSB               (1U << 0)       /* 1b */
+#define SPM2EMI_SLP_PROT_EN_LSB             (1U << 1)       /* 1b */
+#define SPM_DVFS_FORCE_ENABLE_LSB           (1U << 2)       /* 1b */
+#define FORCE_DVFS_WAKE_LSB                 (1U << 3)       /* 1b */
+#define SPM_DVFSRC_ENABLE_LSB               (1U << 4)       /* 1b */
+#define SPM_DVFS_DONE_LSB                   (1U << 5)       /* 1b */
+#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB    (1U << 6)       /* 1b */
+#define SPM2RC_EVENT_ABORT_LSB              (1U << 7)       /* 1b */
+#define EMI_SLP_IDLE_LSB                    (1U << 14)      /* 1b */
+#define SDIO_READY_TO_SPM_LSB               (1U << 15)      /* 1b */
+/* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */
+#define VS1_INIT_LEVEL_LSB                  (1U << 0)       /* 2b */
+#define VS1_INIT_LSB                        (1U << 2)       /* 1b */
+#define VS1_CURR_LEVEL_LSB                  (1U << 3)       /* 2b */
+#define VS1_NEXT_LEVEL_LSB                  (1U << 5)       /* 2b */
+#define VS1_VOTE_LEVEL_LSB                  (1U << 7)       /* 2b */
+#define VS1_TRIGGER_LSB                     (1U << 9)       /* 1b */
+#define VS2_INIT_LEVEL_LSB                  (1U << 10)      /* 3b */
+#define VS2_INIT_LSB                        (1U << 13)      /* 1b */
+#define VS2_CURR_LEVEL_LSB                  (1U << 14)      /* 3b */
+#define VS2_NEXT_LEVEL_LSB                  (1U << 17)      /* 3b */
+#define VS2_VOTE_LEVEL_LSB                  (1U << 20)      /* 3b */
+#define VS2_TRIGGER_LSB                     (1U << 23)      /* 1b */
+#define VS1_FORCE_LSB                       (1U << 24)      /* 1b */
+#define VS2_FORCE_LSB                       (1U << 25)      /* 1b */
+#define VS1_VOTE_LEVEL_FORCE_LSB            (1U << 26)      /* 2b */
+#define VS2_VOTE_LEVEL_FORCE_LSB            (1U << 28)      /* 3b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB    (1U << 0)       /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB    (1U << 0)       /* 32b */
+/* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */
+#define PWR_STATUS_MASK_REQ_0_LSB           (1U << 0)       /* 32b */
+/* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */
+#define PWR_STATUS_MASK_REQ_1_LSB           (1U << 0)       /* 32b */
+/* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */
+#define PWR_STATUS_MASK_REQ_2_LSB           (1U << 0)       /* 32b */
+/* SPM_CG_CHECK_CON (0x10006000+0x4F0) */
+#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB      (1U << 0)       /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB      (1U << 8)       /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB      (1U << 16)      /* 5b */
+#define AUDIOSYS_BUSY_MASK_REQ_0_LSB        (1U << 24)      /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_1_LSB        (1U << 25)      /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_2_LSB        (1U << 26)      /* 1b */
+#define SSUSB_BUSY_MASK_REQ_0_LSB           (1U << 27)      /* 1b */
+#define SSUSB_BUSY_MASK_REQ_1_LSB           (1U << 28)      /* 1b */
+#define SSUSB_BUSY_MASK_REQ_2_LSB           (1U << 29)      /* 1b */
+/* SPM_SRC_RDY_STA (0x10006000+0x4F4) */
+#define SPM_INFRA_INTERNAL_ACK_LSB          (1U << 0)       /* 1b */
+#define SPM_VRF18_INTERNAL_ACK_LSB          (1U << 1)       /* 1b */
+/* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */
+#define SPM_DFS_LEVEL_LSB                   (1U << 0)       /* 16b */
+#define SPM_DVS_LEVEL_LSB                   (1U << 16)      /* 16b */
+/* SPM_FORCE_DVFS (0x10006000+0x4FC) */
+#define FORCE_DVFS_LEVEL_LSB                (1U << 0)       /* 32b */
+/* SRCLKEN_RC_CFG (0x10006000+0x500) */
+#define SRCLKEN_RC_CFG_LSB                  (1U << 0)       /* 32b */
+/* RC_CENTRAL_CFG1 (0x10006000+0x504) */
+#define RC_CENTRAL_CFG1_LSB                 (1U << 0)       /* 32b */
+/* RC_CENTRAL_CFG2 (0x10006000+0x508) */
+#define RC_CENTRAL_CFG2_LSB                 (1U << 0)       /* 32b */
+/* RC_CMD_ARB_CFG (0x10006000+0x50C) */
+#define RC_CMD_ARB_CFG_LSB                  (1U << 0)       /* 32b */
+/* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */
+#define RC_PMIC_RCEN_ADDR_LSB               (1U << 0)       /* 16b */
+#define RC_PMIC_RCEN_RESERVE_LSB            (1U << 16)      /* 16b */
+/* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */
+#define RC_PMIC_RCEN_SET_ADDR_LSB           (1U << 0)       /* 16b */
+#define RC_PMIC_RCEN_CLR_ADDR_LSB           (1U << 16)      /* 16b */
+/* RC_DCXO_FPM_CFG (0x10006000+0x518) */
+#define RC_DCXO_FPM_CFG_LSB                 (1U << 0)       /* 32b */
+/* RC_CENTRAL_CFG3 (0x10006000+0x51C) */
+#define RC_CENTRAL_CFG3_LSB                 (1U << 0)       /* 32b */
+/* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */
+#define RC_M00_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+#define RC_SW_SRCLKEN_RC                    (1U << 3)       /* 1b */
+#define RC_SW_SRCLKEN_FPM                   (1U << 4)       /* 1b */
+/* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */
+#define RC_M01_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */
+#define RC_M02_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */
+#define RC_M03_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */
+#define RC_M04_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */
+#define RC_M05_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */
+#define RC_M06_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */
+#define RC_M07_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */
+#define RC_M08_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */
+#define RC_M09_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */
+#define RC_M10_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */
+#define RC_M11_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */
+#define RC_M12_SRCLKEN_CFG_LSB              (1U << 0)       /* 32b */
+/* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */
+#define RC_SRCLKEN_SW_CON_CFG_LSB           (1U << 0)       /* 32b */
+/* RC_CENTRAL_CFG4 (0x10006000+0x558) */
+#define RC_CENTRAL_CFG4_LSB                 (1U << 0)       /* 32b */
+/* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */
+#define RC_PROTOCOL_CHK_CFG_LSB             (1U << 0)       /* 32b */
+/* RC_DEBUG_CFG (0x10006000+0x564) */
+#define RC_DEBUG_CFG_LSB                    (1U << 0)       /* 32b */
+/* RC_MISC_0 (0x10006000+0x5B4) */
+#define SRCCLKENO_LSB                       (1U << 0)       /* 2b */
+#define PCM_SRCCLKENO_LSB                   (1U << 3)       /* 2b */
+#define RC_VREQ_LSB                         (1U << 5)       /* 1b */
+#define RC_SPM_SRCCLKENO_0_ACK_LSB          (1U << 6)       /* 1b */
+/* RC_SPM_CTRL (0x10006000+0x448) */
+#define SPM_AP_26M_RDY_LSB                  (1U << 0)       /* 1b */
+#define KEEP_RC_SPI_ACTIVE_LSB              (1U << 1)       /* 1b */
+#define SPM2RC_DMY_CTRL_LSB                 (1U << 2)       /* 6b */
+/* SUBSYS_INTF_CFG (0x10006000+0x5BC) */
+#define SRCLKEN_FPM_MASK_B_LSB              (1U << 0)       /* 13b */
+#define SRCLKEN_BBLPM_MASK_B_LSB            (1U << 16)      /* 13b */
+/* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */
+#define PCM_WDT_LATCH_25_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */
+#define PCM_WDT_LATCH_26_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */
+#define PCM_WDT_LATCH_27_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */
+#define PCM_WDT_LATCH_28_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */
+#define PCM_WDT_LATCH_29_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */
+#define PCM_WDT_LATCH_30_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */
+#define PCM_WDT_LATCH_31_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */
+#define PCM_WDT_LATCH_32_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */
+#define PCM_WDT_LATCH_33_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */
+#define PCM_WDT_LATCH_34_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */
+#define PCM_WDT_LATCH_35_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */
+#define PCM_WDT_LATCH_36_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */
+#define PCM_WDT_LATCH_37_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */
+#define PCM_WDT_LATCH_38_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */
+#define PCM_WDT_LATCH_39_LSB                (1U << 0)       /* 32b */
+/* SPM_SW_FLAG_0 (0x10006000+0x600) */
+#define SPM_SW_FLAG_LSB                     (1U << 0)       /* 32b */
+/* SPM_SW_DEBUG_0 (0x10006000+0x604) */
+#define SPM_SW_DEBUG_0_LSB                  (1U << 0)       /* 32b */
+/* SPM_SW_FLAG_1 (0x10006000+0x608) */
+#define SPM_SW_FLAG_1_LSB                   (1U << 0)       /* 32b */
+/* SPM_SW_DEBUG_1 (0x10006000+0x60C) */
+#define SPM_SW_DEBUG_1_LSB                  (1U << 0)       /* 32b */
+/* SPM_SW_RSV_0 (0x10006000+0x610) */
+#define SPM_SW_RSV_0_LSB                    (1U << 0)       /* 32b */
+/* SPM_SW_RSV_1 (0x10006000+0x614) */
+#define SPM_SW_RSV_1_LSB                    (1U << 0)       /* 32b */
+/* SPM_SW_RSV_2 (0x10006000+0x618) */
+#define SPM_SW_RSV_2_LSB                    (1U << 0)       /* 32b */
+/* SPM_SW_RSV_3 (0x10006000+0x61C) */
+#define SPM_SW_RSV_3_LSB                    (1U << 0)       /* 32b */
+/* SPM_SW_RSV_4 (0x10006000+0x620) */
+#define SPM_SW_RSV_4_LSB                    (1U << 0)       /* 32b */
+/* SPM_SW_RSV_5 (0x10006000+0x624) */
+#define SPM_SW_RSV_5_LSB                    (1U << 0)       /* 32b */
+/* SPM_SW_RSV_6 (0x10006000+0x628) */
+#define SPM_SW_RSV_6_LSB                    (1U << 0)       /* 32b */
+/* SPM_SW_RSV_7 (0x10006000+0x62C) */
+#define SPM_SW_RSV_7_LSB                    (1U << 0)       /* 32b */
+/* SPM_SW_RSV_8 (0x10006000+0x630) */
+#define SPM_SW_RSV_8_LSB                    (1U << 0)       /* 32b */
+/* SPM_BK_WAKE_EVENT (0x10006000+0x634) */
+#define SPM_BK_WAKE_EVENT_LSB               (1U << 0)       /* 32b */
+/* SPM_BK_VTCXO_DUR (0x10006000+0x638) */
+#define SPM_BK_VTCXO_DUR_LSB                (1U << 0)       /* 32b */
+/* SPM_BK_WAKE_MISC (0x10006000+0x63C) */
+#define SPM_BK_WAKE_MISC_LSB                (1U << 0)       /* 32b */
+/* SPM_BK_PCM_TIMER (0x10006000+0x640) */
+#define SPM_BK_PCM_TIMER_LSB                (1U << 0)       /* 32b */
+/* SPM_RSV_CON_0 (0x10006000+0x650) */
+#define SPM_RSV_CON_0_LSB                   (1U << 0)       /* 32b */
+/* SPM_RSV_CON_1 (0x10006000+0x654) */
+#define SPM_RSV_CON_1_LSB                   (1U << 0)       /* 32b */
+/* SPM_RSV_STA_0 (0x10006000+0x658) */
+#define SPM_RSV_STA_0_LSB                   (1U << 0)       /* 32b */
+/* SPM_RSV_STA_1 (0x10006000+0x65C) */
+#define SPM_RSV_STA_1_LSB                   (1U << 0)       /* 32b */
+/* SPM_SPARE_CON (0x10006000+0x660) */
+#define SPM_SPARE_CON_LSB                   (1U << 0)       /* 32b */
+/* SPM_SPARE_CON_SET (0x10006000+0x664) */
+#define SPM_SPARE_CON_SET_LSB               (1U << 0)       /* 32b */
+/* SPM_SPARE_CON_CLR (0x10006000+0x668) */
+#define SPM_SPARE_CON_CLR_LSB               (1U << 0)       /* 32b */
+/* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */
+#define SPM_CROSS_WAKE_M00_REQ_LSB          (1U << 0)       /* 4b */
+#define SPM_CROSS_WAKE_M00_CHK_LSB          (1U << 4)       /* 4b */
+/* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */
+#define SPM_CROSS_WAKE_M01_REQ_LSB          (1U << 0)       /* 4b */
+#define SPM_CROSS_WAKE_M01_CHK_LSB          (1U << 4)       /* 4b */
+/* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */
+#define SPM_CROSS_WAKE_M02_REQ_LSB          (1U << 0)       /* 4b */
+#define SPM_CROSS_WAKE_M02_CHK_LSB          (1U << 4)       /* 4b */
+/* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */
+#define SPM_CROSS_WAKE_M03_REQ_LSB          (1U << 0)       /* 4b */
+#define SPM_CROSS_WAKE_M03_CHK_LSB          (1U << 4)       /* 4b */
+/* SCP_VCORE_LEVEL (0x10006000+0x67C) */
+#define SCP_VCORE_LEVEL_LSB                 (1U << 0)       /* 16b */
+/* SC_MM_CK_SEL_CON (0x10006000+0x680) */
+#define SC_MM_CK_SEL_LSB                    (1U << 0)       /* 4b */
+#define SC_MM_CK_SEL_EN_LSB                 (1U << 4)       /* 1b */
+/* SPARE_ACK_MASK (0x10006000+0x684) */
+#define SPARE_ACK_MASK_B_LSB                (1U << 0)       /* 32b */
+/* SPM_DV_CON_0 (0x10006000+0x68C) */
+#define SPM_DV_CON_0_LSB                    (1U << 0)       /* 32b */
+/* SPM_DV_CON_1 (0x10006000+0x690) */
+#define SPM_DV_CON_1_LSB                    (1U << 0)       /* 32b */
+/* SPM_DV_STA (0x10006000+0x694) */
+#define SPM_DV_STA_LSB                      (1U << 0)       /* 32b */
+/* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */
+#define CONN_XOWCN_DEBUG_EN_LSB             (1U << 0)       /* 1b */
+/* SPM_SEMA_M0 (0x10006000+0x69C) */
+#define SPM_SEMA_M0_LSB                     (1U << 0)       /* 8b */
+/* SPM_SEMA_M1 (0x10006000+0x6A0) */
+#define SPM_SEMA_M1_LSB                     (1U << 0)       /* 8b */
+/* SPM_SEMA_M2 (0x10006000+0x6A4) */
+#define SPM_SEMA_M2_LSB                     (1U << 0)       /* 8b */
+/* SPM_SEMA_M3 (0x10006000+0x6A8) */
+#define SPM_SEMA_M3_LSB                     (1U << 0)       /* 8b */
+/* SPM_SEMA_M4 (0x10006000+0x6AC) */
+#define SPM_SEMA_M4_LSB                     (1U << 0)       /* 8b */
+/* SPM_SEMA_M5 (0x10006000+0x6B0) */
+#define SPM_SEMA_M5_LSB                     (1U << 0)       /* 8b */
+/* SPM_SEMA_M6 (0x10006000+0x6B4) */
+#define SPM_SEMA_M6_LSB                     (1U << 0)       /* 8b */
+/* SPM_SEMA_M7 (0x10006000+0x6B8) */
+#define SPM_SEMA_M7_LSB                     (1U << 0)       /* 8b */
+/* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */
+#define SPM2ADSP_MAILBOX_LSB                (1U << 0)       /* 32b */
+/* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */
+#define ADSP2SPM_MAILBOX_LSB                (1U << 0)       /* 32b */
+/* SPM_ADSP_IRQ (0x10006000+0x6C4) */
+#define SC_SPM2ADSP_WAKEUP_LSB              (1U << 0)       /* 1b */
+#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4)       /* 1b */
+/* SPM_MD32_IRQ (0x10006000+0x6C8) */
+#define SC_SPM2SSPM_WAKEUP_LSB              (1U << 0)       /* 4b */
+#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4)       /* 4b */
+/* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */
+#define SPM2PMCU_MAILBOX_0_LSB              (1U << 0)       /* 32b */
+/* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */
+#define SPM2PMCU_MAILBOX_1_LSB              (1U << 0)       /* 32b */
+/* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */
+#define SPM2PMCU_MAILBOX_2_LSB              (1U << 0)       /* 32b */
+/* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */
+#define SPM2PMCU_MAILBOX_3_LSB              (1U << 0)       /* 32b */
+/* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */
+#define PMCU2SPM_MAILBOX_0_LSB              (1U << 0)       /* 32b */
+/* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */
+#define PMCU2SPM_MAILBOX_1_LSB              (1U << 0)       /* 32b */
+/* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */
+#define PMCU2SPM_MAILBOX_2_LSB              (1U << 0)       /* 32b */
+/* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */
+#define PMCU2SPM_MAILBOX_3_LSB              (1U << 0)       /* 32b */
+/* UFS_PSRI_SW (0x10006000+0x6EC) */
+#define UFS_PSRI_SW_LSB                     (1U << 0)       /* 1b */
+/* UFS_PSRI_SW_SET (0x10006000+0x6F0) */
+#define UFS_PSRI_SW_SET_LSB                 (1U << 0)       /* 1b */
+/* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */
+#define UFS_PSRI_SW_CLR_LSB                 (1U << 0)       /* 1b */
+/* SPM_AP_SEMA (0x10006000+0x6F8) */
+#define SPM_AP_SEMA_LSB                     (1U << 0)       /* 1b */
+/* SPM_SPM_SEMA (0x10006000+0x6FC) */
+#define SPM_SPM_SEMA_LSB                    (1U << 0)       /* 1b */
+/* SPM_DVFS_CON (0x10006000+0x700) */
+#define SPM_DVFS_CON_LSB                    (1U << 0)       /* 32b */
+/* SPM_DVFS_CON_STA (0x10006000+0x704) */
+#define SPM_DVFS_CON_STA_LSB                (1U << 0)       /* 32b */
+/* SPM_PMIC_SPMI_CON (0x10006000+0x708) */
+#define SPM_PMIC_SPMI_CMD_LSB               (1U << 0)       /* 2b */
+#define SPM_PMIC_SPMI_SLAVEID_LSB           (1U << 2)       /* 4b */
+#define SPM_PMIC_SPMI_PMIFID_LSB            (1U << 6)       /* 1b */
+#define SPM_PMIC_SPMI_DBCNT_LSB             (1U << 7)       /* 1b */
+/* SPM_DVFS_CMD0 (0x10006000+0x710) */
+#define SPM_DVFS_CMD0_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD1 (0x10006000+0x714) */
+#define SPM_DVFS_CMD1_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD2 (0x10006000+0x718) */
+#define SPM_DVFS_CMD2_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD3 (0x10006000+0x71C) */
+#define SPM_DVFS_CMD3_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD4 (0x10006000+0x720) */
+#define SPM_DVFS_CMD4_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD5 (0x10006000+0x724) */
+#define SPM_DVFS_CMD5_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD6 (0x10006000+0x728) */
+#define SPM_DVFS_CMD6_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD7 (0x10006000+0x72C) */
+#define SPM_DVFS_CMD7_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD8 (0x10006000+0x730) */
+#define SPM_DVFS_CMD8_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD9 (0x10006000+0x734) */
+#define SPM_DVFS_CMD9_LSB                   (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD10 (0x10006000+0x738) */
+#define SPM_DVFS_CMD10_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD11 (0x10006000+0x73C) */
+#define SPM_DVFS_CMD11_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD12 (0x10006000+0x740) */
+#define SPM_DVFS_CMD12_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD13 (0x10006000+0x744) */
+#define SPM_DVFS_CMD13_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD14 (0x10006000+0x748) */
+#define SPM_DVFS_CMD14_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD15 (0x10006000+0x74C) */
+#define SPM_DVFS_CMD15_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD16 (0x10006000+0x750) */
+#define SPM_DVFS_CMD16_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD17 (0x10006000+0x754) */
+#define SPM_DVFS_CMD17_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD18 (0x10006000+0x758) */
+#define SPM_DVFS_CMD18_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD19 (0x10006000+0x75C) */
+#define SPM_DVFS_CMD19_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD20 (0x10006000+0x760) */
+#define SPM_DVFS_CMD20_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD21 (0x10006000+0x764) */
+#define SPM_DVFS_CMD21_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD22 (0x10006000+0x768) */
+#define SPM_DVFS_CMD22_LSB                  (1U << 0)       /* 32b */
+/* SPM_DVFS_CMD23 (0x10006000+0x76C) */
+#define SPM_DVFS_CMD23_LSB                  (1U << 0)       /* 32b */
+/* SYS_TIMER_VALUE_L (0x10006000+0x770) */
+#define SYS_TIMER_VALUE_L_LSB               (1U << 0)       /* 32b */
+/* SYS_TIMER_VALUE_H (0x10006000+0x774) */
+#define SYS_TIMER_VALUE_H_LSB               (1U << 0)       /* 32b */
+/* SYS_TIMER_START_L (0x10006000+0x778) */
+#define SYS_TIMER_START_L_LSB               (1U << 0)       /* 32b */
+/* SYS_TIMER_START_H (0x10006000+0x77C) */
+#define SYS_TIMER_START_H_LSB               (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */
+#define SYS_TIMER_LATCH_L_00_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */
+#define SYS_TIMER_LATCH_H_00_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */
+#define SYS_TIMER_LATCH_L_01_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */
+#define SYS_TIMER_LATCH_H_01_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */
+#define SYS_TIMER_LATCH_L_02_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */
+#define SYS_TIMER_LATCH_H_02_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */
+#define SYS_TIMER_LATCH_L_03_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */
+#define SYS_TIMER_LATCH_H_03_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */
+#define SYS_TIMER_LATCH_L_04_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */
+#define SYS_TIMER_LATCH_H_04_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */
+#define SYS_TIMER_LATCH_L_05_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */
+#define SYS_TIMER_LATCH_H_05_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */
+#define SYS_TIMER_LATCH_L_06_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */
+#define SYS_TIMER_LATCH_H_06_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */
+#define SYS_TIMER_LATCH_L_07_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */
+#define SYS_TIMER_LATCH_H_07_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */
+#define SYS_TIMER_LATCH_L_08_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */
+#define SYS_TIMER_LATCH_H_08_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */
+#define SYS_TIMER_LATCH_L_09_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */
+#define SYS_TIMER_LATCH_H_09_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */
+#define SYS_TIMER_LATCH_L_10_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */
+#define SYS_TIMER_LATCH_H_10_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */
+#define SYS_TIMER_LATCH_L_11_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */
+#define SYS_TIMER_LATCH_H_11_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */
+#define SYS_TIMER_LATCH_L_12_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */
+#define SYS_TIMER_LATCH_H_12_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */
+#define SYS_TIMER_LATCH_L_13_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */
+#define SYS_TIMER_LATCH_H_13_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */
+#define SYS_TIMER_LATCH_L_14_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */
+#define SYS_TIMER_LATCH_H_14_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */
+#define SYS_TIMER_LATCH_L_15_LSB            (1U << 0)       /* 32b */
+/* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */
+#define SYS_TIMER_LATCH_H_15_LSB            (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_0 (0x10006000+0x800) */
+#define PCM_WDT_LATCH_0_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_1 (0x10006000+0x804) */
+#define PCM_WDT_LATCH_1_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_2 (0x10006000+0x808) */
+#define PCM_WDT_LATCH_2_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */
+#define PCM_WDT_LATCH_3_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_4 (0x10006000+0x810) */
+#define PCM_WDT_LATCH_4_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_5 (0x10006000+0x814) */
+#define PCM_WDT_LATCH_5_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_6 (0x10006000+0x818) */
+#define PCM_WDT_LATCH_6_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */
+#define PCM_WDT_LATCH_7_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_8 (0x10006000+0x820) */
+#define PCM_WDT_LATCH_8_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_9 (0x10006000+0x824) */
+#define PCM_WDT_LATCH_9_LSB                 (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_10 (0x10006000+0x828) */
+#define PCM_WDT_LATCH_10_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_11 (0x10006000+0x82C) */
+#define PCM_WDT_LATCH_11_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_12 (0x10006000+0x830) */
+#define PCM_WDT_LATCH_12_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_13 (0x10006000+0x834) */
+#define PCM_WDT_LATCH_13_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_14 (0x10006000+0x838) */
+#define PCM_WDT_LATCH_14_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_15 (0x10006000+0x83C) */
+#define PCM_WDT_LATCH_15_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_16 (0x10006000+0x840) */
+#define PCM_WDT_LATCH_16_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_17 (0x10006000+0x844) */
+#define PCM_WDT_LATCH_17_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_18 (0x10006000+0x848) */
+#define PCM_WDT_LATCH_18_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */
+#define PCM_WDT_LATCH_SPARE_0_LSB           (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */
+#define PCM_WDT_LATCH_SPARE_1_LSB           (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */
+#define PCM_WDT_LATCH_SPARE_2_LSB           (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */
+#define PCM_WDT_LATCH_CONN_0_LSB            (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */
+#define PCM_WDT_LATCH_CONN_1_LSB            (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */
+#define PCM_WDT_LATCH_CONN_2_LSB            (1U << 0)       /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB    (1U << 0)       /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB    (1U << 0)       /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB    (1U << 0)       /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */
+#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB    (1U << 0)       /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB    (1U << 0)       /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB    (1U << 0)       /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB    (1U << 0)       /* 32b */
+/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */
+#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB  (1U << 0)       /* 32b */
+/* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */
+#define SPM_ACK_CHK_SW_EN_0_LSB             (1U << 0)       /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_0_LSB           (1U << 1)       /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_0_LSB         (1U << 2)       /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_0_LSB           (1U << 3)       /* 1b */
+#define SPM_ACK_CHK_STA_EN_0_LSB            (1U << 4)       /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_0_LSB         (1U << 5)       /* 1b */
+#define SPM_ACK_CHK_WDT_EN_0_LSB            (1U << 6)       /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB  (1U << 7)       /* 1b */
+#define SPM_ACK_CHK_HW_EN_0_LSB             (1U << 8)       /* 1b */
+#define SPM_ACK_CHK_HW_MODE_0_LSB           (1U << 9)       /* 3b */
+#define SPM_ACK_CHK_FAIL_0_LSB              (1U << 15)      /* 1b */
+/* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB    (1U << 0)       /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB    (1U << 16)      /* 16b */
+/* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0)       /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5)       /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16)      /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21)      /* 3b */
+/* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_0_LSB         (1U << 0)       /* 16b */
+#define SPM_ACK_CHK_TIMER_0_LSB             (1U << 16)      /* 16b */
+/* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */
+#define SPM_ACK_CHK_STA_0_LSB               (1U << 0)       /* 32b */
+/* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */
+#define SPM_ACK_CHK_SWINT_EN_0_LSB          (1U << 0)       /* 32b */
+/* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */
+#define SPM_ACK_CHK_SW_EN_1_LSB             (1U << 0)       /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_1_LSB           (1U << 1)       /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_1_LSB         (1U << 2)       /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_1_LSB           (1U << 3)       /* 1b */
+#define SPM_ACK_CHK_STA_EN_1_LSB            (1U << 4)       /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_1_LSB         (1U << 5)       /* 1b */
+#define SPM_ACK_CHK_WDT_EN_1_LSB            (1U << 6)       /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB  (1U << 7)       /* 1b */
+#define SPM_ACK_CHK_HW_EN_1_LSB             (1U << 8)       /* 1b */
+#define SPM_ACK_CHK_HW_MODE_1_LSB           (1U << 9)       /* 3b */
+#define SPM_ACK_CHK_FAIL_1_LSB              (1U << 15)      /* 1b */
+/* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB    (1U << 0)       /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB    (1U << 16)      /* 16b */
+/* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0)       /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5)       /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16)      /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21)      /* 3b */
+/* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */
+#define SPM_ACK_CHK_TIMER_VAL_1_LSB         (1U << 0)       /* 16b */
+#define SPM_ACK_CHK_TIMER_1_LSB             (1U << 16)      /* 16b */
+/* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */
+#define SPM_ACK_CHK_STA_1_LSB               (1U << 0)       /* 32b */
+/* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */
+#define SPM_ACK_CHK_SWINT_EN_1_LSB          (1U << 0)       /* 32b */
+/* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */
+#define SPM_ACK_CHK_SW_EN_2_LSB             (1U << 0)       /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_2_LSB           (1U << 1)       /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_2_LSB         (1U << 2)       /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_2_LSB           (1U << 3)       /* 1b */
+#define SPM_ACK_CHK_STA_EN_2_LSB            (1U << 4)       /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_2_LSB         (1U << 5)       /* 1b */
+#define SPM_ACK_CHK_WDT_EN_2_LSB            (1U << 6)       /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB  (1U << 7)       /* 1b */
+#define SPM_ACK_CHK_HW_EN_2_LSB             (1U << 8)       /* 1b */
+#define SPM_ACK_CHK_HW_MODE_2_LSB           (1U << 9)       /* 3b */
+#define SPM_ACK_CHK_FAIL_2_LSB              (1U << 15)      /* 1b */
+/* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB    (1U << 0)       /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB    (1U << 16)      /* 16b */
+/* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0)       /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5)       /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16)      /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21)      /* 3b */
+/* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */
+#define SPM_ACK_CHK_TIMER_VAL_2_LSB         (1U << 0)       /* 16b */
+#define SPM_ACK_CHK_TIMER_2_LSB             (1U << 16)      /* 16b */
+/* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */
+#define SPM_ACK_CHK_STA_2_LSB               (1U << 0)       /* 32b */
+/* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */
+#define SPM_ACK_CHK_SWINT_EN_2_LSB          (1U << 0)       /* 32b */
+/* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */
+#define SPM_ACK_CHK_SW_EN_3_LSB             (1U << 0)       /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_3_LSB           (1U << 1)       /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_3_LSB         (1U << 2)       /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_3_LSB           (1U << 3)       /* 1b */
+#define SPM_ACK_CHK_STA_EN_3_LSB            (1U << 4)       /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_3_LSB         (1U << 5)       /* 1b */
+#define SPM_ACK_CHK_WDT_EN_3_LSB            (1U << 6)       /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB  (1U << 7)       /* 1b */
+#define SPM_ACK_CHK_HW_EN_3_LSB             (1U << 8)       /* 1b */
+#define SPM_ACK_CHK_HW_MODE_3_LSB           (1U << 9)       /* 3b */
+#define SPM_ACK_CHK_FAIL_3_LSB              (1U << 15)      /* 1b */
+/* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB    (1U << 0)       /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB    (1U << 16)      /* 16b */
+/* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0)       /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5)       /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16)      /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21)      /* 3b */
+/* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */
+#define SPM_ACK_CHK_TIMER_VAL_3_LSB         (1U << 0)       /* 16b */
+#define SPM_ACK_CHK_TIMER_3_LSB             (1U << 16)      /* 16b */
+/* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */
+#define SPM_ACK_CHK_STA_3_LSB               (1U << 0)       /* 32b */
+/* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */
+#define SPM_ACK_CHK_SWINT_EN_3_LSB          (1U << 0)       /* 32b */
+/* SPM_COUNTER_0 (0x10006000+0x978) */
+#define SPM_COUNTER_VAL_0_LSB               (1U << 0)       /* 14b */
+#define SPM_COUNTER_OUT_0_LSB               (1U << 14)      /* 14b */
+#define SPM_COUNTER_EN_0_LSB                (1U << 28)      /* 1b */
+#define SPM_COUNTER_CLR_0_LSB               (1U << 29)      /* 1b */
+#define SPM_COUNTER_TIMEOUT_0_LSB           (1U << 30)      /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_0_LSB         (1U << 31)      /* 1b */
+/* SPM_COUNTER_1 (0x10006000+0x97C) */
+#define SPM_COUNTER_VAL_1_LSB               (1U << 0)       /* 14b */
+#define SPM_COUNTER_OUT_1_LSB               (1U << 14)      /* 14b */
+#define SPM_COUNTER_EN_1_LSB                (1U << 28)      /* 1b */
+#define SPM_COUNTER_CLR_1_LSB               (1U << 29)      /* 1b */
+#define SPM_COUNTER_TIMEOUT_1_LSB           (1U << 30)      /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_1_LSB         (1U << 31)      /* 1b */
+/* SPM_COUNTER_2 (0x10006000+0x980) */
+#define SPM_COUNTER_VAL_2_LSB               (1U << 0)       /* 14b */
+#define SPM_COUNTER_OUT_2_LSB               (1U << 14)      /* 14b */
+#define SPM_COUNTER_EN_2_LSB                (1U << 28)      /* 1b */
+#define SPM_COUNTER_CLR_2_LSB               (1U << 29)      /* 1b */
+#define SPM_COUNTER_TIMEOUT_2_LSB           (1U << 30)      /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_2_LSB         (1U << 31)      /* 1b */
+/* SYS_TIMER_CON (0x10006000+0x98C) */
+#define SYS_TIMER_START_EN_LSB              (1U << 0)       /* 1b */
+#define SYS_TIMER_LATCH_EN_LSB              (1U << 1)       /* 1b */
+#define SYS_TIMER_ID_LSB                    (1U << 8)       /* 8b */
+#define SYS_TIMER_VALID_LSB                 (1U << 31)      /* 1b */
+/* RC_FSM_STA_0 (0x10006000+0xE00) */
+#define RC_FSM_STA_0_LSB                    (1U << 0)       /* 32b */
+/* RC_CMD_STA_0 (0x10006000+0xE04) */
+#define RC_CMD_STA_0_LSB                    (1U << 0)       /* 32b */
+/* RC_CMD_STA_1 (0x10006000+0xE08) */
+#define RC_CMD_STA_1_LSB                    (1U << 0)       /* 32b */
+/* RC_SPI_STA_0 (0x10006000+0xE0C) */
+#define RC_SPI_STA_0_LSB                    (1U << 0)       /* 32b */
+/* RC_PI_PO_STA_0 (0x10006000+0xE10) */
+#define RC_PI_PO_STA_0_LSB                  (1U << 0)       /* 32b */
+/* RC_M00_REQ_STA_0 (0x10006000+0xE14) */
+#define RC_M00_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */
+#define RC_M01_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M02_REQ_STA_0 (0x10006000+0xE20) */
+#define RC_M02_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M03_REQ_STA_0 (0x10006000+0xE24) */
+#define RC_M03_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M04_REQ_STA_0 (0x10006000+0xE28) */
+#define RC_M04_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */
+#define RC_M05_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M06_REQ_STA_0 (0x10006000+0xE30) */
+#define RC_M06_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M07_REQ_STA_0 (0x10006000+0xE34) */
+#define RC_M07_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M08_REQ_STA_0 (0x10006000+0xE38) */
+#define RC_M08_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */
+#define RC_M09_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M10_REQ_STA_0 (0x10006000+0xE40) */
+#define RC_M10_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M11_REQ_STA_0 (0x10006000+0xE44) */
+#define RC_M11_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_M12_REQ_STA_0 (0x10006000+0xE48) */
+#define RC_M12_REQ_STA_0_LSB                (1U << 0)       /* 32b */
+/* RC_DEBUG_STA_0 (0x10006000+0xE4C) */
+#define RC_DEBUG_STA_0_LSB                  (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */
+#define RO_PMRC_TRACE_00_LSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */
+#define RO_PMRC_TRACE_00_MSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */
+#define RO_PMRC_TRACE_01_LSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */
+#define RO_PMRC_TRACE_01_MSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */
+#define RO_PMRC_TRACE_02_LSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */
+#define RO_PMRC_TRACE_02_MSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */
+#define RO_PMRC_TRACE_03_LSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */
+#define RO_PMRC_TRACE_03_MSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */
+#define RO_PMRC_TRACE_04_LSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */
+#define RO_PMRC_TRACE_04_MSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */
+#define RO_PMRC_TRACE_05_LSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */
+#define RO_PMRC_TRACE_05_MSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */
+#define RO_PMRC_TRACE_06_LSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */
+#define RO_PMRC_TRACE_06_MSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */
+#define RO_PMRC_TRACE_07_LSB_LSB            (1U << 0)       /* 32b */
+/* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */
+#define RO_PMRC_TRACE_07_MSB_LSB            (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */
+#define RC_SYS_TIMER_LATCH_L_00_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */
+#define RC_SYS_TIMER_LATCH_H_00_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */
+#define RC_SYS_TIMER_LATCH_L_01_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */
+#define RC_SYS_TIMER_LATCH_H_01_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */
+#define RC_SYS_TIMER_LATCH_L_02_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */
+#define RC_SYS_TIMER_LATCH_H_02_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */
+#define RC_SYS_TIMER_LATCH_L_03_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */
+#define RC_SYS_TIMER_LATCH_H_03_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */
+#define RC_SYS_TIMER_LATCH_L_04_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */
+#define RC_SYS_TIMER_LATCH_H_04_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */
+#define RC_SYS_TIMER_LATCH_L_05_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */
+#define RC_SYS_TIMER_LATCH_H_05_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */
+#define RC_SYS_TIMER_LATCH_L_06_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */
+#define RC_SYS_TIMER_LATCH_H_06_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */
+#define RC_SYS_TIMER_LATCH_L_07_LSB         (1U << 0)       /* 32b */
+/* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */
+#define RC_SYS_TIMER_LATCH_H_07_LSB         (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_19 (0x10006000+0xED8) */
+#define PCM_WDT_LATCH_19_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */
+#define PCM_WDT_LATCH_20_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */
+#define PCM_WDT_LATCH_21_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */
+#define PCM_WDT_LATCH_22_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */
+#define PCM_WDT_LATCH_23_LSB                (1U << 0)       /* 32b */
+/* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */
+#define PCM_WDT_LATCH_24_LSB                (1U << 0)       /* 32b */
+/* PMSR_LAST_DAT (0x10006000+0xF00) */
+#define PMSR_LAST_DAT_LSB                   (1U << 0)       /* 32b */
+/* PMSR_LAST_CNT (0x10006000+0xF04) */
+#define PMSR_LAST_CMD_LSB                   (1U << 0)       /* 30b */
+#define PMSR_LAST_REQ_LSB                   (1U << 30)      /* 1b */
+/* PMSR_LAST_ACK (0x10006000+0xF08) */
+#define PMSR_LAST_ACK_LSB                   (1U << 0)       /* 1b */
+/* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */
+#define REG_PMSR_SIG_SEL_0_LSB              (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_1_LSB              (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_2_LSB              (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_3_LSB              (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */
+#define REG_PMSR_SIG_SEL_4_LSB              (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_5_LSB              (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_6_LSB              (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_7_LSB              (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */
+#define REG_PMSR_SIG_SEL_8_LSB              (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_9_LSB              (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_10_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_11_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */
+#define REG_PMSR_SIG_SEL_12_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_13_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_14_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_15_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */
+#define REG_PMSR_SIG_SEL_16_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_17_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_18_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_19_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */
+#define REG_PMSR_SIG_SEL_20_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_21_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_22_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_23_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */
+#define REG_PMSR_SIG_SEL_24_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_25_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_26_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_27_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */
+#define REG_PMSR_SIG_SEL_28_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_29_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_30_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_31_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */
+#define REG_PMSR_SIG_SEL_32_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_33_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_34_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_35_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */
+#define REG_PMSR_SIG_SEL_36_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_37_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_38_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_39_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */
+#define REG_PMSR_SIG_SEL_40_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_41_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_42_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_43_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */
+#define REG_PMSR_SIG_SEL_44_LSB             (1U << 0)       /* 8b */
+#define REG_PMSR_SIG_SEL_45_LSB             (1U << 8)       /* 8b */
+#define REG_PMSR_SIG_SEL_46_LSB             (1U << 16)      /* 8b */
+#define REG_PMSR_SIG_SEL_47_LSB             (1U << 24)      /* 8b */
+/* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */
+#define PMSR_TIMER_SET0_LSB                 (1U << 0)       /* 32b */
+/* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */
+#define PMSR_TIMER_SET1_LSB                 (1U << 0)       /* 32b */
+/* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */
+#define PMSR_TIMER_SET2_LSB                 (1U << 0)       /* 32b */
+/* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */
+#define PMSR_ENABLE_SET0_LSB                (1U << 0)       /* 1b */
+#define PMSR_ENABLE_SET1_LSB                (1U << 1)       /* 1b */
+#define PMSR_ENABLE_SET2_LSB                (1U << 2)       /* 1b */
+#define PMSR_IRQ_CLR_SET0_LSB               (1U << 3)       /* 1b */
+#define PMSR_IRQ_CLR_SET1_LSB               (1U << 4)       /* 1b */
+#define PMSR_IRQ_CLR_SET2_LSB               (1U << 5)       /* 1b */
+#define PMSR_SPEED_MODE_EN_SET0_LSB         (1U << 6)       /* 1b */
+#define PMSR_SPEED_MODE_EN_SET1_LSB         (1U << 7)       /* 1b */
+#define PMSR_SPEED_MODE_EN_SET2_LSB         (1U << 8)       /* 1b */
+#define PMSR_EVENT_CLR_SET0_LSB             (1U << 9)       /* 1b */
+#define PMSR_EVENT_CLR_SET1_LSB             (1U << 10)      /* 1b */
+#define PMSR_EVENT_CLR_SET2_LSB             (1U << 11)      /* 1b */
+#define REG_PMSR_IRQ_MASK_SET0_LSB          (1U << 12)      /* 1b */
+#define REG_PMSR_IRQ_MASK_SET1_LSB          (1U << 13)      /* 1b */
+#define REG_PMSR_IRQ_MASK_SET2_LSB          (1U << 14)      /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15)      /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16)      /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17)      /* 1b */
+#define PMSR_GEN_SW_RST_EN_LSB              (1U << 18)      /* 1b */
+#define PMSR_MODULE_ENABLE_LSB              (1U << 19)      /* 1b */
+#define PMSR_MODE_LSB                       (1U << 20)      /* 2b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29)      /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30)      /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31)      /* 1b */
+/* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */
+#define PMSR_COUNTER_THRES_LSB              (1U << 0)       /* 32b */
+/* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */
+#define PMSR_DEBUG_IN_0_MASK_B_LSB          (1U << 0)       /* 32b */
+/* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */
+#define PMSR_DEBUG_IN_1_MASK_B_LSB          (1U << 0)       /* 32b */
+/* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */
+#define PMSR_DEBUG_IN_2_MASK_B_LSB          (1U << 0)       /* 32b */
+/* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */
+#define PMSR_DEBUG_IN_3_MASK_B_LSB          (1U << 0)       /* 32b */
+/* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */
+#define PMSR_SW_RST_EN_SET0_LSB             (1U << 0)       /* 1b */
+#define PMSR_SW_RST_EN_SET1_LSB             (1U << 1)       /* 1b */
+#define PMSR_SW_RST_EN_SET2_LSB             (1U << 2)       /* 1b */
+/* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */
+#define REG_PMSR_MON_TYPE_0_LSB             (1U << 0)       /* 2b */
+#define REG_PMSR_MON_TYPE_1_LSB             (1U << 2)       /* 2b */
+#define REG_PMSR_MON_TYPE_2_LSB             (1U << 4)       /* 2b */
+#define REG_PMSR_MON_TYPE_3_LSB             (1U << 6)       /* 2b */
+#define REG_PMSR_MON_TYPE_4_LSB             (1U << 8)       /* 2b */
+#define REG_PMSR_MON_TYPE_5_LSB             (1U << 10)      /* 2b */
+#define REG_PMSR_MON_TYPE_6_LSB             (1U << 12)      /* 2b */
+#define REG_PMSR_MON_TYPE_7_LSB             (1U << 14)      /* 2b */
+#define REG_PMSR_MON_TYPE_8_LSB             (1U << 16)      /* 2b */
+#define REG_PMSR_MON_TYPE_9_LSB             (1U << 18)      /* 2b */
+#define REG_PMSR_MON_TYPE_10_LSB            (1U << 20)      /* 2b */
+#define REG_PMSR_MON_TYPE_11_LSB            (1U << 22)      /* 2b */
+#define REG_PMSR_MON_TYPE_12_LSB            (1U << 24)      /* 2b */
+#define REG_PMSR_MON_TYPE_13_LSB            (1U << 26)      /* 2b */
+#define REG_PMSR_MON_TYPE_14_LSB            (1U << 28)      /* 2b */
+#define REG_PMSR_MON_TYPE_15_LSB            (1U << 30)      /* 2b */
+/* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */
+#define REG_PMSR_MON_TYPE_16_LSB            (1U << 0)       /* 2b */
+#define REG_PMSR_MON_TYPE_17_LSB            (1U << 2)       /* 2b */
+#define REG_PMSR_MON_TYPE_18_LSB            (1U << 4)       /* 2b */
+#define REG_PMSR_MON_TYPE_19_LSB            (1U << 6)       /* 2b */
+#define REG_PMSR_MON_TYPE_20_LSB            (1U << 8)       /* 2b */
+#define REG_PMSR_MON_TYPE_21_LSB            (1U << 10)      /* 2b */
+#define REG_PMSR_MON_TYPE_22_LSB            (1U << 12)      /* 2b */
+#define REG_PMSR_MON_TYPE_23_LSB            (1U << 14)      /* 2b */
+#define REG_PMSR_MON_TYPE_24_LSB            (1U << 16)      /* 2b */
+#define REG_PMSR_MON_TYPE_25_LSB            (1U << 18)      /* 2b */
+#define REG_PMSR_MON_TYPE_26_LSB            (1U << 20)      /* 2b */
+#define REG_PMSR_MON_TYPE_27_LSB            (1U << 22)      /* 2b */
+#define REG_PMSR_MON_TYPE_28_LSB            (1U << 24)      /* 2b */
+#define REG_PMSR_MON_TYPE_29_LSB            (1U << 26)      /* 2b */
+#define REG_PMSR_MON_TYPE_30_LSB            (1U << 28)      /* 2b */
+#define REG_PMSR_MON_TYPE_31_LSB            (1U << 30)      /* 2b */
+/* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */
+#define REG_PMSR_MON_TYPE_32_LSB            (1U << 0)       /* 2b */
+#define REG_PMSR_MON_TYPE_33_LSB            (1U << 2)       /* 2b */
+#define REG_PMSR_MON_TYPE_34_LSB            (1U << 4)       /* 2b */
+#define REG_PMSR_MON_TYPE_35_LSB            (1U << 6)       /* 2b */
+#define REG_PMSR_MON_TYPE_36_LSB            (1U << 8)       /* 2b */
+#define REG_PMSR_MON_TYPE_37_LSB            (1U << 10)      /* 2b */
+#define REG_PMSR_MON_TYPE_38_LSB            (1U << 12)      /* 2b */
+#define REG_PMSR_MON_TYPE_39_LSB            (1U << 14)      /* 2b */
+#define REG_PMSR_MON_TYPE_40_LSB            (1U << 16)      /* 2b */
+#define REG_PMSR_MON_TYPE_41_LSB            (1U << 18)      /* 2b */
+#define REG_PMSR_MON_TYPE_42_LSB            (1U << 20)      /* 2b */
+#define REG_PMSR_MON_TYPE_43_LSB            (1U << 22)      /* 2b */
+#define REG_PMSR_MON_TYPE_44_LSB            (1U << 24)      /* 2b */
+#define REG_PMSR_MON_TYPE_45_LSB            (1U << 26)      /* 2b */
+#define REG_PMSR_MON_TYPE_46_LSB            (1U << 28)      /* 2b */
+#define REG_PMSR_MON_TYPE_47_LSB            (1U << 30)      /* 2b */
+/* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */
+#define REG_PMSR_WINDOW_LEN_SET0_LSB        (1U << 0)       /* 32b */
+/* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */
+#define REG_PMSR_WINDOW_LEN_SET1_LSB        (1U << 0)       /* 32b */
+/* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */
+#define REG_PMSR_WINDOW_LEN_SET2_LSB        (1U << 0)       /* 32b */
+
+#define SPM_PROJECT_CODE	0xb16
+#define SPM_REGWR_CFG_KEY	(SPM_PROJECT_CODE << 16)
+#endif
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h
new file mode 100644
index 0000000..26250ba
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM	0
+#define MT_SPM_BIT_26M		1
+#define MT_SPM_BIT_INFRA	2
+#define MT_SPM_BIT_SYSPLL	3
+#define MT_SPM_BIT_DRAM_S0	4
+#define MT_SPM_BIT_DRAM_S1	5
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM	BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M	BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA	BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL	BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0	BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1	BIT(MT_SPM_BIT_DRAM_S1)
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c
new file mode 100644
index 0000000..b40fa87
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <uart.h>
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG			\
+	(SPM_FLAG_DISABLE_INFRA_PDN |			\
+	 SPM_FLAG_DISABLE_VCORE_DVS |			\
+	 SPM_FLAG_DISABLE_VCORE_DFS |			\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH |		\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |	\
+	 SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG1	0
+
+#define SPM_SUSPEND_PCM_FLAG				\
+	(SPM_FLAG_DISABLE_VCORE_DVS |			\
+	 SPM_FLAG_DISABLE_VCORE_DFS |			\
+	 SPM_FLAG_ENABLE_TIA_WORKAROUND |		\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |	\
+	 SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_PCM_FLAG1		0
+
+/* Suspend spm power control */
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__			\
+	(R12_PCM_TIMER |				\
+	 R12_KP_IRQ_B |					\
+	 R12_APWDT_EVENT_B |				\
+	 R12_CONN2AP_SPM_WAKEUP_B |			\
+	 R12_EINT_EVENT_B |				\
+	 R12_CONN_WDT_IRQ_B |				\
+	 R12_CCIF0_EVENT_B |				\
+	 R12_SSPM2SPM_WAKEUP_B |			\
+	 R12_SCP2SPM_WAKEUP_B |				\
+	 R12_ADSP2SPM_WAKEUP_B |			\
+	 R12_USBX_CDSC_B |				\
+	 R12_USBX_POWERDWN_B |				\
+	 R12_SYS_TIMER_EVENT_B |			\
+	 R12_EINT_EVENT_SECURE_B |			\
+	 R12_SYS_CIRQ_IRQ_B |				\
+	 R12_MD2AP_PEER_EVENT_B |			\
+	 R12_MD1_WDT_B |				\
+	 R12_CLDMA_EVENT_B |				\
+	 R12_REG_CPU_WAKEUP |				\
+	 R12_APUSYS_WAKE_HOST_B)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND			\
+	(__WAKE_SRC_FOR_SUSPEND_COMMON__ |	\
+	 R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl suspend_ctrl = {
+	.wake_src = WAKE_SRC_FOR_SUSPEND,
+
+	/* SPM_AP_STANDBY_CON */
+	/* [0] */
+	.reg_wfi_op = 0,
+	/* [1] */
+	.reg_wfi_type = 0,
+	/* [2] */
+	.reg_mp0_cputop_idle_mask = 0,
+	/* [3] */
+	.reg_mp1_cputop_idle_mask = 0,
+	/* [4] */
+	.reg_mcusys_idle_mask = 0,
+	/* [25] */
+	.reg_md_apsrc_1_sel = 0,
+	/* [26] */
+	.reg_md_apsrc_0_sel = 0,
+	/* [29] */
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC_REQ */
+	/* [0] */
+	.reg_spm_apsrc_req = 0,
+	/* [1] */
+	.reg_spm_f26m_req = 0,
+	/* [3] */
+	.reg_spm_infra_req = 0,
+	/* [4] */
+	.reg_spm_vrf18_req = 0,
+	/* [7] FIXME: default disable HW Auto S1*/
+	.reg_spm_ddr_en_req = 1,
+	/* [8] */
+	.reg_spm_dvfs_req = 0,
+	/* [9] */
+	.reg_spm_sw_mailbox_req = 0,
+	/* [10] */
+	.reg_spm_sspm_mailbox_req = 0,
+	/* [11] */
+	.reg_spm_adsp_mailbox_req = 0,
+	/* [12] */
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	/* [0] */
+	.reg_sspm_srcclkena_0_mask_b = 1,
+	/* [1] */
+	.reg_sspm_infra_req_0_mask_b = 1,
+	/* [2] */
+	.reg_sspm_apsrc_req_0_mask_b = 1,
+	/* [3] */
+	.reg_sspm_vrf18_req_0_mask_b = 1,
+	/* [4] */
+	.reg_sspm_ddr_en_0_mask_b = 1,
+	/* [5] */
+	.reg_scp_srcclkena_mask_b = 1,
+	/* [6] */
+	.reg_scp_infra_req_mask_b = 1,
+	/* [7] */
+	.reg_scp_apsrc_req_mask_b = 1,
+	/* [8] */
+	.reg_scp_vrf18_req_mask_b = 1,
+	/* [9] */
+	.reg_scp_ddr_en_mask_b = 1,
+	/* [10] */
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	/* [11] */
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	/* [12] */
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	/* [13] */
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	/* [14] */
+	.reg_audio_dsp_ddr_en_mask_b = 1,
+	/* [15] */
+	.reg_apu_srcclkena_mask_b = 1,
+	/* [16] */
+	.reg_apu_infra_req_mask_b = 1,
+	/* [17] */
+	.reg_apu_apsrc_req_mask_b = 1,
+	/* [18] */
+	.reg_apu_vrf18_req_mask_b = 1,
+	/* [19] */
+	.reg_apu_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_cpueb_srcclkena_mask_b = 1,
+	/* [21] */
+	.reg_cpueb_infra_req_mask_b = 1,
+	/* [22] */
+	.reg_cpueb_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_cpueb_vrf18_req_mask_b = 1,
+	/* [24] */
+	.reg_cpueb_ddr_en_mask_b = 1,
+	/* [25] */
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	/* [26] */
+	.reg_bak_psri_infra_req_mask_b = 0,
+	/* [27] */
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	/* [28] */
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	/* [29] */
+	.reg_bak_psri_ddr_en_mask_b = 0,
+
+	/* SPM_SRC2_MASK */
+	/* [0] */
+	.reg_msdc0_srcclkena_mask_b = 1,
+	/* [1] */
+	.reg_msdc0_infra_req_mask_b = 1,
+	/* [2] */
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	/* [3] */
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	/* [4] */
+	.reg_msdc0_ddr_en_mask_b = 1,
+	/* [5] */
+	.reg_msdc1_srcclkena_mask_b = 1,
+	/* [6] */
+	.reg_msdc1_infra_req_mask_b = 1,
+	/* [7] */
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	/* [8] */
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	/* [9] */
+	.reg_msdc1_ddr_en_mask_b = 1,
+	/* [10] */
+	.reg_msdc2_srcclkena_mask_b = 1,
+	/* [11] */
+	.reg_msdc2_infra_req_mask_b = 1,
+	/* [12] */
+	.reg_msdc2_apsrc_req_mask_b = 1,
+	/* [13] */
+	.reg_msdc2_vrf18_req_mask_b = 1,
+	/* [14] */
+	.reg_msdc2_ddr_en_mask_b = 1,
+	/* [15] */
+	.reg_ufs_srcclkena_mask_b = 0,
+	/* [16] */
+	.reg_ufs_infra_req_mask_b = 0,
+	/* [17] */
+	.reg_ufs_apsrc_req_mask_b = 0,
+	/* [18] */
+	.reg_ufs_vrf18_req_mask_b = 0,
+	/* [19] */
+	.reg_ufs_ddr_en_mask_b = 0,
+	/* [20] */
+	.reg_usb_srcclkena_mask_b = 1,
+	/* [21] */
+	.reg_usb_infra_req_mask_b = 1,
+	/* [22] */
+	.reg_usb_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_usb_vrf18_req_mask_b = 1,
+	/* [24] */
+	.reg_usb_ddr_en_mask_b = 1,
+	/* [25] */
+	.reg_pextp_p0_srcclkena_mask_b = 1,
+	/* [26] */
+	.reg_pextp_p0_infra_req_mask_b = 1,
+	/* [27] */
+	.reg_pextp_p0_apsrc_req_mask_b = 1,
+	/* [28] */
+	.reg_pextp_p0_vrf18_req_mask_b = 1,
+	/* [29] */
+	.reg_pextp_p0_ddr_en_mask_b = 1,
+
+	/* SPM_SRC3_MASK */
+	/* [0] */
+	.reg_pextp_p1_srcclkena_mask_b = 1,
+	/* [1] */
+	.reg_pextp_p1_infra_req_mask_b = 1,
+	/* [2] */
+	.reg_pextp_p1_apsrc_req_mask_b = 1,
+	/* [3] */
+	.reg_pextp_p1_vrf18_req_mask_b = 1,
+	/* [4] */
+	.reg_pextp_p1_ddr_en_mask_b = 1,
+	/* [5] */
+	.reg_gce0_infra_req_mask_b = 1,
+	/* [6] */
+	.reg_gce0_apsrc_req_mask_b = 1,
+	/* [7] */
+	.reg_gce0_vrf18_req_mask_b = 1,
+	/* [8] */
+	.reg_gce0_ddr_en_mask_b = 1,
+	/* [9] */
+	.reg_gce1_infra_req_mask_b = 1,
+	/* [10] */
+	.reg_gce1_apsrc_req_mask_b = 1,
+	/* [11] */
+	.reg_gce1_vrf18_req_mask_b = 1,
+	/* [12] */
+	.reg_gce1_ddr_en_mask_b = 1,
+	/* [13] */
+	.reg_spm_srcclkena_reserved_mask_b = 1,
+	/* [14] */
+	.reg_spm_infra_req_reserved_mask_b = 1,
+	/* [15] */
+	.reg_spm_apsrc_req_reserved_mask_b = 1,
+	/* [16] */
+	.reg_spm_vrf18_req_reserved_mask_b = 1,
+	/* [17] */
+	.reg_spm_ddr_en_reserved_mask_b = 1,
+	/* [18] */
+	.reg_disp0_apsrc_req_mask_b = 1,
+	/* [19] */
+	.reg_disp0_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_disp1_apsrc_req_mask_b = 1,
+	/* [21] */
+	.reg_disp1_ddr_en_mask_b = 1,
+	/* [22] */
+	.reg_disp2_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_disp2_ddr_en_mask_b = 1,
+	/* [24] */
+	.reg_disp3_apsrc_req_mask_b = 1,
+	/* [25] */
+	.reg_disp3_ddr_en_mask_b = 1,
+	/* [26] */
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	/* [27] */
+	.reg_infrasys_ddr_en_mask_b = 1,
+
+	/* [28] */
+	.reg_cg_check_srcclkena_mask_b = 1,
+	/* [29] */
+	.reg_cg_check_apsrc_req_mask_b = 1,
+	/* [30] */
+	.reg_cg_check_vrf18_req_mask_b = 1,
+	/* [31] */
+	.reg_cg_check_ddr_en_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	/* [8:0] */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x17,
+	/* [17:9] */
+	.reg_mcusys_merge_ddr_en_mask_b = 0x17,
+	/* [19:18] */
+	.reg_dramc_md32_infra_req_mask_b = 0,
+	/* [21:20] */
+	.reg_dramc_md32_vrf18_req_mask_b = 0,
+	/* [23:22] */
+	.reg_dramc_md32_ddr_en_mask_b = 0,
+	/* [24] */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK2 */
+	/* [3:0] */
+	.reg_sc_sw2spm_wakeup_mask_b = 0,
+	/* [4] */
+	.reg_sc_adsp2spm_wakeup_mask_b = 0,
+	/* [8:5] */
+	.reg_sc_sspm2spm_wakeup_mask_b = 0,
+	/* [9] */
+	.reg_sc_scp2spm_wakeup_mask_b = 0,
+	/* [10] */
+	.reg_csyspwrup_ack_mask = 0,
+	/* [11] */
+	.reg_csyspwrup_req_mask = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	/* [31:0] */
+	.reg_wakeup_event_mask = 0xC1382213,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	/* [31:0] */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+struct spm_lp_scen __spm_suspend = {
+	.pwrctrl = &suspend_ctrl,
+};
+
+int mt_spm_suspend_mode_set(int mode)
+{
+	if (mode == MT_SPM_SUSPEND_SLEEP) {
+		suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
+		suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
+	} else {
+		suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
+		suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
+	}
+
+	return 0;
+}
+
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+			 unsigned int resource_req)
+{
+	/* If FMAudio / ADSP is active, change to sleep suspend mode */
+	if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+		mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
+	}
+
+	/* Notify MCUPM that device is going suspend flow */
+	mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
+
+	/* Notify UART to sleep */
+	mt_uart_save();
+
+	return spm_conservation(state_id, ext_opand,
+				&__spm_suspend, resource_req);
+}
+
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+			   struct wake_status **status)
+{
+	spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
+
+	/* Notify UART to wakeup */
+	mt_uart_restore();
+
+	/* Notify MCUPM that device leave suspend */
+	mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
+
+	/* If FMAudio / ADSP is active, change back to suspend mode */
+	if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+		mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
+	}
+}
+
+void mt_spm_suspend_init(void)
+{
+	spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h
new file mode 100644
index 0000000..69c5230
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SUSPEND_H
+#define MT_SPM_SUSPEND_H
+
+#include <mt_spm_internal.h>
+
+#define MCUPM_MBOX_OFFSET_PDN	0x1031FF88
+#define MCUPM_POWER_DOWN	0x4D50444E
+
+enum MT_SPM_SUSPEND_MODE {
+	MT_SPM_SUSPEND_SYSTEM_PDN,
+	MT_SPM_SUSPEND_SLEEP,
+};
+
+extern int mt_spm_suspend_mode_set(int mode);
+extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+				unsigned int reosuce_req);
+extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+				  struct wake_status **status);
+extern void mt_spm_suspend_init(void);
+#endif /* MT_SPM_SUSPEND_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h
new file mode 100644
index 0000000..ee3738d
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_NOTIFIER_H
+#define MT_SPM_SSPM_NOTIFIER_H
+
+enum MT_SPM_SSPM_NOTIFY_ID {
+	MT_SPM_NOTIFY_LP_ENTER,
+	MT_SPM_NOTIFY_LP_LEAVE,
+};
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode);
+
+static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
+{
+	return mt_spm_sspm_notify(type, lp_mode);
+}
+#endif /* MT_SPM_SSPM_NOTIFIER_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h
new file mode 100644
index 0000000..6847e77
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_INTC_H
+#define MT_SPM_SSPM_INTC_H
+
+#include <mt_spm_reg.h>
+
+#define MT_SPM_SSPM_INTC_SEL_0		0x10
+#define MT_SPM_SSPM_INTC_SEL_1		0x20
+#define MT_SPM_SSPM_INTC_SEL_2		0x40
+#define MT_SPM_SSPM_INTC_SEL_3		0x80
+
+#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
+	(((0x10 << id) | (sg << id)) & 0xff)
+
+#define MT_SPM_SSPM_INTC0_HIGH	MT_SPM_SSPM_INTC_TRIGGER(0, 1)
+#define MT_SPM_SSPM_INTC0_LOW	MT_SPM_SSPM_INTC_TRIGGER(0, 0)
+#define MT_SPM_SSPM_INTC1_HIGH	MT_SPM_SSPM_INTC_TRIGGER(1, 1)
+#define MT_SPM_SSPM_INTC1_LOW	MT_SPM_SSPM_INTC_TRIGGER(1, 0)
+#define MT_SPM_SSPM_INTC2_HIGH	MT_SPM_SSPM_INTC_TRIGGER(2, 1)
+#define MT_SPM_SSPM_INTC2_LOW	MT_SPM_SSPM_INTC_TRIGGER(2, 0)
+#define MT_SPM_SSPM_INTC3_HIGH	MT_SPM_SSPM_INTC_TRIGGER(3, 1)
+#define MT_SPM_SSPM_INTC3_LOW	MT_SPM_SSPM_INTC_TRIGGER(3, 0)
+
+#define DO_SPM_SSPM_LP_SUSPEND()	\
+	mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
+#define DO_SPM_SSPM_LP_RESUME()		\
+	mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
+#endif /* MT_SPM_SSPM_INTC_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c
new file mode 100644
index 0000000..a755a38
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <lib/mmio.h>
+
+#include <mt_spm_notifier.h>
+#include <mt_spm_sspm_intc.h>
+
+#define MT_SPM_SSPM_MBOX_OFF(x)		(SSPM_MBOX_BASE + x)
+#define MT_SPM_MBOX(slot)		MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
+
+#define SSPM_MBOX_SPM_LP_LOOKUP1	MT_SPM_MBOX(0)
+#define SSPM_MBOX_SPM_LP_LOOKUP2	MT_SPM_MBOX(1)
+#define SSPM_MBOX_SPM_LP1		MT_SPM_MBOX(2)
+#define SSPM_MBOX_SPM_LP2		MT_SPM_MBOX(3)
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode)
+{
+	switch (type) {
+	case MT_SPM_NOTIFY_LP_ENTER:
+		mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+		DO_SPM_SSPM_LP_SUSPEND();
+		break;
+	case MT_SPM_NOTIFY_LP_LEAVE:
+		mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+		DO_SPM_SSPM_LP_RESUME();
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/pcm_def.h b/plat/mediatek/mt8195/drivers/spm/pcm_def.h
new file mode 100644
index 0000000..fa77b95
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/pcm_def.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCM_DEF_H
+#define PCM_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF                      (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN               (1U << 1)
+#define R0_SC_MEM_CK_OFF                      (1U << 2)
+#define R0_SC_AXI_CK_OFF                      (1U << 3)
+#define R0_SC_DR_SRAM_LOAD                    (1U << 4)
+#define R0_SC_MD26M_CK_OFF                    (1U << 5)
+#define R0_SC_DPY_MODE_SW                     (1U << 6)
+#define R0_SC_DMSUS_OFF                       (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN                  (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE                 (1U << 9)
+#define R0_SC_MPLLOUT_OFF                     (1U << 10)
+#define R0_SC_TX_TRACKING_DIS                 (1U << 11)
+#define R0_SC_DPY_DLL_EN                      (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN                   (1U << 13)
+#define R0_SC_DPY_VREF_EN                     (1U << 14)
+#define R0_SC_PHYPLL_EN                       (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN                 (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE                 (1U << 17)
+#define R0_SC_MPLL_OFF                        (1U << 18)
+#define R0_SC_SHU_RESTORE                     (1U << 19)
+#define R0_SC_CKSQ0_OFF                       (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH         (1U << 21)
+#define R0_SC_DR_SHU_EN                       (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP                  (1U << 23)
+#define R0_SC_MPLL_S_OFF                      (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN          (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN                   (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN                  (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW                  (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW                 (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0                   (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1                   (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ                    (1U << 0)
+#define R7_EMI_CLK_OFF_REQ                    (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ                (1U << 2)
+#define R7_SPM_CK_UPDATE                      (1U << 3)
+#define R7_SPM_CK_SEL0                        (1U << 4)
+#define R7_SPM_CK_SEL1                        (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ             (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL                  (1U << 7)
+#define R7_SC_26M_CK_SEL                      (1U << 8)
+#define R7_PCM_TIMER_SET                      (1U << 9)
+#define R7_PCM_TIMER_CLR                      (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ              (1U << 11)
+#define R7_CSYSPWRUPACK                       (1U << 12)
+#define R7_PCM_IM_SLP_EN                      (1U << 13)
+#define R7_SRCCLKENO0                         (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE                  (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK             (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL              (1U << 17)
+#define R7_SC_AXI_DCM_DIS                     (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM                   (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN                  (1U << 20)
+#define R7_SRCCLKENO1                         (1U << 21)
+#define R7_PCM_WDT_KICK_P                     (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC              (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM                 (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM           (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN                    (1U << 26)
+#define R7_FORCE_F26M_WAKE                    (1U << 27)
+#define R7_FORCE_APSRC_WAKE                   (1U << 28)
+#define R7_FORCE_INFRA_WAKE                   (1U << 29)
+#define R7_FORCE_VRF18_WAKE                   (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK            (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER                         (1U << 0)
+#define R12_TWAM_IRQ_B                        (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT1_EVENT_B                   (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B              (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_CONN_WDT_IRQ_B                    (1U << 7)
+#define R12_CCIF0_EVENT_B                     (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B                 (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B                  (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B                 (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B                  (1U << 13)
+#define R12_USBX_CDSC_B                       (1U << 14)
+#define R12_USBX_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_CCIF1_EVENT_B                     (1U << 18)
+#define R12_UART0_IRQ_B                       (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERM_CTRL_EVENT_B                (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B                (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_MD1_WDT_B                         (1U << 25)
+#define R12_CLDMA_EVENT_B                     (1U << 26)
+#define R12_SEJ_EVENT_B                       (1U << 27)
+#define R12_REG_CPU_WAKEUP                    (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B                (1U << 29)
+#define R12_NOT_USED1                         (1U << 30)
+#define R12_NOT_USED2                         (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_MCU_PM_WFI                     (1U << 11)
+#define R12EXT_SSPM_IDLE                      (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE           (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK          (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK         (1U << 20)
+#define R12EXT_VS1_TRIGGER                    (1U << 21)
+#define R12EXT_VS2_TRIGGER                    (1U << 22)
+#define R12EXT_COROSS_REQ_APU                 (1U << 23)
+#define R12EXT_CROSS_REQ_L3                   (1U << 24)
+#define R12EXT_DDR_PST_ACK                    (1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_SRCCLKENA_0                    (1U << 2)
+#define R13_MD_APSRC_REQ_0                    (1U << 3)
+#define R13_CONN_DDR_EN                       (1U << 4)
+#define R13_MD_SRCCLKENA_1                    (1U << 5)
+#define R13_SSPM_SRCCLKENA                    (1U << 6)
+#define R13_SSPM_APSRC_REQ                    (1U << 7)
+#define R13_MD1_STATE                         (1U << 8)
+#define R13_BIT9                              (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_SSPM_STATE                        (1U << 11)
+#define R13_MD_DDR_EN_0                       (1U << 12)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCLKENA                    (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL                (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL          (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL            (1U << 21)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL             (1U << 23)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL           (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0              (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL       (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL        (1U << 29)
+#define R13_MD_VRF18_REQ_0                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+#endif /* PCM_DEF_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/sleep_def.h b/plat/mediatek/mt8195/drivers/spm/sleep_def.h
new file mode 100644
index 0000000..2639b7e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/sleep_def.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright	(c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SLEEP_DEF_H
+#define SLEEP_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN			(1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN			(1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN			(1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS			(1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS			(1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO		(1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF			(1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF			(1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH			(1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND			(1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO			(1U << 10)
+#define SPM_FLAG_RESERVED_BIT11				(1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP		(1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2				(1U << 13)
+#define SPM_FLAG_ENABLE_6315_CTRL			(1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND			(1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP			(1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP		(1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP		(1U << 18)
+#define SPM_FLAG_DISABLE_DRAMC_ISSUE_CMD		(1U << 19)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN			(1U << 20)
+#define SPM_FLAG_RESERVED_BIT21				(1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP		(1U << 22)
+#define SPM_FLAG_DISABLE_DRAMC_MD32_BACKUP		(1U << 23)
+#define SPM_FLAG_RESERVED_BIT24				(1U << 24)
+#define SPM_FLAG_RESERVED_BIT25				(1U << 25)
+#define SPM_FLAG_RESERVED_BIT26				(1U << 26)
+#define SPM_FLAG_VTCXO_STATE				(1U << 27)
+#define SPM_FLAG_INFRA_STATE				(1U << 28)
+#define SPM_FLAG_APSRC_STATE				(1U << 29)
+#define SPM_FLAG_VRF18_STATE				(1U << 30)
+#define SPM_FLAG_DDREN_STATE				(1U << 31)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M		(1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF			(1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH		(1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF			(1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON			(1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5				(1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK				(1U << 6)
+#define SPM_FLAG1_RESERVED_BIT7				(1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8				(1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9				(1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW			(1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH		(1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12			(1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13			(1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14			(1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15			(1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16			(1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17			(1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18			(1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19			(1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP		(1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21			(1U << 21)
+#define SPM_FLAG1_ENABLE_VS1_VOTER			(1U << 22)
+#define SPM_FLAG1_ENABLE_VS2_VOTER			(1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL		(1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25			(1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26			(1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27			(1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28			(1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29			(1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30			(1U << 30)
+#define SPM_FLAG1_RESERVED_BIT31			(1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE			(1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1U << 22)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V		(1U << 23)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V		(1U << 24)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V		(1U << 25)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V		(1U << 26)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE			(1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS	(1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1U << 7)
+#define SPM_DBG1_RESERVED_BIT8				(1U << 8)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF		(1U << 9)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON		(1U << 10)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1U << 18)
+#define SPM_DBG1_RESERVED_BIT19				(1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1U << 20)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW			(1U << 21)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH			(1U << 22)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT	(1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT	(1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT		(1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT	(1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT	(1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT	(1U << 28)
+#define SPM_DBG1_RESERVED_BIT29				(1U << 29)
+#define SPM_DBG1_RESERVED_BIT30				(1U << 30)
+#define SPM_DBG1_RESERVED_BIT31				(1U << 31)
+
+ /* Macro and Inline */
+#define is_cpu_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
+#define is_infra_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
+#define is_ddrphy_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
+#endif /* SLEEP_DEF_H */
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc.c b/plat/mediatek/mt8195/drivers/spmc/mtspmc.c
new file mode 100644
index 0000000..9b332a0
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mcucfg.h>
+#include <mtspmc.h>
+#include <mtspmc_private.h>
+
+
+void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu)
+{
+	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
+}
+
+void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu)
+{
+	mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
+}
+
+void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr)
+{
+	assert(cluster == 0U);
+
+	mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr);
+}
+
+uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu)
+{
+	assert(cluster == 0U);
+
+	return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR));
+}
+
+void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64)
+{
+	uint32_t reg;
+
+	assert(cluster == 0U);
+
+	reg = per_cluster(cluster, MCUCFG_INITARCH);
+
+	if (arm64) {
+		mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
+	} else {
+		mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
+	}
+}
+
+/**
+ * Return subsystem's power state.
+ *
+ * @mask: mask to MCUCFG_CPC_SPMC_PWR_STATUS to query the power state
+ *        of one subsystem.
+ * RETURNS:
+ * 0 (the subsys was powered off)
+ * 1 (the subsys was powered on)
+ */
+bool spm_get_powerstate(uint32_t mask)
+{
+	return (mmio_read_32(MCUCFG_CPC_SPMC_PWR_STATUS) & mask) != 0U;
+}
+
+bool spm_get_cluster_powerstate(unsigned int cluster)
+{
+	assert(cluster == 0U);
+
+	return spm_get_powerstate(BIT(14));
+}
+
+bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu)
+{
+	uint32_t mask = BIT(cpu);
+
+	assert(cluster == 0U);
+
+	return spm_get_powerstate(mask);
+}
+
+int spmc_init(void)
+{
+	INFO("SPM: enable CPC mode\n");
+
+	mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
+
+	mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B);
+	mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B);
+
+	mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
+	mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
+	mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG);
+
+	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE);
+	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_CORE_PWR_ON_EN);
+
+	return 0;
+}
+
+/**
+ * Power on a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered on
+ * @cpu: the CPU ID of the CPU which to be powered on
+ */
+void spm_poweron_cpu(unsigned int cluster, unsigned int cpu)
+{
+	uintptr_t cpu_pwr_con = per_cpu(cluster, cpu, SPM_CPU_PWR);
+
+	/* set to 0 after BIG VPROC bulk on & before B-core power on seq. */
+	if (cpu >= 4U) {
+		mmio_write_32(DREQ20_BIG_VPROC_ISO, 0U);
+	}
+
+	mmio_setbits_32(cpu_pwr_con, PWR_ON);
+
+	while (!spm_get_cpu_powerstate(cluster, cpu)) {
+		mmio_clrbits_32(cpu_pwr_con, PWR_ON);
+		mmio_setbits_32(cpu_pwr_con, PWR_ON);
+	}
+}
+
+/**
+ * Power off a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered off
+ * @cpu: the CPU ID of the CPU which to be powered off
+ */
+void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu)
+{
+	/* Set mp0_spmc_pwr_on_cpuX = 0 */
+	mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
+}
+
+/**
+ * Power off a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered off
+ */
+void spm_poweroff_cluster(unsigned int cluster)
+{
+	/* No need to power on/off cluster on single cluster platform */
+	assert(false);
+}
+
+/**
+ * Power on a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered on
+ */
+void spm_poweron_cluster(unsigned int cluster)
+{
+	/* No need to power on/off cluster on single cluster platform */
+	assert(false);
+}
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc.h b/plat/mediatek/mt8195/drivers/spmc/mtspmc.h
new file mode 100644
index 0000000..34e93d0
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_H
+#define MTSPMC_H
+
+#include <stdint.h>
+
+int spmc_init(void);
+
+void spm_poweron_cpu(unsigned int cluster, unsigned int cpu);
+void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu);
+
+void spm_poweroff_cluster(unsigned int cluster);
+void spm_poweron_cluster(unsigned int cluster);
+
+bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu);
+bool spm_get_cluster_powerstate(unsigned int cluster);
+bool spm_get_powerstate(uint32_t mask);
+
+void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64);
+void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr);
+uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu);
+
+void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu);
+void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu);
+
+#endif /* MTSPMC_H */
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h
new file mode 100644
index 0000000..bf4092e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_PRIVATE_H
+#define MTSPMC_PRIVATE_H
+
+#include <lib/utils_def.h>
+#include <platform_def.h>
+
+unsigned long read_cpuectlr(void);
+void write_cpuectlr(unsigned long cpuectlr);
+
+unsigned long read_cpupwrctlr_el1(void);
+void write_cpupwrctlr_el1(unsigned long cpuectlr);
+
+/*
+ * per_cpu/cluster helper
+ */
+struct per_cpu_reg {
+	unsigned int cluster_addr;
+	unsigned int cpu_stride;
+};
+
+#define per_cpu(cluster, cpu, reg)	\
+	(reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
+
+#define per_cluster(cluster, reg)	(reg[cluster].cluster_addr)
+
+#define SPM_REG(ofs)			(uint32_t)(SPM_BASE + (ofs))
+#define MCUCFG_REG(ofs)			(uint32_t)(MCUCFG_BASE + (ofs))
+#define INFRACFG_AO_REG(ofs)		(uint32_t)(INFRACFG_AO_BASE + (ofs))
+
+/* === SPMC related registers */
+#define SPM_POWERON_CONFIG_EN		SPM_REG(0x000)
+/* bit-fields of SPM_POWERON_CONFIG_EN */
+#define PROJECT_CODE			(U(0xb16) << 16)
+#define BCLK_CG_EN			BIT(0)
+
+#define SPM_PWR_STATUS			SPM_REG(0x16c)
+#define SPM_PWR_STATUS_2ND		SPM_REG(0x170)
+#define SPM_CPU_PWR_STATUS		SPM_REG(0x174)
+
+/* bit-fields of SPM_PWR_STATUS */
+#define MD				BIT(0)
+#define CONN				BIT(1)
+#define DDRPHY				BIT(2)
+#define DISP				BIT(3)
+#define MFG				BIT(4)
+#define ISP				BIT(5)
+#define INFRA				BIT(6)
+#define VDEC				BIT(7)
+#define MP0_CPUTOP			BIT(8)
+#define MP0_CPU0			BIT(9)
+#define MP0_CPU1			BIT(10)
+#define MP0_CPU2			BIT(11)
+#define MP0_CPU3			BIT(12)
+#define MCUSYS				BIT(14)
+#define MP0_CPU4			BIT(15)
+#define MP0_CPU5			BIT(16)
+#define MP0_CPU6			BIT(17)
+#define MP0_CPU7			BIT(18)
+#define VEN				BIT(21)
+
+/* === SPMC related registers */
+#define SPM_MCUSYS_PWR_CON		MCUCFG_REG(0xd200)
+#define SPM_MP0_CPUTOP_PWR_CON		MCUCFG_REG(0xd204)
+#define SPM_MP0_CPU0_PWR_CON		MCUCFG_REG(0xd208)
+#define SPM_MP0_CPU1_PWR_CON		MCUCFG_REG(0xd20c)
+#define SPM_MP0_CPU2_PWR_CON		MCUCFG_REG(0xd210)
+#define SPM_MP0_CPU3_PWR_CON		MCUCFG_REG(0xd214)
+#define SPM_MP0_CPU4_PWR_CON		MCUCFG_REG(0xd218)
+#define SPM_MP0_CPU5_PWR_CON		MCUCFG_REG(0xd21c)
+#define SPM_MP0_CPU6_PWR_CON		MCUCFG_REG(0xd220)
+#define SPM_MP0_CPU7_PWR_CON		MCUCFG_REG(0xd224)
+
+/* bit fields of SPM_*_PWR_CON */
+#define PWR_ON_ACK			BIT(31)
+#define VPROC_EXT_OFF			BIT(7)
+#define DORMANT_EN			BIT(6)
+#define RESETPWRON_CONFIG		BIT(5)
+#define PWR_CLK_DIS			BIT(4)
+#define PWR_ON				BIT(2)
+#define PWR_RST_B			BIT(0)
+
+/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */
+static const struct per_cpu_reg SPM_CPU_PWR[] = {
+	{ .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
+};
+
+/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
+static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
+	{ .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
+};
+
+/* === MCUCFG related registers */
+/* aa64naa32 */
+#define MCUCFG_MP0_CLUSTER_CFG5		MCUCFG_REG(0xc8e4)
+/* reset vectors */
+#define MCUCFG_MP0_CLUSTER_CFG8		MCUCFG_REG(0xc900)
+#define MCUCFG_MP0_CLUSTER_CFG10	MCUCFG_REG(0xc908)
+#define MCUCFG_MP0_CLUSTER_CFG12	MCUCFG_REG(0xc910)
+#define MCUCFG_MP0_CLUSTER_CFG14	MCUCFG_REG(0xc918)
+#define MCUCFG_MP0_CLUSTER_CFG16	MCUCFG_REG(0xc920)
+#define MCUCFG_MP0_CLUSTER_CFG18	MCUCFG_REG(0xc928)
+#define MCUCFG_MP0_CLUSTER_CFG20	MCUCFG_REG(0xc930)
+#define MCUCFG_MP0_CLUSTER_CFG22	MCUCFG_REG(0xc938)
+
+/* MCUSYS DREQ BIG VPROC ISO control */
+#define DREQ20_BIG_VPROC_ISO		MCUCFG_REG(0xad8c)
+
+/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */
+static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
+	{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
+};
+
+/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
+static const struct per_cpu_reg MCUCFG_INITARCH[] = {
+	{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
+};
+
+#define MCUCFG_INITARCH_CPU_BIT(cpu)	BIT(16U + cpu)
+/* === CPC control */
+#define MCUCFG_CPC_FLOW_CTRL_CFG	MCUCFG_REG(0xa814)
+#define MCUCFG_CPC_SPMC_PWR_STATUS	MCUCFG_REG(0xa840)
+
+/* bit fields of CPC_FLOW_CTRL_CFG */
+#define CPC_CTRL_ENABLE			BIT(16)
+#define SSPM_CORE_PWR_ON_EN		BIT(7) /* for cpu-hotplug */
+#define SSPM_ALL_PWR_CTRL_EN		BIT(13) /* for cpu-hotplug */
+#define GIC_WAKEUP_IGNORE(cpu)		BIT(21 + cpu)
+
+/* bit fields of CPC_SPMC_PWR_STATUS */
+#define CORE_SPMC_PWR_ON_ACK		GENMASK(11, 0)
+
+/* === APB Module infracfg_ao */
+#define INFRA_TOPAXI_PROTECTEN		INFRACFG_AO_REG(0x0220)
+#define INFRA_TOPAXI_PROTECTEN_STA0	INFRACFG_AO_REG(0x0224)
+#define INFRA_TOPAXI_PROTECTEN_STA1	INFRACFG_AO_REG(0x0228)
+#define INFRA_TOPAXI_PROTECTEN_SET	INFRACFG_AO_REG(0x02a0)
+#define INFRA_TOPAXI_PROTECTEN_CLR	INFRACFG_AO_REG(0x02a4)
+#define INFRA_TOPAXI_PROTECTEN_1	INFRACFG_AO_REG(0x0250)
+#define INFRA_TOPAXI_PROTECTEN_STA0_1	INFRACFG_AO_REG(0x0254)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1	INFRACFG_AO_REG(0x0258)
+#define INFRA_TOPAXI_PROTECTEN_1_SET	INFRACFG_AO_REG(0x02a8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR	INFRACFG_AO_REG(0x02ac)
+
+/* bit fields of INFRA_TOPAXI_PROTECTEN */
+#define MP0_SPMC_PROT_STEP1_0_MASK	BIT(12)
+#define MP0_SPMC_PROT_STEP1_1_MASK	(BIT(26) | BIT(12))
+
+/* === SPARK */
+#define VOLTAGE_04			U(0x40)
+#define VOLTAGE_05			U(0x60)
+
+#define PTP3_CPU0_SPMC_SW_CFG		MCUCFG_REG(0x200)
+#define CPU0_ILDO_CONTROL5		MCUCFG_REG(0x334)
+#define CPU0_ILDO_CONTROL8		MCUCFG_REG(0x340)
+
+/* bit fields of CPU0_ILDO_CONTROL5 */
+#define ILDO_RET_VOSEL			GENMASK(7, 0)
+
+/* bit fields of PTP3_CPU_SPMC_SW_CFG */
+#define SW_SPARK_EN			BIT(0)
+
+/* bit fields of CPU0_ILDO_CONTROL8 */
+#define ILDO_BYPASS_B			BIT(0)
+
+static const struct per_cpu_reg MCUCFG_SPARK[] = {
+	{ .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
+};
+
+static const struct per_cpu_reg ILDO_CONTROL5[] = {
+	{ .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
+};
+
+static const struct per_cpu_reg ILDO_CONTROL8[] = {
+	{ .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
+};
+
+#endif /* MTSPMC_PRIVATE_H */
diff --git a/plat/mediatek/mt8195/include/mcucfg.h b/plat/mediatek/mt8195/include/mcucfg.h
new file mode 100644
index 0000000..046cf73
--- /dev/null
+++ b/plat/mediatek/mt8195/include/mcucfg.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCUCFG_H
+#define MCUCFG_H
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#endif /* __ASSEMBLER__ */
+
+#include <platform_def.h>
+
+#define MCUCFG_REG(ofs)			(uint32_t)(MCUCFG_BASE + (ofs))
+
+#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
+#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
+
+#define MP2_CPUCFG			MCUCFG_REG(0x2208)
+
+#define MP2_CPU0_STANDBYWFE		BIT(4)
+#define MP2_CPU1_STANDBYWFE		BIT(5)
+
+#define MP0_CPUTOP_SPMC_CTL		MCUCFG_REG(0x788)
+#define MP1_CPUTOP_SPMC_CTL		MCUCFG_REG(0x78C)
+#define MP1_CPUTOP_SPMC_SRAM_CTL	MCUCFG_REG(0x790)
+
+#define sw_spark_en			BIT(0)
+#define sw_no_wait_for_q_channel	BIT(1)
+#define sw_fsm_override			BIT(2)
+#define sw_logic_pre1_pdb		BIT(3)
+#define sw_logic_pre2_pdb		BIT(4)
+#define sw_logic_pdb			BIT(5)
+#define sw_iso				BIT(6)
+#define sw_sram_sleepb			(U(0x3F) << 7)
+#define sw_sram_isointb			BIT(13)
+#define sw_clk_dis			BIT(14)
+#define sw_ckiso			BIT(15)
+#define sw_pd				(U(0x3F) << 16)
+#define sw_hot_plug_reset		BIT(22)
+#define sw_pwr_on_override_en		BIT(23)
+#define sw_pwr_on			BIT(24)
+#define sw_coq_dis			BIT(25)
+#define logic_pdbo_all_off_ack		BIT(26)
+#define logic_pdbo_all_on_ack		BIT(27)
+#define logic_pre2_pdbo_all_on_ack	BIT(28)
+#define logic_pre1_pdbo_all_on_ack	BIT(29)
+
+
+#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \
+	(MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
+
+#define CPUSYS0_CPU0_SPMC_CTL		MCUCFG_REG(0x1c30)
+#define CPUSYS0_CPU1_SPMC_CTL		MCUCFG_REG(0x1c34)
+#define CPUSYS0_CPU2_SPMC_CTL		MCUCFG_REG(0x1c38)
+#define CPUSYS0_CPU3_SPMC_CTL		MCUCFG_REG(0x1c3C)
+
+#define CPUSYS1_CPU0_SPMC_CTL		MCUCFG_REG(0x3c30)
+#define CPUSYS1_CPU1_SPMC_CTL		MCUCFG_REG(0x3c34)
+#define CPUSYS1_CPU2_SPMC_CTL		MCUCFG_REG(0x3c38)
+#define CPUSYS1_CPU3_SPMC_CTL		MCUCFG_REG(0x3c3C)
+
+#define cpu_sw_spark_en			BIT(0)
+#define cpu_sw_no_wait_for_q_channel	BIT(1)
+#define cpu_sw_fsm_override		BIT(2)
+#define cpu_sw_logic_pre1_pdb		BIT(3)
+#define cpu_sw_logic_pre2_pdb		BIT(4)
+#define cpu_sw_logic_pdb		BIT(5)
+#define cpu_sw_iso			BIT(6)
+#define cpu_sw_sram_sleepb		BIT(7)
+#define cpu_sw_sram_isointb		BIT(8)
+#define cpu_sw_clk_dis			BIT(9)
+#define cpu_sw_ckiso			BIT(10)
+#define cpu_sw_pd			(U(0x1F) << 11)
+#define cpu_sw_hot_plug_reset		BIT(16)
+#define cpu_sw_powr_on_override_en	BIT(17)
+#define cpu_sw_pwr_on			BIT(18)
+#define cpu_spark2ldo_allswoff		BIT(19)
+#define cpu_pdbo_all_on_ack		BIT(20)
+#define cpu_pre2_pdbo_allon_ack		BIT(21)
+#define cpu_pre1_pdbo_allon_ack		BIT(22)
+
+/* CPC related registers */
+#define CPC_MCUSYS_CPC_OFF_THRES	MCUCFG_REG(0xa714)
+#define CPC_MCUSYS_PWR_CTRL		MCUCFG_REG(0xa804)
+#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG	MCUCFG_REG(0xa814)
+#define CPC_MCUSYS_LAST_CORE_REQ	MCUCFG_REG(0xa818)
+#define CPC_MCUSYS_MP_LAST_CORE_RESP	MCUCFG_REG(0xa81c)
+#define CPC_MCUSYS_LAST_CORE_RESP	MCUCFG_REG(0xa824)
+#define CPC_MCUSYS_PWR_ON_MASK		MCUCFG_REG(0xa828)
+#define CPC_MCUSYS_CPU_ON_SW_HINT_SET	MCUCFG_REG(0xa8a8)
+#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR	MCUCFG_REG(0xa8ac)
+#define CPC_MCUSYS_CPC_DBG_SETTING	MCUCFG_REG(0xab00)
+#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE	MCUCFG_REG(0xab04)
+#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE	MCUCFG_REG(0xab08)
+#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE	MCUCFG_REG(0xab0c)
+#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE	MCUCFG_REG(0xab10)
+#define CPC_MCUSYS_TRACE_SEL		MCUCFG_REG(0xab14)
+#define CPC_MCUSYS_TRACE_DATA		MCUCFG_REG(0xab20)
+#define CPC_MCUSYS_CLUSTER_COUNTER	MCUCFG_REG(0xab70)
+#define CPC_MCUSYS_CLUSTER_COUNTER_CLR	MCUCFG_REG(0xab74)
+
+#define SPARK2LDO			MCUCFG_REG(0x2700)
+/* APB Module mcucfg */
+#define MP0_CA7_CACHE_CONFIG		MCUCFG_REG(0x000)
+#define MP0_AXI_CONFIG			MCUCFG_REG(0x02C)
+#define MP0_MISC_CONFIG0		MCUCFG_REG(0x030)
+#define MP0_MISC_CONFIG1		MCUCFG_REG(0x034)
+#define MP0_MISC_CONFIG2		MCUCFG_REG(0x038)
+#define MP0_MISC_CONFIG_BOOT_ADDR(cpu)	(MP0_MISC_CONFIG2 + ((cpu) * 8))
+#define MP0_MISC_CONFIG3		MCUCFG_REG(0x03C)
+#define MP0_MISC_CONFIG9		MCUCFG_REG(0x054)
+#define MP0_CA7_MISC_CONFIG		MCUCFG_REG(0x064)
+
+#define MP0_RW_RSVD0			MCUCFG_REG(0x06C)
+
+
+#define MP1_CA7_CACHE_CONFIG		MCUCFG_REG(0x200)
+#define MP1_AXI_CONFIG			MCUCFG_REG(0x22C)
+#define MP1_MISC_CONFIG0		MCUCFG_REG(0x230)
+#define MP1_MISC_CONFIG1		MCUCFG_REG(0x234)
+#define MP1_MISC_CONFIG2		MCUCFG_REG(0x238)
+#define MP1_MISC_CONFIG_BOOT_ADDR(cpu)	(MP1_MISC_CONFIG2 + ((cpu) * 8))
+#define MP1_MISC_CONFIG3		MCUCFG_REG(0x23C)
+#define MP1_MISC_CONFIG9		MCUCFG_REG(0x254)
+#define MP1_CA7_MISC_CONFIG		MCUCFG_REG(0x264)
+
+#define CCI_ADB400_DCM_CONFIG		MCUCFG_REG(0x740)
+#define SYNC_DCM_CONFIG			MCUCFG_REG(0x744)
+
+#define MP0_CLUSTER_CFG0		MCUCFG_REG(0xC8D0)
+
+#define MP0_SPMC			MCUCFG_REG(0x788)
+#define MP1_SPMC			MCUCFG_REG(0x78C)
+#define MP2_AXI_CONFIG			MCUCFG_REG(0x220C)
+#define MP2_AXI_CONFIG_ACINACTM		BIT(0)
+#define MP2_AXI_CONFIG_AINACTS		BIT(4)
+
+#define MPx_AXI_CONFIG_ACINACTM		BIT(4)
+#define MPx_AXI_CONFIG_AINACTS		BIT(5)
+
+#define MPx_CA7_MISC_CONFIG_standbywfil2	BIT(28)
+
+#define MP0_CPU0_STANDBYWFE		BIT(20)
+#define MP0_CPU1_STANDBYWFE		BIT(21)
+#define MP0_CPU2_STANDBYWFE		BIT(22)
+#define MP0_CPU3_STANDBYWFE		BIT(23)
+
+#define MP1_CPU0_STANDBYWFE		BIT(20)
+#define MP1_CPU1_STANDBYWFE		BIT(21)
+#define MP1_CPU2_STANDBYWFE		BIT(22)
+#define MP1_CPU3_STANDBYWFE		BIT(23)
+
+#define CPUSYS0_SPARKVRETCNTRL		MCUCFG_REG(0x1c00)
+#define CPUSYS0_SPARKEN			MCUCFG_REG(0x1c04)
+#define CPUSYS0_AMUXSEL			MCUCFG_REG(0x1c08)
+#define CPUSYS1_SPARKVRETCNTRL		MCUCFG_REG(0x3c00)
+#define CPUSYS1_SPARKEN			MCUCFG_REG(0x3c04)
+#define CPUSYS1_AMUXSEL			MCUCFG_REG(0x3c08)
+
+#define MP2_PWR_RST_CTL			MCUCFG_REG(0x2008)
+#define MP2_PTP3_CPUTOP_SPMC0		MCUCFG_REG(0x22A0)
+#define MP2_PTP3_CPUTOP_SPMC1		MCUCFG_REG(0x22A4)
+
+#define MP2_COQ				MCUCFG_REG(0x22BC)
+#define MP2_COQ_SW_DIS			BIT(0)
+
+#define MP2_CA15M_MON_SEL		MCUCFG_REG(0x2400)
+#define MP2_CA15M_MON_L			MCUCFG_REG(0x2404)
+
+#define CPUSYS2_CPU0_SPMC_CTL		MCUCFG_REG(0x2430)
+#define CPUSYS2_CPU1_SPMC_CTL		MCUCFG_REG(0x2438)
+#define CPUSYS2_CPU0_SPMC_STA		MCUCFG_REG(0x2434)
+#define CPUSYS2_CPU1_SPMC_STA		MCUCFG_REG(0x243C)
+
+#define MP0_CA7L_DBG_PWR_CTRL		MCUCFG_REG(0x068)
+#define MP1_CA7L_DBG_PWR_CTRL		MCUCFG_REG(0x268)
+#define BIG_DBG_PWR_CTRL		MCUCFG_REG(0x75C)
+
+#define MP2_SW_RST_B			BIT(0)
+#define MP2_TOPAON_APB_MASK		BIT(1)
+
+#define B_SW_HOT_PLUG_RESET		BIT(30)
+
+#define B_SW_PD_OFFSET			18U
+#define B_SW_PD				(U(0x3f) << B_SW_PD_OFFSET)
+
+#define B_SW_SRAM_SLEEPB_OFFSET		12U
+#define B_SW_SRAM_SLEEPB		(U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET)
+
+#define B_SW_SRAM_ISOINTB		BIT(9)
+#define B_SW_ISO			BIT(8)
+#define B_SW_LOGIC_PDB			BIT(7)
+#define B_SW_LOGIC_PRE2_PDB		BIT(6)
+#define B_SW_LOGIC_PRE1_PDB		BIT(5)
+#define B_SW_FSM_OVERRIDE		BIT(4)
+#define B_SW_PWR_ON			BIT(3)
+#define B_SW_PWR_ON_OVERRIDE_EN		BIT(2)
+
+#define B_FSM_STATE_OUT_OFFSET		(6U)
+#define B_FSM_STATE_OUT_MASK		(U(0x1f) << B_FSM_STATE_OUT_OFFSET)
+#define B_SW_LOGIC_PDBO_ALL_OFF_ACK	BIT(5)
+#define B_SW_LOGIC_PDBO_ALL_ON_ACK	BIT(4)
+#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK	BIT(3)
+#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK	BIT(2)
+
+#define B_FSM_OFF			(0U << B_FSM_STATE_OUT_OFFSET)
+#define B_FSM_ON			(1U << B_FSM_STATE_OUT_OFFSET)
+#define B_FSM_RET			(2U << B_FSM_STATE_OUT_OFFSET)
+
+#ifndef __ASSEMBLER__
+/* cpu boot mode */
+enum {
+	MP0_CPUCFG_64BIT_SHIFT = 12U,
+	MP1_CPUCFG_64BIT_SHIFT = 28U,
+	MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT,
+	MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT
+};
+
+enum {
+	MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U,
+	MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U,
+	MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U,
+	MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U,
+	MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U,
+
+	MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
+	MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
+	MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
+	MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
+	MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
+		U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
+};
+
+enum {
+	MP1_AINACTS_SHIFT = 4U,
+	MP1_AINACTS = 1U << MP1_AINACTS_SHIFT
+};
+
+enum {
+	MP1_SW_CG_GEN_SHIFT = 12U,
+	MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT
+};
+
+enum {
+	MP1_L2RSTDISABLE_SHIFT = 14U,
+	MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT
+};
+#endif /* __ASSEMBLER__ */
+
+#endif  /* MCUCFG_H */
diff --git a/plat/mediatek/mt8195/include/plat_helpers.h b/plat/mediatek/mt8195/include/plat_helpers.h
new file mode 100644
index 0000000..ebc9fa0
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_HELPERS_H__
+#define __PLAT_HELPERS_H__
+
+unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+
+#endif /* __PLAT_HELPERS_H__ */
diff --git a/plat/mediatek/mt8195/include/plat_macros.S b/plat/mediatek/mt8195/include/plat_macros.S
new file mode 100644
index 0000000..39727ea
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_macros.S
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <platform_def.h>
+
+.section .rodata.gic_reg_name, "aS"
+gicc_regs:
+	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
+gicd_pend_reg:
+	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
+		" Offset:\t\t\tvalue\n"
+newline:
+	.asciz "\n"
+spacer:
+	.asciz ":\t\t0x"
+
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
+	/* ---------------------------------------------
+	 * The below macro prints out relevant GIC
+	 * registers whenever an unhandled exception
+	 * is taken in BL31.
+	 * Clobbers: x0 - x10, x26, x27, sp
+	 * ---------------------------------------------
+	 */
+	.macro plat_crash_print_regs
+	/* TODO: leave implementation to GIC owner */
+	.endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/mediatek/mt8195/include/plat_mtk_lpm.h b/plat/mediatek/mt8195/include/plat_mtk_lpm.h
new file mode 100644
index 0000000..347f358
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_mtk_lpm.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MTK_LPM_H
+#define PLAT_MTK_LPM_H
+
+#include <lib/psci/psci.h>
+#include <lib/utils_def.h>
+
+#define MT_IRQ_REMAIN_MAX	U(32)
+#define MT_IRQ_REMAIN_CAT_LOG	BIT(31)
+
+struct mt_irqremain {
+	unsigned int count;
+	unsigned int irqs[MT_IRQ_REMAIN_MAX];
+	unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX];
+	unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX];
+};
+
+#define PLAT_RC_STATUS_READY		BIT(0)
+#define PLAT_RC_STATUS_FEATURE_EN	BIT(1)
+#define PLAT_RC_STATUS_UART_NONSLEEP	BIT(31)
+
+struct mt_lpm_tz {
+	int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
+	int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
+
+	int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
+	int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
+
+	int (*pwr_cluster_on)(unsigned int cpu,
+					const psci_power_state_t *state);
+	int (*pwr_cluster_dwn)(unsigned int cpu,
+					const psci_power_state_t *state);
+
+	int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
+	int (*pwr_mcusys_on_finished)(unsigned int cpu,
+					const psci_power_state_t *state);
+	int (*pwr_mcusys_dwn)(unsigned int cpu,
+					const psci_power_state_t *state);
+};
+
+const struct mt_lpm_tz *mt_plat_cpu_pm_init(void);
+
+#endif /* PLAT_MTK_LPM_H */
diff --git a/plat/mediatek/mt8195/include/plat_pm.h b/plat/mediatek/mt8195/include/plat_pm.h
new file mode 100644
index 0000000..a2881ce
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_pm.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PM_H
+#define PLAT_PM_H
+
+#include <lib/utils_def.h>
+
+#define MT_PLAT_PWR_STATE_CPU			U(1)
+#define MT_PLAT_PWR_STATE_CLUSTER		U(2)
+#define MT_PLAT_PWR_STATE_MCUSYS		U(3)
+#define MT_PLAT_PWR_STATE_SUSPEND2IDLE		U(8)
+#define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND	U(9)
+
+#define MTK_LOCAL_STATE_RUN			U(0)
+#define MTK_LOCAL_STATE_RET			U(1)
+#define MTK_LOCAL_STATE_OFF			U(2)
+
+#define MTK_AFFLVL_CPU				U(0)
+#define MTK_AFFLVL_CLUSTER			U(1)
+#define MTK_AFFLVL_MCUSYS			U(2)
+#define MTK_AFFLVL_SYSTEM			U(3)
+
+#define IS_CLUSTER_OFF_STATE(s)		\
+		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
+#define IS_MCUSYS_OFF_STATE(s)		\
+		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
+#define IS_SYSTEM_SUSPEND_STATE(s)	\
+		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
+
+#define IS_PLAT_SUSPEND_ID(stateid)\
+		((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)	\
+		|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+
+#endif /* PLAT_PM_H */
diff --git a/plat/mediatek/mt8195/include/plat_private.h b/plat/mediatek/mt8195/include/plat_private.h
new file mode 100644
index 0000000..7ef2b85
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_private.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PRIVATE_H
+#define PLAT_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+			    uintptr_t total_size,
+			    uintptr_t ro_start,
+			    uintptr_t ro_limit);
+
+#endif /* PLAT_PRIVATE_H */
diff --git a/plat/mediatek/mt8195/include/plat_sip_calls.h b/plat/mediatek/mt8195/include/plat_sip_calls.h
new file mode 100644
index 0000000..181aec0
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_sip_calls.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_SIP_CALLS_H
+#define PLAT_SIP_CALLS_H
+
+/*******************************************************************************
+ * Plat SiP function constants
+ ******************************************************************************/
+#define MTK_PLAT_SIP_NUM_CALLS    2
+
+/* DP/eDP */
+#define MTK_SIP_DP_CONTROL_AARCH32	0x82000523
+#define MTK_SIP_DP_CONTROL_AARCH64	0xC2000523
+
+#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
new file mode 100644
index 0000000..b84e73f
--- /dev/null
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#define PLAT_PRIMARY_CPU	0x0
+
+#define MT_GIC_BASE		(0x0C000000)
+#define MCUCFG_BASE		(0x0C530000)
+#define IO_PHYS			(0x10000000)
+
+/* Aggregate of all devices for MMU mapping */
+#define MTK_DEV_RNG0_BASE	IO_PHYS
+#define MTK_DEV_RNG0_SIZE	0x10000000
+#define MTK_DEV_RNG2_BASE	MT_GIC_BASE
+#define MTK_DEV_RNG2_SIZE	0x600000
+#define MTK_MCDI_SRAM_BASE	0x11B000
+#define MTK_MCDI_SRAM_MAP_SIZE	0x1000
+
+#define TOPCKGEN_BASE           (IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE        (IO_PHYS + 0x00001000)
+#define SPM_BASE		(IO_PHYS + 0x00006000)
+#define APMIXEDSYS              (IO_PHYS + 0x0000C000)
+#define SSPM_MBOX_BASE          (IO_PHYS + 0x00480000)
+#define PERICFG_AO_BASE         (IO_PHYS + 0x01003000)
+#define VPPSYS0_BASE            (IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE            (IO_PHYS + 0x04f00000)
+#define VDOSYS0_BASE            (IO_PHYS + 0x0C01A000)
+#define VDOSYS1_BASE            (IO_PHYS + 0x0C100000)
+
+/*******************************************************************************
+ * DP/eDP related constants
+ ******************************************************************************/
+#define eDP_SEC_BASE		(IO_PHYS + 0x0C504000)
+#define DP_SEC_BASE		(IO_PHYS + 0x0C604000)
+#define eDP_SEC_SIZE		0x1000
+#define DP_SEC_SIZE		0x1000
+
+/*******************************************************************************
+ * GPIO related constants
+ ******************************************************************************/
+#define GPIO_BASE		(IO_PHYS + 0x00005000)
+#define IOCFG_BM_BASE		(IO_PHYS + 0x01D10000)
+#define IOCFG_BL_BASE		(IO_PHYS + 0x01D30000)
+#define IOCFG_BR_BASE		(IO_PHYS + 0x01D40000)
+#define IOCFG_LM_BASE		(IO_PHYS + 0x01E20000)
+#define IOCFG_RB_BASE		(IO_PHYS + 0x01EB0000)
+#define IOCFG_TL_BASE		(IO_PHYS + 0x01F40000)
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define UART0_BASE			(IO_PHYS + 0x01001100)
+#define UART1_BASE			(IO_PHYS + 0x01001200)
+
+#define UART_BAUDRATE			115200
+
+/*******************************************************************************
+ * PMIC related constants
+ ******************************************************************************/
+#define PMIC_WRAP_BASE			(IO_PHYS + 0x00024000)
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define SYS_COUNTER_FREQ_IN_TICKS	13000000
+#define SYS_COUNTER_FREQ_IN_MHZ		13
+
+/*******************************************************************************
+ * GIC-600 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE			MT_GIC_BASE
+#define MT_GIC_RDIST_BASE		(MT_GIC_BASE + 0x40000)
+
+#define SYS_CIRQ_BASE			(IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM			23
+#define CIRQ_IRQ_NUM			730
+#define CIRQ_SPI_START			96
+#define MD_WDT_IRQ_BIT_ID		141
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+#define PLATFORM_STACK_SIZE		0x800
+
+#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+
+#define PLAT_MAX_PWR_LVL		U(3)
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(9)
+
+#define PLATFORM_SYSTEM_COUNT		U(1)
+#define PLATFORM_MCUSYS_COUNT		U(1)
+#define PLATFORM_CLUSTER_COUNT		U(1)
+#define PLATFORM_CLUSTER0_CORE_COUNT	U(8)
+#define PLATFORM_CLUSTER1_CORE_COUNT	U(0)
+
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(8)
+
+#define SOC_CHIP_ID			U(0x8195)
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define TZRAM_BASE			0x54600000
+#define TZRAM_SIZE			0x00030000
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
+ */
+#define BL31_BASE			(TZRAM_BASE + 0x1000)
+#define BL31_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#define MAX_XLAT_TABLES			16
+#define MAX_MMAP_REGIONS		16
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT		6
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8195/include/rtc.h b/plat/mediatek/mt8195/include/rtc.h
new file mode 100644
index 0000000..a9c7bc8
--- /dev/null
+++ b/plat/mediatek/mt8195/include/rtc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+#include <rtc_mt6359p.h>
+
+#endif  /* RTC_H */
diff --git a/plat/mediatek/mt8195/plat_pm.c b/plat/mediatek/mt8195/plat_pm.c
new file mode 100644
index 0000000..2beeb02
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_pm.c
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* common headers */
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/gpio.h>
+#include <lib/psci/psci.h>
+
+/* platform specific headers */
+#include <mt_gic_v3.h>
+#include <mtk_ptp3_common.h>
+#include <mtspmc.h>
+#include <plat/common/platform.h>
+#include <plat_mtk_lpm.h>
+#include <plat_params.h>
+#include <plat_pm.h>
+#include <pmic.h>
+#include <rtc.h>
+
+/*
+ * Cluster state request:
+ * [0] : The CPU requires cluster power down
+ * [1] : The CPU requires cluster power on
+ */
+#define coordinate_cluster(onoff)	write_clusterpwrdn_el1(onoff)
+#define coordinate_cluster_pwron()	coordinate_cluster(1)
+#define coordinate_cluster_pwroff()	coordinate_cluster(0)
+
+/* platform secure entry point */
+static uintptr_t secure_entrypoint;
+/* per-CPU power state */
+static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
+
+/* platform CPU power domain - ops */
+static const struct mt_lpm_tz *plat_mt_pm;
+
+#define plat_mt_pm_invoke(_name, _cpu, _state) ({ \
+	int ret = -1; \
+	if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
+		ret = plat_mt_pm->_name(_cpu, _state); \
+	} \
+	ret; })
+
+#define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \
+	if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
+		(void) plat_mt_pm->_name(_cpu, _state); \
+	} \
+	})
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_cpu_pwrdwn_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state);
+
+	if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
+			(req_pstate == 0U)) { /* hotplug off */
+		coordinate_cluster_pwroff();
+	}
+
+	/* Prevent interrupts from spuriously waking up this CPU */
+	mt_gic_rdistif_save();
+	gicv3_cpuif_disable(cpu);
+	gicv3_rdistif_off(cpu);
+}
+
+static void plat_cpu_pwron_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state);
+
+	coordinate_cluster_pwron();
+
+	/* PTP3 config */
+	ptp3_core_init(cpu);
+
+	/*
+	 * If mcusys does power down before then restore
+	 * all CPUs' GIC Redistributors
+	 */
+	if (IS_MCUSYS_OFF_STATE(state)) {
+		mt_gic_rdistif_restore_all();
+	} else {
+		gicv3_rdistif_on(cpu);
+		gicv3_cpuif_enable(cpu);
+		mt_gic_rdistif_init();
+		mt_gic_rdistif_restore();
+	}
+}
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_cluster_pwrdwn_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) {
+		coordinate_cluster_pwron();
+
+		/* TODO: return on fail.
+		 *       Add a 'return' here before adding any code following
+		 *       the if-block.
+		 */
+	}
+}
+
+static void plat_cluster_pwron_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) {
+		/* TODO: return on fail.
+		 *       Add a 'return' here before adding any code following
+		 *       the if-block.
+		 */
+	}
+}
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_mcusys_pwrdwn_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) {
+		return;		/* return on fail */
+	}
+
+	mt_gic_distif_save();
+	gic_sgi_save_all();
+}
+
+static void plat_mcusys_pwron_common(unsigned int cpu,
+		const psci_power_state_t *state, unsigned int req_pstate)
+{
+	assert(cpu == plat_my_core_pos());
+
+	if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) {
+		return;		/* return on fail */
+	}
+
+	mt_gic_init();
+	mt_gic_distif_restore();
+	gic_sgi_restore_all();
+
+	plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
+}
+
+/*
+ * plat_psci_ops implementation
+ */
+
+static void plat_cpu_standby(plat_local_state_t cpu_state)
+{
+	uint64_t scr;
+
+	scr = read_scr_el3();
+	write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
+
+	isb();
+	dsb();
+	wfi();
+
+	write_scr_el3(scr);
+}
+
+static int plat_power_domain_on(u_register_t mpidr)
+{
+	unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+	unsigned int cluster = 0U;
+
+	if (cpu >= PLATFORM_CORE_COUNT) {
+		return PSCI_E_INVALID_PARAMS;
+	}
+
+	if (!spm_get_cluster_powerstate(cluster)) {
+		spm_poweron_cluster(cluster);
+	}
+
+	/* init CPU reset arch as AARCH64 */
+	mcucfg_init_archstate(cluster, cpu, true);
+	mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+	spm_poweron_cpu(cluster, cpu);
+
+	return PSCI_E_SUCCESS;
+}
+
+static void plat_power_domain_on_finish(const psci_power_state_t *state)
+{
+	unsigned long mpidr = read_mpidr_el1();
+	unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+
+	assert(cpu < PLATFORM_CORE_COUNT);
+
+	/* Allow IRQs to wakeup this core in IDLE flow */
+	mcucfg_enable_gic_wakeup(0U, cpu);
+
+	if (IS_CLUSTER_OFF_STATE(state)) {
+		plat_cluster_pwron_common(cpu, state, 0U);
+	}
+
+	plat_cpu_pwron_common(cpu, state, 0U);
+}
+
+static void plat_power_domain_off(const psci_power_state_t *state)
+{
+	unsigned long mpidr = read_mpidr_el1();
+	unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+
+	assert(cpu < PLATFORM_CORE_COUNT);
+
+	plat_cpu_pwrdwn_common(cpu, state, 0U);
+	spm_poweroff_cpu(0U, cpu);
+
+	/* prevent unintended IRQs from waking up the hot-unplugged core */
+	mcucfg_disable_gic_wakeup(0U, cpu);
+
+	if (IS_CLUSTER_OFF_STATE(state)) {
+		plat_cluster_pwrdwn_common(cpu, state, 0U);
+	}
+}
+
+static void plat_power_domain_suspend(const psci_power_state_t *state)
+{
+	unsigned int cpu = plat_my_core_pos();
+
+	assert(cpu < PLATFORM_CORE_COUNT);
+
+	plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state);
+
+	/* Perform the common CPU specific operations */
+	plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+
+	if (IS_CLUSTER_OFF_STATE(state)) {
+		/* Perform the common cluster specific operations */
+		plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+	}
+
+	if (IS_MCUSYS_OFF_STATE(state)) {
+		/* Perform the common mcusys specific operations */
+		plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+	}
+}
+
+static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
+{
+	unsigned int cpu = plat_my_core_pos();
+
+	assert(cpu < PLATFORM_CORE_COUNT);
+
+	if (IS_MCUSYS_OFF_STATE(state)) {
+		/* Perform the common mcusys specific operations */
+		plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
+	}
+
+	if (IS_CLUSTER_OFF_STATE(state)) {
+		/* Perform the common cluster specific operations */
+		plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
+	}
+
+	/* Perform the common CPU specific operations */
+	plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
+
+	plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state);
+}
+
+static int plat_validate_power_state(unsigned int power_state,
+					psci_power_state_t *req_state)
+{
+	unsigned int pstate = psci_get_pstate_type(power_state);
+	unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
+	unsigned int cpu = plat_my_core_pos();
+
+	if (aff_lvl > PLAT_MAX_PWR_LVL) {
+		return PSCI_E_INVALID_PARAMS;
+	}
+
+	if (pstate == PSTATE_TYPE_STANDBY) {
+		req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
+	} else {
+		unsigned int i;
+		unsigned int pstate_id = psci_get_pstate_id(power_state);
+		plat_local_state_t s = MTK_LOCAL_STATE_OFF;
+
+		/* Use pstate_id to be power domain state */
+		if (pstate_id > s) {
+			s = (plat_local_state_t)pstate_id;
+		}
+
+		for (i = 0U; i <= aff_lvl; i++) {
+			req_state->pwr_domain_state[i] = s;
+		}
+	}
+
+	plat_power_state[cpu] = power_state;
+	return PSCI_E_SUCCESS;
+}
+
+static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+	unsigned int lv;
+	unsigned int cpu = plat_my_core_pos();
+
+	for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
+		req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
+	}
+
+	plat_power_state[cpu] =
+			psci_make_powerstate(
+				MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
+				PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
+
+	flush_dcache_range((uintptr_t)
+			&plat_power_state[cpu],
+			sizeof(plat_power_state[cpu]));
+}
+
+/*******************************************************************************
+ * MTK handlers to shutdown/reboot the system
+ ******************************************************************************/
+static void __dead2 plat_mtk_system_reset(void)
+{
+	struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
+
+	INFO("MTK System Reset\n");
+
+	gpio_set_value(gpio_reset->index, gpio_reset->polarity);
+
+	wfi();
+	ERROR("MTK System Reset: operation not handled.\n");
+	panic();
+}
+
+static void __dead2 plat_mtk_system_off(void)
+{
+	INFO("MTK System Off\n");
+
+	rtc_power_off_sequence();
+	pmic_power_off();
+
+	wfi();
+	ERROR("MTK System Off: operation not handled.\n");
+	panic();
+}
+
+static const plat_psci_ops_t plat_psci_ops = {
+	.system_reset			= plat_mtk_system_reset,
+	.system_off			= plat_mtk_system_off,
+	.cpu_standby			= plat_cpu_standby,
+	.pwr_domain_on			= plat_power_domain_on,
+	.pwr_domain_on_finish		= plat_power_domain_on_finish,
+	.pwr_domain_off			= plat_power_domain_off,
+	.pwr_domain_suspend		= plat_power_domain_suspend,
+	.pwr_domain_suspend_finish	= plat_power_domain_suspend_finish,
+	.validate_power_state		= plat_validate_power_state,
+	.get_sys_suspend_power_state	= plat_get_sys_suspend_power_state
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+			const plat_psci_ops_t **psci_ops)
+{
+	*psci_ops = &plat_psci_ops;
+	secure_entrypoint = sec_entrypoint;
+
+	/*
+	 * init the warm reset config for boot CPU
+	 * reset arch as AARCH64
+	 * reset addr as function bl31_warm_entrypoint()
+	 */
+	mcucfg_init_archstate(0U, 0U, true);
+	mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
+
+	spmc_init();
+	plat_mt_pm = mt_plat_cpu_pm_init();
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
new file mode 100644
index 0000000..99e1eb3
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_sip_calls.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <mt_dp.h>
+#include <mtk_sip_svc.h>
+#include "plat_sip_calls.h"
+
+uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
+				u_register_t x1,
+				u_register_t x2,
+				u_register_t x3,
+				u_register_t x4,
+				void *cookie,
+				void *handle,
+				u_register_t flags)
+{
+	int32_t ret;
+	uint32_t ret_val;
+
+	switch (smc_fid) {
+	case MTK_SIP_DP_CONTROL_AARCH32:
+	case MTK_SIP_DP_CONTROL_AARCH64:
+		ret = dp_secure_handler(x1, x2, &ret_val);
+		SMC_RET2(handle, ret, ret_val);
+		break;
+	default:
+		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+		break;
+	}
+
+	SMC_RET1(handle, SMC_UNK);
+}
diff --git a/plat/mediatek/mt8195/plat_topology.c b/plat/mediatek/mt8195/plat_topology.c
new file mode 100644
index 0000000..bc95c64
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_topology.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+
+#include <plat_helpers.h>
+#include <platform_def.h>
+
+const unsigned char mtk_power_domain_tree_desc[] = {
+	/* Number of root nodes */
+	PLATFORM_SYSTEM_COUNT,
+	/* Number of children for the root node */
+	PLATFORM_MCUSYS_COUNT,
+	/* Number of children for the mcusys node */
+	PLATFORM_CLUSTER_COUNT,
+	/* Number of children for the first cluster node */
+	PLATFORM_CLUSTER0_CORE_COUNT,
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return mtk_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	unsigned int cluster_id, cpu_id;
+
+	if ((read_mpidr() & MPIDR_MT_MASK) != 0) {
+		/* ARMv8.2 arch */
+		if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) {
+			return -1;
+		}
+		return plat_mediatek_calc_core_pos(mpidr);
+	}
+
+	mpidr &= MPIDR_AFFINITY_MASK;
+
+	if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) {
+		return -1;
+	}
+
+	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+	if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
+		return -1;
+	}
+
+	/*
+	 * Validate cpu_id by checking whether it represents a CPU in
+	 * one of the two clusters present on the platform.
+	 */
+	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
+		return -1;
+	}
+
+	return (cpu_id + (cluster_id * 8));
+}
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
new file mode 100644
index 0000000..f4604c4
--- /dev/null
+++ b/plat/mediatek/mt8195/platform.mk
@@ -0,0 +1,93 @@
+#
+# Copyright (c) 2021, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+MTK_PLAT     := plat/mediatek
+MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
+
+PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
+                 -I${MTK_PLAT}/common/drivers/gic600/             \
+                 -I${MTK_PLAT}/common/drivers/gpio/               \
+                 -I${MTK_PLAT}/common/drivers/rtc/                \
+                 -I${MTK_PLAT}/common/drivers/timer/              \
+                 -I${MTK_PLAT}/common/drivers/uart/               \
+                 -I${MTK_PLAT}/common/lpm/                        \
+                 -I${MTK_PLAT_SOC}/drivers/dcm                    \
+                 -I${MTK_PLAT_SOC}/drivers/dp/                    \
+                 -I${MTK_PLAT_SOC}/drivers/gpio/                  \
+                 -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
+                 -I${MTK_PLAT_SOC}/drivers/pmic/                  \
+                 -I${MTK_PLAT_SOC}/drivers/spmc/                  \
+                 -I${MTK_PLAT_SOC}/drivers/ptp3/                   \
+                 -I${MTK_PLAT_SOC}/include/
+
+GICV3_SUPPORT_GIC600        :=      1
+include drivers/arm/gic/v3/gicv3.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES}                              \
+                          ${XLAT_TABLES_LIB_SRCS}                       \
+                          plat/common/aarch64/crash_console_helpers.S   \
+                          plat/common/plat_psci_common.c
+
+
+BL31_SOURCES += common/desc_image_load.c                              \
+                drivers/delay_timer/delay_timer.c                     \
+                drivers/gpio/gpio.c                                   \
+                drivers/delay_timer/generic_delay_timer.c             \
+                drivers/ti/uart/aarch64/16550_console.S               \
+                lib/bl_aux_params/bl_aux_params.c                     \
+                lib/cpus/aarch64/cortex_a55.S                         \
+                lib/cpus/aarch64/cortex_a78.S                         \
+                plat/common/plat_gicv3.c                              \
+                ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c         \
+                ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c       \
+                ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
+                ${MTK_PLAT}/common/drivers/rtc/rtc_common.c           \
+                ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c          \
+                ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
+		${MTK_PLAT}/common/drivers/uart/uart.c                \
+		${MTK_PLAT}/common/lpm/mt_lp_rm.c                     \
+                ${MTK_PLAT}/common/mtk_cirq.c                         \
+                ${MTK_PLAT}/common/mtk_plat_common.c                  \
+                ${MTK_PLAT}/common/mtk_sip_svc.c                      \
+                ${MTK_PLAT}/common/params_setup.c                     \
+                ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
+                ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
+                ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
+                ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c                 \
+                ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c           \
+                ${MTK_PLAT_SOC}/drivers/dp/mt_dp.c                    \
+                ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c              \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c          \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c                \
+		${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c        \
+                ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
+                ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
+                ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c          \
+                ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
+                ${MTK_PLAT_SOC}/plat_pm.c                             \
+                ${MTK_PLAT_SOC}/plat_sip_calls.c                      \
+                ${MTK_PLAT_SOC}/plat_topology.c
+
+# Build SPM drivers
+include ${MTK_PLAT_SOC}/drivers/spm/build.mk
+
+# Configs for A78 and A55
+HW_ASSISTED_COHERENCY := 1
+USE_COHERENT_MEM := 0
+CTX_INCLUDE_AARCH32_REGS := 0
+ERRATA_A55_1530923 := 1
+
+# indicate the reset vector address can be programmed
+PROGRAMMABLE_RESET_ADDRESS := 1
+
+COLD_BOOT_SINGLE_CPU := 1
+
+MACH_MT8195 := 1
+$(eval $(call add_define,MACH_MT8195))
+
+include lib/coreboot/coreboot.mk
diff --git a/plat/nvidia/tegra/common/tegra_platform.c b/plat/nvidia/tegra/common/tegra_platform.c
index d45d988..3894b74 100644
--- a/plat/nvidia/tegra/common/tegra_platform.c
+++ b/plat/nvidia/tegra/common/tegra_platform.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -280,9 +280,9 @@
 int32_t plat_get_soc_version(void)
 {
 	uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
-	uint32_t manfid = (JEDEC_NVIDIA_BKID << 24) | (JEDEC_NVIDIA_MFID << 16);
+	uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_NVIDIA_BKID, JEDEC_NVIDIA_MFID);
 
-	return (int32_t)(manfid | (chip_id & 0xFFFF));
+	return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
 }
 
 /*
@@ -293,7 +293,8 @@
  */
 int32_t plat_get_soc_revision(void)
 {
-	return (int32_t)((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor());
+	return (int32_t)(((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor()) &
+			 SOC_ID_REV_MASK);
 }
 
 /*****************************************************************************
diff --git a/plat/nxp/common/plat_make_helper/plat_common_def.mk b/plat/nxp/common/plat_make_helper/plat_common_def.mk
new file mode 100644
index 0000000..86dacf8
--- /dev/null
+++ b/plat/nxp/common/plat_make_helper/plat_common_def.mk
@@ -0,0 +1,103 @@
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Include build macros, for example: SET_NXP_MAKE_FLAG
+include plat/nxp/common/plat_make_helper/plat_build_macros.mk
+
+# Adding platform specific defines
+
+$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
+
+ifeq (${POVDD_ENABLE},yes)
+$(eval $(call add_define,CONFIG_POVDD_ENABLE))
+endif
+
+ifneq (${FLASH_TYPE},)
+$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
+endif
+
+ifneq (${XSPI_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
+endif
+
+ifneq (${QSPI_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_QSPI_FLASH_SIZE,${QSPI_FLASH_SZ}))
+endif
+
+ifneq (${NOR_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_NOR_FLASH_SIZE,${NOR_FLASH_SZ}))
+endif
+
+
+ifneq (${FSPI_ERASE_4K},)
+$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
+endif
+
+ifneq (${NUM_OF_DDRC},)
+$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
+endif
+
+ifeq (${CONFIG_DDR_NODIMM},1)
+$(eval $(call add_define,CONFIG_DDR_NODIMM))
+DDRC_NUM_DIMM := 1
+endif
+
+ifneq (${DDRC_NUM_DIMM},)
+$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
+endif
+
+ifneq (${DDRC_NUM_CS},)
+$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
+endif
+
+ifeq (${DDR_ADDR_DEC},yes)
+$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
+endif
+
+ifeq (${DDR_ECC_EN},yes)
+$(eval $(call add_define,CONFIG_DDR_ECC_EN))
+endif
+
+ifeq (${CONFIG_STATIC_DDR},1)
+$(eval $(call add_define,CONFIG_STATIC_DDR))
+endif
+
+# Platform can control the base address for non-volatile storage.
+#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
+
+ifeq (${WARM_BOOT},yes)
+$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
+endif
+
+# Selecting Boot Source for the TFA images.
+define add_boot_mode_define
+    ifeq ($(1),qspi)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,QSPI_NEEDED,BL2))
+        $$(eval $$(call add_define,QSPI_BOOT))
+    else ifeq ($(1),sd)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+        $$(eval $$(call add_define,SD_BOOT))
+    else ifeq ($(1),emmc)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+        $$(eval $$(call add_define,EMMC_BOOT))
+    else ifeq ($(1),nor)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NOR_NEEDED,BL2))
+        $$(eval $$(call add_define,NOR_BOOT))
+    else ifeq ($(1),nand)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NAND_NEEDED,BL2))
+        $$(eval $$(call add_define,NAND_BOOT))
+    else ifeq ($(1),flexspi_nor)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
+        $$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
+    else
+        $$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE))
+    endif
+endef
+
+ifneq (,$(findstring $(BOOT_MODE),$(SUPPORTED_BOOT_MODE)))
+    $(eval $(call add_boot_mode_define,$(strip $(BOOT_MODE))))
+else
+    $(error $(PLAT) Un-supported Boot Mode = $(BOOT_MODE))
+endif
diff --git a/plat/nxp/common/plat_make_helper/soc_common_def.mk b/plat/nxp/common/plat_make_helper/soc_common_def.mk
new file mode 100644
index 0000000..fdd7249
--- /dev/null
+++ b/plat/nxp/common/plat_make_helper/soc_common_def.mk
@@ -0,0 +1,114 @@
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Adding SoC specific defines
+
+ifneq (${CACHE_LINE},)
+$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
+$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
+$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
+endif
+
+ifeq (${INTERCONNECT}, "CCI400")
+$(eval $(call add_define,NXP_HAS_${INTERCONNECT}))
+ICNNCT_ID := 0x420
+$(eval $(call add_define,ICNNCT_ID))
+endif
+
+ifeq (${INTERCONNECT}, "CCN508")
+$(eval $(call add_define,NXP_HAS_CCN508))
+endif
+
+ifneq (${CHASSIS},)
+$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
+endif
+
+ifneq (${PLAT_DDR_PHY},)
+$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
+endif
+
+ifneq (${PHYS_SYS},)
+$(eval $(call add_define,CONFIG_PHYS_64BIT))
+endif
+
+ifneq (${CSF_HDR_SZ},)
+$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
+endif
+
+ifneq (${OCRAM_START_ADDR},)
+$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
+endif
+
+ifneq (${OCRAM_SIZE},)
+$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
+endif
+
+ifneq (${NXP_ROM_RSVD},)
+$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
+endif
+
+ifneq (${BL2_BASE},)
+$(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
+endif
+
+ifeq (${SEC_MEM_NON_COHERENT},yes)
+$(eval $(call add_define,SEC_MEM_NON_COHERENT))
+endif
+
+ifneq (${NXP_ESDHC_ENDIANNESS},)
+$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SFP_VER},)
+$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
+endif
+
+ifneq (${NXP_SFP_ENDIANNESS},)
+$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
+endif
+
+ifneq (${NXP_GPIO_ENDIANNESS},)
+$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SNVS_ENDIANNESS},)
+$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
+endif
+
+ifneq (${NXP_GUR_ENDIANNESS},)
+$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
+endif
+
+ifneq (${NXP_FSPI_ENDIANNESS},)
+$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SEC_ENDIANNESS},)
+$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_DDR_ENDIANNESS},)
+$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
+endif
+
+ifneq (${NXP_QSPI_ENDIANNESS},)
+$(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SCFG_ENDIANNESS},)
+$(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS}))
+endif
+
+ifneq (${NXP_IFC_ENDIANNESS},)
+$(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_DDR_INTLV_256B},)
+$(eval $(call add_define,NXP_DDR_INTLV_256B))
+endif
+
+ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+endif
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
index 5b95222..226b22b 100644
--- a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
@@ -33,59 +33,19 @@
 # config is enabled for future use cases.
 FSPI_ERASE_4K	:= 0
 
- # Platform specific features.
+# Platform specific features.
 WARM_BOOT	:=	yes
 
- # Adding platform specific defines
-
-$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
-
-ifeq (${POVDD_ENABLE},yes)
-$(eval $(call add_define,CONFIG_POVDD_ENABLE))
-endif
-
-ifneq (${FLASH_TYPE},)
-$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
-endif
-
-ifneq (${XSPI_FLASH_SZ},)
-$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
-endif
-
-ifneq (${FSPI_ERASE_4K},)
-$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
-endif
-
-ifneq (${NUM_OF_DDRC},)
-$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
-endif
-
-ifneq (${DDRC_NUM_DIMM},)
-$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
-endif
-
-ifneq (${DDRC_NUM_CS},)
-$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
-endif
-
-ifeq (${DDR_ADDR_DEC},yes)
-$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
-endif
-
-ifeq (${DDR_ECC_EN},yes)
-$(eval $(call add_define,CONFIG_DDR_ECC_EN))
-endif
-
-# Platform can control the base address for non-volatile storage.
-#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
-
-ifeq (${WARM_BOOT},yes)
-$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
-endif
-
- # Adding Platform files build files
+# Adding Platform files build files
 BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
 			${BOARD_PATH}/platform.c
 
+SUPPORTED_BOOT_MODE	:=	flexspi_nor	\
+				sd		\
+				emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
- # Adding SoC build info
+# Adding SoC build info
 include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
index e56fbf1..ffb5fad 100644
--- a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
@@ -36,56 +36,16 @@
  # Platform specific features.
 WARM_BOOT	:=	no
 
- # Adding platform specific defines
-
-$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
-
-ifeq (${POVDD_ENABLE},yes)
-$(eval $(call add_define,CONFIG_POVDD_ENABLE))
-endif
-
-ifneq (${FLASH_TYPE},)
-$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
-endif
-
-ifneq (${XSPI_FLASH_SZ},)
-$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
-endif
-
-ifneq (${FSPI_ERASE_4K},)
-$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
-endif
-
-ifneq (${NUM_OF_DDRC},)
-$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
-endif
-
-ifneq (${DDRC_NUM_DIMM},)
-$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
-endif
-
-ifneq (${DDRC_NUM_CS},)
-$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
-endif
-
-ifeq (${DDR_ADDR_DEC},yes)
-$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
-endif
-
-ifeq (${DDR_ECC_EN},yes)
-$(eval $(call add_define,CONFIG_DDR_ECC_EN))
-endif
-
-# Platform can control the base address for non-volatile storage.
-#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
-
-ifeq (${WARM_BOOT},yes)
-$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
-endif
-
  # Adding Platform files build files
 BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
 			${BOARD_PATH}/platform.c
 
+SUPPORTED_BOOT_MODE	:=	flexspi_nor	\
+				sd		\
+				emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
  # Adding SoC build info
 include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk b/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
index fbdcd83..2b4712c 100644
--- a/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
@@ -25,7 +25,7 @@
 ERRATA_DDR_A050450	:= 1
 
 
- # On-Board Flash Details
+# On-Board Flash Details
 FLASH_TYPE	:=	MT35XU512A
 XSPI_FLASH_SZ	:=	0x10000000
 NXP_XSPI_NOR_UNIT_SIZE		:=	0x20000
@@ -34,59 +34,19 @@
 # config is enabled for future use cases.
 FSPI_ERASE_4K	:= 0
 
- # Platform specific features.
+# Platform specific features.
 WARM_BOOT	:=	yes
 
- # Adding platform specific defines
-
-$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
-
-ifeq (${POVDD_ENABLE},yes)
-$(eval $(call add_define,CONFIG_POVDD_ENABLE))
-endif
-
-ifneq (${FLASH_TYPE},)
-$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
-endif
-
-ifneq (${XSPI_FLASH_SZ},)
-$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
-endif
-
-ifneq (${FSPI_ERASE_4K},)
-$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
-endif
-
-ifneq (${NUM_OF_DDRC},)
-$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
-endif
-
-ifneq (${DDRC_NUM_DIMM},)
-$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
-endif
-
-ifneq (${DDRC_NUM_CS},)
-$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
-endif
-
-ifeq (${DDR_ADDR_DEC},yes)
-$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
-endif
-
-ifeq (${DDR_ECC_EN},yes)
-$(eval $(call add_define,CONFIG_DDR_ECC_EN))
-endif
-
-# Platform can control the base address for non-volatile storage.
-#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
-
-ifeq (${WARM_BOOT},yes)
-$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
-endif
-
- # Adding Platform files build files
+# Adding Platform files build files
 BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
 			${BOARD_PATH}/platform.c
 
+SUPPORTED_BOOT_MODE	:=	flexspi_nor	\
+				sd		\
+				emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
- # Adding SoC build info
+# Adding SoC build info
 include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/soc.def b/plat/nxp/soc-lx2160a/soc.def
index bd0dd15..24d1d13 100644
--- a/plat/nxp/soc-lx2160a/soc.def
+++ b/plat/nxp/soc-lx2160a/soc.def
@@ -91,7 +91,7 @@
 # Location of BL2 on OCRAM
 BL2_BASE_ADDR	:=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))
 # Covert to HEX to be used by create_pbl.mk
-BL2_BASE	:=	$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)
+BL2_BASE	:=	$(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
 
 # BL2_HDR_LOC is at  (OCRAM_ADDR + NXP_ROM_RSVD)
 # This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE
@@ -107,95 +107,5 @@
 # SoC Errata
 ERRATA_SOC_A050426	:= 1
 
-ifneq (${CACHE_LINE},)
-$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
-$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
-$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
-endif
-
-ifneq (${INTERCONNECT},)
-$(eval $(call add_define,NXP_HAS_CCN508))
-endif
-
-ifneq (${CHASSIS},)
-$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
-endif
-
-ifneq (${PLAT_DDR_PHY},)
-$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
-endif
-
-ifneq (${PHYS_SYS},)
-$(eval $(call add_define,CONFIG_PHYS_64BIT))
-endif
-
-ifneq (${CSF_HDR_SZ},)
-$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
-endif
-
-ifneq (${OCRAM_START_ADDR},)
-$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
-endif
-
-ifneq (${OCRAM_SIZE},)
-$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
-endif
-
-ifneq (${NXP_ROM_RSVD},)
-$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
-endif
-
-ifneq (${BL2_BASE_ADDR},)
-$(eval $(call add_define_val,BL2_BASE,${BL2_BASE_ADDR}))
-endif
-
-ifeq (${SEC_MEM_NON_COHERENT},yes)
-$(eval $(call add_define,SEC_MEM_NON_COHERENT))
-endif
-
-ifneq (${NXP_ESDHC_ENDIANNESS},)
-$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
-endif
-
-ifneq (${NXP_SFP_VER},)
-$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
-endif
-
-ifneq (${NXP_SFP_ENDIANNESS},)
-$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
-endif
-
-ifneq (${NXP_GPIO_ENDIANNESS},)
-$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
-endif
-
-ifneq (${NXP_SNVS_ENDIANNESS},)
-$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
-endif
-
-ifneq (${NXP_GUR_ENDIANNESS},)
-$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
-endif
-
-ifneq (${NXP_FSPI_ENDIANNESS},)
-$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
-endif
-
 # enable dynamic memory mapping
 PLAT_XLAT_TABLES_DYNAMIC :=	1
-
-ifneq (${NXP_SEC_ENDIANNESS},)
-$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
-endif
-
-ifneq (${NXP_DDR_ENDIANNESS},)
-$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
-endif
-
-ifneq (${NXP_DDR_INTLV_256B},)
-$(eval $(call add_define,NXP_DDR_INTLV_256B))
-endif
-
-ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
-$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
-endif
diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
index b9649b4..8ab1430 100644
--- a/plat/nxp/soc-lx2160a/soc.mk
+++ b/plat/nxp/soc-lx2160a/soc.mk
@@ -15,7 +15,7 @@
 
  # get SoC-specific defnitions
 include ${PLAT_SOC_PATH}/soc.def
-
+include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
 include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
 
  # SoC-specific
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index fbcaa63..0891d80 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -81,7 +81,7 @@
 #define SEC_ROM_SIZE			0x00020000
 
 #define NS_DRAM0_BASE			0x40000000
-#define NS_DRAM0_SIZE			0x3de00000
+#define NS_DRAM0_SIZE			0xc0000000
 
 #define SEC_SRAM_BASE			0x0e000000
 #define SEC_SRAM_SIZE			0x00060000
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 88a95c8..a3b353f 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -107,7 +107,10 @@
 ifeq (${ARM_ARCH_MAJOR},8)
 BL1_SOURCES		+=	lib/cpus/aarch64/aem_generic.S		\
 				lib/cpus/aarch64/cortex_a53.S		\
-				lib/cpus/aarch64/cortex_a57.S
+				lib/cpus/aarch64/cortex_a57.S		\
+				lib/cpus/aarch64/cortex_a72.S		\
+				lib/cpus/aarch64/qemu_max.S		\
+
 else
 BL1_SOURCES		+=	lib/cpus/${ARCH}/cortex_a15.S
 endif
@@ -135,9 +138,9 @@
 BL2_SOURCES		+=	drivers/io/io_encrypted.c
 endif
 
-QEMU_GICV2_SOURCES	:=	drivers/arm/gic/v2/gicv2_helpers.c	\
-				drivers/arm/gic/v2/gicv2_main.c		\
-				drivers/arm/gic/common/gic_common.c	\
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+QEMU_GICV2_SOURCES	:=	${GICV2_SOURCES}			\
 				plat/common/plat_gicv2.c		\
 				${PLAT_QEMU_COMMON_PATH}/qemu_gicv2.c
 
@@ -160,6 +163,8 @@
 BL31_SOURCES		+=	lib/cpus/aarch64/aem_generic.S		\
 				lib/cpus/aarch64/cortex_a53.S		\
 				lib/cpus/aarch64/cortex_a57.S		\
+				lib/cpus/aarch64/cortex_a72.S		\
+				lib/cpus/aarch64/qemu_max.S		\
 				lib/semihosting/semihosting.c		\
 				lib/semihosting/${ARCH}/semihosting_call.S \
 				plat/common/plat_psci_common.c		\
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index d45f3f1..9fb30ad 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -48,7 +48,8 @@
 				${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
 
 BL1_SOURCES		+=	lib/cpus/aarch64/cortex_a57.S			\
-				lib/cpus/aarch64/cortex_a72.S
+				lib/cpus/aarch64/cortex_a72.S			\
+				lib/cpus/aarch64/qemu_max.S			\
 
 BL2_SOURCES		+=	drivers/io/io_semihosting.c			\
 				drivers/io/io_storage.c				\
@@ -76,6 +77,7 @@
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a57.S			\
 				lib/cpus/aarch64/cortex_a72.S			\
+				lib/cpus/aarch64/qemu_max.S			\
 				lib/semihosting/semihosting.c			\
 				lib/semihosting/${ARCH}/semihosting_call.S	\
 				plat/common/plat_psci_common.c			\
diff --git a/plat/renesas/common/bl2_cpg_init.c b/plat/renesas/common/bl2_cpg_init.c
index 677a57d..ba8e53b 100644
--- a/plat/renesas/common/bl2_cpg_init.c
+++ b/plat/renesas/common/bl2_cpg_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,8 @@
 
 static void bl2_secure_cpg_init(void);
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
+	(RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 static void bl2_realtime_cpg_init_h3(void);
 static void bl2_system_cpg_init_h3(void);
 #endif
@@ -23,7 +24,7 @@
 static void bl2_system_cpg_init_m3(void);
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) || (RCAR_LSI == RZ_G2N)
 static void bl2_realtime_cpg_init_m3n(void);
 static void bl2_system_cpg_init_m3n(void);
 #endif
@@ -33,7 +34,7 @@
 static void bl2_system_cpg_init_v3m(void);
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 static void bl2_realtime_cpg_init_e3(void);
 static void bl2_system_cpg_init_e3(void);
 #endif
@@ -57,7 +58,7 @@
 #if (RCAR_LSI == RCAR_D3)
 	reset_cr2 = 0x00000000U;
 	stop_cr2 = 0xFFFFFFFFU;
-#elif (RCAR_LSI == RCAR_E3)
+#elif (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 	reset_cr2 = 0x10000000U;
 	stop_cr2 = 0xEFFFFFFFU;
 #else
@@ -106,7 +107,8 @@
 	cpg_write(SCSRSTECR11, 0x00000000U);
 }
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
+	(RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 static void bl2_realtime_cpg_init_h3(void)
 {
 	uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
@@ -185,7 +187,7 @@
 }
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)  || (RCAR_LSI == RZ_G2N)
 static void bl2_realtime_cpg_init_m3n(void)
 {
 	/* Realtime Module Stop Control Registers */
@@ -253,7 +255,7 @@
 }
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 static void bl2_realtime_cpg_init_e3(void)
 {
 	/* Realtime Module Stop Control Registers */
@@ -360,15 +362,15 @@
 			panic();
 			break;
 		}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 		bl2_realtime_cpg_init_h3();
 #elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
 		bl2_realtime_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
+#elif RCAR_LSI == RCAR_M3N || (RCAR_LSI == RZ_G2N)
 		bl2_realtime_cpg_init_m3n();
 #elif RCAR_LSI == RCAR_V3M
 		bl2_realtime_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
+#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
 		bl2_realtime_cpg_init_e3();
 #elif RCAR_LSI == RCAR_D3
 		bl2_realtime_cpg_init_d3();
@@ -406,15 +408,15 @@
 		panic();
 		break;
 	}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 	bl2_system_cpg_init_h3();
 #elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
 	bl2_system_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
+#elif RCAR_LSI == RCAR_M3N  || (RCAR_LSI == RZ_G2N)
 	bl2_system_cpg_init_m3n();
 #elif RCAR_LSI == RCAR_V3M
 	bl2_system_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
+#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
 	bl2_system_cpg_init_e3();
 #elif RCAR_LSI == RCAR_D3
 	bl2_system_cpg_init_d3();
diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk
index 984ab5b..fafce98 100644
--- a/plat/renesas/common/common.mk
+++ b/plat/renesas/common/common.mk
@@ -34,6 +34,9 @@
 RCAR_V3M:=6
 RCAR_AUTO:=99
 RZ_G2M:=100
+RZ_G2H:=101
+RZ_G2N:=102
+RZ_G2E:=103
 $(eval $(call add_define,RCAR_H3))
 $(eval $(call add_define,RCAR_M3))
 $(eval $(call add_define,RCAR_M3N))
@@ -43,6 +46,9 @@
 $(eval $(call add_define,RCAR_V3M))
 $(eval $(call add_define,RCAR_AUTO))
 $(eval $(call add_define,RZ_G2M))
+$(eval $(call add_define,RZ_G2H))
+$(eval $(call add_define,RZ_G2N))
+$(eval $(call add_define,RZ_G2E))
 
 RCAR_CUT_10:=0
 RCAR_CUT_11:=1
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 5e4978c..7a7a56c 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -293,12 +293,12 @@
   endif
 endif
 
-include drivers/renesas/rcar/ddr/ddr.mk
+include drivers/renesas/common/ddr/ddr.mk
 include drivers/renesas/rcar/qos/qos.mk
 include drivers/renesas/rcar/pfc/pfc.mk
 include lib/libfdt/libfdt.mk
 
-PLAT_INCLUDES	+=	-Idrivers/renesas/rcar/ddr		\
+PLAT_INCLUDES	+=	-Idrivers/renesas/common/ddr		\
 			-Idrivers/renesas/rcar/qos		\
 			-Idrivers/renesas/rcar/board		\
 			-Idrivers/renesas/rcar/cpld/		\
diff --git a/plat/renesas/rzg/bl2_plat_setup.c b/plat/renesas/rzg/bl2_plat_setup.c
index 13f413b..ccc2562 100644
--- a/plat/renesas/rzg/bl2_plat_setup.c
+++ b/plat/renesas/rzg/bl2_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -78,12 +78,26 @@
 #if RCAR_LSI == RZ_G2M
 #define TARGET_PRODUCT			PRR_PRODUCT_M3
 #define TARGET_NAME			"RZ/G2M"
+#elif RCAR_LSI == RZ_G2H
+#define TARGET_PRODUCT			PRR_PRODUCT_H3
+#define TARGET_NAME			"RZ/G2H"
+#elif RCAR_LSI == RZ_G2N
+#define TARGET_PRODUCT			PRR_PRODUCT_M3N
+#define TARGET_NAME			"RZ/G2N"
+#elif RCAR_LSI == RZ_G2E
+#define TARGET_PRODUCT			PRR_PRODUCT_E3
+#define TARGET_NAME			"RZ/G2E"
 #elif RCAR_LSI == RCAR_AUTO
 #define TARGET_NAME			"RZ/G2M"
 #endif /* RCAR_LSI == RZ_G2M */
 
+#if (RCAR_LSI == RZ_G2E)
+#define GPIO_INDT			(GPIO_INDT6)
+#define GPIO_BKUP_TRG_SHIFT		((uint32_t)1U << 13U)
+#else
 #define GPIO_INDT			(GPIO_INDT1)
 #define GPIO_BKUP_TRG_SHIFT		(1U << 8U)
+#endif /* RCAR_LSI == RZ_G2E */
 
 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
 	 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
@@ -424,6 +438,18 @@
 		ret = fdt_setprop_string(dt, 0, "compatible",
 					 "hoperun,hihope-rzg2m");
 		break;
+	case BOARD_HIHOPE_RZ_G2H:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "hoperun,hihope-rzg2h");
+		break;
+	case BOARD_HIHOPE_RZ_G2N:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "hoperun,hihope-rzg2n");
+		break;
+	case BOARD_EK874_RZ_G2E:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "si-linux,cat874");
+		break;
 	default:
 		NOTICE("BL2: Cannot set compatible string, board unsupported\n");
 		panic();
@@ -441,6 +467,18 @@
 		ret = fdt_appendprop_string(dt, 0, "compatible",
 					    "renesas,r8a774a1");
 		break;
+	case PRR_PRODUCT_H3:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774e1");
+		break;
+	case PRR_PRODUCT_M3N:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774b1");
+		break;
+	case PRR_PRODUCT_E3:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774c0");
+		break;
 	default:
 		NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
 		panic();
@@ -560,6 +598,42 @@
 		dram_config[1] = 0x80000000ULL;
 		dram_config[5] = 0x80000000ULL;
 		break;
+	case PRR_PRODUCT_H3:
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+		/* 4GB(1GBx4) */
+		dram_config[1] = 0x40000000ULL;
+		dram_config[3] = 0x40000000ULL;
+		dram_config[5] = 0x40000000ULL;
+		dram_config[7] = 0x40000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \
+	(RCAR_DRAM_SPLIT == 2)
+		/* 4GB(2GBx2 2ch split) */
+		dram_config[1] = 0x80000000ULL;
+		dram_config[3] = 0x80000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
+		/* 8GB(2GBx4: default) */
+		dram_config[1] = 0x80000000ULL;
+		dram_config[3] = 0x80000000ULL;
+		dram_config[5] = 0x80000000ULL;
+		dram_config[7] = 0x80000000ULL;
+#endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
+		break;
+	case PRR_PRODUCT_M3N:
+		/* 4GB(4GBx1) */
+		dram_config[1] = 0x100000000ULL;
+		break;
+	case PRR_PRODUCT_E3:
+#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
+		/* 1GB(512MBx2) */
+		dram_config[1] = 0x40000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
+		/* 2GB(512MBx4) */
+		dram_config[1] = 0x80000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
+		/* 4GB(1GBx4) */
+		dram_config[1] = 0x100000000ULL;
+#endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
+		break;
 	default:
 		NOTICE("BL2: Detected invalid DRAM entries\n");
 		break;
@@ -578,13 +652,23 @@
 	const char *unknown = "unknown";
 	const char *cpu_ca57 = "CA57";
 	const char *cpu_ca53 = "CA53";
+	const char *product_g2e = "G2E";
+	const char *product_g2h = "G2H";
 	const char *product_g2m = "G2M";
+	const char *product_g2n = "G2N";
 	const char *boot_hyper80 = "HyperFlash(80MHz)";
 	const char *boot_qspi40 = "QSPI Flash(40MHz)";
 	const char *boot_qspi80 = "QSPI Flash(80MHz)";
 	const char *boot_emmc25x1 = "eMMC(25MHz x1)";
 	const char *boot_emmc50x8 = "eMMC(50MHz x8)";
+#if (RCAR_LSI == RZ_G2E)
+	uint32_t sscg;
+	const char *sscg_on = "PLL1 SSCG Clock select";
+	const char *sscg_off = "PLL1 nonSSCG Clock select";
+	const char *boot_hyper160 = "HyperFlash(150MHz)";
+#else
 	const char *boot_hyper160 = "HyperFlash(160MHz)";
+#endif /* RCAR_LSI == RZ_G2E */
 #if RZG_LCS_STATE_DETECTION_ENABLE
 	uint32_t lcs;
 	const char *lcs_secure = "SE";
@@ -646,6 +730,15 @@
 	case PRR_PRODUCT_M3:
 		str = product_g2m;
 		break;
+	case PRR_PRODUCT_H3:
+		str = product_g2h;
+		break;
+	case PRR_PRODUCT_M3N:
+		str = product_g2n;
+		break;
+	case PRR_PRODUCT_E3:
+		str = product_g2e;
+		break;
 	default:
 		str = unknown;
 		break;
@@ -666,11 +759,23 @@
 		minor = reg & RCAR_MINOR_MASK;
 		NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor);
 	}
+
+#if (RCAR_LSI == RZ_G2E)
+	if (product == PRR_PRODUCT_E3) {
+		reg = mmio_read_32(RCAR_MODEMR);
+		sscg = reg & RCAR_SSCG_MASK;
+		str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
+		NOTICE("BL2: %s\n", str);
+	}
+#endif /* RCAR_LSI == RZ_G2E */
 
 	rzg_get_board_type(&type, &rev);
 
 	switch (type) {
 	case BOARD_HIHOPE_RZ_G2M:
+	case BOARD_HIHOPE_RZ_G2H:
+	case BOARD_HIHOPE_RZ_G2N:
+	case BOARD_EK874_RZ_G2E:
 		break;
 	default:
 		type = BOARD_UNKNOWN;
@@ -762,7 +867,7 @@
 
 	if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
 	    boot_cpu == MODEMR_BOOT_CPU_CA53) {
-		ret = rzg_dram_init();
+		ret = rcar_dram_init();
 		if (ret != 0) {
 			NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
 			panic();
@@ -884,6 +989,9 @@
 
 static void bl2_init_generic_timer(void)
 {
+#if RCAR_LSI == RZ_G2E
+	uint32_t reg_cntfid = EXTAL_EBISU;
+#else
 	uint32_t reg_cntfid;
 	uint32_t modemr;
 	uint32_t modemr_pll;
@@ -899,6 +1007,7 @@
 
 	/* Set frequency data in CNTFID0 */
 	reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
+#endif /* RCAR_LSI == RZ_G2E */
 
 	/* Update memory mapped and register based frequency */
 	write_cntfrq_el0((u_register_t)reg_cntfid);
diff --git a/plat/renesas/rzg/platform.mk b/plat/renesas/rzg/platform.mk
index 421cbbe..f37d7d0 100644
--- a/plat/renesas/rzg/platform.mk
+++ b/plat/renesas/rzg/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -32,6 +32,55 @@
       endif
       $(eval $(call add_define,RCAR_LSI_CUT))
     endif
+  else ifeq (${LSI},G2H)
+    RCAR_LSI:=${RZ_G2H}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},30)
+        RCAR_LSI_CUT:=20
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},G2N)
+    RCAR_LSI:=${RZ_G2N}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},G2E)
+    RCAR_LSI:=${RZ_G2E}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
   else
     $(error "Error: ${LSI} is not supported.")
   endif
@@ -168,12 +217,15 @@
 endif
 $(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
 
-include drivers/renesas/rzg/ddr/ddr.mk
+RZG_SOC :=1
+$(eval $(call add_define,RZG_SOC))
+
+include drivers/renesas/common/ddr/ddr.mk
 include drivers/renesas/rzg/qos/qos.mk
 include drivers/renesas/rzg/pfc/pfc.mk
 include lib/libfdt/libfdt.mk
 
-PLAT_INCLUDES	+=	-Idrivers/renesas/rzg/ddr		\
+PLAT_INCLUDES	+=	-Idrivers/renesas/common/ddr		\
 			-Idrivers/renesas/rzg/qos		\
 			-Idrivers/renesas/rzg/board		\
 			-Idrivers/renesas/common		\
diff --git a/plat/rockchip/rk3399/drivers/dram/dram.h b/plat/rockchip/rk3399/drivers/dram/dram.h
index 0eb12cf..5572b16 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram.h
+++ b/plat/rockchip/rk3399/drivers/dram/dram.h
@@ -149,7 +149,7 @@
 	uint32_t rx_cal_dqs[2][4];
 };
 
-extern __sramdata struct rk3399_sdram_params sdram_config;
+extern struct rk3399_sdram_params sdram_config;
 
 void dram_init(void);
 
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
index 7f9fad1..a8b1c32 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -49,6 +49,7 @@
 
 __pmusramdata uint32_t dpll_data[PLL_CON_COUNT];
 __pmusramdata uint32_t cru_clksel_con6;
+__pmusramdata uint8_t pmu_enable_watchdog0;
 
 /*
  * Copy @num registers from @src to @dst
@@ -562,8 +563,14 @@
 
 	/* LPDDR4 f2 cann't do training, all training will fail */
 	for (ch = 0; ch < ch_count; ch++) {
-		mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
-				   fn << 8);
+		/*
+		 * Without this disabled for LPDDR4 we end up writing 0's
+		 * in place of real data in an interesting pattern.
+		 */
+		if (sdram_params->dramtype != LPDDR4) {
+			mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
+					fn << 8);
+		}
 
 		/* data_training failed */
 		if (data_training(ch, sdram_params, PI_FULL_TRAINING))
@@ -748,13 +755,44 @@
 	phy_regs->phy896[0] &= ~(0x3 << 8);
 }
 
+__pmusramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t freq)
+{
+	if (freq <= (125 * 1000 * 1000)) {
+		/* Set master mode to SW for slices*/
+		mmio_setbits_32(PHY_REG(ch, 86), 3 << 10);
+		mmio_setbits_32(PHY_REG(ch, 214), 3 << 10);
+		mmio_setbits_32(PHY_REG(ch, 342), 3 << 10);
+		mmio_setbits_32(PHY_REG(ch, 470), 3 << 10);
+		/* Set master mode to SW for address slices*/
+		mmio_setbits_32(PHY_REG(ch, 547), 3 << 18);
+		mmio_setbits_32(PHY_REG(ch, 675), 3 << 18);
+		mmio_setbits_32(PHY_REG(ch, 803), 3 << 18);
+	} else {
+		/* Clear SW master mode for slices*/
+		mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10);
+		mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10);
+		mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10);
+		mmio_clrbits_32(PHY_REG(ch, 470), 3 << 10);
+		/* Clear SW master mode for address slices*/
+		mmio_clrbits_32(PHY_REG(ch, 547), 3 << 18);
+		mmio_clrbits_32(PHY_REG(ch, 675), 3 << 18);
+		mmio_clrbits_32(PHY_REG(ch, 803), 3 << 18);
+	}
+}
+
 __pmusramfunc void dmc_resume(void)
 {
 	struct rk3399_sdram_params *sdram_params = &sdram_config;
 	uint32_t channel_mask = 0;
 	uint32_t channel;
 
-	pmusram_enable_watchdog();
+	/*
+	 * We can't turn off the watchdog, so if we have not turned it on before
+	 * we should not turn it on here.
+	 */
+	if ((pmu_enable_watchdog0 & 0x1) == 0x1) {
+		pmusram_enable_watchdog();
+	}
 	pmu_sgrf_rst_hld_release();
 	restore_pmu_rsthold();
 	sram_secure_timer_init();
@@ -772,6 +810,13 @@
 retry:
 	for (channel = 0; channel < sdram_params->num_channels; channel++) {
 		phy_pctrl_reset(channel);
+		/*
+		 * Without this, LPDDR4 will write 0's in place of real data
+		 * in a strange pattern.
+		 */
+		if (sdram_params->dramtype == LPDDR4) {
+			phy_dll_bypass_set(channel, sdram_params->ddr_freq);
+		}
 		pctl_cfg(channel, sdram_params);
 	}
 
@@ -788,8 +833,12 @@
 		if (sdram_params->dramtype == LPDDR3)
 			sram_udelay(10);
 
-		/* If traning fail, retry to do it again. */
-		if (data_training(channel, sdram_params, PI_FULL_TRAINING))
+		/*
+		 * Training here will always fail for LPDDR4, so skip it
+		 * If traning fail, retry to do it again.
+		 */
+		if (sdram_params->dramtype != LPDDR4 &&
+		    data_training(channel, sdram_params, PI_FULL_TRAINING))
 			goto retry;
 
 		set_ddrconfig(sdram_params, channel,
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.h b/plat/rockchip/rk3399/drivers/dram/suspend.h
index b99a926..1389944 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.h
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,7 @@
 #ifndef SUSPEND_H
 #define SUSPEND_H
 
+#include <stdint.h>
 #include <dram.h>
 
 #define KHz (1000)
@@ -22,5 +23,6 @@
 
 void dmc_suspend(void);
 __pmusramfunc void dmc_resume(void);
+extern __pmusramdata uint8_t pmu_enable_watchdog0;
 
 #endif /* SUSPEND_H */
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index faee678..3084c4f 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -1324,6 +1324,7 @@
 		store_wdt0[i] = mmio_read_32(WDT0_BASE + i * 4);
 		store_wdt1[i] = mmio_read_32(WDT1_BASE + i * 4);
 	}
+	pmu_enable_watchdog0 = (uint8_t) store_wdt0[0] & 0x1;
 }
 
 void wdt_register_restore(void)
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index 7185106..0430d46 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,14 +13,16 @@
  * Peripherals
  */
 
-#define RPI_IO_BASE			ULL(0xFE000000)
-#define RPI_IO_SIZE			ULL(0x02000000)
+#define RPI_IO_BASE			ULL(0xFC000000)
+#define RPI_IO_SIZE			ULL(0x04000000)
+
+#define RPI_LEGACY_BASE			(ULL(0x02000000) + RPI_IO_BASE)
 
 /*
  * ARM <-> VideoCore mailboxes
  */
 #define RPI3_MBOX_OFFSET		ULL(0x0000B880)
-#define RPI3_MBOX_BASE			(RPI_IO_BASE + RPI3_MBOX_OFFSET)
+#define RPI3_MBOX_BASE			(RPI_LEGACY_BASE + RPI3_MBOX_OFFSET)
 /* VideoCore -> ARM */
 #define RPI3_MBOX0_READ_OFFSET		ULL(0x00000000)
 #define RPI3_MBOX0_PEEK_OFFSET		ULL(0x00000010)
@@ -41,7 +43,7 @@
  * Power management, reset controller, watchdog.
  */
 #define RPI3_IO_PM_OFFSET		ULL(0x00100000)
-#define RPI3_PM_BASE			(RPI_IO_BASE + RPI3_IO_PM_OFFSET)
+#define RPI3_PM_BASE			(RPI_LEGACY_BASE + RPI3_IO_PM_OFFSET)
 /* Registers on top of RPI3_PM_BASE. */
 #define RPI3_PM_RSTC_OFFSET		ULL(0x0000001C)
 #define RPI3_PM_RSTS_OFFSET		ULL(0x00000020)
@@ -62,7 +64,7 @@
  * Hardware random number generator.
  */
 #define RPI3_IO_RNG_OFFSET		ULL(0x00104000)
-#define RPI3_RNG_BASE			(RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
+#define RPI3_RNG_BASE			(RPI_LEGACY_BASE + RPI3_IO_RNG_OFFSET)
 #define RPI3_RNG_CTRL_OFFSET		ULL(0x00000000)
 #define RPI3_RNG_STATUS_OFFSET		ULL(0x00000004)
 #define RPI3_RNG_DATA_OFFSET		ULL(0x00000008)
@@ -82,22 +84,22 @@
  * There is also a PL011 UART, multiplexed to the same pins.
  */
 #define RPI4_IO_MINI_UART_OFFSET	ULL(0x00215040)
-#define RPI4_MINI_UART_BASE		(RPI_IO_BASE + RPI4_IO_MINI_UART_OFFSET)
+#define RPI4_MINI_UART_BASE		(RPI_LEGACY_BASE + RPI4_IO_MINI_UART_OFFSET)
 #define RPI4_IO_PL011_UART_OFFSET	ULL(0x00201000)
-#define RPI4_PL011_UART_BASE		(RPI_IO_BASE + RPI4_IO_PL011_UART_OFFSET)
+#define RPI4_PL011_UART_BASE		(RPI_LEGACY_BASE + RPI4_IO_PL011_UART_OFFSET)
 #define RPI4_PL011_UART_CLOCK		ULL(48000000)
 
 /*
  * GPIO controller
  */
 #define RPI3_IO_GPIO_OFFSET		ULL(0x00200000)
-#define RPI3_GPIO_BASE			(RPI_IO_BASE + RPI3_IO_GPIO_OFFSET)
+#define RPI3_GPIO_BASE			(RPI_LEGACY_BASE + RPI3_IO_GPIO_OFFSET)
 
 /*
  * SDHost controller
  */
 #define RPI3_IO_SDHOST_OFFSET           ULL(0x00202000)
-#define RPI3_SDHOST_BASE                (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET)
+#define RPI3_SDHOST_BASE                (RPI_LEGACY_BASE + RPI3_IO_SDHOST_OFFSET)
 
 /*
  * GIC interrupt controller
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index 3ec7d40..e603267 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -31,14 +31,17 @@
 #include <plat/common/platform.h>
 
 /* IO devices */
+#ifndef AARCH32_SP_OPTEE
 static const io_dev_connector_t *dummy_dev_con;
 static uintptr_t dummy_dev_handle;
 static uintptr_t dummy_dev_spec;
+#endif
 
 static uintptr_t image_dev_handle;
 static uintptr_t storage_dev_handle;
 
 #if STM32MP_SDMMC || STM32MP_EMMC
+static struct mmc_device_info mmc_info;
 static io_block_spec_t gpt_block_spec = {
 	.offset = 0,
 	.length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */
@@ -59,6 +62,30 @@
 	.block_size = MMC_BLOCK_SIZE,
 };
 
+#if STM32MP_EMMC_BOOT
+static io_block_spec_t emmc_boot_ssbl_block_spec = {
+	.offset = PLAT_EMMC_BOOT_SSBL_OFFSET,
+	.length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */
+};
+
+static const io_block_dev_spec_t mmc_block_dev_boot_part_spec = {
+	/* It's used as temp buffer in block driver */
+	.buffer = {
+		.offset = (size_t)&block_buffer,
+		.length = MMC_BLOCK_SIZE,
+	},
+	.ops = {
+		.read = mmc_boot_part_read_blocks,
+		.write = NULL,
+	},
+	.block_size = MMC_BLOCK_SIZE,
+};
+#endif
+
+static struct io_mmc_dev_spec mmc_device_spec = {
+	.use_boot_part = false,
+};
+
 static const io_dev_connector_t *mmc_dev_con;
 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
 
@@ -101,9 +128,9 @@
 	.binary_type = OPTEE_HEADER_BINARY_TYPE,
 };
 
-static const struct stm32image_part_info optee_pager_partition_spec = {
-	.name = OPTEE_PAGER_IMAGE_NAME,
-	.binary_type = OPTEE_PAGER_BINARY_TYPE,
+static const struct stm32image_part_info optee_core_partition_spec = {
+	.name = OPTEE_CORE_IMAGE_NAME,
+	.binary_type = OPTEE_CORE_BINARY_TYPE,
 };
 
 static const struct stm32image_part_info optee_paged_partition_spec = {
@@ -117,11 +144,6 @@
 };
 #endif
 
-static const io_block_spec_t bl2_block_spec = {
-	.offset = BL2_BASE,
-	.length = STM32MP_BL2_SIZE,
-};
-
 static const struct stm32image_part_info bl33_partition_spec = {
 	.name = BL33_IMAGE_NAME,
 	.binary_type = BL33_BINARY_TYPE,
@@ -131,7 +153,7 @@
 	IMG_IDX_BL33,
 #ifdef AARCH32_SP_OPTEE
 	IMG_IDX_OPTEE_HEADER,
-	IMG_IDX_OPTEE_PAGER,
+	IMG_IDX_OPTEE_CORE,
 	IMG_IDX_OPTEE_PAGED,
 #endif
 	IMG_IDX_NUM
@@ -148,9 +170,9 @@
 		.name = OPTEE_HEADER_IMAGE_NAME,
 		.binary_type = OPTEE_HEADER_BINARY_TYPE,
 	},
-	.part_info[IMG_IDX_OPTEE_PAGER] = {
-		.name = OPTEE_PAGER_IMAGE_NAME,
-		.binary_type = OPTEE_PAGER_BINARY_TYPE,
+	.part_info[IMG_IDX_OPTEE_CORE] = {
+		.name = OPTEE_CORE_IMAGE_NAME,
+		.binary_type = OPTEE_CORE_BINARY_TYPE,
 	},
 	.part_info[IMG_IDX_OPTEE_PAGED] = {
 		.name = OPTEE_PAGED_IMAGE_NAME,
@@ -166,7 +188,9 @@
 
 static const io_dev_connector_t *stm32image_dev_con __unused;
 
+#ifndef AARCH32_SP_OPTEE
 static int open_dummy(const uintptr_t spec);
+#endif
 static int open_image(const uintptr_t spec);
 static int open_storage(const uintptr_t spec);
 
@@ -177,11 +201,6 @@
 };
 
 static const struct plat_io_policy policies[] = {
-	[BL2_IMAGE_ID] = {
-		.dev_handle = &dummy_dev_handle,
-		.image_spec = (uintptr_t)&bl2_block_spec,
-		.check = open_dummy
-	},
 #ifdef AARCH32_SP_OPTEE
 	[BL32_IMAGE_ID] = {
 		.dev_handle = &image_dev_handle,
@@ -190,7 +209,7 @@
 	},
 	[BL32_EXTRA1_IMAGE_ID] = {
 		.dev_handle = &image_dev_handle,
-		.image_spec = (uintptr_t)&optee_pager_partition_spec,
+		.image_spec = (uintptr_t)&optee_core_partition_spec,
 		.check = open_image
 	},
 	[BL32_EXTRA2_IMAGE_ID] = {
@@ -224,10 +243,12 @@
 	}
 };
 
+#ifndef AARCH32_SP_OPTEE
 static int open_dummy(const uintptr_t spec)
 {
 	return io_dev_init(dummy_dev_handle, 0);
 }
+#endif
 
 static int open_image(const uintptr_t spec)
 {
@@ -239,6 +260,38 @@
 	return io_dev_init(storage_dev_handle, 0);
 }
 
+#if STM32MP_EMMC_BOOT
+static uint32_t get_boot_part_ssbl_header(void)
+{
+	uint32_t magic = 0;
+	int io_result;
+	size_t bytes_read;
+
+	io_result = register_io_dev_block(&mmc_dev_con);
+	if (io_result != 0) {
+		panic();
+	}
+
+	io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_boot_part_spec,
+				&storage_dev_handle);
+	assert(io_result == 0);
+
+	io_result = io_open(storage_dev_handle, (uintptr_t) &emmc_boot_ssbl_block_spec,
+			    &image_dev_handle);
+	assert(io_result == 0);
+
+	io_result = io_read(image_dev_handle, (uintptr_t) &magic, sizeof(magic),
+			    &bytes_read);
+	assert(io_result == 0);
+	assert(bytes_read == sizeof(magic));
+
+	io_result = io_dev_close(storage_dev_handle);
+	assert(io_result == 0);
+
+	return magic;
+}
+#endif
+
 static void print_boot_device(boot_api_context_t *boot_context)
 {
 	switch (boot_context->boot_interface_selected) {
@@ -268,6 +321,19 @@
 	}
 }
 
+static void stm32image_io_setup(void)
+{
+	int io_result __unused;
+
+	io_result = register_io_dev_stm32image(&stm32image_dev_con);
+	assert(io_result == 0);
+
+	io_result = io_dev_open(stm32image_dev_con,
+				(uintptr_t)&stm32image_dev_info_spec,
+				&image_dev_handle);
+	assert(io_result == 0);
+}
+
 #if STM32MP_SDMMC || STM32MP_EMMC
 static void boot_mmc(enum mmc_device_type mmc_dev_type,
 		     uint16_t boot_interface_instance)
@@ -276,13 +342,12 @@
 	uint8_t idx;
 	struct stm32image_part_info *part;
 	struct stm32_sdmmc2_params params;
-	struct mmc_device_info device_info;
-	const partition_entry_t *entry;
+	const partition_entry_t *entry __unused;
+	uint32_t magic __unused;
 
-	zeromem(&device_info, sizeof(struct mmc_device_info));
 	zeromem(&params, sizeof(struct stm32_sdmmc2_params));
 
-	device_info.mmc_dev_type = mmc_dev_type;
+	mmc_info.mmc_dev_type = mmc_dev_type;
 
 	switch (boot_interface_instance) {
 	case 1:
@@ -304,12 +369,32 @@
 		break;
 	}
 
-	params.device_info = &device_info;
+	params.device_info = &mmc_info;
 	if (stm32_sdmmc2_mmc_init(&params) != 0) {
 		ERROR("SDMMC%u init failed\n", boot_interface_instance);
 		panic();
 	}
 
+	stm32image_dev_info_spec.device_size =
+		stm32_sdmmc2_mmc_get_device_size();
+
+#if STM32MP_EMMC_BOOT
+	magic = get_boot_part_ssbl_header();
+
+	if (magic == BOOT_API_IMAGE_HEADER_MAGIC_NB) {
+		VERBOSE("%s, header found, jump to emmc load\n", __func__);
+		idx = IMG_IDX_BL33;
+		part = &stm32image_dev_info_spec.part_info[idx];
+		part->part_offset = PLAT_EMMC_BOOT_SSBL_OFFSET;
+		part->bkp_offset = 0U;
+		mmc_device_spec.use_boot_part = true;
+
+		goto emmc_boot;
+	} else {
+		WARN("%s: Can't find STM32 header on a boot partition\n", __func__);
+	}
+#endif
+
 	/* Open MMC as a block device to read GPT table */
 	io_result = register_io_dev_block(&mmc_dev_con);
 	if (io_result != 0) {
@@ -325,9 +410,6 @@
 	io_result = io_dev_close(storage_dev_handle);
 	assert(io_result == 0);
 
-	stm32image_dev_info_spec.device_size =
-		stm32_sdmmc2_mmc_get_device_size();
-
 	for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
 		part = &stm32image_dev_info_spec.part_info[idx];
 		entry = get_partition_entry(part->name);
@@ -340,6 +422,9 @@
 		part->bkp_offset = 0U;
 	}
 
+#if STM32MP_EMMC_BOOT
+emmc_boot:
+#endif
 	/*
 	 * Re-open MMC with io_mmc, for better perfs compared to
 	 * io_block.
@@ -347,15 +432,8 @@
 	io_result = register_io_dev_mmc(&mmc_dev_con);
 	assert(io_result == 0);
 
-	io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle);
-	assert(io_result == 0);
-
-	io_result = register_io_dev_stm32image(&stm32image_dev_con);
-	assert(io_result == 0);
-
-	io_result = io_dev_open(stm32image_dev_con,
-				(uintptr_t)&stm32image_dev_info_spec,
-				&image_dev_handle);
+	io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_device_spec,
+				&storage_dev_handle);
 	assert(io_result == 0);
 }
 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
@@ -397,19 +475,11 @@
 	part->part_offset = STM32MP_NOR_TEED_OFFSET;
 	part->bkp_offset = 0U;
 
-	idx = IMG_IDX_OPTEE_PAGER;
+	idx = IMG_IDX_OPTEE_CORE;
 	part = &stm32image_dev_info_spec.part_info[idx];
 	part->part_offset = STM32MP_NOR_TEEX_OFFSET;
 	part->bkp_offset = 0U;
 #endif
-
-	io_result = register_io_dev_stm32image(&stm32image_dev_con);
-	assert(io_result == 0);
-
-	io_result = io_dev_open(stm32image_dev_con,
-				(uintptr_t)&stm32image_dev_info_spec,
-				&image_dev_handle);
-	assert(io_result == 0);
 }
 #endif /* STM32MP_SPI_NOR */
 
@@ -450,19 +520,11 @@
 	part->part_offset = STM32MP_NAND_TEED_OFFSET;
 	part->bkp_offset = nand_dev_spec.erase_size;
 
-	idx = IMG_IDX_OPTEE_PAGER;
+	idx = IMG_IDX_OPTEE_CORE;
 	part = &stm32image_dev_info_spec.part_info[idx];
 	part->part_offset = STM32MP_NAND_TEEX_OFFSET;
 	part->bkp_offset = nand_dev_spec.erase_size;
 #endif
-
-	io_result = register_io_dev_stm32image(&stm32image_dev_con);
-	assert(io_result == 0);
-
-	io_result = io_dev_open(stm32image_dev_con,
-				(uintptr_t)&stm32image_dev_info_spec,
-				&image_dev_handle);
-	assert(io_result == 0);
 }
 #endif /* STM32MP_RAW_NAND */
 
@@ -504,19 +566,11 @@
 	part->part_offset = STM32MP_NAND_TEED_OFFSET;
 	part->bkp_offset = spi_nand_dev_spec.erase_size;
 
-	idx = IMG_IDX_OPTEE_PAGER;
+	idx = IMG_IDX_OPTEE_CORE;
 	part = &stm32image_dev_info_spec.part_info[idx];
 	part->part_offset = STM32MP_NAND_TEEX_OFFSET;
 	part->bkp_offset = spi_nand_dev_spec.erase_size;
 #endif
-
-	io_result = register_io_dev_stm32image(&stm32image_dev_con);
-	assert(io_result == 0);
-
-	io_result = io_dev_open(stm32image_dev_con,
-				(uintptr_t)&stm32image_dev_info_spec,
-				&image_dev_handle);
-	assert(io_result == 0);
 }
 #endif /* STM32MP_SPI_NAND */
 
@@ -534,48 +588,56 @@
 		     boot_context->boot_partition_used_toboot);
 	}
 
+#ifndef AARCH32_SP_OPTEE
 	io_result = register_io_dev_dummy(&dummy_dev_con);
 	assert(io_result == 0);
 
 	io_result = io_dev_open(dummy_dev_con, dummy_dev_spec,
 				&dummy_dev_handle);
 	assert(io_result == 0);
+#endif
 
 	switch (boot_context->boot_interface_selected) {
 #if STM32MP_SDMMC
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
 		dmbsy();
 		boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
+		stm32image_io_setup();
 		break;
 #endif
 #if STM32MP_EMMC
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
 		dmbsy();
 		boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
+		stm32image_io_setup();
 		break;
 #endif
 #if STM32MP_SPI_NOR
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
 		dmbsy();
 		boot_spi_nor(boot_context);
+		stm32image_io_setup();
 		break;
 #endif
 #if STM32MP_RAW_NAND
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
 		dmbsy();
 		boot_fmc2_nand(boot_context);
+		stm32image_io_setup();
 		break;
 #endif
 #if STM32MP_SPI_NAND
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
 		dmbsy();
 		boot_spi_nand(boot_context);
+		stm32image_io_setup();
 		break;
 #endif
 
 	default:
 		ERROR("Boot interface %d not supported\n",
 		      boot_context->boot_interface_selected);
+		panic();
 		break;
 	}
 }
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index feeb4a7..42d3487 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,9 @@
 
 #include <platform_def.h>
 
+#define JEDEC_ST_BKID U(0x0)
+#define JEDEC_ST_MFID U(0x20)
+
 /* Functions to save and get boot context address given by ROM code */
 void stm32mp_save_boot_ctx_address(uintptr_t address);
 uintptr_t stm32mp_get_boot_ctx_address(void);
@@ -64,6 +67,15 @@
 /* Return node offset for target GPIO bank ID @bank or a FDT error code */
 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
 
+/* Get the chip revision */
+uint32_t stm32mp_get_chip_version(void);
+/* Get the chip device ID */
+uint32_t stm32mp_get_chip_dev_id(void);
+
+/* Get SOC name */
+#define STM32_SOC_NAME_SIZE 20
+void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]);
+
 /* Print CPU information */
 void stm32mp_print_cpuinfo(void);
 
diff --git a/plat/st/common/include/stm32mp_dt.h b/plat/st/common/include/stm32mp_dt.h
index e3b4e59..299c0b1 100644
--- a/plat/st/common/include/stm32mp_dt.h
+++ b/plat/st/common/include/stm32mp_dt.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #define STM32MP_DT_H
 
 #include <stdbool.h>
+#include <stdint.h>
 
 #define DT_DISABLED		U(0)
 #define DT_NON_SECURE		U(1)
@@ -25,7 +26,7 @@
 /*******************************************************************************
  * Function and variable prototypes
  ******************************************************************************/
-int dt_open_and_check(void);
+int dt_open_and_check(uintptr_t dt_addr);
 int fdt_get_address(void **fdt_addr);
 bool fdt_check_node(int node);
 uint8_t fdt_get_status(int node);
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 89d8078..d3de1e1 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,8 +12,10 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/st/stm32mp_clkfunc.h>
+#include <lib/smccc.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
+#include <services/arm_arch_svc.h>
 
 uintptr_t plat_get_ns_image_entrypoint(void)
 {
@@ -111,3 +113,36 @@
 	return  mmap_remove_dynamic_region(STM32MP_DDR_BASE,
 					   STM32MP_DDR_MAX_SIZE);
 }
+
+/*****************************************************************************
+ * plat_is_smccc_feature_available() - This function checks whether SMCCC
+ *                                     feature is availabile for platform.
+ * @fid: SMCCC function id
+ *
+ * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
+ * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
+ *****************************************************************************/
+int32_t plat_is_smccc_feature_available(u_register_t fid)
+{
+	switch (fid) {
+	case SMCCC_ARCH_SOC_ID:
+		return SMC_ARCH_CALL_SUCCESS;
+	default:
+		return SMC_ARCH_CALL_NOT_SUPPORTED;
+	}
+}
+
+/* Get SOC version */
+int32_t plat_get_soc_version(void)
+{
+	uint32_t chip_id = stm32mp_get_chip_dev_id();
+	uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID);
+
+	return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
+}
+
+/* Get SOC revision */
+int32_t plat_get_soc_revision(void)
+{
+	return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
+}
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 391e5f0..6465c10 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,20 +19,19 @@
 
 #include <stm32mp_dt.h>
 
-static int fdt_checked;
-
-static void *fdt = (void *)(uintptr_t)STM32MP_DTB_BASE;
+static void *fdt;
 
 /*******************************************************************************
  * This function checks device tree file with its header.
  * Returns 0 on success and a negative FDT error code on failure.
  ******************************************************************************/
-int dt_open_and_check(void)
+int dt_open_and_check(uintptr_t dt_addr)
 {
-	int ret = fdt_check_header(fdt);
+	int ret;
 
+	ret = fdt_check_header((void *)dt_addr);
 	if (ret == 0) {
-		fdt_checked = 1;
+		fdt = (void *)dt_addr;
 	}
 
 	return ret;
@@ -45,11 +44,13 @@
  ******************************************************************************/
 int fdt_get_address(void **fdt_addr)
 {
-	if (fdt_checked == 1) {
-		*fdt_addr = fdt;
+	if (fdt == NULL) {
+		return 0;
 	}
 
-	return fdt_checked;
+	*fdt_addr = fdt;
+
+	return 1;
 }
 
 /*******************************************************************************
@@ -72,21 +73,20 @@
 uint8_t fdt_get_status(int node)
 {
 	uint8_t status = DT_DISABLED;
-	int len;
 	const char *cchar;
 
-	cchar = fdt_getprop(fdt, node, "status", &len);
+	cchar = fdt_getprop(fdt, node, "status", NULL);
 	if ((cchar == NULL) ||
-	    (strncmp(cchar, "okay", (size_t)len) == 0)) {
+	    (strncmp(cchar, "okay", strlen("okay")) == 0)) {
 		status |= DT_NON_SECURE;
 	}
 
-	cchar = fdt_getprop(fdt, node, "secure-status", &len);
+	cchar = fdt_getprop(fdt, node, "secure-status", NULL);
 	if (cchar == NULL) {
 		if (status == DT_NON_SECURE) {
 			status |= DT_SECURE;
 		}
-	} else if (strncmp(cchar, "okay", (size_t)len) == 0) {
+	} else if (strncmp(cchar, "okay", strlen("okay")) == 0) {
 		status |= DT_SECURE;
 	}
 
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index e09ce63..91073b8 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -188,11 +188,6 @@
 	mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
 			STM32MP_OPTEE_SIZE,
 			MT_MEMORY | MT_RW | MT_SECURE);
-#else
-	/* Prevent corruption of preloaded BL32 */
-	mmap_add_region(BL32_BASE, BL32_BASE,
-			BL32_LIMIT - BL32_BASE,
-			MT_RO_DATA | MT_SECURE);
 #endif
 	/* Prevent corruption of preloaded Device Tree */
 	mmap_add_region(DTB_BASE, DTB_BASE,
@@ -201,7 +196,7 @@
 
 	configure_mmu();
 
-	if (dt_open_and_check() < 0) {
+	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
 		panic();
 	}
 
diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h
index 7076a71..2d7d369 100644
--- a/plat/st/stm32mp1/include/platform_def.h
+++ b/plat/st/stm32mp1/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,10 +27,10 @@
 
 #ifdef AARCH32_SP_OPTEE
 #define OPTEE_HEADER_IMAGE_NAME		"teeh"
+#define OPTEE_CORE_IMAGE_NAME		"teex"
 #define OPTEE_PAGED_IMAGE_NAME		"teed"
-#define OPTEE_PAGER_IMAGE_NAME		"teex"
 #define OPTEE_HEADER_BINARY_TYPE	U(0x20)
-#define OPTEE_PAGER_BINARY_TYPE		U(0x21)
+#define OPTEE_CORE_BINARY_TYPE		U(0x21)
 #define OPTEE_PAGED_BINARY_TYPE		U(0x22)
 #endif
 
@@ -68,10 +68,15 @@
  * BL32 specific defines.
  ******************************************************************************/
 #ifndef AARCH32_SP_OPTEE
+#if ENABLE_PIE
+#define BL32_BASE			0
+#define BL32_LIMIT			STM32MP_BL32_SIZE
+#else
 #define BL32_BASE			STM32MP_BL32_BASE
 #define BL32_LIMIT			(STM32MP_BL32_BASE + \
 					 STM32MP_BL32_SIZE)
 #endif
+#endif
 
 /*******************************************************************************
  * BL33 specific defines.
@@ -83,6 +88,12 @@
  */
 #define PLAT_STM32MP_NS_IMAGE_OFFSET	BL33_BASE
 
+/*
+ * SSBL offset in case it's stored in eMMC boot partition.
+ * We can fix it to 256K because TF-A size can't be bigger than SRAM
+ */
+#define PLAT_EMMC_BOOT_SSBL_OFFSET		U(0x40000)
+
 /*******************************************************************************
  * DTB specific defines.
  ******************************************************************************/
diff --git a/plat/st/stm32mp1/include/stm32mp1_smc.h b/plat/st/stm32mp1/include/stm32mp1_smc.h
index 57240bc..52088de 100644
--- a/plat/st/stm32mp1/include/stm32mp1_smc.h
+++ b/plat/st/stm32mp1/include/stm32mp1_smc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -58,4 +58,10 @@
 #define STM32_SMC_WRITE_SHADOW		0x03
 #define STM32_SMC_READ_OTP		0x04
 
+/* SMC error codes */
+#define STM32_SMC_OK			0x00000000U
+#define STM32_SMC_NOT_SUPPORTED		0xFFFFFFFFU
+#define STM32_SMC_FAILED		0xFFFFFFFEU
+#define STM32_SMC_INVALID_PARAMS	0xFFFFFFFDU
+
 #endif /* STM32MP1_SMC_H */
diff --git a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
index 1d407bb..984c6ba 100644
--- a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
+++ b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,7 +28,7 @@
 				      SECURE | EXECUTABLE | EP_FIRST_EXE),
 
 #if !defined(AARCH32_SP_OPTEE)
-		.ep_info.pc = BL32_BASE,
+		.ep_info.pc = STM32MP_BL32_BASE,
 #endif
 		.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
 					    SPSR_E_LITTLE,
@@ -42,8 +42,8 @@
 		.image_info.image_base = STM32MP_OPTEE_BASE,
 		.image_info.image_max_size = STM32MP_OPTEE_SIZE,
 #else
-		.image_info.image_base = BL32_BASE,
-		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		.image_info.image_base = STM32MP_BL32_BASE,
+		.image_info.image_max_size = STM32MP_BL32_SIZE,
 #endif
 		.next_handoff_image_id = BL33_IMAGE_ID,
 	},
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 3595819..1693135 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -9,6 +9,8 @@
 BL2_AT_EL3		:=	1
 USE_COHERENT_MEM	:=	0
 
+ENABLE_PIE		:=	1
+
 STM32_TF_VERSION	?=	0
 
 # Enable dynamic memory mapping
@@ -40,11 +42,7 @@
 STM32MP_RAW_NAND	?=	0
 STM32MP_SPI_NAND	?=	0
 STM32MP_SPI_NOR		?=	0
-
-ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND} \
-	${STM32MP_SPI_NAND} ${STM32MP_SPI_NOR}),)
-$(error "No boot device driver is enabled")
-endif
+STM32MP_EMMC_BOOT	?=	0
 
 # Device tree
 DTB_FILE_NAME		?=	stm32mp157c-ev1.dtb
@@ -66,6 +64,7 @@
 # Variables for use with stm32image
 STM32IMAGEPATH		?= tools/stm32image
 STM32IMAGE		?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}
+STM32IMAGE_SRC		:= ${STM32IMAGEPATH}/stm32image.c
 
 # Enable flags for C files
 $(eval $(call assert_booleans,\
@@ -75,6 +74,7 @@
 		STM32MP_RAW_NAND \
 		STM32MP_SPI_NAND \
 		STM32MP_SPI_NOR \
+		STM32MP_EMMC_BOOT \
 		PLAT_XLAT_TABLES_DYNAMIC \
 )))
 
@@ -91,6 +91,7 @@
 		STM32MP_RAW_NAND \
 		STM32MP_SPI_NAND \
 		STM32MP_SPI_NOR \
+		STM32MP_EMMC_BOOT \
 		PLAT_XLAT_TABLES_DYNAMIC \
 		STM32_TF_A_COPIES \
 		PLAT_PARTITION_MAX_ENTRIES \
@@ -194,13 +195,25 @@
 endif
 
 # Compilation rules
-.PHONY: check_dtc_version stm32image clean_stm32image
+.PHONY: check_dtc_version stm32image clean_stm32image check_boot_device
 .SUFFIXES:
 
 all: check_dtc_version stm32image ${STM32_TF_STM32}
 
 distclean realclean clean: clean_stm32image
 
+bl2: check_boot_device
+
+check_boot_device:
+	@if [ ${STM32MP_EMMC} != 1 ] && \
+	    [ ${STM32MP_SDMMC} != 1 ] && \
+	    [ ${STM32MP_RAW_NAND} != 1 ] && \
+	    [ ${STM32MP_SPI_NAND} != 1 ] && \
+	    [ ${STM32MP_SPI_NOR} != 1 ]; then \
+		echo "No boot device driver is enabled"; \
+		false; \
+	fi
+
 stm32image: ${STM32IMAGE}
 
 ${STM32IMAGE}: ${STM32IMAGE_SRC}
diff --git a/plat/st/stm32mp1/services/bsec_svc.c b/plat/st/stm32mp1/services/bsec_svc.c
index 2a60e43..a1d7fc6 100644
--- a/plat/st/stm32mp1/services/bsec_svc.c
+++ b/plat/st/stm32mp1/services/bsec_svc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,11 +28,11 @@
 		result = bsec_program_otp(x3, x2);
 		break;
 	case STM32_SMC_WRITE_SHADOW:
-		*ret_otp_value = 0;
+		*ret_otp_value = 0U;
 		result = bsec_write_otp(x3, x2);
 		break;
 	case STM32_SMC_READ_OTP:
-		*ret_otp_value = 0;
+		*ret_otp_value = 0U;
 		result = bsec_read_otp(&tmp_data, x2);
 		if (result != BSEC_OK) {
 			break;
@@ -52,9 +52,8 @@
 		break;
 
 	default:
-		result = BSEC_ERROR;
-		break;
+		return STM32_SMC_INVALID_PARAMS;
 	}
 
-	return result;
+	return (result == BSEC_OK) ? STM32_SMC_OK : STM32_SMC_FAILED;
 }
diff --git a/plat/st/stm32mp1/services/stm32mp1_svc_setup.c b/plat/st/stm32mp1/services/stm32mp1_svc_setup.c
index d4ed445..ed8a448 100644
--- a/plat/st/stm32mp1/services/stm32mp1_svc_setup.c
+++ b/plat/st/stm32mp1/services/stm32mp1_svc_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2014-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -75,7 +75,7 @@
 
 	default:
 		WARN("Unimplemented STM32MP1 Service Call: 0x%x\n", smc_fid);
-		ret1 = SMC_UNK;
+		ret1 = STM32_SMC_NOT_SUPPORTED;
 		break;
 	}
 
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index b639fcb..334f914 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,7 +45,7 @@
 {
 	switch (id & INT_ID_MASK) {
 	case STM32MP1_IRQ_TZC400:
-		ERROR("STM32MP1_IRQ_TZC400 generated\n");
+		(void)tzc400_it_handler();
 		panic();
 		break;
 	case STM32MP1_IRQ_AXIERRIRQ:
@@ -146,7 +146,7 @@
 		bl_params = bl_params->next_params_info;
 	}
 
-	if (dt_open_and_check() < 0) {
+	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
 		panic();
 	}
 
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index ee04a23..155d63d 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -31,6 +31,8 @@
 /*******************************************************************************
  * CHIP ID
  ******************************************************************************/
+#define STM32MP1_CHIP_ID	U(0x500)
+
 #define STM32MP157C_PART_NB	U(0x05000000)
 #define STM32MP157A_PART_NB	U(0x05000001)
 #define STM32MP153C_PART_NB	U(0x05000024)
@@ -117,30 +119,14 @@
 #define STM32MP_OPTEE_SIZE		(STM32MP_DTB_BASE -  \
 					 STM32MP_OPTEE_BASE)
 #else
-#if STACK_PROTECTOR_ENABLED
 #define STM32MP_BL32_SIZE		U(0x00012000)	/* 72 KB for BL32 */
-#else
-#define STM32MP_BL32_SIZE		U(0x00011000)	/* 68 KB for BL32 */
-#endif
 #endif
 
 #define STM32MP_BL32_BASE		(STM32MP_SEC_SYSRAM_BASE + \
 					 STM32MP_SEC_SYSRAM_SIZE - \
 					 STM32MP_BL32_SIZE)
 
-#ifdef AARCH32_SP_OPTEE
-#if STACK_PROTECTOR_ENABLED
 #define STM32MP_BL2_SIZE		U(0x0001A000)	/* 100 KB for BL2 */
-#else
-#define STM32MP_BL2_SIZE		U(0x00018000)	/* 92 KB for BL2 */
-#endif
-#else
-#if STACK_PROTECTOR_ENABLED
-#define STM32MP_BL2_SIZE		U(0x00019000)	/* 96 KB for BL2 */
-#else
-#define STM32MP_BL2_SIZE		U(0x00017000)	/* 88 KB for BL2 */
-#endif
-#endif
 
 #define STM32MP_BL2_BASE		(STM32MP_BL32_BASE - \
 					 STM32MP_BL2_SIZE)
@@ -381,7 +367,8 @@
 #define STM32MP1_TZC_ETH_ID		U(10)
 #define STM32MP1_TZC_DAP_ID		U(15)
 
-#define STM32MP1_FILTER_BIT_ALL		U(3)
+#define STM32MP1_FILTER_BIT_ALL		(TZC_400_REGION_ATTR_FILTER_BIT(0) | \
+					 TZC_400_REGION_ATTR_FILTER_BIT(1))
 
 /*******************************************************************************
  * STM32MP1 SDMMC
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index bc77ee3..1af0075 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -153,63 +153,70 @@
 	}
 }
 
-static int get_part_number(uint32_t *part_nb)
+uint32_t stm32mp_get_chip_version(void)
 {
-	uint32_t part_number;
-	uint32_t dev_id;
+	uint32_t version = 0U;
+
+	if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) {
+		INFO("Cannot get CPU version, debug disabled\n");
+		return 0U;
+	}
+
+	return version;
+}
 
-	assert(part_nb != NULL);
+uint32_t stm32mp_get_chip_dev_id(void)
+{
+	uint32_t dev_id;
 
 	if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
-		return -1;
+		INFO("Use default chip ID, debug disabled\n");
+		dev_id = STM32MP1_CHIP_ID;
 	}
 
+	return dev_id;
+}
+
+static uint32_t get_part_number(void)
+{
+	static uint32_t part_number;
+
+	if (part_number != 0U) {
+		return part_number;
+	}
+
 	if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) {
-		ERROR("BSEC: PART_NUMBER_OTP Error\n");
-		return -1;
+		panic();
 	}
 
 	part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
 		PART_NUMBER_OTP_PART_SHIFT;
 
-	*part_nb = part_number | (dev_id << 16);
+	part_number |= stm32mp_get_chip_dev_id() << 16;
 
-	return 0;
+	return part_number;
 }
 
-static int get_cpu_package(uint32_t *cpu_package)
+static uint32_t get_cpu_package(void)
 {
 	uint32_t package;
 
-	assert(cpu_package != NULL);
-
 	if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
-		ERROR("BSEC: PACKAGE_OTP Error\n");
-		return -1;
+		panic();
 	}
 
-	*cpu_package = (package & PACKAGE_OTP_PKG_MASK) >>
+	package = (package & PACKAGE_OTP_PKG_MASK) >>
 		PACKAGE_OTP_PKG_SHIFT;
 
-	return 0;
+	return package;
 }
 
-void stm32mp_print_cpuinfo(void)
+void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
 {
-	const char *cpu_s, *cpu_r, *pkg;
-	uint32_t part_number;
-	uint32_t cpu_package;
-	uint32_t chip_dev_id;
-	int ret;
+	char *cpu_s, *cpu_r, *pkg;
 
 	/* MPUs Part Numbers */
-	ret = get_part_number(&part_number);
-	if (ret < 0) {
-		WARN("Cannot get part number\n");
-		return;
-	}
-
-	switch (part_number) {
+	switch (get_part_number()) {
 	case STM32MP157C_PART_NB:
 		cpu_s = "157C";
 		break;
@@ -252,13 +259,7 @@
 	}
 
 	/* Package */
-	ret = get_cpu_package(&cpu_package);
-	if (ret < 0) {
-		WARN("Cannot get CPU package\n");
-		return;
-	}
-
-	switch (cpu_package) {
+	switch (get_cpu_package()) {
 	case PKG_AA_LFBGA448:
 		pkg = "AA";
 		break;
@@ -277,13 +278,7 @@
 	}
 
 	/* REVISION */
-	ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id);
-	if (ret < 0) {
-		WARN("Cannot get CPU version\n");
-		return;
-	}
-
-	switch (chip_dev_id) {
+	switch (stm32mp_get_chip_version()) {
 	case STM32MP1_REV_B:
 		cpu_r = "B";
 		break;
@@ -295,7 +290,16 @@
 		break;
 	}
 
+	snprintf(name, STM32_SOC_NAME_SIZE,
+		 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
+}
+
-	NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
+void stm32mp_print_cpuinfo(void)
+{
+	char name[STM32_SOC_NAME_SIZE];
+
+	stm32mp_get_soc_name(name);
+	NOTICE("CPU: %s\n", name);
 }
 
 void stm32mp_print_boardinfo(void)
@@ -349,20 +353,12 @@
 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
 bool stm32mp_is_single_core(void)
 {
-	uint32_t part_number;
-
-	if (get_part_number(&part_number) < 0) {
-		ERROR("Invalid part number, assume single core chip");
-		return true;
-	}
-
-	switch (part_number) {
+	switch (get_part_number()) {
 	case STM32MP151A_PART_NB:
 	case STM32MP151C_PART_NB:
 	case STM32MP151D_PART_NB:
 	case STM32MP151F_PART_NB:
 		return true;
-
 	default:
 		return false;
 	}
diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c
index 3a29ba9..195b3a5 100644
--- a/plat/st/stm32mp1/stm32mp1_security.c
+++ b/plat/st/stm32mp1/stm32mp1_security.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -75,8 +75,7 @@
 				TZC_REGION_NSEC_ALL_ACCESS_RDWR);
 #endif
 
-	/* Raise an exception if a NS device tries to access secure memory */
-	tzc400_set_action(TZC_ACTION_ERR);
+	tzc400_set_action(TZC_ACTION_INT);
 
 	tzc400_enable_filters();
 }
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 109725c..793ad71 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,6 +22,7 @@
 #define SYSCFG_ICNR				0x1CU
 #define SYSCFG_CMPCR				0x20U
 #define SYSCFG_CMPENSETR			0x24U
+#define SYSCFG_CMPENCLRR			0x28U
 
 /*
  * SYSCFG_BOOTR Register
@@ -167,8 +168,7 @@
 
 	mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
 
-	mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
-			SYSCFG_CMPENSETR_MPU_EN);
+	mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENCLRR, SYSCFG_CMPENSETR_MPU_EN);
 
 	stm32mp1_clk_disable_non_secure(SYSCFG);
 }
diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h
index 0d45116..4ff687c 100644
--- a/plat/ti/k3/board/generic/include/board_def.h
+++ b/plat/ti/k3/board/generic/include/board_def.h
@@ -18,15 +18,26 @@
 /*
  * This RAM will be used for the bootloader including code, bss, and stacks.
  * It may need to be increased if BL31 grows in size.
+ *
+ * The link addresses are determined by SEC_SRAM_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * SEC_SRAM_BASE is really arbitrary.
+ *
+ * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * SEC_SRAM_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
  */
-#define SEC_SRAM_BASE			0x70000000 /* Base of MSMC SRAM */
-#define SEC_SRAM_SIZE			0x00020000 /* 128k */
+#define SEC_SRAM_BASE			UL(0x00000000) /* PIE remapped on fly */
+#define SEC_SRAM_SIZE			UL(0x00020000) /* 128k */
 
 #define PLAT_MAX_OFF_STATE		U(2)
 #define PLAT_MAX_RET_STATE		U(1)
 
-#define PLAT_PROC_START_ID		32
-#define PLAT_PROC_DEVICE_START_ID	202
-#define PLAT_CLUSTER_DEVICE_START_ID	198
+#define PLAT_PROC_START_ID		U(32)
+#define PLAT_PROC_DEVICE_START_ID	U(202)
+#define PLAT_CLUSTER_DEVICE_START_ID	U(198)
 
 #endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/board/lite/include/board_def.h b/plat/ti/k3/board/lite/include/board_def.h
index 7c7ea62..18b7f42 100644
--- a/plat/ti/k3/board/lite/include/board_def.h
+++ b/plat/ti/k3/board/lite/include/board_def.h
@@ -20,15 +20,26 @@
  * It may need to be increased if BL31 grows in size.
  * Current computation assumes data structures necessary for GIC and ARM for
  * a single cluster of 4 processor.
+ *
+ * The link addresses are determined by SEC_SRAM_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * SEC_SRAM_BASE is really arbitrary.
+ *
+ * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * SEC_SRAM_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
  */
-#define SEC_SRAM_BASE			0x70000000 /* Base of SRAM */
-#define SEC_SRAM_SIZE			0x0001a000 /* 104k */
+#define SEC_SRAM_BASE			UL(0x00000000) /* PIE remapped on fly */
+#define SEC_SRAM_SIZE			UL(0x0001c000) /* 112k */
 
 #define PLAT_MAX_OFF_STATE		U(2)
 #define PLAT_MAX_RET_STATE		U(1)
 
-#define PLAT_PROC_START_ID		32
-#define PLAT_PROC_DEVICE_START_ID	135
-#define PLAT_CLUSTER_DEVICE_START_ID	134
+#define PLAT_PROC_START_ID		U(32)
+#define PLAT_PROC_DEVICE_START_ID	U(135)
+#define PLAT_CLUSTER_DEVICE_START_ID	U(134)
 
 #endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index ac4e60e..457c95d 100644
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c
@@ -101,7 +101,7 @@
 void bl31_plat_arch_setup(void)
 {
 	const mmap_region_t bl_regions[] = {
-		MAP_REGION_FLAT(BL31_START,           BL31_END            - BL31_START,           MT_MEMORY  | MT_RW | MT_SECURE),
+		MAP_REGION_FLAT(BL31_START,           BL31_SIZE,			          MT_MEMORY  | MT_RW | MT_SECURE),
 		MAP_REGION_FLAT(BL_CODE_BASE,         BL_CODE_END         - BL_CODE_BASE,         MT_CODE    | MT_RO | MT_SECURE),
 		MAP_REGION_FLAT(BL_RO_DATA_BASE,      BL_RO_DATA_END      - BL_RO_DATA_BASE,      MT_RO_DATA | MT_RO | MT_SECURE),
 #if USE_COHERENT_MEM
diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index f12fb0b..81a383a 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -60,7 +60,11 @@
  * used, choose the smallest value needed to map the required virtual addresses
  * for each BL stage.
  */
-#define MAX_XLAT_TABLES		8
+#if USE_COHERENT_MEM
+#define MAX_XLAT_TABLES		10
+#else
+#define MAX_XLAT_TABLES		9
+#endif
 
 /*
  * Defines the maximum number of regions that are allocated by the translation
diff --git a/plat/xilinx/common/include/pm_common.h b/plat/xilinx/common/include/pm_common.h
index c0a51f0..0c24a36 100644
--- a/plat/xilinx/common/include/pm_common.h
+++ b/plat/xilinx/common/include/pm_common.h
@@ -15,6 +15,18 @@
 #include <stdint.h>
 #include <plat_pm_common.h>
 
+#if IPI_CRC_CHECK
+#define PAYLOAD_ARG_CNT         8U
+#define IPI_W0_TO_W6_SIZE       28U
+#define PAYLOAD_CRC_POS         7U
+#define CRC_INIT_VALUE          0x4F4EU
+#define CRC_ORDER               16U
+#define CRC_POLYNOM             0x8005U
+#else
+#define PAYLOAD_ARG_CNT         6U
+#endif
+#define PAYLOAD_ARG_SIZE	4U	/* size in bytes */
+
 /**
  * pm_ipi - struct for capturing IPI-channel specific info
  * @local_ipi_id	Local IPI agent ID
diff --git a/plat/xilinx/common/include/pm_ipi.h b/plat/xilinx/common/include/pm_ipi.h
index 7bcf596..8c7738d 100644
--- a/plat/xilinx/common/include/pm_ipi.h
+++ b/plat/xilinx/common/include/pm_ipi.h
@@ -26,7 +26,7 @@
 void pm_ipi_irq_enable(const struct pm_proc *proc);
 void pm_ipi_irq_clear(const struct pm_proc *proc);
 uint32_t pm_ipi_irq_status(const struct pm_proc *proc);
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
 uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize);
 #endif
 
diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index ab8088d..7b5bd02 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -60,7 +60,7 @@
 	uintptr_t buffer_base = proc->ipi->buffer_base +
 					IPI_BUFFER_TARGET_REMOTE_OFFSET +
 					IPI_BUFFER_REQ_OFFSET;
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
 	payload[PAYLOAD_CRC_POS] = calculate_crc(payload, IPI_W0_TO_W6_SIZE);
 #endif
 
@@ -141,7 +141,7 @@
 					   unsigned int *value, size_t count)
 {
 	size_t i;
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
 	size_t j;
 	unsigned int response_payload[PAYLOAD_ARG_CNT];
 #endif
@@ -160,7 +160,7 @@
 		*value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
 		value++;
 	}
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
 	for (j = 0; j < PAYLOAD_ARG_CNT; j++)
 		response_payload[j] = mmio_read_32(buffer_base +
 						(j * PAYLOAD_ARG_SIZE));
@@ -185,7 +185,7 @@
 void pm_ipi_buff_read_callb(unsigned int *value, size_t count)
 {
 	size_t i;
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
 	size_t j;
 	unsigned int response_payload[PAYLOAD_ARG_CNT];
 #endif
@@ -200,7 +200,7 @@
 		*value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
 		value++;
 	}
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
 	for (j = 0; j < PAYLOAD_ARG_CNT; j++)
 		response_payload[j] = mmio_read_32(buffer_base +
 						(j * PAYLOAD_ARG_SIZE));
@@ -266,7 +266,7 @@
 		return 0;
 }
 
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
 uint32_t calculate_crc(uint32_t *payload, uint32_t bufsize)
 {
 	uint32_t crcinit = CRC_INIT_VALUE;
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 5e870ff..8b8714c 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #include <bl31/bl31.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <drivers/arm/dcc.h>
 #include <drivers/arm/pl011.h>
 #include <drivers/console.h>
 #include <lib/mmio.h>
@@ -22,7 +23,6 @@
 
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
-static console_t versal_runtime_console;
 
 /*
  * Return a pointer to the 'entry_point_info' structure of the next image for
@@ -64,18 +64,26 @@
 {
 	uint64_t atf_handoff_addr;
 
-	/* Initialize the console to provide early debug support */
-	int rc = console_pl011_register(VERSAL_UART_BASE,
-					VERSAL_UART_CLOCK,
-					VERSAL_UART_BAUDRATE,
-					&versal_runtime_console);
-	if (rc == 0) {
-		panic();
-	}
-
-	console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
-			  CONSOLE_FLAG_RUNTIME);
+	if (VERSAL_CONSOLE_IS(pl011)) {
+		static console_t versal_runtime_console;
+		/* Initialize the console to provide early debug support */
+		int rc = console_pl011_register(VERSAL_UART_BASE,
+						VERSAL_UART_CLOCK,
+						VERSAL_UART_BAUDRATE,
+						&versal_runtime_console);
+		if (rc == 0) {
+			panic();
+		}
 
+		console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
+				  CONSOLE_FLAG_RUNTIME);
+	} else if (VERSAL_CONSOLE_IS(dcc)) {
+		/* Initialize the dcc console for debug */
+		int rc = console_dcc_register();
+		if (rc == 0) {
+			panic();
+		}
+	}
 	/* Initialize the platform config for future decision making */
 	versal_config_setup();
 	/* There are no parameters from BL2 if BL31 is a reset vector */
@@ -109,6 +117,40 @@
 	NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
 }
 
+static interrupt_type_handler_t type_el3_interrupt_handler;
+
+int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
+{
+	/* Validate 'handler'*/
+	if (!handler) {
+		return -EINVAL;
+	}
+
+	type_el3_interrupt_handler = handler;
+
+	return 0;
+}
+
+static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
+					  void *handle, void *cookie)
+{
+	uint32_t intr_id;
+	interrupt_type_handler_t handler;
+
+	intr_id = plat_ic_get_pending_interrupt_id();
+	/* Currently we support one interrupt */
+	if (intr_id != PLAT_VERSAL_IPI_IRQ) {
+		WARN("Unexpected interrupt call: 0x%x\n", intr_id);
+		return 0;
+	}
+
+	handler = type_el3_interrupt_handler;
+	if (handler) {
+		return handler(intr_id, flags, handle, cookie);
+	}
+
+	return 0;
+}
 void bl31_platform_setup(void)
 {
 	/* Initialize the gic cpu and distributor interfaces */
@@ -118,6 +160,15 @@
 
 void bl31_plat_runtime_setup(void)
 {
+	uint64_t flags = 0;
+	uint64_t rc;
+
+	set_interrupt_rm_flag(flags, NON_SECURE);
+	rc = register_interrupt_type_handler(INTR_TYPE_EL3,
+					     rdo_el3_interrupt_handler, flags);
+	if (rc) {
+		panic();
+	}
 }
 
 /*
diff --git a/plat/xilinx/versal/include/plat_ipi.h b/plat/xilinx/versal/include/plat_ipi.h
index 6b08f32..36a4380 100644
--- a/plat/xilinx/versal/include/plat_ipi.h
+++ b/plat/xilinx/versal/include/plat_ipi.h
@@ -31,7 +31,7 @@
 #define IPI_BUFFER_APU_BASE	(IPI_BUFFER_BASEADDR + 0x400U)
 #define IPI_BUFFER_PMC_BASE	(IPI_BUFFER_BASEADDR + 0x200U)
 
-#define IPI_BUFFER_TARGET_APU_OFFSET	0x0U
+#define IPI_BUFFER_TARGET_APU_OFFSET	0x80U
 #define IPI_BUFFER_TARGET_PMC_OFFSET	0x40U
 
 #define IPI_BUFFER_LOCAL_BASE	IPI_BUFFER_APU_BASE
diff --git a/plat/xilinx/versal/include/plat_pm_common.h b/plat/xilinx/versal/include/plat_pm_common.h
index fac5096..22c9d11 100644
--- a/plat/xilinx/versal/include/plat_pm_common.h
+++ b/plat/xilinx/versal/include/plat_pm_common.h
@@ -16,9 +16,6 @@
 #include <stdint.h>
 #include "pm_defs.h"
 
-#define PAYLOAD_ARG_CNT		6U
-#define PAYLOAD_ARG_SIZE	4U	/* size in bytes */
-
 #define NON_SECURE_FLAG		1U
 #define SECURE_FLAG		0U
 
diff --git a/plat/xilinx/versal/include/plat_private.h b/plat/xilinx/versal/include/plat_private.h
index e302096..d12d13a 100644
--- a/plat/xilinx/versal/include/plat_private.h
+++ b/plat/xilinx/versal/include/plat_private.h
@@ -8,6 +8,7 @@
 #define PLAT_PRIVATE_H
 
 #include <lib/xlat_tables/xlat_tables.h>
+#include <bl31/interrupt_mgmt.h>
 
 void versal_config_setup(void);
 
@@ -22,5 +23,10 @@
 void plat_versal_gic_resume(void);
 
 unsigned int versal_calc_core_pos(u_register_t mpidr);
+/*
+ * Register handler to specific GIC entrance
+ * for INTR_TYPE_EL3 type of interrupt
+ */
+int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler);
 
 #endif /* PLAT_PRIVATE_H */
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 4cdaea2..8b513ef 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -91,11 +91,14 @@
  */
 #define PLAT_VERSAL_G1S_IRQS	VERSAL_IRQ_SEC_PHY_TIMER
 #define PLAT_VERSAL_G0_IRQS	VERSAL_IRQ_SEC_PHY_TIMER
+#define PLAT_VERSAL_IPI_IRQ	62
 
 #define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
 	INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_LEVEL)
 
-#define PLAT_VERSAL_G0_IRQ_PROPS(grp)
+#define PLAT_VERSAL_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
 
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 810e5d8..001fb04 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -67,7 +67,7 @@
 #define VERSAL_UART0_BASE		0xFF000000
 #define VERSAL_UART1_BASE		0xFF010000
 
-#if VERSAL_CONSOLE_IS(pl011)
+#if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc)
 # define VERSAL_UART_BASE	VERSAL_UART0_BASE
 #elif VERSAL_CONSOLE_IS(pl011_1)
 # define VERSAL_UART_BASE	VERSAL_UART1_BASE
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 1007e55..a0b317f 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -1,4 +1,4 @@
-# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
@@ -8,6 +8,7 @@
 SEPARATE_CODE_AND_RODATA := 1
 override RESET_TO_BL31 := 1
 PL011_GENERIC_UART := 1
+IPI_CRC_CHECK := 0
 
 ifdef VERSAL_ATF_MEM_BASE
     $(eval $(call add_define,VERSAL_ATF_MEM_BASE))
@@ -31,12 +32,13 @@
     $(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
 endif
 
+ifdef IPI_CRC_CHECK
+    $(eval $(call add_define,IPI_CRC_CHECK))
+endif
+
 VERSAL_PLATFORM ?= silicon
 $(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
 
-VERSAL_CONSOLE	?=	pl011
-$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
-
 PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
 				-Iplat/xilinx/common/include/			\
 				-Iplat/xilinx/common/ipi_mailbox_service/	\
@@ -48,6 +50,7 @@
 
 PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
 				lib/xlat_tables/aarch64/xlat_tables.c		\
+				drivers/arm/dcc/dcc_console.c			\
 				drivers/delay_timer/delay_timer.c		\
 				drivers/delay_timer/generic_delay_timer.c	\
 				${GICV3_SOURCES}				\
@@ -59,6 +62,14 @@
 				plat/xilinx/versal/aarch64/versal_helpers.S	\
 				plat/xilinx/versal/aarch64/versal_common.c
 
+VERSAL_CONSOLE	?=	pl011
+ifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc))
+else
+  $(error "Please define VERSAL_CONSOLE")
+endif
+
+$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
+
 BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				lib/cpus/aarch64/cortex_a72.S			\
 				plat/common/plat_psci_common.c			\
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c
index a578543..912835a 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.c
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.c
@@ -15,6 +15,8 @@
 #include "pm_api_sys.h"
 #include "pm_client.h"
 #include "pm_defs.h"
+#include "pm_svc_main.h"
+#include "../drivers/arm/gic/v3/gicv3_private.h"
 
 /*********************************************************************
  * Target module IDs macros
@@ -22,6 +24,7 @@
 #define LIBPM_MODULE_ID		0x2
 #define LOADER_MODULE_ID	0x7
 
+#define  MODE	0x80000000
 /* default shutdown/reboot scope is system(2) */
 static unsigned int pm_shutdown_scope = XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM;
 
@@ -170,7 +173,7 @@
 	/* Send request to the PLM */
 	PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_ABORT_SUSPEND,
 			 reason, primary_proc->node_id);
-	return pm_ipi_send(primary_proc, payload);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /**
@@ -861,6 +864,7 @@
 				uint32_t flag)
 {
 	uint32_t payload[PAYLOAD_ARG_CNT];
+	int ret;
 
 	switch (ioctl_id) {
 	case IOCTL_SET_PLL_FRAC_MODE:
@@ -871,6 +875,15 @@
 		return pm_pll_set_param(arg1, PM_PLL_PARAM_DATA, arg2, flag);
 	case IOCTL_GET_PLL_FRAC_DATA:
 		return pm_pll_get_param(arg1, PM_PLL_PARAM_DATA, value, flag);
+	case IOCTL_SET_SGI:
+		/* Get the sgi number */
+		ret = pm_register_sgi(arg1);
+		if (ret) {
+			return PM_RET_ERROR_ARGS;
+		}
+		gicd_write_irouter(gicv3_driver_data->gicd_base,
+				PLAT_VERSAL_IPI_IRQ, MODE);
+		return PM_RET_SUCCESS;
 	default:
 		/* Send request to the PMC */
 		PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_IOCTL,
@@ -896,7 +909,7 @@
 
 	PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag, PM_SET_WAKEUP_SOURCE,
 			 target, wkup_device, enable);
-	return pm_ipi_send(primary_proc, payload);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /**
diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h
index 793f750..ccb2617 100644
--- a/plat/xilinx/versal/pm_service/pm_defs.h
+++ b/plat/xilinx/versal/pm_service/pm_defs.h
@@ -92,6 +92,7 @@
 #define	IOCTL_GET_PLL_FRAC_MODE		9
 #define	IOCTL_SET_PLL_FRAC_DATA		10
 #define	IOCTL_GET_PLL_FRAC_DATA		11
+#define	IOCTL_SET_SGI			25
 
 /* Parameter ID for PLL IOCTLs */
 /* Fractional data portion for PLL */
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c
index 55a0956..87ba732 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.c
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.c
@@ -13,12 +13,64 @@
 #include <plat_private.h>
 #include <stdbool.h>
 #include <common/runtime_svc.h>
+#include <plat/common/platform.h>
 #include "pm_api_sys.h"
 #include "pm_client.h"
 #include "pm_ipi.h"
+#include <drivers/arm/gicv3.h>
+
+#define XSCUGIC_SGIR_EL1_INITID_SHIFT    24U
+#define INVALID_SGI    0xFF
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r_el1, S3_0_C12_C11_6)
 
 /* pm_up = true - UP, pm_up = false - DOWN */
 static bool pm_up;
+static unsigned int sgi = INVALID_SGI;
+
+static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
+				void *cookie)
+{
+	int cpu;
+	unsigned int reg;
+
+	(void)plat_ic_acknowledge_interrupt();
+	cpu = plat_my_core_pos() + 1;
+
+	if (sgi != INVALID_SGI) {
+		reg = (cpu | (sgi << XSCUGIC_SGIR_EL1_INITID_SHIFT));
+		write_icc_asgi1r_el1(reg);
+	}
+
+	/* Clear FIQ */
+	plat_ic_end_of_interrupt(id);
+
+	return 0;
+}
+
+/**
+ * pm_register_sgi() - PM register the IPI interrupt
+ *
+ * @sgi -  SGI number to be used for communication.
+ * @return	On success, the initialization function must return 0.
+ *		Any other return value will cause the framework to ignore
+ *		the service
+ *
+ * Update the SGI number to be used.
+ *
+ */
+int pm_register_sgi(unsigned int sgi_num)
+{
+	if (sgi != INVALID_SGI) {
+		return -EBUSY;
+	}
+
+	if (sgi_num >= GICV3_MAX_SGI_TARGETS) {
+		return -EINVAL;
+	}
+
+	sgi = sgi_num;
+	return 0;
+}
 
 /**
  * pm_setup() - PM service setup
@@ -46,6 +98,18 @@
 		pm_up = true;
 	}
 
+	/*
+	 * Enable IPI IRQ
+	 * assume the rich OS is OK to handle callback IRQs now.
+	 * Even if we were wrong, it would not enable the IRQ in
+	 * the GIC.
+	 */
+	pm_ipi_irq_enable(primary_proc);
+
+	ret = request_intr_type_el3(PLAT_VERSAL_IPI_IRQ, ipi_fiq_handler);
+	if (ret) {
+		WARN("BL31: registering IPI interrupt failed\n");
+	}
 	return ret;
 }
 
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.h b/plat/xilinx/versal/pm_service/pm_svc_main.h
index 71329ca..4f8dc2b 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.h
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.h
@@ -14,4 +14,5 @@
 			uint64_t x4, void *cookie, void *handle,
 			uint64_t flags);
 
+int pm_register_sgi(unsigned int sgi_num);
 #endif /* PM_SVC_MAIN_H */
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 339967c..fae73cf 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -62,156 +62,151 @@
 } zynqmp_devices[] = {
 	{
 		.id = 0x10,
-		.name = "3EG",
+		.name = "XCZU3EG",
 	},
 	{
 		.id = 0x10,
 		.ver = 0x2c,
-		.name = "3CG",
+		.name = "XCZU3CG",
 	},
 	{
 		.id = 0x11,
-		.name = "2EG",
+		.name = "XCZU2EG",
 	},
 	{
 		.id = 0x11,
 		.ver = 0x2c,
-		.name = "2CG",
+		.name = "XCZU2CG",
 	},
 	{
 		.id = 0x20,
-		.name = "5EV",
+		.name = "XCZU5EV",
 		.evexists = true,
 	},
 	{
 		.id = 0x20,
 		.ver = 0x100,
-		.name = "5EG",
+		.name = "XCZU5EG",
 		.evexists = true,
 	},
 	{
 		.id = 0x20,
 		.ver = 0x12c,
-		.name = "5CG",
+		.name = "XCZU5CG",
 	},
 	{
 		.id = 0x21,
-		.name = "4EV",
+		.name = "XCZU4EV",
 		.evexists = true,
 	},
 	{
 		.id = 0x21,
 		.ver = 0x100,
-		.name = "4EG",
+		.name = "XCZU4EG",
 		.evexists = true,
 	},
 	{
 		.id = 0x21,
 		.ver = 0x12c,
-		.name = "4CG",
+		.name = "XCZU4CG",
 	},
 	{
 		.id = 0x30,
-		.name = "7EV",
+		.name = "XCZU7EV",
 		.evexists = true,
 	},
 	{
 		.id = 0x30,
 		.ver = 0x100,
-		.name = "7EG",
+		.name = "XCZU7EG",
 		.evexists = true,
 	},
 	{
 		.id = 0x30,
 		.ver = 0x12c,
-		.name = "7CG",
+		.name = "XCZU7CG",
 	},
 	{
 		.id = 0x38,
-		.name = "9EG",
+		.name = "XCZU9EG",
 	},
 	{
 		.id = 0x38,
 		.ver = 0x2c,
-		.name = "9CG",
+		.name = "XCZU9CG",
 	},
 	{
 		.id = 0x39,
-		.name = "6EG",
+		.name = "XCZU6EG",
 	},
 	{
 		.id = 0x39,
 		.ver = 0x2c,
-		.name = "6CG",
+		.name = "XCZU6CG",
 	},
 	{
 		.id = 0x40,
-		.name = "11EG",
-	},
-	{ /* For testing purpose only */
-		.id = 0x50,
-		.ver = 0x2c,
-		.name = "15CG",
+		.name = "XCZU11EG",
 	},
 	{
 		.id = 0x50,
-		.name = "15EG",
+		.name = "XCZU15EG",
 	},
 	{
 		.id = 0x58,
-		.name = "19EG",
+		.name = "XCZU19EG",
 	},
 	{
 		.id = 0x59,
-		.name = "17EG",
+		.name = "XCZU17EG",
 	},
 	{
 		.id = 0x60,
-		.name = "28DR",
+		.name = "XCZU28DR",
 	},
 	{
 		.id = 0x61,
-		.name = "21DR",
+		.name = "XCZU21DR",
 	},
 	{
 		.id = 0x62,
-		.name = "29DR",
+		.name = "XCZU29DR",
 	},
 	{
 		.id = 0x63,
-		.name = "23DR",
+		.name = "XCZU23DR",
 	},
 	{
 		.id = 0x64,
-		.name = "27DR",
+		.name = "XCZU27DR",
 	},
 	{
 		.id = 0x65,
-		.name = "25DR",
+		.name = "XCZU25DR",
 	},
 	{
 		.id = 0x66,
-		.name = "39DR",
+		.name = "XCZU39DR",
 	},
 	{
 		.id = 0x7d,
-		.name = "43DR",
+		.name = "XCZU43DR",
 	},
 	{
 		.id = 0x78,
-		.name = "46DR",
+		.name = "XCZU46DR",
 	},
 	{
 		.id = 0x7f,
-		.name = "47DR",
+		.name = "XCZU47DR",
 	},
 	{
 		.id = 0x7b,
-		.name = "48DR",
+		.name = "XCZU48DR",
 	},
 	{
 		.id = 0x7e,
-		.name = "49DR",
+		.name = "XCZU49DR",
 	},
 };
 
@@ -219,6 +214,8 @@
 #define ZYNQMP_PL_STATUS_MASK	BIT(ZYNQMP_PL_STATUS_BIT)
 #define ZYNQMP_CSU_VERSION_MASK	~(ZYNQMP_PL_STATUS_MASK)
 
+#define SILICON_ID_XCK26       0x4724093
+
 static char *zynqmp_get_silicon_idcode_name(void)
 {
 	uint32_t id, ver, chipid[2];
@@ -236,7 +233,7 @@
 	chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
 #else
 	if (pm_get_chipid(chipid) != PM_RET_SUCCESS)
-		return "UNKN";
+		return "XCZUUNKN";
 #endif
 
 	id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
@@ -250,8 +247,13 @@
 			break;
 	}
 
-	if (i >= ARRAY_SIZE(zynqmp_devices))
-		return "UNKN";
+	if (i >= ARRAY_SIZE(zynqmp_devices)) {
+		if (chipid[0] == SILICON_ID_XCK26) {
+			return "XCK26";
+		} else {
+			return "XCZUUNKN";
+		}
+	}
 
 	if (!zynqmp_devices[i].evexists)
 		return zynqmp_devices[i].name;
@@ -327,9 +329,10 @@
 		break;
 	}
 
-	NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x\n",
-	       zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(),
-	       (rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE);
+	NOTICE("TF-A running on %s/%s at 0x%x\n",
+	       zynqmp_print_silicon_idcode(), label, BL31_BASE);
+	VERBOSE("TF-A running on v%d/RTL%d.%d\n",
+	       zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf);
 }
 #else
 static inline void zynqmp_print_platform_name(void) { }
@@ -350,10 +353,19 @@
 
 void zynqmp_config_setup(void)
 {
+	uint64_t counter_freq;
+
 	/* Configure IPI data for ZynqMP */
 	zynqmp_ipi_config_table_init();
 
 	zynqmp_print_platform_name();
+
+	/* Configure counter frequency */
+	counter_freq = read_cntfrq_el0();
+	if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) {
+		write_cntfrq_el0(plat_get_syscnt_freq2());
+	}
+
 	generic_delay_timer_init();
 }
 
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index d4cd7f6..47be4e1 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 #include <bl31/bl31.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <drivers/arm/dcc.h>
 #include <drivers/console.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
@@ -19,6 +20,10 @@
 #include <plat_private.h>
 #include <zynqmp_def.h>
 
+#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
+#include <libfdt.h>
+
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
 
@@ -62,15 +67,23 @@
 				u_register_t arg2, u_register_t arg3)
 {
 	uint64_t atf_handoff_addr;
-	/* Register the console to provide early debug support */
-	static console_t bl31_boot_console;
-	(void)console_cdns_register(ZYNQMP_UART_BASE,
-				       zynqmp_get_uart_clk(),
-				       ZYNQMP_UART_BAUDRATE,
-				       &bl31_boot_console);
-	console_set_scope(&bl31_boot_console,
-			  CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
 
+	if (ZYNQMP_CONSOLE_IS(cadence)) {
+		/* Register the console to provide early debug support */
+		static console_t bl31_boot_console;
+		(void)console_cdns_register(ZYNQMP_UART_BASE,
+					       zynqmp_get_uart_clk(),
+					       ZYNQMP_UART_BAUDRATE,
+					       &bl31_boot_console);
+		console_set_scope(&bl31_boot_console,
+				  CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
+	} else if (ZYNQMP_CONSOLE_IS(dcc)) {
+		/* Initialize the dcc console for debug */
+		int rc = console_dcc_register();
+		if (rc == 0) {
+			panic();
+		}
+	}
 	/* Initialize the platform config for future decision making */
 	zynqmp_config_setup();
 
@@ -114,25 +127,6 @@
 	}
 }
 
-/* Enable the test setup */
-#ifndef ZYNQMP_TESTING
-static void zynqmp_testing_setup(void) { }
-#else
-static void zynqmp_testing_setup(void)
-{
-	uint32_t actlr_el3, actlr_el2;
-
-	/* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */
-	actlr_el3 = read_actlr_el3();
-	actlr_el2 = read_actlr_el2();
-
-	actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
-	actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
-	write_actlr_el3(actlr_el3);
-	write_actlr_el2(actlr_el2);
-}
-#endif
-
 #if ZYNQMP_WDT_RESTART
 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
 
@@ -169,12 +163,58 @@
 }
 #endif
 
+#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
+static void prepare_dtb(void)
+{
+	void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
+	int ret;
+
+	/* Return if no device tree is detected */
+	if (fdt_check_header(dtb) != 0) {
+		NOTICE("Can't read DT at 0x%p\n", dtb);
+		return;
+	}
+
+	ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE);
+	if (ret < 0) {
+		ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
+		return;
+	}
+
+	if (dt_add_psci_node(dtb)) {
+		ERROR("Failed to add PSCI Device Tree node\n");
+		return;
+	}
+
+	if (dt_add_psci_cpu_enable_methods(dtb)) {
+		ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
+		return;
+	}
+
+	/* Reserve memory used by Trusted Firmware. */
+	if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) {
+		WARN("Failed to add reserved memory nodes to DT.\n");
+	}
+
+	ret = fdt_pack(dtb);
+	if (ret < 0) {
+		ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
+	}
+
+	clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
+	INFO("Changed device tree to advertise PSCI and reserved memories.\n");
+}
+#endif
+
 void bl31_platform_setup(void)
 {
+#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
+		prepare_dtb();
+#endif
+
 	/* Initialize the gic cpu and distributor interfaces */
 	plat_arm_gic_driver_init();
 	plat_arm_gic_init();
-	zynqmp_testing_setup();
 }
 
 void bl31_plat_runtime_setup(void)
@@ -202,6 +242,10 @@
 
 
 	const mmap_region_t bl_regions[] = {
+#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
+		MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
+			MT_MEMORY | MT_RW | MT_NS),
+#endif
 		MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
 			MT_MEMORY | MT_RW | MT_SECURE),
 		MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
diff --git a/plat/xilinx/zynqmp/include/plat_pm_common.h b/plat/xilinx/zynqmp/include/plat_pm_common.h
index 56a747a..a57aebe 100644
--- a/plat/xilinx/zynqmp/include/plat_pm_common.h
+++ b/plat/xilinx/zynqmp/include/plat_pm_common.h
@@ -16,17 +16,6 @@
 #include <common/debug.h>
 #include "pm_defs.h"
 
-#if ZYNQMP_IPI_CRC_CHECK
-#define PAYLOAD_ARG_CNT         8U
-#define IPI_W0_TO_W6_SIZE       28U
-#define PAYLOAD_CRC_POS         7U
-#define CRC_INIT_VALUE          0x4F4EU
-#define CRC_ORDER               16U
-#define CRC_POLYNOM             0x8005U
-#else
-#define PAYLOAD_ARG_CNT         6U
-#endif
-#define PAYLOAD_ARG_SIZE	4U	/* size in bytes */
 
 #define ZYNQMP_TZ_VERSION_MAJOR		1
 #define ZYNQMP_TZ_VERSION_MINOR		0
diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
index 2796840..0c14315 100644
--- a/plat/xilinx/zynqmp/include/platform_def.h
+++ b/plat/xilinx/zynqmp/include/platform_def.h
@@ -36,7 +36,7 @@
  * little space for growth.
  */
 #ifndef ZYNQMP_ATF_MEM_BASE
-#if !DEBUG && defined(SPD_none)
+#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT
 # define BL31_BASE			0xfffea000
 # define BL31_LIMIT			0xffffffff
 #else
@@ -83,14 +83,29 @@
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
+#define XILINX_OF_BOARD_DTB_ADDR	0x100000
+#define XILINX_OF_BOARD_DTB_MAX_SIZE	0x200000
+#define PLAT_DDR_LOWMEM_MAX		0x80000000
+
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
+#define MAX_MMAP_REGIONS		8
+#else
 #define MAX_MMAP_REGIONS		7
+#endif
 #define MAX_XLAT_TABLES			5
 
 #define CACHE_WRITEBACK_SHIFT   6
 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
 
+#define ZYNQMP_SDEI_SGI_PRIVATE		U(8)
+
+/* Platform macros to support exception handling framework */
+#define PLAT_PRI_BITS			U(3)
+#define PLAT_SDEI_CRITICAL_PRI		0x10
+#define PLAT_SDEI_NORMAL_PRI		0x20
+
 #define PLAT_ARM_GICD_BASE	BASE_GICD_BASE
 #define PLAT_ARM_GICC_BASE	BASE_GICC_BASE
 /*
@@ -102,8 +117,6 @@
 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
 	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_EDGE), \
 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
@@ -124,8 +137,6 @@
 			GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_EDGE), \
 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
@@ -142,6 +153,8 @@
 			GIC_INTR_CFG_EDGE)
 #endif
 
-#define PLAT_ARM_G0_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI,	grp, \
+			GIC_INTR_CFG_EDGE)
 
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index f474630..7e58391 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -17,6 +17,9 @@
 
 #define ZYNQMP_CONSOLE_IS(con)	(ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
 
+/* Default counter frequency */
+#define ZYNQMP_DEFAULT_COUNTER_FREQ	0U
+
 /* Firmware Image Package */
 #define ZYNQMP_PRIMARY_CPU		0
 
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index f579f79..f78b88c 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -179,14 +179,6 @@
 	return PSCI_E_SUCCESS;
 }
 
-int zynqmp_validate_ns_entrypoint(unsigned long ns_entrypoint)
-{
-	VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
-
-	/* FIXME: Actually validate */
-	return PSCI_E_SUCCESS;
-}
-
 void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state)
 {
 	req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
@@ -206,7 +198,6 @@
 	.system_off			= zynqmp_system_off,
 	.system_reset			= zynqmp_system_reset,
 	.validate_power_state		= zynqmp_validate_power_state,
-	.validate_ns_entrypoint		= zynqmp_validate_ns_entrypoint,
 	.get_sys_suspend_power_state	= zynqmp_get_sys_suspend_power_state,
 };
 
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 6e700b9..d075a56 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
@@ -9,11 +9,13 @@
 A53_DISABLE_NON_TEMPORAL_HINT := 0
 SEPARATE_CODE_AND_RODATA := 1
 ZYNQMP_WDT_RESTART := 0
-ZYNQMP_IPI_CRC_CHECK := 0
+IPI_CRC_CHECK := 0
 override RESET_TO_BL31 := 1
 override GICV2_G0_FOR_EL3 := 1
 override WARMBOOT_ENABLE_DCACHE_EARLY := 1
 
+EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
+
 # Do not enable SVE
 ENABLE_SVE_FOR_NS	:= 0
 
@@ -41,17 +43,19 @@
     $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
 endif
 
-ZYNQMP_CONSOLE	?=	cadence
-$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
 
 ifdef ZYNQMP_WDT_RESTART
 $(eval $(call add_define,ZYNQMP_WDT_RESTART))
 endif
 
 ifdef ZYNQMP_IPI_CRC_CHECK
-    $(eval $(call add_define,ZYNQMP_IPI_CRC_CHECK))
+  $(warning "ZYNQMP_IPI_CRC_CHECK macro is deprecated...instead please use IPI_CRC_CHECK.")
 endif
 
+ifdef IPI_CRC_CHECK
+    $(eval $(call add_define,IPI_CRC_CHECK))
+endif
+
 PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
 				-Iinclude/plat/arm/common/aarch64/		\
 				-Iplat/xilinx/common/include/			\
@@ -59,11 +63,13 @@
 				-Iplat/xilinx/zynqmp/include/			\
 				-Iplat/xilinx/zynqmp/pm_service/		\
 
+include lib/libfdt/libfdt.mk
 # Include GICv2 driver files
 include drivers/arm/gic/v2/gicv2.mk
 
 PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
 				lib/xlat_tables/aarch64/xlat_tables.c		\
+				drivers/arm/dcc/dcc_console.c			\
 				drivers/delay_timer/delay_timer.c		\
 				drivers/delay_timer/generic_delay_timer.c	\
 				${GICV2_SOURCES}				\
@@ -78,10 +84,19 @@
 				plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S	\
 				plat/xilinx/zynqmp/aarch64/zynqmp_common.c
 
+ZYNQMP_CONSOLE	?=	cadence
+ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc))
+else
+  $(error "Please define ZYNQMP_CONSOLE")
+endif
+$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
+
 BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				lib/cpus/aarch64/aem_generic.S			\
 				lib/cpus/aarch64/cortex_a53.S			\
 				plat/common/plat_psci_common.c			\
+				common/fdt_fixup.c				\
+				${LIBFDT_SRCS}					\
 				plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
 				plat/xilinx/common/pm_service/pm_ipi.c		\
 				plat/xilinx/common/plat_startup.c		\
@@ -97,6 +112,11 @@
 				plat/xilinx/zynqmp/pm_service/pm_api_clock.c	\
 				plat/xilinx/zynqmp/pm_service/pm_client.c
 
+ifeq (${SDEI_SUPPORT},1)
+BL31_SOURCES		+=	plat/xilinx/zynqmp/zynqmp_ehf.c			\
+				plat/xilinx/zynqmp/zynqmp_sdei.c
+endif
+
 BL31_CPPFLAGS		+=	-fno-jump-tables
 
 ifneq (${RESET_TO_BL31},1)
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index 9a53408..62260bc 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -209,7 +209,7 @@
 	/* TODO: allow passing the node ID of the affected CPU */
 	PM_PACK_PAYLOAD3(payload, PM_ABORT_SUSPEND, reason,
 			 primary_proc->node_id);
-	return pm_ipi_send(primary_proc, payload);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /**
@@ -228,7 +228,7 @@
 
 	PM_PACK_PAYLOAD4(payload, PM_SET_WAKEUP_SOURCE, target, wkup_node,
 			 enable);
-	return pm_ipi_send(primary_proc, payload);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /**
@@ -316,7 +316,7 @@
 	uint32_t payload[PAYLOAD_ARG_CNT];
 
 	PM_PACK_PAYLOAD2(payload, PM_RELEASE_NODE, nid);
-	return pm_ipi_send(primary_proc, payload);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /**
@@ -332,7 +332,7 @@
 	uint32_t payload[PAYLOAD_ARG_CNT];
 
 	PM_PACK_PAYLOAD3(payload, PM_SET_MAX_LATENCY, nid, latency);
-	return pm_ipi_send(primary_proc, payload);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /* Miscellaneous API functions */
@@ -461,7 +461,7 @@
 
 	/* Send request to the PMU */
 	PM_PACK_PAYLOAD3(payload, PM_RESET_ASSERT, reset, assert);
-	return pm_ipi_send(primary_proc, payload);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /**
diff --git a/plat/xilinx/zynqmp/zynqmp_ehf.c b/plat/xilinx/zynqmp/zynqmp_ehf.c
new file mode 100644
index 0000000..fbf1ed0
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_ehf.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) Siemens AG, 2020-2021
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <bl31/ehf.h>
+
+/*
+ * Enumeration of priority levels on ARM platforms.
+ */
+ehf_pri_desc_t zynqmp_exceptions[] = {
+	/* Critical priority SDEI */
+	EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
+
+	/* Normal priority SDEI */
+	EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
+};
+
+/* Plug in ARM exceptions to Exception Handling Framework. */
+EHF_REGISTER_PRIORITIES(zynqmp_exceptions, ARRAY_SIZE(zynqmp_exceptions), PLAT_PRI_BITS);
diff --git a/plat/xilinx/zynqmp/zynqmp_sdei.c b/plat/xilinx/zynqmp/zynqmp_sdei.c
new file mode 100644
index 0000000..7e92b58
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_sdei.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) Siemens AG, 2020-2021
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* SDEI configuration for ARM platforms */
+
+#include <bl31/ehf.h>
+#include <common/debug.h>
+#include <services/sdei.h>
+
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+int arm_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+	return (entrypoint < BL31_BASE || entrypoint > BL31_LIMIT) ? 0 : -1;
+}
+
+/* Private event mappings */
+static sdei_ev_map_t zynqmp_sdei_private[] = {
+	SDEI_DEFINE_EVENT_0(ZYNQMP_SDEI_SGI_PRIVATE),
+};
+
+/* Shared event mappings */
+static sdei_ev_map_t zynqmp_sdei_shared[] = {
+};
+
+void plat_sdei_setup(void)
+{
+	INFO("SDEI platform setup\n");
+}
+
+/* Export ARM SDEI events */
+REGISTER_SDEI_MAP(zynqmp_sdei_private, zynqmp_sdei_shared);
diff --git a/services/std_svc/pci_svc.c b/services/std_svc/pci_svc.c
new file mode 100644
index 0000000..a02b8a7
--- /dev/null
+++ b/services/std_svc/pci_svc.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <services/pci_svc.h>
+#include <services/std_svc.h>
+#include <smccc_helpers.h>
+
+static uint64_t validate_rw_addr_sz(uint32_t addr, uint64_t off, uint64_t sz)
+{
+	uint32_t nseg;
+	uint32_t ret;
+	uint32_t start_end_bus;
+
+	ret = pci_get_bus_for_seg(PCI_ADDR_SEG(addr), &start_end_bus, &nseg);
+
+	if (ret != SMC_PCI_CALL_SUCCESS) {
+		return SMC_PCI_CALL_INVAL_PARAM;
+	}
+	switch (sz) {
+	case SMC_PCI_SZ_8BIT:
+	case SMC_PCI_SZ_16BIT:
+	case SMC_PCI_SZ_32BIT:
+		break;
+	default:
+		return SMC_PCI_CALL_INVAL_PARAM;
+	}
+	if ((off + sz) > (PCI_OFFSET_MASK + 1U)) {
+		return SMC_PCI_CALL_INVAL_PARAM;
+	}
+	return SMC_PCI_CALL_SUCCESS;
+}
+
+uint64_t pci_smc_handler(uint32_t smc_fid,
+			     u_register_t x1,
+			     u_register_t x2,
+			     u_register_t x3,
+			     u_register_t x4,
+			     void *cookie,
+			     void *handle,
+			     u_register_t flags)
+{
+	switch (smc_fid) {
+	case SMC_PCI_VERSION: {
+		pcie_version ver;
+
+		ver.major = 1U;
+		ver.minor = 0U;
+		SMC_RET4(handle, ver.val, 0U, 0U, 0U);
+	}
+	case SMC_PCI_FEATURES:
+		switch (x1) {
+		case SMC_PCI_VERSION:
+		case SMC_PCI_FEATURES:
+		case SMC_PCI_READ:
+		case SMC_PCI_WRITE:
+		case SMC_PCI_SEG_INFO:
+			SMC_RET1(handle, SMC_PCI_CALL_SUCCESS);
+		default:
+			SMC_RET1(handle, SMC_PCI_CALL_NOT_SUPPORTED);
+		}
+		break;
+	case SMC_PCI_READ: {
+		uint32_t ret;
+
+		if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) {
+			SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+		}
+		if (x4 != 0U) {
+			SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+		}
+		if (pci_read_config(x1, x2, x3, &ret) != 0U) {
+			SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+		} else {
+			SMC_RET2(handle, SMC_PCI_CALL_SUCCESS, ret);
+		}
+		break;
+	}
+	case SMC_PCI_WRITE: {
+		uint32_t ret;
+
+		if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) {
+			SMC_RET1(handle, SMC_PCI_CALL_INVAL_PARAM);
+		}
+		ret = pci_write_config(x1, x2, x3, x4);
+		SMC_RET1(handle, ret);
+		break;
+	}
+	case SMC_PCI_SEG_INFO: {
+		uint32_t nseg;
+		uint32_t ret;
+		uint32_t start_end_bus;
+
+		if ((x2 != 0U) || (x3 != 0U) || (x4 != 0U)) {
+		    SMC_RET3(handle, SMC_PCI_CALL_INVAL_PARAM, 0U, 0U);
+		}
+		ret = pci_get_bus_for_seg(x1, &start_end_bus, &nseg);
+		SMC_RET3(handle, ret, start_end_bus, nseg);
+		break;
+	}
+	default:
+		/* should be unreachable */
+		WARN("Unimplemented PCI Service Call: 0x%x\n", smc_fid);
+		SMC_RET1(handle, SMC_PCI_CALL_NOT_SUPPORTED);
+	}
+}
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index fa1d3d2..f12b2ca 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #include <string.h>
 
 #include <arch_helpers.h>
+#include <arch_features.h>
 #include <bl31/ehf.h>
 #include <bl31/interrupt_mgmt.h>
 #include <common/bl_common.h>
@@ -232,6 +233,77 @@
 }
 
 /*
+ * Prepare for ERET:
+ * - Set the ELR to the registered handler address
+ * - Set the SPSR register as described in the SDEI documentation and
+ *   the AArch64.TakeException() pseudocode function in
+ *   ARM DDI 0487F.c page J1-7635
+ */
+
+static void sdei_set_elr_spsr(sdei_entry_t *se, sdei_dispatch_context_t *disp_ctx)
+{
+	unsigned int client_el = sdei_client_el();
+	u_register_t sdei_spsr = SPSR_64(client_el, MODE_SP_ELX,
+					DISABLE_ALL_EXCEPTIONS);
+
+	u_register_t interrupted_pstate = disp_ctx->spsr_el3;
+
+	/* Check the SPAN bit in the client el SCTLR */
+	u_register_t client_el_sctlr;
+
+	if (client_el == MODE_EL2) {
+		client_el_sctlr = read_sctlr_el2();
+	} else {
+		client_el_sctlr = read_sctlr_el1();
+	}
+
+	/*
+	 * Check whether to force the PAN bit or use the value in the
+	 * interrupted EL according to the check described in
+	 * TakeException. Since the client can only be Non-Secure
+	 * EL2 or El1 some of the conditions in ElIsInHost() we know
+	 * will always be True.
+	 * When the client_el is EL2 we know that there will be a SPAN
+	 * bit in SCTLR_EL2 as we have already checked for the condition
+	 * HCR_EL2.E2H = 1 and HCR_EL2.TGE = 1
+	 */
+	u_register_t hcr_el2 = read_hcr();
+	bool el_is_in_host = is_armv8_1_vhe_present() &&
+			     (hcr_el2 & HCR_TGE_BIT) &&
+			     (hcr_el2 & HCR_E2H_BIT);
+
+	if (is_armv8_1_pan_present() &&
+	    ((client_el == MODE_EL1) ||
+		(client_el == MODE_EL2 && el_is_in_host)) &&
+	    ((client_el_sctlr & SCTLR_SPAN_BIT) == 0U)) {
+		sdei_spsr |=  SPSR_PAN_BIT;
+	} else {
+		sdei_spsr |= (interrupted_pstate & SPSR_PAN_BIT);
+	}
+
+	/* If SSBS is implemented, take the value from the client el SCTLR */
+	u_register_t ssbs_enabled = (read_id_aa64pfr1_el1()
+					>> ID_AA64PFR1_EL1_SSBS_SHIFT)
+					& ID_AA64PFR1_EL1_SSBS_MASK;
+	if (ssbs_enabled != SSBS_UNAVAILABLE) {
+		u_register_t  ssbs_bit = ((client_el_sctlr & SCTLR_DSSBS_BIT)
+						>> SCTLR_DSSBS_SHIFT)
+						<< SPSR_SSBS_SHIFT_AARCH64;
+		sdei_spsr |= ssbs_bit;
+	}
+
+	/* If MTE is implemented in the client el set the TCO bit */
+	if (get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX) {
+		sdei_spsr |= SPSR_TCO_BIT_AARCH64;
+	}
+
+	/* Take the DIT field from the pstate of the interrupted el */
+	sdei_spsr |= (interrupted_pstate & SPSR_DIT_BIT);
+
+	cm_set_elr_spsr_el3(NON_SECURE, (uintptr_t) se->ep, sdei_spsr);
+}
+
+/*
  * Populate the Non-secure context so that the next ERET will dispatch to the
  * SDEI client.
  */
@@ -256,15 +328,8 @@
 	SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3);
 	SMC_SET_GP(ctx, CTX_GPREG_X3, disp_ctx->spsr_el3);
 
-	/*
-	 * Prepare for ERET:
-	 *
-	 * - Set PC to the registered handler address
-	 * - Set SPSR to jump to client EL with exceptions masked
-	 */
-	cm_set_elr_spsr_el3(NON_SECURE, (uintptr_t) se->ep,
-			SPSR_64(sdei_client_el(), MODE_SP_ELX,
-				DISABLE_ALL_EXCEPTIONS));
+	/* Setup the elr and spsr register to prepare for ERET */
+	sdei_set_elr_spsr(se, disp_ctx);
 
 #if DYNAMIC_WORKAROUND_CVE_2018_3639
 	cve_2018_3639_t *tgt_cve_2018_3639;
diff --git a/services/std_svc/spm_mm/spm_mm_setup.c b/services/std_svc/spm_mm/spm_mm_setup.c
index 32562c3..9d681c2 100644
--- a/services/std_svc/spm_mm/spm_mm_setup.c
+++ b/services/std_svc/spm_mm/spm_mm_setup.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,6 +27,10 @@
 {
 	cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
 
+	/* Pointer to the MP information from the platform port. */
+	const spm_mm_boot_info_t *sp_boot_info =
+			plat_get_secure_partition_boot_info(NULL);
+
 	/*
 	 * Initialize CPU context
 	 * ----------------------
@@ -36,7 +41,7 @@
 	SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
 
 	/* Setup entrypoint and SPSR */
-	ep_info.pc = BL32_BASE;
+	ep_info.pc = sp_boot_info->sp_image_base;
 	ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
 
 	/*
@@ -53,8 +58,8 @@
 	 *
 	 * X4 to X7 = 0
 	 */
-	ep_info.args.arg0 = PLAT_SPM_BUF_BASE;
-	ep_info.args.arg1 = PLAT_SPM_BUF_SIZE;
+	ep_info.args.arg0 = sp_boot_info->sp_shared_buf_base;
+	ep_info.args.arg1 = sp_boot_info->sp_shared_buf_size;
 	ep_info.args.arg2 = PLAT_SPM_COOKIE_0;
 	ep_info.args.arg3 = PLAT_SPM_COOKIE_1;
 
@@ -66,7 +71,7 @@
 	 * implementation defined means. The value will be 0 otherwise.
 	 */
 	write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0,
-			PLAT_SP_IMAGE_STACK_BASE + PLAT_SP_IMAGE_STACK_PCPU_SIZE);
+			sp_boot_info->sp_stack_base + sp_boot_info->sp_pcpu_stack_size);
 
 	/*
 	 * Setup translation tables
@@ -84,10 +89,10 @@
 	unsigned int max_granule_mask = max_granule - 1U;
 
 	/* Base must be aligned to the max granularity */
-	assert((PLAT_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0);
+	assert((sp_boot_info->sp_ns_comm_buf_base & max_granule_mask) == 0);
 
 	/* Size must be a multiple of the max granularity */
-	assert((PLAT_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0);
+	assert((sp_boot_info->sp_ns_comm_buf_size & max_granule_mask) == 0);
 
 #endif /* ENABLE_ASSERTIONS */
 
@@ -191,16 +196,14 @@
 	 * ----------------------------------------------------------
 	 */
 
-	void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE;
+	void *shared_buf_ptr = (void *) sp_boot_info->sp_shared_buf_base;
 
 	/* Copy the boot information into the shared buffer with the SP. */
 	assert((uintptr_t)shared_buf_ptr + sizeof(spm_mm_boot_info_t)
-	       <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE));
+	       <= (sp_boot_info->sp_shared_buf_base + sp_boot_info->sp_shared_buf_size));
 
-	assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1));
-
-	const spm_mm_boot_info_t *sp_boot_info =
-			plat_get_secure_partition_boot_info(NULL);
+	assert(sp_boot_info->sp_shared_buf_base <=
+				(UINTPTR_MAX - sp_boot_info->sp_shared_buf_size + 1));
 
 	assert(sp_boot_info != NULL);
 
@@ -234,7 +237,7 @@
 	assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT);
 
 	assert((uintptr_t)shared_buf_ptr
-	       <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE -
+	       <= (sp_boot_info->sp_shared_buf_base + sp_boot_info->sp_shared_buf_size -
 		       (sp_boot_info->num_cpus * sizeof(*sp_mp_info))));
 
 	memcpy(shared_buf_ptr, (const void *) sp_mp_info,
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 7b20bf1..dda127f 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -108,9 +108,10 @@
 	cm_set_context(&(spmc_ctx->cpu_ctx), SECURE);
 
 	/* Restore the context assigned above */
-	cm_el1_sysregs_context_restore(SECURE);
 #if SPMD_SPM_AT_SEL2
 	cm_el2_sysregs_context_restore(SECURE);
+#else
+	cm_el1_sysregs_context_restore(SECURE);
 #endif
 	cm_set_next_eret_context(SECURE);
 
@@ -118,9 +119,10 @@
 	rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx);
 
 	/* Save secure state */
-	cm_el1_sysregs_context_save(SECURE);
 #if SPMD_SPM_AT_SEL2
 	cm_el2_sysregs_context_save(SECURE);
+#else
+	cm_el1_sysregs_context_save(SECURE);
 #endif
 
 	return rc;
@@ -346,15 +348,23 @@
 	unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
 
 	/* Save incoming security state */
-	cm_el1_sysregs_context_save(secure_state_in);
 #if SPMD_SPM_AT_SEL2
+	if (secure_state_in == NON_SECURE) {
+		cm_el1_sysregs_context_save(secure_state_in);
+	}
 	cm_el2_sysregs_context_save(secure_state_in);
+#else
+	cm_el1_sysregs_context_save(secure_state_in);
 #endif
 
 	/* Restore outgoing security state */
-	cm_el1_sysregs_context_restore(secure_state_out);
 #if SPMD_SPM_AT_SEL2
+	if (secure_state_out == NON_SECURE) {
+		cm_el1_sysregs_context_restore(secure_state_out);
+	}
 	cm_el2_sysregs_context_restore(secure_state_out);
+#else
+	cm_el1_sysregs_context_restore(secure_state_out);
 #endif
 	cm_set_next_eret_context(secure_state_out);
 
@@ -552,6 +562,30 @@
 		return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
 		break; /* Not reached */
 
+	case FFA_SPM_ID_GET:
+		if (MAKE_FFA_VERSION(1, 1) > FFA_VERSION_COMPILED) {
+			return spmd_ffa_error_return(handle,
+						     FFA_ERROR_NOT_SUPPORTED);
+		}
+		/*
+		 * Returns the ID of the SPMC or SPMD depending on the FF-A
+		 * instance where this function is invoked
+		 */
+		if (!secure_origin) {
+			SMC_RET8(handle, FFA_SUCCESS_SMC32,
+				 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id,
+				 FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+				 FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+				 FFA_PARAM_MBZ);
+		}
+		SMC_RET8(handle, FFA_SUCCESS_SMC32,
+			 FFA_TARGET_INFO_MBZ, SPMD_DIRECT_MSG_ENDPOINT_ID,
+			 FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+			 FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+			 FFA_PARAM_MBZ);
+
+		break; /* not reached */
+
 	case FFA_MSG_SEND_DIRECT_REQ_SMC32:
 		if (secure_origin && spmd_is_spmc_message(x1)) {
 			ret = spmd_handle_spmc_message(x3, x4,
@@ -639,7 +673,7 @@
 		}
 
 		/* Fall through to forward the call to the other world */
-
+	case FFA_INTERRUPT:
 	case FFA_MSG_YIELD:
 		/* This interface must be invoked only by the Secure world */
 		if (!secure_origin) {
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index 23f13ab..1917d0a 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -13,6 +13,7 @@
 #include <lib/pmf/pmf.h>
 #include <lib/psci/psci.h>
 #include <lib/runtime_instr.h>
+#include <services/pci_svc.h>
 #include <services/sdei.h>
 #include <services/spm_mm_svc.h>
 #include <services/spmd_svc.h>
@@ -82,6 +83,15 @@
 			     void *handle,
 			     u_register_t flags)
 {
+	if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
+		/* 32-bit SMC function, clear top parameter bits */
+
+		x1 &= UINT32_MAX;
+		x2 &= UINT32_MAX;
+		x3 &= UINT32_MAX;
+		x4 &= UINT32_MAX;
+	}
+
 	/*
 	 * Dispatch PSCI calls to PSCI SMC handler and return its return
 	 * value
@@ -149,6 +159,13 @@
 	}
 #endif
 
+#if SMC_PCI_SUPPORT
+	if (is_pci_fid(smc_fid)) {
+		return pci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
+				       flags);
+	}
+#endif
+
 	switch (smc_fid) {
 	case ARM_STD_SVC_CALL_COUNT:
 		/*
@@ -166,7 +183,7 @@
 		SMC_RET2(handle, STD_SVC_VERSION_MAJOR, STD_SVC_VERSION_MINOR);
 
 	default:
-		WARN("Unimplemented Standard Service Call: 0x%x \n", smc_fid);
+		VERBOSE("Unimplemented Standard Service Call: 0x%x \n", smc_fid);
 		SMC_RET1(handle, SMC_UNK);
 	}
 }
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index b75907d..11d2e7b 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -44,11 +44,7 @@
 
 .PHONY: all clean distclean
 
-# Clean before build as old fiptool might be created with
-# including different PLAT_FIPTOOL_HELPER_MK.
-all:
-	${MAKE}	clean
-	${MAKE}	${PROJECT}
+all: ${PROJECT}
 
 ${PROJECT}: ${OBJECTS} Makefile
 	@echo "  HOSTLD  $@"
diff --git a/tools/stm32image/stm32image.c b/tools/stm32image/stm32image.c
index 41024e2..fb1dee0 100644
--- a/tools/stm32image/stm32image.c
+++ b/tools/stm32image/stm32image.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,8 +45,6 @@
 	uint8_t binary_type;
 };
 
-static struct stm32_header stm32image_header;
-
 static void stm32image_default_header(struct stm32_header *ptr)
 {
 	if (!ptr) {
@@ -54,10 +52,9 @@
 	}
 
 	ptr->magic_number = HEADER_MAGIC;
-	ptr->header_version[VER_MAJOR] = HEADER_VERSION_V1;
 	ptr->option_flags = HEADER_DEFAULT_OPTION;
-	ptr->ecdsa_algorithm = 1;
-	ptr->version_number = 0;
+	ptr->ecdsa_algorithm = __cpu_to_le32(1);
+	ptr->version_number = __cpu_to_le32(0);
 	ptr->binary_type = TF_BINARY_TYPE;
 }
 
@@ -105,27 +102,33 @@
 }
 
 static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,
-				  uint32_t loadaddr, uint32_t ep, uint32_t ver)
+				  uint32_t loadaddr, uint32_t ep, uint32_t ver,
+				  uint32_t major, uint32_t minor)
 {
 	struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
 
 	stm32image_default_header(stm32hdr);
 
+	stm32hdr->header_version[VER_MAJOR] = major;
+	stm32hdr->header_version[VER_MINOR] = minor;
 	stm32hdr->load_address = __cpu_to_le32(loadaddr);
 	stm32hdr->image_entry_point = __cpu_to_le32(ep);
 	stm32hdr->image_length = __cpu_to_le32((uint32_t)sbuf->st_size -
 					     sizeof(struct stm32_header));
-	stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size);
+	stm32hdr->image_checksum =
+		__cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size));
 	stm32hdr->version_number = __cpu_to_le32(ver);
 }
 
 static int stm32image_create_header_file(char *srcname, char *destname,
 					 uint32_t loadaddr, uint32_t entry,
-					 uint32_t version)
+					 uint32_t version, uint32_t major,
+					 uint32_t minor)
 {
 	int src_fd, dest_fd;
 	struct stat sbuf;
 	unsigned char *ptr;
+	struct stm32_header stm32image_header;
 
 	dest_fd = open(destname, O_RDWR | O_CREAT | O_TRUNC | O_APPEND, 0666);
 	if (dest_fd == -1) {
@@ -177,11 +180,12 @@
 		   dest_fd, 0);
 
 	if (ptr == MAP_FAILED) {
-		fprintf(stderr, "Can't read %s\n", srcname);
+		fprintf(stderr, "Can't write %s\n", destname);
 		return -1;
 	}
 
-	stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr, entry, version);
+	stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr, entry, version,
+			      major, minor);
 
 	stm32image_print_header(ptr);
 
@@ -193,9 +197,11 @@
 int main(int argc, char *argv[])
 {
 	int opt, loadaddr = -1, entry = -1, err = 0, version = 0;
+	int major = HEADER_VERSION_V1;
+	int minor = 0;
 	char *dest = NULL, *src = NULL;
 
-	while ((opt = getopt(argc, argv, ":s:d:l:e:v:")) != -1) {
+	while ((opt = getopt(argc, argv, ":s:d:l:e:v:m:n:")) != -1) {
 		switch (opt) {
 		case 's':
 			src = optarg;
@@ -204,17 +210,23 @@
 			dest = optarg;
 			break;
 		case 'l':
-			loadaddr = strtol(optarg, NULL, 16);
+			loadaddr = strtol(optarg, NULL, 0);
 			break;
 		case 'e':
-			entry = strtol(optarg, NULL, 16);
+			entry = strtol(optarg, NULL, 0);
 			break;
 		case 'v':
-			version = strtol(optarg, NULL, 10);
+			version = strtol(optarg, NULL, 0);
+			break;
+		case 'm':
+			major = strtol(optarg, NULL, 0);
+			break;
+		case 'n':
+			minor = strtol(optarg, NULL, 0);
 			break;
 		default:
 			fprintf(stderr,
-				"Usage : %s [-s srcfile] [-d destfile] [-l loadaddr] [-e entry_point]\n",
+				"Usage : %s [-s srcfile] [-d destfile] [-l loadaddr] [-e entry_point] [-m major] [-n minor]\n",
 					argv[0]);
 			return -1;
 		}
@@ -241,7 +253,7 @@
 	}
 
 	err = stm32image_create_header_file(src, dest, loadaddr,
-					    entry, version);
+					    entry, version, major, minor);
 
 	return err;
 }