diff --git a/plat/imx/common/include/imx_io_mux.h b/plat/imx/common/include/imx_io_mux.h
index 9b30421..d588cfd 100644
--- a/plat/imx/common/include/imx_io_mux.h
+++ b/plat/imx/common/include/imx_io_mux.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #define IMX_IO_MUX_H
 
 #include <stdint.h>
+#include <lib/utils_def.h>
 
 /*
  * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
@@ -20,7 +21,10 @@
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET		0x0020
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET		0x0024
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET		0x0028
+
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET		0x002C
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B	BIT(0)
+
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET		0x0030
 
 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET	0x0034
@@ -121,8 +125,24 @@
 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET		0x0154
 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET		0x0158
 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET		0x015C
+
 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET		0x0160
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT0_I2C4_SCL		0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA	BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT2_WDOG4_WDOG_B	BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT3_CSI_PIXCLK		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT4_USB_OTG1_ID		BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT5_GPIO4_IO14		(BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT6_EPDC_VCOM0		(BIT(2) | BIT(1))
+
 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET		0x0164
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT0_I2C4_SDA		0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA	BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT2_WDOG4_WDOG_RST_B_DEB BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT3_CSI_MCLK		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT4_USB_OTG2_ID		BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT5_GPIO4_IO15		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT6_EPDC_VCOM1		(BIT(2) | BIT(1))
 
 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET	0x0168
 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK	0x00
@@ -165,6 +185,7 @@
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET		0x01C4
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET		0x01C8
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET		0x01CC
+
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET		0x01D0
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET		0x01D4
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET		0x01D8
@@ -391,6 +412,7 @@
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET		0x0434
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET		0x0438
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET		0x043C
+
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET		0x0440
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET		0x0444
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET		0x0448
@@ -403,6 +425,19 @@
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET		0x0464
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET		0x0468
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET	0x046C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_0_X1		0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4		BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_2_X2		BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6		(BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4		BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW		BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_FAST		0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_HYS			BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PE			BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PD_100K		(0 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_5K			(1 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K		(2 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_100K		(3 << 5)
 
 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET	0x0470
 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET	0x0474
@@ -588,7 +623,15 @@
 #define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET		0x0708
 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET	0x070C
 #define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET		0x0710
+
 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET	0x0714
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SCL_ALT1	0x00
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SDA_ALT1	BIT(0)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_RX_DATA_ALT2	BIT(1)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_TX_BCLK_ALT2	(BIT(1) | BIT(0))
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO06_ALT3	BIT(2)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO07_ALT3	(BIT(2) | BIT(1))
+
 #define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET		0x0718
 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET	0x071C
 #define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET		0x0720