Merge "doc: Isolate security-related build options" into integration
diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S
index af93a0c..82b51a8 100644
--- a/bl2/bl2_el3.ld.S
+++ b/bl2/bl2_el3.ld.S
@@ -21,6 +21,9 @@
#endif
}
+#if !BL2_IN_XIP_MEM
+#define ROM RAM
+#endif
SECTIONS
{
@@ -45,11 +48,7 @@
*(.vectors)
. = ALIGN(PAGE_SIZE);
__TEXT_END__ = .;
-#if BL2_IN_XIP_MEM
} >ROM
-#else
- } >RAM
-#endif
.rodata . : {
__RODATA_START__ = .;
@@ -72,11 +71,7 @@
. = ALIGN(PAGE_SIZE);
__RODATA_END__ = .;
-#if BL2_IN_XIP_MEM
} >ROM
-#else
- } >RAM
-#endif
ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
"Resident part of BL2 has exceeded its limit.")
@@ -115,11 +110,7 @@
. = ALIGN(PAGE_SIZE);
__RO_END__ = .;
-#if BL2_IN_XIP_MEM
} >ROM
-#else
- } >RAM
-#endif
#endif
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
@@ -146,11 +137,7 @@
__DATA_RAM_START__ = .;
*(.data*)
__DATA_RAM_END__ = .;
-#if BL2_IN_XIP_MEM
} >RAM AT>ROM
-#else
- } >RAM
-#endif
stacks (NOLOAD) : {
__STACKS_START__ = .;
diff --git a/docs/maintainers.rst b/docs/maintainers.rst
index 5449faa..098fc5f 100644
--- a/docs/maintainers.rst
+++ b/docs/maintainers.rst
@@ -11,10 +11,16 @@
----------------
:M: Dan Handley <dan.handley@arm.com>
:G: `danh-arm`_
-:M: Dimitris Papastamos <dimitrs.papastamos@arm.com>
-:G: `dp-arm`_
:M: Soby Mathew <soby.mathew@arm.com>
:G: `soby-mathew`_
+:M: Sandrine Bailleux <sandrine.bailleux@arm.com>
+:G: `sandrine-bailleux-arm`_
+:M: Alexei Fedorov <alexei.fedorov@arm.com>
+:G: `AlexeiFedorov`_
+:M: Paul Beesley <paul.beesley@arm.com>
+:G: `pbeesley-arm`_
+:M: John Tsichritzis <john.tsichritzis@arm.com>
+:G: `jts-arm`_
Allwinner ARMv8 platform port
-----------------------------
@@ -260,28 +266,33 @@
:F: docs/plat/xilinx-zynqmp.rst
:F: plat/xilinx/
+.. _AlexeiFedorov: https://github.com/AlexeiFedorov
.. _Andre-ARM: https://github.com/Andre-ARM
.. _Anson-Huang: https://github.com/Anson-Huang
.. _bryanodonoghue: https://github.com/bryanodonoghue
.. _b49020: https://github.com/b49020
.. _danh-arm: https://github.com/danh-arm
-.. _dp-arm: https://github.com/dp-arm
.. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo
+.. _grandpaul: https://github.com/grandpaul
.. _hzhuang1: https://github.com/hzhuang1
.. _JackyBai: https://github.com/JackyBai
.. _jenswi-linaro: https://github.com/jenswi-linaro
+.. _jts-arm: https://github.com/jts-arm
+.. _jwerner-chromium: https://github.com/jwerner-chromium
+.. _kostapr: https://github.com/kostapr
.. _ldts: https://github.com/ldts
.. _marex: https://github.com/marex
-.. _niej: https://github.com/niej
-.. _kostapr: https://github.com/kostapr
.. _masahir0y: https://github.com/masahir0y
.. _mmind: https://github.com/mmind
.. _mtk09422: https://github.com/mtk09422
+.. _niej: https://github.com/niej
.. _npoushin: https://github.com/npoushin
+.. _pbeesley-arm: https://github.com/pbeesley-arm
.. _qoriq-open-source: https://github.com/qoriq-open-source
.. _remi-triplefault: https://github.com/repk
.. _rockchip-linux: https://github.com/rockchip-linux
+.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
.. _shawnguo2: https://github.com/shawnguo2
.. _sivadur: https://github.com/sivadur
.. _smaeul: https://github.com/smaeul
@@ -290,5 +301,3 @@
.. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar
.. _Yann-lms: https://github.com/Yann-lms
-.. _grandpaul: https://github.com/grandpaul
-.. _jwerner-chromium: https://github.com/jwerner-chromium
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index 7adc3c8..88251d6 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -83,9 +83,8 @@
make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb
cd <u-boot_directory>
- make stm32mp15_basic_defconfig
+ make stm32mp15_trusted_defconfig
make DEVICE_TREE=stm32mp157c-ev1 all
- ./tools/mkimage -T stm32image -a 0xC0100000 -e 0xC0100000 -d u-boot.bin u-boot.stm32
To build TF-A with with Op-TEE support:
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 01f8f29..a6538c4 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -31,7 +31,7 @@
#pragma weak plat_set_nv_ctr2
/* Pointer to CoT */
-extern const auth_img_desc_t **const cot_desc_ptr;
+extern const auth_img_desc_t *const *const cot_desc_ptr;
extern unsigned int auth_img_flags[MAX_NUMBER_IDS];
static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a,
diff --git a/drivers/renesas/rcar/console/rcar_console.S b/drivers/renesas/rcar/console/rcar_console.S
index e3c7363..859efec 100644
--- a/drivers/renesas/rcar/console/rcar_console.S
+++ b/drivers/renesas/rcar/console/rcar_console.S
@@ -1,81 +1,88 @@
/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
+#include <console_macros.S>
+#include <drivers/renesas/rcar/console/console.h>
- .globl console_init
- .globl console_putc
- .globl console_uninit
- .globl console_core_init
- .globl console_core_putc
- .globl console_core_getc
- .globl console_flush
+ .globl console_rcar_register
+ .globl console_rcar_init
+ .globl console_rcar_putc
+ .globl console_rcar_flush
.extern rcar_log_init
.extern rcar_set_log_data
/* -----------------------------------------------
- * int console_core_init(unsigned long base_addr,
- * unsigned int uart_clk, unsigned int baud_rate)
- * Function to initialize the log area. This
- * function will be accessed by console_init and
- * crash reporting.
- * Return 1 on SUCCESS, 0 on error
- * In: x0 - Not used
- * w1 - Not used
- * w2 - Not used
+ * int console_rcar_register(
+ * uintptr_t base, uint32_t clk, uint32_t baud,
+ * console_rcar_t *console)
+ * Function to initialize and register a new rcar
+ * console. Storage passed in for the console struct
+ * *must* be persistent (i.e. not from the stack).
+ * In: x0 - UART register base address
+ * w1 - UART clock in Hz
+ * w2 - Baud rate
+ * x3 - pointer to empty console_rcar_t struct
+ * Out: return 1 on success, 0 on error
+ * Clobber list : x0, x1, x2, x6, x7, x14
* -----------------------------------------------
*/
-func console_core_init
- b rcar_log_init
-endfunc console_core_init
-func console_init
- b console_core_init
-endfunc console_init
+func console_rcar_register
+ mov x7, x30
+ mov x6, x3
+ cbz x6, register_fail
+ str x0, [x6, #CONSOLE_T_RCAR_BASE]
- /* --------------------------------------------------------
- * int console_core_putc(int c, unsigned long base_addr)
- * Function to output a character over the log area.
- * Return 1 on SUCCESS, 0 on error
- * In : w0 - Not used
- * x1 - Not used
- * --------------------------------------------------------
- */
-func console_core_putc
- b rcar_set_log_data
-endfunc console_core_putc
-func console_putc
- b console_core_putc
-endfunc console_putc
+ bl rcar_log_init
+ cbz x0, register_fail
+
+ mov x0, x6
+ mov x30, x7
+ finish_console_register rcar, putc=1, getc=0, flush=1
+
+register_fail:
+ ret x7
+endfunc console_rcar_register
/* ---------------------------------------------
- * int console_core_getc(unsigned long base_addr)
- * Function to get a character from the console.
- * It returns the character grabbed on success
- * or -1 on error.
- * In : x0 - console base address
- * Clobber list : x0, x1
+ * int console_rcar_init(unsigned long base_addr,
+ * unsigned int uart_clk, unsigned int baud_rate)
+ * Function to initialize the console without a
+ * C Runtime to print debug information. This
+ * function will be accessed by crash reporting.
+ * In: x0 - console base address
+ * w1 - Uart clock in Hz
+ * w2 - Baud rate
+ * Out: return 1 on success
+ * Clobber list : x1, x2
* ---------------------------------------------
*/
-func console_core_getc
+func console_rcar_init
+ mov w0, #0
ret
-endfunc console_core_getc
+endfunc console_rcar_init
- /* -----------------------------------------------
- * void console_uninit(void)
- * Function to finish the use of console driver.
- * -----------------------------------------------
+ /* --------------------------------------------------------
+ * int console_rcar_putc(int c, console_rcar_t *console)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : w0 - character to be printed
+ * x1 - pointer to console_rcar_t structure
+ * Out : return -1 on error else return character.
+ * Clobber list : x2
+ * --------------------------------------------------------
*/
-func console_uninit
- ret
-endfunc console_uninit
+func console_rcar_putc
+ b rcar_set_log_data
+endfunc console_rcar_putc
/* ---------------------------------------------
- * int console_flush(void)
+ * int console_rcar_flush(void)
* Function to force a write of all buffered
* data that hasn't been output. It returns 0
* upon successful completion, otherwise it
@@ -83,7 +90,7 @@
* Clobber list : x0, x1
* ---------------------------------------------
*/
-func console_flush
+func console_rcar_flush
mov w0, #0
ret
-endfunc console_flush
+endfunc console_rcar_flush
diff --git a/drivers/renesas/rcar/qos/D3/qos_init_d3.c b/drivers/renesas/rcar/qos/D3/qos_init_d3.c
new file mode 100644
index 0000000..b96e822
--- /dev/null
+++ b/drivers/renesas/rcar/qos/D3/qos_init_d3.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_d3.h"
+
+#define RCAR_QOS_VERSION "rev.0.05"
+
+#include "qos_init_d3_mstat.h"
+
+struct rcar_gen3_dbsc_qos_settings d3_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF2, 0x000000F4 },
+ { DBSC_DBSCHCNT0, 0x000F0037 },
+ { DBSC_DBSCHSZ0, 0x00000001 },
+ { DBSC_DBSCHRW0, 0x22421111 },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123 },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00 },
+ { DBSC_DBSCHQOS01, 0x00000B00 },
+ { DBSC_DBSCHQOS02, 0x00000000 },
+ { DBSC_DBSCHQOS03, 0x00000000 },
+ { DBSC_DBSCHQOS40, 0x00000300 },
+ { DBSC_DBSCHQOS41, 0x000002F0 },
+ { DBSC_DBSCHQOS42, 0x00000200 },
+ { DBSC_DBSCHQOS43, 0x00000100 },
+ { DBSC_DBSCHQOS90, 0x00000300 },
+ { DBSC_DBSCHQOS91, 0x000002F0 },
+ { DBSC_DBSCHQOS92, 0x00000200 },
+ { DBSC_DBSCHQOS93, 0x00000100 },
+ { DBSC_DBSCHQOS130, 0x00000100 },
+ { DBSC_DBSCHQOS131, 0x000000F0 },
+ { DBSC_DBSCHQOS132, 0x000000A0 },
+ { DBSC_DBSCHQOS133, 0x00000040 },
+ { DBSC_DBSCHQOS140, 0x000000C0 },
+ { DBSC_DBSCHQOS141, 0x000000B0 },
+ { DBSC_DBSCHQOS142, 0x00000080 },
+ { DBSC_DBSCHQOS143, 0x00000040 },
+ { DBSC_DBSCHQOS150, 0x00000040 },
+ { DBSC_DBSCHQOS151, 0x00000030 },
+ { DBSC_DBSCHQOS152, 0x00000020 },
+ { DBSC_DBSCHQOS153, 0x00000010 },
+};
+
+void qos_init_d3(void)
+{
+ rcar_qos_dbsc_setting(d3_qos, ARRAY_SIZE(d3_qos), true);
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+ ERROR("DRAM Split 4ch not supported.(D3)");
+ panic();
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+ ERROR("DRAM Split 2ch not supported.(D3)");
+ panic();
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
+ ERROR("DRAM Split Auto not supported.(D3)");
+ panic();
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
+/* NOTICE("BL2: DRAM Split is OFF\n"); */
+ /* Split setting(DDR 1ch) */
+ io_write_32(AXI_ADSPLCR0, 0x00000000U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ ERROR("DRAM split is an invalid value.(D3)");
+ panic();
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+ /* Resource Alloc setting */
+ io_write_32(QOSCTRL_RAS, 0x00000020U);
+ io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+ io_write_32(QOSCTRL_REGGD, 0x00000000U);
+ io_write_64(QOSCTRL_DANN, 0x0404020002020201U);
+ io_write_32(QOSCTRL_DANT, 0x00100804U);
+ io_write_32(QOSCTRL_EC, 0x00000000U);
+ io_write_64(QOSCTRL_EMS, 0x0000000000000000U);
+ io_write_32(QOSCTRL_FSS, 0x0000000AU);
+ io_write_32(QOSCTRL_INSFC, 0xC7840001U);
+ io_write_32(QOSCTRL_BERR, 0x00000000U);
+ io_write_32(QOSCTRL_EARLYR, 0x00000000U);
+ io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+ io_write_32(QOSCTRL_STATGEN0, 0x00000000U);
+
+ /* GPU setting */
+ io_write_32(0xFD812030U, 0x00000000U);
+
+ /* QOSBW setting */
+ io_write_32(QOSCTRL_SL_INIT, 0x030500ACU);
+ io_write_32(QOSCTRL_REF_ARS, 0x00780000U);
+
+ /* QOSBW SRAM setting */
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+
+ /* 3DG bus Leaf setting */
+ io_write_32(GPU_ACT_GRD, 0x00001234U);
+ io_write_32(GPU_ACT0, 0x00000000U);
+ io_write_32(GPU_ACT1, 0x00000000U);
+ io_write_32(GPU_ACT2, 0x00000000U);
+ io_write_32(GPU_ACT3, 0x00000000U);
+
+ /* RT bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* Resource Alloc start */
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+ /* QOSBW start */
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ /* Resource Alloc setting */
+ io_write_32(QOSCTRL_EC, 0x00000000U);
+ /* Resource Alloc start */
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h b/drivers/renesas/rcar/qos/D3/qos_init_d3.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h
rename to drivers/renesas/rcar/qos/D3/qos_init_d3.h
diff --git a/drivers/renesas/rcar/qos/D3/qos_init_d3_mstat.h b/drivers/renesas/rcar/qos/D3/qos_init_d3_mstat.h
new file mode 100644
index 0000000..cbf1f65
--- /dev/null
+++ b/drivers/renesas/rcar/qos/D3/qos_init_d3_mstat.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+static const uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001004340000FFFFUL,
+ /* 0x0038, */ 0x001004140000FFFFUL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x00140B030000FFFFUL,
+ /* 0x0060, */ 0x001408610000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x001410620000FFFFUL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00A0, */ 0x000C041C0000FFFFUL,
+ /* 0x00A8, */ 0x000C04090000FFFFUL,
+ /* 0x00B0, */ 0x000C04110000FFFFUL,
+ /* 0x00B8, */ 0x0000000000000000UL,
+ /* 0x00C0, */ 0x000C041C0000FFFFUL,
+ /* 0x00C8, */ 0x000C04090000FFFFUL,
+ /* 0x00D0, */ 0x000C04110000FFFFUL,
+ /* 0x00D8, */ 0x0000000000000000UL,
+ /* 0x00E0, */ 0x0000000000000000UL,
+ /* 0x00E8, */ 0x0000000000000000UL,
+ /* 0x00F0, */ 0x001018570000FFFFUL,
+ /* 0x00F8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x001008570000FFFFUL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x001008520000FFFFUL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x00100CA30000FFFFUL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01A0, */ 0x0000000000000000UL,
+ /* 0x01A8, */ 0x0000000000000000UL,
+ /* 0x01B0, */ 0x0000000000000000UL,
+ /* 0x01B8, */ 0x0000000000000000UL,
+ /* 0x01C0, */ 0x0000000000000000UL,
+ /* 0x01C8, */ 0x0000000000000000UL,
+ /* 0x01D0, */ 0x0000000000000000UL,
+ /* 0x01D8, */ 0x0000000000000000UL,
+ /* 0x01E0, */ 0x0000000000000000UL,
+ /* 0x01E8, */ 0x000C04020000FFFFUL,
+ /* 0x01F0, */ 0x0000000000000000UL,
+ /* 0x01F8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x000C04090000FFFFUL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x001410040000FFFFUL,
+ /* 0x0270, */ 0x001404020000FFFFUL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001410040000FFFFUL,
+ /* 0x0298, */ 0x001404020000FFFFUL,
+ /* 0x02A0, */ 0x000C04050000FFFFUL,
+ /* 0x02A8, */ 0x000C04050000FFFFUL,
+ /* 0x02B0, */ 0x0000000000000000UL,
+ /* 0x02B8, */ 0x0000000000000000UL,
+ /* 0x02C0, */ 0x0000000000000000UL,
+ /* 0x02C8, */ 0x0000000000000000UL,
+ /* 0x02D0, */ 0x000C04050000FFFFUL,
+ /* 0x02D8, */ 0x000C04050000FFFFUL,
+ /* 0x02E0, */ 0x0000000000000000UL,
+ /* 0x02E8, */ 0x0000000000000000UL,
+ /* 0x02F0, */ 0x0000000000000000UL,
+ /* 0x02F8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x000C04020000FFFFUL,
+ /* 0x0378, */ 0x000C04020000FFFFUL,
+ /* 0x0380, */ 0x000C04090000FFFFUL,
+ /* 0x0388, */ 0x000C04090000FFFFUL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+
+static const uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00A0, */ 0x0000000000000000UL,
+ /* 0x00A8, */ 0x0000000000000000UL,
+ /* 0x00B0, */ 0x0000000000000000UL,
+ /* 0x00B8, */ 0x0000000000000000UL,
+ /* 0x00C0, */ 0x0000000000000000UL,
+ /* 0x00C8, */ 0x0000000000000000UL,
+ /* 0x00D0, */ 0x0000000000000000UL,
+ /* 0x00D8, */ 0x0000000000000000UL,
+ /* 0x00E0, */ 0x0000000000000000UL,
+ /* 0x00E8, */ 0x0000000000000000UL,
+ /* 0x00F0, */ 0x0000000000000000UL,
+ /* 0x00F8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01A0, */ 0x0000000000000000UL,
+ /* 0x01A8, */ 0x0000000000000000UL,
+ /* 0x01B0, */ 0x0000000000000000UL,
+ /* 0x01B8, */ 0x0000000000000000UL,
+ /* 0x01C0, */ 0x00110090060FA001UL,
+ /* 0x01C8, */ 0x00110090060FA001UL,
+ /* 0x01D0, */ 0x0000000000000000UL,
+ /* 0x01D8, */ 0x0000000000000000UL,
+ /* 0x01E0, */ 0x0000000000000000UL,
+ /* 0x01E8, */ 0x0000000000000000UL,
+ /* 0x01F0, */ 0x0011001006004401UL,
+ /* 0x01F8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0011001006004401UL,
+ /* 0x0218, */ 0x0011001006009801UL,
+ /* 0x0220, */ 0x0011001006009801UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0011001006009801UL,
+ /* 0x0238, */ 0x0011001006009801UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02A0, */ 0x0000000000000000UL,
+ /* 0x02A8, */ 0x0000000000000000UL,
+ /* 0x02B0, */ 0x0000000000000000UL,
+ /* 0x02B8, */ 0x0011001006003401UL,
+ /* 0x02C0, */ 0x0000000000000000UL,
+ /* 0x02C8, */ 0x0000000000000000UL,
+ /* 0x02D0, */ 0x0000000000000000UL,
+ /* 0x02D8, */ 0x0000000000000000UL,
+ /* 0x02E0, */ 0x0000000000000000UL,
+ /* 0x02E8, */ 0x0011001006003401UL,
+ /* 0x02F0, */ 0x00110090060FA001UL,
+ /* 0x02F8, */ 0x00110090060FA001UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0012001006003401UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x00120090060FA001UL,
+ /* 0x0360, */ 0x00120090060FA001UL,
+ /* 0x0368, */ 0x0012001006003401UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x0012001006003401UL,
+};
+#endif
+
diff --git a/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c b/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
new file mode 100644
index 0000000..6f4c66c
--- /dev/null
+++ b/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_e3_v10.h"
+
+#define RCAR_QOS_VERSION "rev.0.05"
+
+#define REF_ARS_ARBSTOPCYCLE_E3 (((SL_INIT_SSLOTCLK_E3) - 5U) << 16U)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_e3_v10_mstat390.h"
+#else
+#include "qos_init_e3_v10_mstat780.h"
+#endif
+
+#endif
+
+struct rcar_gen3_dbsc_qos_settings e3_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF2, 0x000000F4 },
+ { DBSC_DBSCHCNT0, 0x000F0037 },
+ { DBSC_DBSCHSZ0, 0x00000001 },
+ { DBSC_DBSCHRW0, 0x22421111 },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123 },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00 },
+ { DBSC_DBSCHQOS01, 0x00000B00 },
+ { DBSC_DBSCHQOS02, 0x00000000 },
+ { DBSC_DBSCHQOS03, 0x00000000 },
+ { DBSC_DBSCHQOS40, 0x00000300 },
+ { DBSC_DBSCHQOS41, 0x000002F0 },
+ { DBSC_DBSCHQOS42, 0x00000200 },
+ { DBSC_DBSCHQOS43, 0x00000100 },
+ { DBSC_DBSCHQOS90, 0x00000100 },
+ { DBSC_DBSCHQOS91, 0x000000F0 },
+ { DBSC_DBSCHQOS92, 0x000000A0 },
+ { DBSC_DBSCHQOS93, 0x00000040 },
+ { DBSC_DBSCHQOS130, 0x00000100 },
+ { DBSC_DBSCHQOS131, 0x000000F0 },
+ { DBSC_DBSCHQOS132, 0x000000A0 },
+ { DBSC_DBSCHQOS133, 0x00000040 },
+ { DBSC_DBSCHQOS140, 0x000000C0 },
+ { DBSC_DBSCHQOS141, 0x000000B0 },
+ { DBSC_DBSCHQOS142, 0x00000080 },
+ { DBSC_DBSCHQOS143, 0x00000040 },
+ { DBSC_DBSCHQOS150, 0x00000040 },
+ { DBSC_DBSCHQOS151, 0x00000030 },
+ { DBSC_DBSCHQOS152, 0x00000020 },
+ { DBSC_DBSCHQOS153, 0x00000010 },
+};
+
+void qos_init_e3_v10(void)
+{
+ rcar_qos_dbsc_setting(e3_qos, ARRAY_SIZE(e3_qos), true);
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_E3
+#error "Don't set DRAM Split 4ch(E3)"
+#else
+ ERROR("DRAM Split 4ch not supported.(E3)");
+ panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RCAR_E3
+#error "Don't set DRAM Split 2ch(E3)"
+#else
+ ERROR("DRAM Split 2ch not supported.(E3)");
+ panic();
+#endif
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 7.8 usec\n");
+#endif
+
+ io_write_32(QOSCTRL_RAS, 0x00000020U);
+ io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+ io_write_32(QOSCTRL_DANT, 0x00100804U);
+ io_write_32(QOSCTRL_FSS, 0x0000000AU);
+ io_write_32(QOSCTRL_INSFC, 0x06330001U);
+ io_write_32(QOSCTRL_EARLYR, 0x00000000U);
+ io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+ SL_INIT_SSLOTCLK_E3);
+ io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_E3);
+
+ /* QOSBW SRAM setting */
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+
+ /* RT bus Leaf setting */
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif
+}
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.h b/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.h
rename to drivers/renesas/rcar/qos/E3/qos_init_e3_v10.h
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h b/drivers/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
rename to drivers/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h b/drivers/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
rename to drivers/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c b/drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
new file mode 100644
index 0000000..1fb43a7
--- /dev/null
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_h3_v10.h"
+
+#define RCAR_QOS_VERSION "rev.0.36"
+
+#include "qos_init_h3_v10_mstat.h"
+
+void qos_init_h3_v10(void)
+{
+ /* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 4ch\n");
+ io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1BU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR1, 0x00000000U);
+ io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+ NOTICE("BL2: DRAM Split is 2ch\n");
+ io_write_32(AXI_ADSPLCR0, 0x00000000U);
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1BU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x00000000U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+ /* AR Cache setting */
+ io_write_32(0xE67D1000U, 0x00000100U);
+ io_write_32(0xE67D1008U, 0x00000100U);
+
+ /* Resource Alloc setting */
+ io_write_32(QOSCTRL_RAS, 0x00000040U);
+ io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
+ io_write_32(QOSCTRL_REGGD, 0x00000004U);
+ io_write_64(QOSCTRL_DANN, 0x0202000004040404UL);
+ io_write_32(QOSCTRL_DANT, 0x003C1110U);
+ io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
+ io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
+ io_write_32(QOSCTRL_INSFC, 0xC7840001U);
+ io_write_32(QOSCTRL_BERR, 0x00000000U);
+
+ /* QOSBW setting */
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
+ io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
+
+ /* QOSBW SRAM setting */
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+
+ /* 3DG bus Leaf setting */
+ io_write_32(0xFD820808U, 0x00001234U);
+ io_write_32(0xFD820800U, 0x0000003FU);
+ io_write_32(0xFD821800U, 0x0000003FU);
+ io_write_32(0xFD822800U, 0x0000003FU);
+ io_write_32(0xFD823800U, 0x0000003FU);
+ io_write_32(0xFD824800U, 0x0000003FU);
+ io_write_32(0xFD825800U, 0x0000003FU);
+ io_write_32(0xFD826800U, 0x0000003FU);
+ io_write_32(0xFD827800U, 0x0000003FU);
+
+ /* Resource Alloc start */
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+ /* QOSBW start */
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ /* Resource Alloc setting */
+ io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v10.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v10.h
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v10_mstat.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v10_mstat.h
new file mode 100644
index 0000000..fe63236
--- /dev/null
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v10_mstat.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+static const uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x00140C050000FFFFUL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x001404030000FFFFUL,
+ /* 0x0060, */ 0x001408060000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x00140C050000FFFFUL,
+ /* 0x0090, */ 0x001408060000FFFFUL,
+ /* 0x0098, */ 0x001404020000FFFFUL,
+ /* 0x00A0, */ 0x0000000000000000UL,
+ /* 0x00A8, */ 0x0000000000000000UL,
+ /* 0x00B0, */ 0x0000000000000000UL,
+ /* 0x00B8, */ 0x0000000000000000UL,
+ /* 0x00C0, */ 0x0000000000000000UL,
+ /* 0x00C8, */ 0x0000000000000000UL,
+ /* 0x00D0, */ 0x0000000000000000UL,
+ /* 0x00D8, */ 0x0000000000000000UL,
+ /* 0x00E0, */ 0x0000000000000000UL,
+ /* 0x00E8, */ 0x0000000000000000UL,
+ /* 0x00F0, */ 0x0000000000000000UL,
+ /* 0x00F8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x001004020000FFFFUL,
+ /* 0x0140, */ 0x001004020000FFFFUL,
+ /* 0x0148, */ 0x001004020000FFFFUL,
+ /* 0x0150, */ 0x001008050000FFFFUL,
+ /* 0x0158, */ 0x001008050000FFFFUL,
+ /* 0x0160, */ 0x001008050000FFFFUL,
+ /* 0x0168, */ 0x001008050000FFFFUL,
+ /* 0x0170, */ 0x001008050000FFFFUL,
+ /* 0x0178, */ 0x001004030000FFFFUL,
+ /* 0x0180, */ 0x001004030000FFFFUL,
+ /* 0x0188, */ 0x001004030000FFFFUL,
+ /* 0x0190, */ 0x001014140000FFFFUL,
+ /* 0x0198, */ 0x001014140000FFFFUL,
+ /* 0x01A0, */ 0x001008060000FFFFUL,
+ /* 0x01A8, */ 0x001008060000FFFFUL,
+ /* 0x01B0, */ 0x001008060000FFFFUL,
+ /* 0x01B8, */ 0x0000000000000000UL,
+ /* 0x01C0, */ 0x0000000000000000UL,
+ /* 0x01C8, */ 0x0000000000000000UL,
+ /* 0x01D0, */ 0x0000000000000000UL,
+ /* 0x01D8, */ 0x0000000000000000UL,
+ /* 0x01E0, */ 0x0000000000000000UL,
+ /* 0x01E8, */ 0x0000000000000000UL,
+ /* 0x01F0, */ 0x0000000000000000UL,
+ /* 0x01F8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02A0, */ 0x0000000000000000UL,
+ /* 0x02A8, */ 0x0000000000000000UL,
+ /* 0x02B0, */ 0x0000000000000000UL,
+ /* 0x02B8, */ 0x0000000000000000UL,
+ /* 0x02C0, */ 0x0000000000000000UL,
+ /* 0x02C8, */ 0x0000000000000000UL,
+ /* 0x02D0, */ 0x0000000000000000UL,
+ /* 0x02D8, */ 0x0000000000000000UL,
+ /* 0x02E0, */ 0x0000000000000000UL,
+ /* 0x02E8, */ 0x0000000000000000UL,
+ /* 0x02F0, */ 0x0000000000000000UL,
+ /* 0x02F8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+};
+
+static const uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x001000100C8FFC01UL,
+ /* 0x0008, */ 0x001000100C8FFC01UL,
+ /* 0x0010, */ 0x001000100C8FFC01UL,
+ /* 0x0018, */ 0x001000100C8FFC01UL,
+ /* 0x0020, */ 0x001000100C8FFC01UL,
+ /* 0x0028, */ 0x001000100C8FFC01UL,
+ /* 0x0030, */ 0x001000100C8FFC01UL,
+ /* 0x0038, */ 0x001000100C8FFC01UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x001000100C8FFC01UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x001000100C8FFC01UL,
+ /* 0x0070, */ 0x001000100C8FFC01UL,
+ /* 0x0078, */ 0x001000100C8FFC01UL,
+ /* 0x0080, */ 0x001000100C8FFC01UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00A0, */ 0x001000100C8FFC01UL,
+ /* 0x00A8, */ 0x001000100C8FFC01UL,
+ /* 0x00B0, */ 0x001000100C8FFC01UL,
+ /* 0x00B8, */ 0x001000100C8FFC01UL,
+ /* 0x00C0, */ 0x001000100C8FFC01UL,
+ /* 0x00C8, */ 0x001000100C8FFC01UL,
+ /* 0x00D0, */ 0x001000100C8FFC01UL,
+ /* 0x00D8, */ 0x002000200C8FFC01UL,
+ /* 0x00E0, */ 0x002000200C8FFC01UL,
+ /* 0x00E8, */ 0x001000100C8FFC01UL,
+ /* 0x00F0, */ 0x001000100C8FFC01UL,
+ /* 0x00F8, */ 0x001000100C8FFC01UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x002000200C8FFC01UL,
+ /* 0x0110, */ 0x001000100C8FFC01UL,
+ /* 0x0118, */ 0x001000100C8FFC01UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x002000200C8FFC01UL,
+ /* 0x0130, */ 0x001000100C8FFC01UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01A0, */ 0x0000000000000000UL,
+ /* 0x01A8, */ 0x0000000000000000UL,
+ /* 0x01B0, */ 0x0000000000000000UL,
+ /* 0x01B8, */ 0x001000100C8FFC01UL,
+ /* 0x01C0, */ 0x001000200C8FFC01UL,
+ /* 0x01C8, */ 0x001000200C8FFC01UL,
+ /* 0x01D0, */ 0x001000200C8FFC01UL,
+ /* 0x01D8, */ 0x001000200C8FFC01UL,
+ /* 0x01E0, */ 0x001000100C8FFC01UL,
+ /* 0x01E8, */ 0x001000100C8FFC01UL,
+ /* 0x01F0, */ 0x001000100C8FFC01UL,
+ /* 0x01F8, */ 0x001000100C8FFC01UL,
+ /* 0x0200, */ 0x001000100C8FFC01UL,
+ /* 0x0208, */ 0x001000100C8FFC01UL,
+ /* 0x0210, */ 0x001000100C8FFC01UL,
+ /* 0x0218, */ 0x001000100C8FFC01UL,
+ /* 0x0220, */ 0x001000100C8FFC01UL,
+ /* 0x0228, */ 0x001000100C8FFC01UL,
+ /* 0x0230, */ 0x001000100C8FFC01UL,
+ /* 0x0238, */ 0x001000100C8FFC01UL,
+ /* 0x0240, */ 0x001000100C8FFC01UL,
+ /* 0x0248, */ 0x001000100C8FFC01UL,
+ /* 0x0250, */ 0x001000100C8FFC01UL,
+ /* 0x0258, */ 0x001000100C8FFC01UL,
+ /* 0x0260, */ 0x001000100C8FFC01UL,
+ /* 0x0268, */ 0x001000100C8FFC01UL,
+ /* 0x0270, */ 0x001000100C8FFC01UL,
+ /* 0x0278, */ 0x001000100C8FFC01UL,
+ /* 0x0280, */ 0x001000100C8FFC01UL,
+ /* 0x0288, */ 0x001000100C8FFC01UL,
+ /* 0x0290, */ 0x001000100C8FFC01UL,
+ /* 0x0298, */ 0x001000100C8FFC01UL,
+ /* 0x02A0, */ 0x001000100C8FFC01UL,
+ /* 0x02A8, */ 0x001000100C8FFC01UL,
+ /* 0x02B0, */ 0x001000100C8FFC01UL,
+ /* 0x02B8, */ 0x001000100C8FFC01UL,
+ /* 0x02C0, */ 0x001000100C8FFC01UL,
+ /* 0x02C8, */ 0x001000100C8FFC01UL,
+ /* 0x02D0, */ 0x001000100C8FFC01UL,
+ /* 0x02D8, */ 0x001000100C8FFC01UL,
+ /* 0x02E0, */ 0x001000100C8FFC01UL,
+ /* 0x02E8, */ 0x001000100C8FFC01UL,
+ /* 0x02F0, */ 0x001000200C8FFC01UL,
+ /* 0x02F8, */ 0x001000300C8FFC01UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x001000200C8FFC01UL,
+ /* 0x0310, */ 0x001000300C8FFC01UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x001000200C8FFC01UL,
+ /* 0x0328, */ 0x001000300C8FFC01UL,
+ /* 0x0330, */ 0x001000200C8FFC01UL,
+ /* 0x0338, */ 0x001000300C8FFC01UL,
+};
+#endif
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c b/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
new file mode 100644
index 0000000..329bcb8
--- /dev/null
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include <rcar_def.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_h3_v11.h"
+
+#define RCAR_QOS_VERSION "rev.0.37"
+
+#include "qos_init_h3_v11_mstat.h"
+
+struct rcar_gen3_dbsc_qos_settings h3_v11_qos[] = {
+ /* BUFCAM settings */
+ /* DBSC_DBCAM0CNF0 not set */
+ { DBSC_DBCAM0CNF1, 0x00044218 },
+ { DBSC_DBCAM0CNF2, 0x000000F4 },
+ /* DBSC_DBCAM0CNF3 not set */
+ { DBSC_DBSCHCNT0, 0x080F0037 },
+ { DBSC_DBSCHCNT1, 0x00001010 },
+ { DBSC_DBSCHSZ0, 0x00000001 },
+ { DBSC_DBSCHRW0, 0x22421111 },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123 },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x0000F000 },
+ { DBSC_DBSCHQOS01, 0x0000E000 },
+ { DBSC_DBSCHQOS02, 0x00007000 },
+ { DBSC_DBSCHQOS03, 0x00000000 },
+ { DBSC_DBSCHQOS40, 0x00000E00 },
+ { DBSC_DBSCHQOS41, 0x00000DFF },
+ { DBSC_DBSCHQOS42, 0x00000400 },
+ { DBSC_DBSCHQOS43, 0x00000200 },
+ { DBSC_DBSCHQOS90, 0x00000C00 },
+ { DBSC_DBSCHQOS91, 0x00000BFF },
+ { DBSC_DBSCHQOS92, 0x00000400 },
+ { DBSC_DBSCHQOS93, 0x00000200 },
+ { DBSC_DBSCHQOS130, 0x00000980 },
+ { DBSC_DBSCHQOS131, 0x0000097F },
+ { DBSC_DBSCHQOS132, 0x00000300 },
+ { DBSC_DBSCHQOS133, 0x00000180 },
+ { DBSC_DBSCHQOS140, 0x00000800 },
+ { DBSC_DBSCHQOS141, 0x000007FF },
+ { DBSC_DBSCHQOS142, 0x00000300 },
+ { DBSC_DBSCHQOS143, 0x00000180 },
+ { DBSC_DBSCHQOS150, 0x000007D0 },
+ { DBSC_DBSCHQOS151, 0x000007CF },
+ { DBSC_DBSCHQOS152, 0x000005D0 },
+ { DBSC_DBSCHQOS153, 0x000003D0 },
+};
+
+void qos_init_h3_v11(void)
+{
+ rcar_qos_dbsc_setting(h3_v11_qos, ARRAY_SIZE(h3_v11_qos), false);
+
+ /* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 4ch\n");
+ io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1BU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR1, 0x00000000U);
+ io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+ NOTICE("BL2: DRAM Split is 2ch\n");
+ io_write_32(AXI_ADSPLCR0, 0x00000000U);
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1BU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x00000000U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+ /* AR Cache setting */
+ io_write_32(0xE67D1000U, 0x00000100U);
+ io_write_32(0xE67D1008U, 0x00000100U);
+
+ /* Resource Alloc setting */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+ io_write_32(QOSCTRL_RAS, 0x00000020U);
+#else
+ io_write_32(QOSCTRL_RAS, 0x00000040U);
+#endif
+ io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
+ io_write_32(QOSCTRL_REGGD, 0x00000000U);
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+ io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
+ io_write_32(QOSCTRL_DANT, 0x00181008U);
+#else
+ io_write_64(QOSCTRL_DANN, 0x0101000004040401UL);
+ io_write_32(QOSCTRL_DANT, 0x003C2010U);
+#endif
+ io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
+ io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
+ io_write_32(QOSCTRL_INSFC, 0xC7840001U);
+ io_write_32(QOSCTRL_BERR, 0x00000000U);
+ io_write_32(QOSCTRL_RACNT0, 0x00000000U);
+
+ /* QOSBW setting */
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
+ io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
+
+ /* QOSBW SRAM setting */
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+
+ /* 3DG bus Leaf setting */
+ io_write_32(0xFD820808U, 0x00001234U);
+ io_write_32(0xFD820800U, 0x0000003FU);
+ io_write_32(0xFD821800U, 0x0000003FU);
+ io_write_32(0xFD822800U, 0x0000003FU);
+ io_write_32(0xFD823800U, 0x0000003FU);
+ io_write_32(0xFD824800U, 0x0000003FU);
+ io_write_32(0xFD825800U, 0x0000003FU);
+ io_write_32(0xFD826800U, 0x0000003FU);
+ io_write_32(0xFD827800U, 0x0000003FU);
+
+ /* VIO bus Leaf setting */
+ io_write_32(0xFEB89800, 0x00000001U);
+ io_write_32(0xFEB8A800, 0x00000001U);
+ io_write_32(0xFEB8B800, 0x00000001U);
+ io_write_32(0xFEB8C800, 0x00000001U);
+
+ /* HSC bus Leaf setting */
+ io_write_32(0xE6430800, 0x00000001U);
+ io_write_32(0xE6431800, 0x00000001U);
+ io_write_32(0xE6432800, 0x00000001U);
+ io_write_32(0xE6433800, 0x00000001U);
+
+ /* MP bus Leaf setting */
+ io_write_32(0xEC620800, 0x00000001U);
+ io_write_32(0xEC621800, 0x00000001U);
+
+ /* PERIE bus Leaf setting */
+ io_write_32(0xE7760800, 0x00000001U);
+ io_write_32(0xE7768800, 0x00000001U);
+
+ /* PERIW bus Leaf setting */
+ io_write_32(0xE6760800, 0x00000001U);
+ io_write_32(0xE6768800, 0x00000001U);
+
+ /* RT bus Leaf setting */
+ io_write_32(0xFFC50800, 0x00000001U);
+ io_write_32(0xFFC51800, 0x00000001U);
+
+ /* CCI bus Leaf setting */
+ uint32_t modemr = io_read_32(RCAR_MODEMR);
+
+ modemr &= MODEMR_BOOT_CPU_MASK;
+
+ if ((modemr == MODEMR_BOOT_CPU_CA57) ||
+ (modemr == MODEMR_BOOT_CPU_CA53)) {
+ io_write_32(0xF1300800, 0x00000001U);
+ io_write_32(0xF1340800, 0x00000001U);
+ io_write_32(0xF1380800, 0x00000001U);
+ io_write_32(0xF13C0800, 0x00000001U);
+ }
+
+ /* Resource Alloc start */
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+ /* QOSBW start */
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ /* Resource Alloc setting */
+ io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v11.h
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v11_mstat.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v11_mstat.h
new file mode 100644
index 0000000..46c68c8
--- /dev/null
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v11_mstat.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+static const uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001004030000FFFFUL,
+ /* 0x0038, */ 0x001008060000FFFFUL,
+ /* 0x0040, */ 0x001414090000FFFFUL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x001410010000FFFFUL,
+ /* 0x0058, */ 0x00140C0C0000FFFFUL,
+ /* 0x0060, */ 0x00140C0C0000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x001410010000FFFFUL,
+ /* 0x0078, */ 0x001008060000FFFFUL,
+ /* 0x0080, */ 0x001004020000FFFFUL,
+ /* 0x0088, */ 0x001414090000FFFFUL,
+ /* 0x0090, */ 0x00140C0C0000FFFFUL,
+ /* 0x0098, */ 0x001408080000FFFFUL,
+ /* 0x00A0, */ 0x000C08020000FFFFUL,
+ /* 0x00A8, */ 0x000C04010000FFFFUL,
+ /* 0x00B0, */ 0x000C04010000FFFFUL,
+ /* 0x00B8, */ 0x0000000000000000UL,
+ /* 0x00C0, */ 0x000C08020000FFFFUL,
+ /* 0x00C8, */ 0x000C04010000FFFFUL,
+ /* 0x00D0, */ 0x000C04010000FFFFUL,
+ /* 0x00D8, */ 0x000C04030000FFFFUL,
+ /* 0x00E0, */ 0x000C100F0000FFFFUL,
+ /* 0x00E8, */ 0x0000000000000000UL,
+ /* 0x00F0, */ 0x001010080000FFFFUL,
+ /* 0x00F8, */ 0x001010080000FFFFUL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x000C04030000FFFFUL,
+ /* 0x0110, */ 0x001010080000FFFFUL,
+ /* 0x0118, */ 0x001010080000FFFFUL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x000C100E0000FFFFUL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x001008050000FFFFUL,
+ /* 0x0140, */ 0x001008050000FFFFUL,
+ /* 0x0148, */ 0x001008050000FFFFUL,
+ /* 0x0150, */ 0x001008050000FFFFUL,
+ /* 0x0158, */ 0x001008050000FFFFUL,
+ /* 0x0160, */ 0x001008050000FFFFUL,
+ /* 0x0168, */ 0x001008050000FFFFUL,
+ /* 0x0170, */ 0x001008050000FFFFUL,
+ /* 0x0178, */ 0x001004030000FFFFUL,
+ /* 0x0180, */ 0x001004030000FFFFUL,
+ /* 0x0188, */ 0x001004030000FFFFUL,
+ /* 0x0190, */ 0x001014140000FFFFUL,
+ /* 0x0198, */ 0x001014140000FFFFUL,
+ /* 0x01A0, */ 0x001008050000FFFFUL,
+ /* 0x01A8, */ 0x001008050000FFFFUL,
+ /* 0x01B0, */ 0x001008050000FFFFUL,
+ /* 0x01B8, */ 0x0000000000000000UL,
+ /* 0x01C0, */ 0x0000000000000000UL,
+ /* 0x01C8, */ 0x0000000000000000UL,
+ /* 0x01D0, */ 0x0000000000000000UL,
+ /* 0x01D8, */ 0x0000000000000000UL,
+ /* 0x01E0, */ 0x0000000000000000UL,
+ /* 0x01E8, */ 0x0000000000000000UL,
+ /* 0x01F0, */ 0x0000000000000000UL,
+ /* 0x01F8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x001408010000FFFFUL,
+ /* 0x0270, */ 0x001404010000FFFFUL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001408010000FFFFUL,
+ /* 0x0298, */ 0x001404010000FFFFUL,
+ /* 0x02A0, */ 0x000C04010000FFFFUL,
+ /* 0x02A8, */ 0x000C04010000FFFFUL,
+ /* 0x02B0, */ 0x001404010000FFFFUL,
+ /* 0x02B8, */ 0x0000000000000000UL,
+ /* 0x02C0, */ 0x0000000000000000UL,
+ /* 0x02C8, */ 0x0000000000000000UL,
+ /* 0x02D0, */ 0x000C04010000FFFFUL,
+ /* 0x02D8, */ 0x000C04010000FFFFUL,
+ /* 0x02E0, */ 0x001404010000FFFFUL,
+ /* 0x02E8, */ 0x0000000000000000UL,
+ /* 0x02F0, */ 0x0000000000000000UL,
+ /* 0x02F8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+};
+
+static const uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x001200100C89C401UL,
+ /* 0x0008, */ 0x001200100C89C401UL,
+ /* 0x0010, */ 0x001200100C89C401UL,
+ /* 0x0018, */ 0x001200100C89C401UL,
+ /* 0x0020, */ 0x001100100C803401UL,
+ /* 0x0028, */ 0x001100100C80FC01UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x001100100C803401UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00A0, */ 0x0000000000000000UL,
+ /* 0x00A8, */ 0x0000000000000000UL,
+ /* 0x00B0, */ 0x0000000000000000UL,
+ /* 0x00B8, */ 0x001100100C803401UL,
+ /* 0x00C0, */ 0x0000000000000000UL,
+ /* 0x00C8, */ 0x0000000000000000UL,
+ /* 0x00D0, */ 0x0000000000000000UL,
+ /* 0x00D8, */ 0x0000000000000000UL,
+ /* 0x00E0, */ 0x0000000000000000UL,
+ /* 0x00E8, */ 0x001100100C803401UL,
+ /* 0x00F0, */ 0x0000000000000000UL,
+ /* 0x00F8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x001100100C803401UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01A0, */ 0x0000000000000000UL,
+ /* 0x01A8, */ 0x0000000000000000UL,
+ /* 0x01B0, */ 0x0000000000000000UL,
+ /* 0x01B8, */ 0x001100100C803401UL,
+ /* 0x01C0, */ 0x001100800C8FFC01UL,
+ /* 0x01C8, */ 0x001100800C8FFC01UL,
+ /* 0x01D0, */ 0x001100800C8FFC01UL,
+ /* 0x01D8, */ 0x001100800C8FFC01UL,
+ /* 0x01E0, */ 0x001100100C80FC01UL,
+ /* 0x01E8, */ 0x001200100C80FC01UL,
+ /* 0x01F0, */ 0x001100100C80FC01UL,
+ /* 0x01F8, */ 0x001100100C803401UL,
+ /* 0x0200, */ 0x001100100C80FC01UL,
+ /* 0x0208, */ 0x001200100C80FC01UL,
+ /* 0x0210, */ 0x001100100C80FC01UL,
+ /* 0x0218, */ 0x001100100C825801UL,
+ /* 0x0220, */ 0x001100100C825801UL,
+ /* 0x0228, */ 0x001100100C803401UL,
+ /* 0x0230, */ 0x001100100C825801UL,
+ /* 0x0238, */ 0x001100100C825801UL,
+ /* 0x0240, */ 0x001200100C8BB801UL,
+ /* 0x0248, */ 0x001100200C8FFC01UL,
+ /* 0x0250, */ 0x001200100C8BB801UL,
+ /* 0x0258, */ 0x001100200C8FFC01UL,
+ /* 0x0260, */ 0x001100100C84E401UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x001100100C81F401UL,
+ /* 0x0280, */ 0x001100100C803401UL,
+ /* 0x0288, */ 0x001100100C803401UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02A0, */ 0x0000000000000000UL,
+ /* 0x02A8, */ 0x0000000000000000UL,
+ /* 0x02B0, */ 0x0000000000000000UL,
+ /* 0x02B8, */ 0x001100100C803401UL,
+ /* 0x02C0, */ 0x001100100C803401UL,
+ /* 0x02C8, */ 0x001100100C803401UL,
+ /* 0x02D0, */ 0x0000000000000000UL,
+ /* 0x02D8, */ 0x0000000000000000UL,
+ /* 0x02E0, */ 0x0000000000000000UL,
+ /* 0x02E8, */ 0x001100100C803401UL,
+ /* 0x02F0, */ 0x001100300C8FFC01UL,
+ /* 0x02F8, */ 0x001100500C8FFC01UL,
+ /* 0x0300, */ 0x001100100C803401UL,
+ /* 0x0308, */ 0x001100300C8FFC01UL,
+ /* 0x0310, */ 0x001100500C8FFC01UL,
+ /* 0x0318, */ 0x001200100C803401UL,
+ /* 0x0320, */ 0x001100300C8FFC01UL,
+ /* 0x0328, */ 0x001100500C8FFC01UL,
+ /* 0x0330, */ 0x001100300C8FFC01UL,
+ /* 0x0338, */ 0x001100500C8FFC01UL,
+};
+#endif
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
new file mode 100644
index 0000000..c20ab08
--- /dev/null
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_h3_v20.h"
+
+#define RCAR_QOS_VERSION "rev.0.21"
+
+#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
+
+#define QOSWT_WTEN_ENABLE 0x1U
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 (SL_INIT_SSLOTCLK_H3_20 - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
+#define QOSWT_WTREF_SLOT0_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0 5U
+#define WT_BASE_SUB_SLOT_NUM0 12U
+#define QOSWT_WTSET0_PERIOD0_H3_20 \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_20) - 1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_H3_20 \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_20) - 1U)
+#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3_v20_mstat195.h"
+#else
+#include "qos_init_h3_v20_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3_v20_qoswt195.h"
+#else
+#include "qos_init_h3_v20_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+#endif
+
+struct rcar_gen3_dbsc_qos_settings h3_v20_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF2, 0x000000F4U },
+ { DBSC_DBCAM0CNF3, 0x00000000U },
+ { DBSC_DBSCHCNT0, 0x000F0037U },
+ { DBSC_DBSCHSZ0, 0x00000001U },
+ { DBSC_DBSCHRW0, 0x22421111U },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123U },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00U },
+ { DBSC_DBSCHQOS01, 0x00000B00U },
+ { DBSC_DBSCHQOS02, 0x00000000U },
+ { DBSC_DBSCHQOS03, 0x00000000U },
+ { DBSC_DBSCHQOS40, 0x00000300U },
+ { DBSC_DBSCHQOS41, 0x000002F0U },
+ { DBSC_DBSCHQOS42, 0x00000200U },
+ { DBSC_DBSCHQOS43, 0x00000100U },
+ { DBSC_DBSCHQOS90, 0x00000100U },
+ { DBSC_DBSCHQOS91, 0x000000F0U },
+ { DBSC_DBSCHQOS92, 0x000000A0U },
+ { DBSC_DBSCHQOS93, 0x00000040U },
+ { DBSC_DBSCHQOS120, 0x00000040U },
+ { DBSC_DBSCHQOS121, 0x00000030U },
+ { DBSC_DBSCHQOS122, 0x00000020U },
+ { DBSC_DBSCHQOS123, 0x00000010U },
+ { DBSC_DBSCHQOS130, 0x00000100U },
+ { DBSC_DBSCHQOS131, 0x000000F0U },
+ { DBSC_DBSCHQOS132, 0x000000A0U },
+ { DBSC_DBSCHQOS133, 0x00000040U },
+ { DBSC_DBSCHQOS140, 0x000000C0U },
+ { DBSC_DBSCHQOS141, 0x000000B0U },
+ { DBSC_DBSCHQOS142, 0x00000080U },
+ { DBSC_DBSCHQOS143, 0x00000040U },
+ { DBSC_DBSCHQOS150, 0x00000040U },
+ { DBSC_DBSCHQOS151, 0x00000030U },
+ { DBSC_DBSCHQOS152, 0x00000020U },
+ { DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_h3_v20(void)
+{
+ rcar_qos_dbsc_setting(h3_v20_qos, ARRAY_SIZE(h3_v20_qos), true);
+
+ /* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 4ch\n");
+ io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1BU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR1, 0x00000000U);
+ io_write_32(AXI_ADSPLCR2, 0x00001054U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+ NOTICE("BL2: DRAM Split is 2ch\n");
+ io_write_32(AXI_ADSPLCR0, 0x00000000U);
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1BU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x00001004U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_RAS, 0x00000044U);
+ io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
+ io_write_32(QOSCTRL_DANT, 0x0020100AU);
+ io_write_32(QOSCTRL_INSFC, 0x06330001U);
+ io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+ /* GPU Boost Mode */
+ io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+ SL_INIT_SSLOTCLK_H3_20);
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ io_write_32(QOSCTRL_REF_ARS,
+ ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 << 16)));
+#else
+ io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+ qoswt_fix[i]);
+ io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+ qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+ io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ /* 3DG bus Leaf setting */
+ io_write_32(GPU_ACT0, 0x00000000U);
+ io_write_32(GPU_ACT1, 0x00000000U);
+ io_write_32(GPU_ACT2, 0x00000000U);
+ io_write_32(GPU_ACT3, 0x00000000U);
+ io_write_32(GPU_ACT4, 0x00000000U);
+ io_write_32(GPU_ACT5, 0x00000000U);
+ io_write_32(GPU_ACT6, 0x00000000U);
+ io_write_32(GPU_ACT7, 0x00000000U);
+
+ /* RT bus Leaf setting */
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+ io_write_32(CPU_ACT2, 0x00000003U);
+ io_write_32(CPU_ACT3, 0x00000003U);
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ io_write_32(QOSWT_WTREF,
+ ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ io_write_32(QOSWT_WTSET0,
+ ((QOSWT_WTSET0_PERIOD0_H3_20 << 16) |
+ (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ io_write_32(QOSWT_WTSET1,
+ ((QOSWT_WTSET1_PERIOD1_H3_20 << 16) |
+ (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v20.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
new file mode 100644
index 0000000..1fe6182
--- /dev/null
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_h3_v30.h"
+
+#define RCAR_QOS_VERSION "rev.0.11"
+
+#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
+
+#define QOSWT_WTEN_ENABLE 0x1U
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 (SL_INIT_SSLOTCLK_H3_30 - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
+#define QOSWT_WTREF_SLOT0_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0 5U
+#define WT_BASE_SUB_SLOT_NUM0 12U
+#define QOSWT_WTSET0_PERIOD0_H3_30 \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_30) - 1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_H3_30 (QOSWT_WTSET0_PERIOD0_H3_30)
+#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3_v30_mstat195.h"
+#else
+#include "qos_init_h3_v30_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3_v30_qoswt195.h"
+#else
+#include "qos_init_h3_v30_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+#endif
+
+struct rcar_gen3_dbsc_qos_settings h3_v30_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF2, 0x000000F4U },
+ { DBSC_DBCAM0CNF3, 0x00000000U },
+ { DBSC_DBSCHCNT0, 0x000F0037U },
+ { DBSC_DBSCHSZ0, 0x00000001U },
+ { DBSC_DBSCHRW0, 0x22421111U },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123U },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00U },
+ { DBSC_DBSCHQOS01, 0x00000B00U },
+ { DBSC_DBSCHQOS02, 0x00000000U },
+ { DBSC_DBSCHQOS03, 0x00000000U },
+ { DBSC_DBSCHQOS40, 0x00000300U },
+ { DBSC_DBSCHQOS41, 0x000002F0U },
+ { DBSC_DBSCHQOS42, 0x00000200U },
+ { DBSC_DBSCHQOS43, 0x00000100U },
+ { DBSC_DBSCHQOS90, 0x00000100U },
+ { DBSC_DBSCHQOS91, 0x000000F0U },
+ { DBSC_DBSCHQOS92, 0x000000A0U },
+ { DBSC_DBSCHQOS93, 0x00000040U },
+ { DBSC_DBSCHQOS120, 0x00000040U },
+ { DBSC_DBSCHQOS121, 0x00000030U },
+ { DBSC_DBSCHQOS122, 0x00000020U },
+ { DBSC_DBSCHQOS123, 0x00000010U },
+ { DBSC_DBSCHQOS130, 0x00000100U },
+ { DBSC_DBSCHQOS131, 0x000000F0U },
+ { DBSC_DBSCHQOS132, 0x000000A0U },
+ { DBSC_DBSCHQOS133, 0x00000040U },
+ { DBSC_DBSCHQOS140, 0x000000C0U },
+ { DBSC_DBSCHQOS141, 0x000000B0U },
+ { DBSC_DBSCHQOS142, 0x00000080U },
+ { DBSC_DBSCHQOS143, 0x00000040U },
+ { DBSC_DBSCHQOS150, 0x00000040U },
+ { DBSC_DBSCHQOS151, 0x00000030U },
+ { DBSC_DBSCHQOS152, 0x00000020U },
+ { DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_h3_v30(void)
+{
+ unsigned int split_area;
+
+ rcar_qos_dbsc_setting(h3_v30_qos, ARRAY_SIZE(h3_v30_qos), true);
+
+#if RCAR_DRAM_LPDDR4_MEMCONF == 0 /* 1GB */
+ split_area = 0x1BU;
+#else /* default 2GB */
+ split_area = 0x1CU;
+#endif
+
+ /* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 4ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+ io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(split_area)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR1, 0x00000000U);
+ io_write_32(AXI_ADSPLCR2, 0x00001054U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+ NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+ io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(split_area)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x00001004U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+ NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_RAS, 0x00000044U);
+ io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
+ io_write_32(QOSCTRL_DANT, 0x0020100AU);
+ io_write_32(QOSCTRL_FSS, 0x0000000AU);
+ io_write_32(QOSCTRL_INSFC, 0x06330001U);
+ io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+ /* GPU Boost Mode */
+ io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+ SL_INIT_SSLOTCLK_H3_30);
+ io_write_32(QOSCTRL_REF_ARS,
+ ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 << 16)));
+
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+ qoswt_fix[i]);
+ io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+ qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+ io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ /* AXI setting */
+ io_write_32(AXI_MMCR, 0x00010008U);
+ io_write_32(AXI_TR3CR, 0x00010000U);
+ io_write_32(AXI_TR4CR, 0x00010000U);
+
+ /* RT bus Leaf setting */
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+ io_write_32(CPU_ACT2, 0x00000003U);
+ io_write_32(CPU_ACT3, 0x00000003U);
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ io_write_32(QOSWT_WTREF,
+ ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ io_write_32(QOSWT_WTSET0,
+ ((QOSWT_WTSET0_PERIOD0_H3_30 << 16) |
+ (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ io_write_32(QOSWT_WTSET1,
+ ((QOSWT_WTSET1_PERIOD1_H3_30 << 16) |
+ (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v30.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
new file mode 100644
index 0000000..f1ee41b
--- /dev/null
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_h3n_v30.h"
+
+#define RCAR_QOS_VERSION "rev.0.07"
+
+#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
+
+#define QOSWT_WTEN_ENABLE 0x1U
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N (SL_INIT_SSLOTCLK_H3N - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
+#define QOSWT_WTREF_SLOT0_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0 5U
+#define WT_BASE_SUB_SLOT_NUM0 12U
+#define QOSWT_WTSET0_PERIOD0_H3N \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3N) - 1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_H3N (QOSWT_WTSET0_PERIOD0_H3N)
+#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3n_v30_mstat195.h"
+#else
+#include "qos_init_h3n_v30_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3n_v30_qoswt195.h"
+#else
+#include "qos_init_h3n_v30_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+#endif
+
+struct rcar_gen3_dbsc_qos_settings h3n_v30_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF2, 0x000000F4U },
+ { DBSC_DBCAM0CNF3, 0x00000000U },
+ { DBSC_DBSCHCNT0, 0x000F0037U },
+ { DBSC_DBSCHSZ0, 0x00000001U },
+ { DBSC_DBSCHRW0, 0x22421111U },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123U },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00U },
+ { DBSC_DBSCHQOS01, 0x00000B00U },
+ { DBSC_DBSCHQOS02, 0x00000000U },
+ { DBSC_DBSCHQOS03, 0x00000000U },
+ { DBSC_DBSCHQOS40, 0x00000300U },
+ { DBSC_DBSCHQOS41, 0x000002F0U },
+ { DBSC_DBSCHQOS42, 0x00000200U },
+ { DBSC_DBSCHQOS43, 0x00000100U },
+ { DBSC_DBSCHQOS90, 0x00000100U },
+ { DBSC_DBSCHQOS91, 0x000000F0U },
+ { DBSC_DBSCHQOS92, 0x000000A0U },
+ { DBSC_DBSCHQOS93, 0x00000040U },
+ { DBSC_DBSCHQOS120, 0x00000040U },
+ { DBSC_DBSCHQOS121, 0x00000030U },
+ { DBSC_DBSCHQOS122, 0x00000020U },
+ { DBSC_DBSCHQOS123, 0x00000010U },
+ { DBSC_DBSCHQOS130, 0x00000100U },
+ { DBSC_DBSCHQOS131, 0x000000F0U },
+ { DBSC_DBSCHQOS132, 0x000000A0U },
+ { DBSC_DBSCHQOS133, 0x00000040U },
+ { DBSC_DBSCHQOS140, 0x000000C0U },
+ { DBSC_DBSCHQOS141, 0x000000B0U },
+ { DBSC_DBSCHQOS142, 0x00000080U },
+ { DBSC_DBSCHQOS143, 0x00000040U },
+ { DBSC_DBSCHQOS150, 0x00000040U },
+ { DBSC_DBSCHQOS151, 0x00000030U },
+ { DBSC_DBSCHQOS152, 0x00000020U },
+ { DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_h3n_v30(void)
+{
+ unsigned int split_area;
+
+ rcar_qos_dbsc_setting(h3n_v30_qos, ARRAY_SIZE(h3n_v30_qos), true);
+
+ /* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
+ split_area = 0x1CU;
+
+ /* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
+#if RCAR_LSI == RCAR_H3N
+#error "Don't set DRAM Split 4ch(H3N)"
+#else
+ ERROR("DRAM Split 4ch not supported.(H3N)");
+ panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+ io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(split_area)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x00001004U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+ NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_RAS, 0x00000044U);
+ io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+ io_write_32(QOSCTRL_DANT, 0x0020100AU);
+ io_write_32(QOSCTRL_FSS, 0x0000000AU);
+ io_write_32(QOSCTRL_INSFC, 0x06330001U);
+ io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+ /* GPU Boost Mode */
+ io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+ SL_INIT_SSLOTCLK_H3N);
+ io_write_32(QOSCTRL_REF_ARS,
+ ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
+
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+ qoswt_fix[i]);
+ io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+ qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+ io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ /* AXI setting */
+ io_write_32(AXI_MMCR, 0x00010008U);
+ io_write_32(AXI_TR3CR, 0x00010000U);
+ io_write_32(AXI_TR4CR, 0x00010000U);
+
+ /* RT bus Leaf setting */
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+ io_write_32(CPU_ACT2, 0x00000003U);
+ io_write_32(CPU_ACT3, 0x00000003U);
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ io_write_32(QOSWT_WTREF,
+ ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ io_write_32(QOSWT_WTSET0,
+ ((QOSWT_WTSET0_PERIOD0_H3N << 16) |
+ (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ io_write_32(QOSWT_WTSET1,
+ ((QOSWT_WTSET1_PERIOD1_H3N << 16) |
+ (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.h b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h
rename to drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
new file mode 100644
index 0000000..a8264cb
--- /dev/null
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_m3_v10.h"
+
+#define RCAR_QOS_VERSION "rev.0.19"
+
+#include "qos_init_m3_v10_mstat.h"
+
+struct rcar_gen3_dbsc_qos_settings m3_v10_qos[] = {
+ /* BUFCAM settings */
+ /* DBSC_DBCAM0CNF0 not set */
+ { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF2, 0x000000F4 },
+ { DBSC_DBCAM0CNF3, 0x00000000 },
+ { DBSC_DBSCHCNT0, 0x080F0037 },
+ /* DBSC_DBSCHCNT1 not set */
+ { DBSC_DBSCHSZ0, 0x00000001 },
+ { DBSC_DBSCHRW0, 0x22421111 },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123 },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00 },
+ { DBSC_DBSCHQOS01, 0x00000B00 },
+ { DBSC_DBSCHQOS02, 0x00000000 },
+ { DBSC_DBSCHQOS03, 0x00000000 },
+ { DBSC_DBSCHQOS40, 0x00000300 },
+ { DBSC_DBSCHQOS41, 0x000002F0 },
+ { DBSC_DBSCHQOS42, 0x00000200 },
+ { DBSC_DBSCHQOS43, 0x00000100 },
+ { DBSC_DBSCHQOS90, 0x00000300 },
+ { DBSC_DBSCHQOS91, 0x000002F0 },
+ { DBSC_DBSCHQOS92, 0x00000200 },
+ { DBSC_DBSCHQOS93, 0x00000100 },
+ { DBSC_DBSCHQOS130, 0x00000100 },
+ { DBSC_DBSCHQOS131, 0x000000F0 },
+ { DBSC_DBSCHQOS132, 0x000000A0 },
+ { DBSC_DBSCHQOS133, 0x00000040 },
+ { DBSC_DBSCHQOS140, 0x000000C0 },
+ { DBSC_DBSCHQOS141, 0x000000B0 },
+ { DBSC_DBSCHQOS142, 0x00000080 },
+ { DBSC_DBSCHQOS143, 0x00000040 },
+ { DBSC_DBSCHQOS150, 0x00000040 },
+ { DBSC_DBSCHQOS151, 0x00000030 },
+ { DBSC_DBSCHQOS152, 0x00000020 },
+ { DBSC_DBSCHQOS153, 0x00000010 },
+};
+
+void qos_init_m3_v10(void)
+{
+ rcar_qos_dbsc_setting(m3_v10_qos, ARRAY_SIZE(m3_v10_qos), false);
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_M3
+#error "Don't set DRAM Split 4ch(M3)"
+#else
+ ERROR("DRAM Split 4ch not supported.(M3)");
+ panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 2ch\n");
+ io_write_32(AXI_ADSPLCR0, 0x00000000U);
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1CU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x089A0000U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+ /* Resource Alloc setting */
+ io_write_32(QOSCTRL_RAS, 0x00000028U);
+ io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
+ io_write_32(QOSCTRL_REGGD, 0x00000000U);
+ io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
+ io_write_32(QOSCTRL_DANT, 0x00100804U);
+ io_write_32(QOSCTRL_EC, 0x00000000U);
+ io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
+ io_write_32(QOSCTRL_FSS, 0x000003e8U);
+ io_write_32(QOSCTRL_INSFC, 0xC7840001U);
+ io_write_32(QOSCTRL_BERR, 0x00000000U);
+ io_write_32(QOSCTRL_RACNT0, 0x00000000U);
+
+ /* QOSBW setting */
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
+ io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
+
+ /* QOSBW SRAM setting */
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+
+ /* 3DG bus Leaf setting */
+ io_write_32(0xFD820808U, 0x00001234U);
+ io_write_32(0xFD820800U, 0x00000006U);
+ io_write_32(0xFD821800U, 0x00000006U);
+ io_write_32(0xFD822800U, 0x00000006U);
+ io_write_32(0xFD823800U, 0x00000006U);
+ io_write_32(0xFD824800U, 0x00000006U);
+ io_write_32(0xFD825800U, 0x00000006U);
+ io_write_32(0xFD826800U, 0x00000006U);
+ io_write_32(0xFD827800U, 0x00000006U);
+
+ /* RT bus Leaf setting */
+ io_write_32(0xFFC50800U, 0x00000000U);
+ io_write_32(0xFFC51800U, 0x00000000U);
+
+ /* Resource Alloc start */
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+ /* QOSBW start */
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ /* Resource Alloc setting */
+ io_write_32(QOSCTRL_EC, 0x00000000U);
+ /* Resource Alloc start */
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v10.h
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v10_mstat.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v10_mstat.h
new file mode 100644
index 0000000..b78b5f1
--- /dev/null
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v10_mstat.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+static const uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001004030000FFFFUL,
+ /* 0x0038, */ 0x001004030000FFFFUL,
+ /* 0x0040, */ 0x001414090000FFFFUL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x001410010000FFFFUL,
+ /* 0x0058, */ 0x00140C090000FFFFUL,
+ /* 0x0060, */ 0x00140C090000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x001410010000FFFFUL,
+ /* 0x0078, */ 0x001004020000FFFFUL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x001414090000FFFFUL,
+ /* 0x0090, */ 0x001408060000FFFFUL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00A0, */ 0x000C08020000FFFFUL,
+ /* 0x00A8, */ 0x000C04010000FFFFUL,
+ /* 0x00B0, */ 0x000C04010000FFFFUL,
+ /* 0x00B8, */ 0x0000000000000000UL,
+ /* 0x00C0, */ 0x000C08020000FFFFUL,
+ /* 0x00C8, */ 0x000C04010000FFFFUL,
+ /* 0x00D0, */ 0x000C04010000FFFFUL,
+ /* 0x00D8, */ 0x000C04030000FFFFUL,
+ /* 0x00E0, */ 0x000C100F0000FFFFUL,
+ /* 0x00E8, */ 0x0000000000000000UL,
+ /* 0x00F0, */ 0x001010080000FFFFUL,
+ /* 0x00F8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x001010080000FFFFUL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x00100C0A0000FFFFUL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x00100C0A0000FFFFUL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x00100C0A0000FFFFUL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x001008050000FFFFUL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x001028280000FFFFUL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01A0, */ 0x00100C0A0000FFFFUL,
+ /* 0x01A8, */ 0x0000000000000000UL,
+ /* 0x01B0, */ 0x0000000000000000UL,
+ /* 0x01B8, */ 0x0000000000000000UL,
+ /* 0x01C0, */ 0x0000000000000000UL,
+ /* 0x01C8, */ 0x0000000000000000UL,
+ /* 0x01D0, */ 0x0000000000000000UL,
+ /* 0x01D8, */ 0x0000000000000000UL,
+ /* 0x01E0, */ 0x0000000000000000UL,
+ /* 0x01E8, */ 0x0000000000000000UL,
+ /* 0x01F0, */ 0x0000000000000000UL,
+ /* 0x01F8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x001408010000FFFFUL,
+ /* 0x0270, */ 0x001404010000FFFFUL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001408010000FFFFUL,
+ /* 0x0298, */ 0x001404010000FFFFUL,
+ /* 0x02A0, */ 0x000C04010000FFFFUL,
+ /* 0x02A8, */ 0x000C04010000FFFFUL,
+ /* 0x02B0, */ 0x001404010000FFFFUL,
+ /* 0x02B8, */ 0x0000000000000000UL,
+ /* 0x02C0, */ 0x0000000000000000UL,
+ /* 0x02C8, */ 0x0000000000000000UL,
+ /* 0x02D0, */ 0x000C04010000FFFFUL,
+ /* 0x02D8, */ 0x000C04010000FFFFUL,
+ /* 0x02E0, */ 0x001404010000FFFFUL,
+ /* 0x02E8, */ 0x0000000000000000UL,
+ /* 0x02F0, */ 0x0000000000000000UL,
+ /* 0x02F8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+};
+
+static const uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x001200100C89C401UL,
+ /* 0x0008, */ 0x001200100C89C401UL,
+ /* 0x0010, */ 0x001200100C89C401UL,
+ /* 0x0018, */ 0x001200100C89C401UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x001100100C803401UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00A0, */ 0x0000000000000000UL,
+ /* 0x00A8, */ 0x0000000000000000UL,
+ /* 0x00B0, */ 0x0000000000000000UL,
+ /* 0x00B8, */ 0x0000000000000000UL,
+ /* 0x00C0, */ 0x0000000000000000UL,
+ /* 0x00C8, */ 0x0000000000000000UL,
+ /* 0x00D0, */ 0x0000000000000000UL,
+ /* 0x00D8, */ 0x0000000000000000UL,
+ /* 0x00E0, */ 0x0000000000000000UL,
+ /* 0x00E8, */ 0x0000000000000000UL,
+ /* 0x00F0, */ 0x0000000000000000UL,
+ /* 0x00F8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01A0, */ 0x0000000000000000UL,
+ /* 0x01A8, */ 0x0000000000000000UL,
+ /* 0x01B0, */ 0x0000000000000000UL,
+ /* 0x01B8, */ 0x0000000000000000UL,
+ /* 0x01C0, */ 0x001100500C8FFC01UL,
+ /* 0x01C8, */ 0x001100500C8FFC01UL,
+ /* 0x01D0, */ 0x001100500C8FFC01UL,
+ /* 0x01D8, */ 0x001100500C8FFC01UL,
+ /* 0x01E0, */ 0x0000000000000000UL,
+ /* 0x01E8, */ 0x001200100C803401UL,
+ /* 0x01F0, */ 0x001100100C80FC01UL,
+ /* 0x01F8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x001200100C80FC01UL,
+ /* 0x0210, */ 0x001100100C80FC01UL,
+ /* 0x0218, */ 0x001100100C825801UL,
+ /* 0x0220, */ 0x001100100C825801UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x001100100C825801UL,
+ /* 0x0238, */ 0x001100100C825801UL,
+ /* 0x0240, */ 0x001200100C8BB801UL,
+ /* 0x0248, */ 0x001100100C8EA401UL,
+ /* 0x0250, */ 0x001200100C8BB801UL,
+ /* 0x0258, */ 0x001100100C8EA401UL,
+ /* 0x0260, */ 0x001100100C84E401UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x001100100C81F401UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02A0, */ 0x0000000000000000UL,
+ /* 0x02A8, */ 0x0000000000000000UL,
+ /* 0x02B0, */ 0x0000000000000000UL,
+ /* 0x02B8, */ 0x001100100C803401UL,
+ /* 0x02C0, */ 0x0000000000000000UL,
+ /* 0x02C8, */ 0x0000000000000000UL,
+ /* 0x02D0, */ 0x0000000000000000UL,
+ /* 0x02D8, */ 0x0000000000000000UL,
+ /* 0x02E0, */ 0x0000000000000000UL,
+ /* 0x02E8, */ 0x001100100C803401UL,
+ /* 0x02F0, */ 0x001100300C8FFC01UL,
+ /* 0x02F8, */ 0x001100500C8FFC01UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x001100300C8FFC01UL,
+ /* 0x0310, */ 0x001100500C8FFC01UL,
+ /* 0x0318, */ 0x001200100C803401UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+};
+#endif
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
new file mode 100644
index 0000000..22fd83a
--- /dev/null
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_m3_v11.h"
+
+#define RCAR_QOS_VERSION "rev.0.19"
+
+#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
+
+#define QOSWT_WTEN_ENABLE 0x1U
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 (SL_INIT_SSLOTCLK_M3_11 - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
+#define QOSWT_WTREF_SLOT0_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0 5U
+#define WT_BASE_SUB_SLOT_NUM0 12U
+#define QOSWT_WTSET0_PERIOD0_M3_11 \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_11) - 1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_M3_11 \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_11) - 1U)
+#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3_v11_mstat195.h"
+#else
+#include "qos_init_m3_v11_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3_v11_qoswt195.h"
+#else
+#include "qos_init_m3_v11_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+struct rcar_gen3_dbsc_qos_settings m3_v11_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF2, 0x000000F4 },
+ { DBSC_DBCAM0CNF3, 0x00000000 },
+ { DBSC_DBSCHCNT0, 0x000F0037 },
+ { DBSC_DBSCHSZ0, 0x00000001 },
+ { DBSC_DBSCHRW0, 0x22421111 },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123 },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00 },
+ { DBSC_DBSCHQOS01, 0x00000B00 },
+ { DBSC_DBSCHQOS02, 0x00000000 },
+ { DBSC_DBSCHQOS03, 0x00000000 },
+ { DBSC_DBSCHQOS40, 0x00000300 },
+ { DBSC_DBSCHQOS41, 0x000002F0 },
+ { DBSC_DBSCHQOS42, 0x00000200 },
+ { DBSC_DBSCHQOS43, 0x00000100 },
+ { DBSC_DBSCHQOS90, 0x00000100 },
+ { DBSC_DBSCHQOS91, 0x000000F0 },
+ { DBSC_DBSCHQOS92, 0x000000A0 },
+ { DBSC_DBSCHQOS93, 0x00000040 },
+ { DBSC_DBSCHQOS120, 0x00000040 },
+ { DBSC_DBSCHQOS121, 0x00000030 },
+ { DBSC_DBSCHQOS122, 0x00000020 },
+ { DBSC_DBSCHQOS123, 0x00000010 },
+ { DBSC_DBSCHQOS130, 0x00000100 },
+ { DBSC_DBSCHQOS131, 0x000000F0 },
+ { DBSC_DBSCHQOS132, 0x000000A0 },
+ { DBSC_DBSCHQOS133, 0x00000040 },
+ { DBSC_DBSCHQOS140, 0x000000C0 },
+ { DBSC_DBSCHQOS141, 0x000000B0 },
+ { DBSC_DBSCHQOS142, 0x00000080 },
+ { DBSC_DBSCHQOS143, 0x00000040 },
+ { DBSC_DBSCHQOS150, 0x00000040 },
+ { DBSC_DBSCHQOS151, 0x00000030 },
+ { DBSC_DBSCHQOS152, 0x00000020 },
+ { DBSC_DBSCHQOS153, 0x00000010 },
+};
+
+void qos_init_m3_v11(void)
+{
+ rcar_qos_dbsc_setting(m3_v11_qos, ARRAY_SIZE(m3_v11_qos), false);
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_M3
+#error "Don't set DRAM Split 4ch(M3)"
+#else
+ ERROR("DRAM Split 4ch not supported.(M3)");
+ panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 2ch\n");
+ io_write_32(AXI_ADSPLCR0, 0x00000000U);
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1CU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x00001004U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_RAS, 0x00000044U);
+ io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+ io_write_32(QOSCTRL_DANT, 0x0020100AU);
+ io_write_32(QOSCTRL_INSFC, 0x06330001U);
+ io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */
+
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+ SL_INIT_SSLOTCLK_M3_11);
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ io_write_32(QOSCTRL_REF_ARS,
+ ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 << 16)));
+#else
+ io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
+ io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+ io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ /* 3DG bus Leaf setting */
+ io_write_32(GPU_ACT_GRD, 0x00001234U);
+ io_write_32(GPU_ACT0, 0x00000000U);
+ io_write_32(GPU_ACT1, 0x00000000U);
+ io_write_32(GPU_ACT2, 0x00000000U);
+ io_write_32(GPU_ACT3, 0x00000000U);
+
+ /* RT bus Leaf setting */
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+ io_write_32(CPU_ACT2, 0x00000003U);
+ io_write_32(CPU_ACT3, 0x00000003U);
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ io_write_32(QOSWT_WTREF,
+ ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ io_write_32(QOSWT_WTSET0,
+ ((QOSWT_WTSET0_PERIOD0_M3_11 << 16) |
+ (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ io_write_32(QOSWT_WTSET1,
+ ((QOSWT_WTSET1_PERIOD1_M3_11 << 16) |
+ (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v11.h
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
new file mode 100644
index 0000000..e300fd5
--- /dev/null
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_m3_v30.h"
+
+#define RCAR_QOS_VERSION "rev.0.03"
+
+#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
+
+#define QOSWT_WTEN_ENABLE 0x1U
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 (SL_INIT_SSLOTCLK_M3_30 - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
+#define QOSWT_WTREF_SLOT0_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0 5U
+#define WT_BASE_SUB_SLOT_NUM0 12U
+#define QOSWT_WTSET0_PERIOD0_M3_30 \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_M3_30 \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U)
+#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3_v30_mstat195.h"
+#else
+#include "qos_init_m3_v30_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3_v30_qoswt195.h"
+#else
+#include "qos_init_m3_v30_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+struct rcar_gen3_dbsc_qos_settings m3_v30_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF2, 0x000000F4 },
+ { DBSC_DBCAM0CNF3, 0x00000000 },
+ { DBSC_DBSCHCNT0, 0x000F0037 },
+ { DBSC_DBSCHSZ0, 0x00000001 },
+ { DBSC_DBSCHRW0, 0x22421111 },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123 },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00 },
+ { DBSC_DBSCHQOS01, 0x00000B00 },
+ { DBSC_DBSCHQOS02, 0x00000000 },
+ { DBSC_DBSCHQOS03, 0x00000000 },
+ { DBSC_DBSCHQOS40, 0x00000300 },
+ { DBSC_DBSCHQOS41, 0x000002F0 },
+ { DBSC_DBSCHQOS42, 0x00000200 },
+ { DBSC_DBSCHQOS43, 0x00000100 },
+ { DBSC_DBSCHQOS90, 0x00000100 },
+ { DBSC_DBSCHQOS91, 0x000000F0 },
+ { DBSC_DBSCHQOS92, 0x000000A0 },
+ { DBSC_DBSCHQOS93, 0x00000040 },
+ { DBSC_DBSCHQOS120, 0x00000040 },
+ { DBSC_DBSCHQOS121, 0x00000030 },
+ { DBSC_DBSCHQOS122, 0x00000020 },
+ { DBSC_DBSCHQOS123, 0x00000010 },
+ { DBSC_DBSCHQOS130, 0x00000100 },
+ { DBSC_DBSCHQOS131, 0x000000F0 },
+ { DBSC_DBSCHQOS132, 0x000000A0 },
+ { DBSC_DBSCHQOS133, 0x00000040 },
+ { DBSC_DBSCHQOS140, 0x000000C0 },
+ { DBSC_DBSCHQOS141, 0x000000B0 },
+ { DBSC_DBSCHQOS142, 0x00000080 },
+ { DBSC_DBSCHQOS143, 0x00000040 },
+ { DBSC_DBSCHQOS150, 0x00000040 },
+ { DBSC_DBSCHQOS151, 0x00000030 },
+ { DBSC_DBSCHQOS152, 0x00000020 },
+ { DBSC_DBSCHQOS153, 0x00000010 },
+};
+
+void qos_init_m3_v30(void)
+{
+ rcar_qos_dbsc_setting(m3_v30_qos, ARRAY_SIZE(m3_v30_qos), true);
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+ #if RCAR_LSI == RCAR_M3
+ #error "Don't set DRAM Split 4ch(M3)"
+ #else
+ ERROR("DRAM Split 4ch not supported.(M3)");
+ panic();
+ #endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 2ch\n");
+ io_write_32(AXI_ADSPLCR0, 0x00000000U);
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1DU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x00001004U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_RAS, 0x00000044U);
+ io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+ io_write_32(QOSCTRL_DANT, 0x0020100AU);
+ io_write_32(QOSCTRL_FSS, 0x0000000AU);
+ io_write_32(QOSCTRL_INSFC, 0x06330001U);
+ io_write_32(QOSCTRL_EARLYR, 0x00000001U);
+ io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */
+
+ /* GPU Boost Mode */
+ io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+ io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30);
+ io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16)));
+
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
+ io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+ io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ /* RT bus Leaf setting */
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+ io_write_32(CPU_ACT2, 0x00000003U);
+ io_write_32(CPU_ACT3, 0x00000003U);
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ io_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ io_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_M3_30 << 16) | (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ io_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_M3_30 << 16) | (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v30.h
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt195.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt195.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt195.h
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt390.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt390.h
rename to drivers/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt390.h
diff --git a/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
new file mode 100644
index 0000000..446340b
--- /dev/null
+++ b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_m3n_v10.h"
+
+#define RCAR_QOS_VERSION "rev.0.09"
+
+#define REF_ARS_ARBSTOPCYCLE_M3N \
+ (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
+
+#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
+
+#define QOSWT_WTEN_ENABLE 0x1U
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
+#define QOSWT_WTREF_SLOT0_EN \
+ ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
+
+#define QOSWT_WTSET0_REQ_SSLOT0 5U
+#define WT_BASE_SUB_SLOT_NUM0 12U
+#define QOSWT_WTSET0_PERIOD0_M3N \
+ ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3N) - 1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_M3N QOSWT_WTSET0_PERIOD0_M3N
+#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
+#define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3n_v10_mstat195.h"
+#else
+#include "qos_init_m3n_v10_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3n_v10_qoswt195.h"
+#else
+#include "qos_init_m3n_v10_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+struct rcar_gen3_dbsc_qos_settings m3n_v10_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF2, 0x000000F4 },
+ { DBSC_DBSCHCNT0, 0x000F0037 },
+ { DBSC_DBSCHSZ0, 0x00000001 },
+ { DBSC_DBSCHRW0, 0x22421111 },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123 },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00 },
+ { DBSC_DBSCHQOS01, 0x00000B00 },
+ { DBSC_DBSCHQOS02, 0x00000000 },
+ { DBSC_DBSCHQOS03, 0x00000000 },
+ { DBSC_DBSCHQOS40, 0x00000300 },
+ { DBSC_DBSCHQOS41, 0x000002F0 },
+ { DBSC_DBSCHQOS42, 0x00000200 },
+ { DBSC_DBSCHQOS43, 0x00000100 },
+ { DBSC_DBSCHQOS90, 0x00000100 },
+ { DBSC_DBSCHQOS91, 0x000000F0 },
+ { DBSC_DBSCHQOS92, 0x000000A0 },
+ { DBSC_DBSCHQOS93, 0x00000040 },
+ { DBSC_DBSCHQOS130, 0x00000100 },
+ { DBSC_DBSCHQOS131, 0x000000F0 },
+ { DBSC_DBSCHQOS132, 0x000000A0 },
+ { DBSC_DBSCHQOS133, 0x00000040 },
+ { DBSC_DBSCHQOS140, 0x000000C0 },
+ { DBSC_DBSCHQOS141, 0x000000B0 },
+ { DBSC_DBSCHQOS142, 0x00000080 },
+ { DBSC_DBSCHQOS143, 0x00000040 },
+ { DBSC_DBSCHQOS150, 0x00000040 },
+ { DBSC_DBSCHQOS151, 0x00000030 },
+ { DBSC_DBSCHQOS152, 0x00000020 },
+ { DBSC_DBSCHQOS153, 0x00000010 },
+};
+
+void qos_init_m3n_v10(void)
+{
+ rcar_qos_dbsc_setting(m3n_v10_qos, ARRAY_SIZE(m3n_v10_qos), true);
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_M3N
+#error "Don't set DRAM Split 4ch(M3N)"
+#else
+ ERROR("DRAM Split 4ch not supported.(M3N)");
+ panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RCAR_M3N
+#error "Don't set DRAM Split 2ch(M3N)"
+#else
+ ERROR("DRAM Split 2ch not supported.(M3N)");
+ panic();
+#endif
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_RAS, 0x00000028U);
+ io_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
+ io_write_32(QOSCTRL_DANT, 0x00100804U);
+ io_write_32(QOSCTRL_FSS, 0x0000000AU);
+ io_write_32(QOSCTRL_INSFC, 0x06330001U);
+ io_write_32(QOSCTRL_EARLYR, 0x00000001U);
+ io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+ io_write_32(QOSCTRL_SL_INIT,
+ SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+ SL_INIT_SSLOTCLK_M3N);
+ io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_M3N);
+
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+ qoswt_fix[i]);
+ io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+ qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+ io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ /* RT bus Leaf setting */
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ io_write_32(QOSWT_WTREF,
+ ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ io_write_32(QOSWT_WTSET0,
+ ((QOSWT_WTSET0_PERIOD0_M3N << 16) |
+ (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ io_write_32(QOSWT_WTSET1,
+ ((QOSWT_WTSET1_PERIOD1_M3N << 16) |
+ (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.h b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.h
rename to drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.h
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
rename to drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
rename to drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h
rename to drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h
rename to drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h
diff --git a/drivers/renesas/rcar/qos/V3M/qos_init_v3m.c b/drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
new file mode 100644
index 0000000..076876c
--- /dev/null
+++ b/drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_v3m.h"
+
+#define RCAR_QOS_VERSION "rev.0.01"
+
+#include "qos_init_v3m_mstat.h"
+
+struct rcar_gen3_dbsc_qos_settings v3m_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00044218 },
+ { DBSC_DBCAM0CNF2, 0x000000F4 },
+ { DBSC_DBSCHCNT0, 0x080F003F },
+ { DBSC_DBSCHCNT1, 0x00001010 },
+
+ { DBSC_DBSCHSZ0, 0x00000001 },
+ { DBSC_DBSCHRW0, 0x22421111 },
+ { DBSC_DBSCHRW1, 0x00180034 },
+ { DBSC_SCFCTST0, 0x180B1708 },
+ { DBSC_SCFCTST1, 0x0808070C },
+ { DBSC_SCFCTST2, 0x012F1123 },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x0000F000 },
+ { DBSC_DBSCHQOS01, 0x0000E000 },
+ { DBSC_DBSCHQOS02, 0x00007000 },
+ { DBSC_DBSCHQOS03, 0x00000000 },
+ { DBSC_DBSCHQOS40, 0x0000F000 },
+ { DBSC_DBSCHQOS41, 0x0000EFFF },
+ { DBSC_DBSCHQOS42, 0x0000B000 },
+ { DBSC_DBSCHQOS43, 0x00000000 },
+ { DBSC_DBSCHQOS90, 0x0000F000 },
+ { DBSC_DBSCHQOS91, 0x0000EFFF },
+ { DBSC_DBSCHQOS92, 0x0000D000 },
+ { DBSC_DBSCHQOS93, 0x00000000 },
+ { DBSC_DBSCHQOS130, 0x0000F000 },
+ { DBSC_DBSCHQOS131, 0x0000EFFF },
+ { DBSC_DBSCHQOS132, 0x0000E800 },
+ { DBSC_DBSCHQOS133, 0x00007000 },
+ { DBSC_DBSCHQOS140, 0x0000F000 },
+ { DBSC_DBSCHQOS141, 0x0000EFFF },
+ { DBSC_DBSCHQOS142, 0x0000E800 },
+ { DBSC_DBSCHQOS143, 0x0000B000 },
+ { DBSC_DBSCHQOS150, 0x000007D0 },
+ { DBSC_DBSCHQOS151, 0x000007CF },
+ { DBSC_DBSCHQOS152, 0x000005D0 },
+ { DBSC_DBSCHQOS153, 0x000003D0 },
+};
+
+void qos_init_v3m(void)
+{
+return;
+
+ rcar_qos_dbsc_setting(v3m_qos, ARRAY_SIZE(v3m_qos), false);
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+ /* Resource Alloc setting */
+ io_write_32(QOSCTRL_RAS, 0x00000020U);
+ io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
+ io_write_32(QOSCTRL_REGGD, 0x00000004U);
+ io_write_64(QOSCTRL_DANN, 0x0202020104040200U);
+ io_write_32(QOSCTRL_DANT, 0x00201008U);
+ io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 ES1 */
+ io_write_64(QOSCTRL_EMS, 0x0000000000000000U);
+ io_write_32(QOSCTRL_INSFC, 0x63C20001U);
+ io_write_32(QOSCTRL_BERR, 0x00000000U);
+
+ /* QOSBW setting */
+ io_write_32(QOSCTRL_SL_INIT, 0x0305007DU);
+ io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
+
+ /* QOSBW SRAM setting */
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
+
+ /* AXI-IF arbitration setting */
+ io_write_32(DBSC_AXARB, 0x18010000U);
+
+ /* Resource Alloc start */
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+ /* QOSBW start */
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+
+#else
+ NOTICE("BL2: QoS is None\n");
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.h b/drivers/renesas/rcar/qos/V3M/qos_init_v3m.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.h
rename to drivers/renesas/rcar/qos/V3M/qos_init_v3m.h
diff --git a/drivers/renesas/rcar/qos/V3M/qos_init_v3m_mstat.h b/drivers/renesas/rcar/qos/V3M/qos_init_v3m_mstat.h
new file mode 100644
index 0000000..d0b7fc3
--- /dev/null
+++ b/drivers/renesas/rcar/qos/V3M/qos_init_v3m_mstat.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+static const uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x000000000000FFFFUL,
+ /* 0x0008, */ 0x000000000000FFFFUL,
+ /* 0x0010, */ 0x000000000000FFFFUL,
+ /* 0x0018, */ 0x000000000000FFFFUL,
+ /* 0x0020, */ 0x001414090000FFFFUL,
+ /* 0x0028, */ 0x000C00000000FFFFUL,
+ /* 0x0030, */ 0x001008040000FFFFUL,
+ /* 0x0038, */ 0x001004040000FFFFUL,
+ /* 0x0040, */ 0x001004040000FFFFUL,
+ /* 0x0048, */ 0x000000000000FFFFUL,
+ /* 0x0050, */ 0x001004040000FFFFUL,
+ /* 0x0058, */ 0x001004040000FFFFUL,
+ /* 0x0060, */ 0x000000000000FFFFUL,
+ /* 0x0068, */ 0x001404040000FFFFUL,
+ /* 0x0070, */ 0x001008030000FFFFUL,
+ /* 0x0078, */ 0x001004030000FFFFUL,
+ /* 0x0080, */ 0x001004030000FFFFUL,
+ /* 0x0088, */ 0x000000000000FFFFUL,
+ /* 0x0090, */ 0x001004040000FFFFUL,
+ /* 0x0098, */ 0x001004040000FFFFUL,
+ /* 0x00A0, */ 0x000000000000FFFFUL,
+ /* 0x00A8, */ 0x000000000000FFFFUL,
+ /* 0x00B0, */ 0x000000000000FFFFUL,
+ /* 0x00B8, */ 0x000000000000FFFFUL,
+ /* 0x00C0, */ 0x000000000000FFFFUL,
+ /* 0x00C8, */ 0x000000000000FFFFUL,
+ /* 0x00D0, */ 0x000000000000FFFFUL,
+ /* 0x00D8, */ 0x000000000000FFFFUL,
+ /* 0x00E0, */ 0x001404020000FFFFUL,
+ /* 0x00E8, */ 0x000000000000FFFFUL,
+ /* 0x00F0, */ 0x000000000000FFFFUL,
+ /* 0x00F8, */ 0x000000000000FFFFUL,
+ /* 0x0100, */ 0x000000000000FFFFUL,
+ /* 0x0108, */ 0x000C04020000FFFFUL,
+ /* 0x0110, */ 0x000000000000FFFFUL,
+ /* 0x0118, */ 0x001404020000FFFFUL,
+ /* 0x0120, */ 0x000000000000FFFFUL,
+ /* 0x0128, */ 0x000000000000FFFFUL,
+ /* 0x0130, */ 0x000000000000FFFFUL,
+ /* 0x0138, */ 0x000000000000FFFFUL,
+ /* 0x0140, */ 0x000000000000FFFFUL,
+ /* 0x0148, */ 0x000000000000FFFFUL,
+};
+
+static const uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x00100020447FFC01UL,
+ /* 0x0008, */ 0x00100020447FFC01UL,
+ /* 0x0010, */ 0x00100040447FFC01UL,
+ /* 0x0018, */ 0x00100040447FFC01UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00A0, */ 0x00100010447FFC01UL,
+ /* 0x00A8, */ 0x00100010447FFC01UL,
+ /* 0x00B0, */ 0x00100010447FFC01UL,
+ /* 0x00B8, */ 0x00100010447FFC01UL,
+ /* 0x00C0, */ 0x00100010447FFC01UL,
+ /* 0x00C8, */ 0x00100010447FFC01UL,
+ /* 0x00D0, */ 0x0000000000000000UL,
+ /* 0x00D8, */ 0x00100010447FFC01UL,
+ /* 0x00E0, */ 0x0000000000000000UL,
+ /* 0x00E8, */ 0x00100010447FFC01UL,
+ /* 0x00F0, */ 0x00100010447FFC01UL,
+ /* 0x00F8, */ 0x00100010447FFC01UL,
+ /* 0x0100, */ 0x00100010447FFC01UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x00100010447FFC01UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x00100010447FFC01UL,
+ /* 0x0128, */ 0x00100010447FFC01UL,
+ /* 0x0130, */ 0x00100010447FFC01UL,
+ /* 0x0138, */ 0x00100010447FFC01UL,
+ /* 0x0140, */ 0x00100020447FFC01UL,
+ /* 0x0148, */ 0x00100020447FFC01UL,
+};
+#endif
diff --git a/drivers/renesas/rcar/qos/qos.mk b/drivers/renesas/rcar/qos/qos.mk
new file mode 100644
index 0000000..da10da2
--- /dev/null
+++ b/drivers/renesas/rcar/qos/qos.mk
@@ -0,0 +1,106 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_AUTO})
+# E3, H3N not available for LSI_AUTO
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
+else ifdef RCAR_LSI_CUT_COMPAT
+ ifeq (${RCAR_LSI},${RCAR_H3})
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_H3N})
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_M3})
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_M3N})
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_V3M})
+ BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_E3})
+ BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_D3})
+ BL2_SOURCES += drivers/renesas/rcar/qos/D3/qos_init_d3.c
+ endif
+else
+ ifeq (${RCAR_LSI},${RCAR_H3})
+ ifeq (${LSI_CUT},10)
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
+ else ifeq (${LSI_CUT},11)
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
+ else ifeq (${LSI_CUT},20)
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
+ else ifeq (${LSI_CUT},30)
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
+ else
+# LSI_CUT 30 or later
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
+ endif
+ endif
+ ifeq (${RCAR_LSI},${RCAR_H3N})
+ ifeq (${LSI_CUT},30)
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+ else
+# LSI_CUT 30 or later
+ BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+ endif
+ endif
+ ifeq (${RCAR_LSI},${RCAR_M3})
+ ifeq (${LSI_CUT},10)
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
+ else ifeq (${LSI_CUT},11)
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
+ else ifeq (${LSI_CUT},13)
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
+ else ifeq (${LSI_CUT},30)
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
+ else
+# LSI_CUT 30 or later
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
+ endif
+ endif
+ ifeq (${RCAR_LSI},${RCAR_M3N})
+ ifeq (${LSI_CUT},10)
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+ else
+# LSI_CUT 10 or later
+ BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+ endif
+ endif
+ ifeq (${RCAR_LSI},${RCAR_V3M})
+ BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_E3})
+ ifeq (${LSI_CUT},10)
+ BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
+ else
+# LSI_CUT 10 or later
+ BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
+ endif
+ endif
+ ifeq (${RCAR_LSI},${RCAR_D3})
+ BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_d3.c
+ endif
+endif
+
+BL2_SOURCES += drivers/renesas/rcar/qos/qos_init.c
diff --git a/drivers/renesas/rcar/qos/qos_common.h b/drivers/renesas/rcar/qos/qos_common.h
new file mode 100644
index 0000000..2c130ae
--- /dev/null
+++ b/drivers/renesas/rcar/qos/qos_common.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_COMMON_H
+#define QOS_COMMON_H
+
+#define RCAR_REF_DEFAULT 0U
+
+/* define used for get_refperiod. */
+/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
+/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
+#define REFPERIOD_CYCLE /* unit:ns */ \
+ ((126 * BASE_SUB_SLOT_NUM * 1000U) / 400)
+#else /* REF option */
+#define REFPERIOD_CYCLE /* unit:ns */ \
+ ((252 * BASE_SUB_SLOT_NUM * 1000U) / 400)
+#endif
+
+#if (RCAR_LSI == RCAR_E3)
+/* define used for E3 */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_E3 0xAFU /* 175 */
+#else /* REF 7.8usec */
+#define SUB_SLOT_CYCLE_E3 0x15EU /* 350 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define OPERATING_FREQ_E3 266U /* MHz */
+#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 - 1U)
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+/* define used for M3N */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
+#define SUB_SLOT_CYCLE_M3N 0x7EU /* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_M3N 0xFCU /* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N - 1U)
+#define QOSWT_WTSET0_CYCLE_M3N /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
+/* define used for H3 */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
+#define SUB_SLOT_CYCLE_H3_20 0x7EU /* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_H3_20 0xFCU /* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 - 1U)
+#define QOSWT_WTSET0_CYCLE_H3_20 /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+
+/* define used for H3 Cut 30 */
+#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
+#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 - 1U)
+#define QOSWT_WTSET0_CYCLE_H3_30 /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+
+#endif
+
+#if (RCAR_LSI == RCAR_H3N)
+/* define used for H3N */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
+#define SUB_SLOT_CYCLE_H3N 0x7EU /* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_H3N 0xFCU /* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N - 1U)
+#define QOSWT_WTSET0_CYCLE_H3N /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
+/* define used for M3 */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
+#define SUB_SLOT_CYCLE_M3_11 0x7EU /* 126 */
+#define SUB_SLOT_CYCLE_M3_30 0x7EU /* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_M3_11 0xFCU /* 252 */
+#define SUB_SLOT_CYCLE_M3_30 0xFCU /* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 - 1U)
+#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 - 1U)
+#define QOSWT_WTSET0_CYCLE_M3_11 /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#define QOSWT_WTSET0_CYCLE_M3_30 /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#endif
+
+#define OPERATING_FREQ 400U /* MHz */
+#define BASE_SUB_SLOT_NUM 0x6U
+#define SUB_SLOT_CYCLE 0x7EU /* 126 */
+
+#define QOSWT_WTSET0_CYCLE /* unit:ns */ \
+ ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+
+#define SL_INIT_REFFSSLOT (0x3U << 24U)
+#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
+#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U)
+
+static inline void io_write_32(uintptr_t addr, uint32_t value)
+{
+ *(volatile uint32_t *)addr = value;
+}
+
+static inline uint32_t io_read_32(uintptr_t addr)
+{
+ return *(volatile uint32_t *)addr;
+}
+
+static inline void io_write_64(uintptr_t addr, uint64_t value)
+{
+ *(volatile uint64_t *)addr = value;
+}
+
+typedef struct {
+ uintptr_t addr;
+ uint64_t value;
+} mstat_slot_t;
+
+struct rcar_gen3_dbsc_qos_settings {
+ uint32_t reg;
+ uint32_t val;
+};
+
+extern uint32_t qos_init_ddr_ch;
+extern uint8_t qos_init_ddr_phyvalid;
+
+void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos,
+ unsigned int qos_size, bool dbsc_wren);
+
+#endif /* QOS_COMMON_H */
diff --git a/drivers/staging/renesas/rcar/qos/qos_init.c b/drivers/renesas/rcar/qos/qos_init.c
similarity index 87%
rename from drivers/staging/renesas/rcar/qos/qos_init.c
rename to drivers/renesas/rcar/qos/qos_init.c
index c5f9a42..884e031 100644
--- a/drivers/staging/renesas/rcar/qos/qos_init.c
+++ b/drivers/renesas/rcar/qos/qos_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include "qos_init.h"
#include "qos_common.h"
+#include "qos_reg.h"
#if RCAR_LSI == RCAR_AUTO
#include "H3/qos_init_h3_v10.h"
#include "H3/qos_init_h3_v11.h"
@@ -50,42 +51,41 @@
#endif
/* Product Register */
-#define PRR (0xFFF00044U)
-#define PRR_PRODUCT_MASK (0x00007F00U)
-#define PRR_CUT_MASK (0x000000FFU)
-#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
-#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
-#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
-#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
-#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
-#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
-#define PRR_PRODUCT_10 (0x00U)
-#define PRR_PRODUCT_11 (0x01U)
-#define PRR_PRODUCT_20 (0x10U)
-#define PRR_PRODUCT_21 (0x11U)
-#define PRR_PRODUCT_30 (0x20U)
+#define PRR 0xFFF00044U
+#define PRR_PRODUCT_MASK 0x00007F00U
+#define PRR_CUT_MASK 0x000000FFU
+#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */
+#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3 */
+#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */
+#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3N */
+#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */
+#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */
+#define PRR_PRODUCT_10 0x00U
+#define PRR_PRODUCT_11 0x01U
+#define PRR_PRODUCT_20 0x10U
+#define PRR_PRODUCT_21 0x11U
+#define PRR_PRODUCT_30 0x20U
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
#define DRAM_CH_CNT 0x04
uint32_t qos_init_ddr_ch;
uint8_t qos_init_ddr_phyvalid;
-
#endif
#define PRR_PRODUCT_ERR(reg) \
- do{ \
+ do { \
ERROR("LSI Product ID(PRR=0x%x) QoS " \
- "initialize not supported.\n",reg); \
+ "initialize not supported.\n", reg); \
panic(); \
- } while(0)
+ } while (0)
#define PRR_CUT_ERR(reg) \
- do{ \
+ do { \
ERROR("LSI Cut ID(PRR=0x%x) QoS " \
- "initialize not supported.\n",reg); \
+ "initialize not supported.\n", reg); \
panic(); \
- } while(0)
+ } while (0)
void rcar_qos_init(void)
{
@@ -390,3 +390,20 @@
return refperiod;
}
#endif
+
+void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos,
+ unsigned int qos_size, bool dbsc_wren)
+{
+ int i;
+
+ /* Register write enable */
+ if (dbsc_wren)
+ io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
+
+ for (i = 0; i < qos_size; i++)
+ io_write_32(qos[i].reg, qos[i].val);
+
+ /* Register write protect */
+ if (dbsc_wren)
+ io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
+}
diff --git a/drivers/staging/renesas/rcar/qos/qos_init.h b/drivers/renesas/rcar/qos/qos_init.h
similarity index 100%
rename from drivers/staging/renesas/rcar/qos/qos_init.h
rename to drivers/renesas/rcar/qos/qos_init.h
diff --git a/drivers/renesas/rcar/qos/qos_reg.h b/drivers/renesas/rcar/qos/qos_reg.h
new file mode 100644
index 0000000..f2012fa
--- /dev/null
+++ b/drivers/renesas/rcar/qos/qos_reg.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_REG_H
+#define QOS_REG_H
+
+#define RCAR_QOS_NONE 3U
+#define RCAR_QOS_TYPE_DEFAULT 0U
+
+#define RCAR_DRAM_SPLIT_LINEAR 0U
+#define RCAR_DRAM_SPLIT_4CH 1U
+#define RCAR_DRAM_SPLIT_2CH 2U
+#define RCAR_DRAM_SPLIT_AUTO 3U
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+
+#define DBSC_BASE 0xE6790000U
+#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
+#define DBSC_AXARB (DBSC_BASE + 0x0800U)
+#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
+#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
+#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
+#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
+#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
+#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
+#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
+#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
+#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
+#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
+#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
+#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
+
+#define AXI_BASE 0xE6784000U
+#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
+#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
+#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
+#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
+#define AXI_MMCR (AXI_BASE + 0x0300U)
+#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
+#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
+#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
+#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
+#define ADSPLCR0_SWP 0x0CU
+
+#define AXI_TR3CR 0xE67D100CU
+#define AXI_TR4CR 0xE67D1014U
+
+#define QOS_BASE0 0xE67E0000U
+#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
+#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
+#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
+#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
+#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
+#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
+#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
+
+#define QOS_BASE1 0xE67F0000U
+#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
+#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
+#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
+#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
+#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
+#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
+#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
+#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
+#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
+#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
+#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
+#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
+#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
+#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
+
+#define GPU_ACT_GRD 0xFD820808U
+#define GPU_ACT0 0xFD820800U
+#define GPU_ACT1 0xFD821800U
+#define GPU_ACT2 0xFD822800U
+#define GPU_ACT3 0xFD823800U
+#define GPU_ACT4 0xFD824800U
+#define GPU_ACT5 0xFD825800U
+#define GPU_ACT6 0xFD826800U
+#define GPU_ACT7 0xFD827800U
+
+#define RT_ACT0 0xFFC50800U
+#define RT_ACT1 0xFFC51800U
+
+#define CPU_ACT0 0xF1300800U
+#define CPU_ACT1 0xF1340800U
+#define CPU_ACT2 0xF1380800U
+#define CPU_ACT3 0xF13C0800U
+
+#define RCAR_REWT_TRAINING_DISABLE 0U
+#define RCAR_REWT_TRAINING_ENABLE 1U
+
+#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
+#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
+#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
+#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
+#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
+#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
+#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
+#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
+
+#endif /* QOS_REG_H */
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S
index 471d7b8..8309bb2 100644
--- a/drivers/renesas/rcar/scif/scif.S
+++ b/drivers/renesas/rcar/scif/scif.S
@@ -1,11 +1,13 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
+#include <console_macros.S>
+#include <drivers/renesas/rcar/console/console.h>
#define SCIF_INTERNAL_CLK 0
#define SCIF_EXTARNAL_CLK 1
@@ -116,49 +118,49 @@
#define CKS_XIN_SCIF_CLK (0x0000)
#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
- .globl console_init
- .globl console_uninit
- .globl console_putc
- .globl console_core_init
- .globl console_core_putc
- .globl console_getc
- .globl console_flush
+ .globl console_rcar_register
+ .globl console_rcar_init
+ .globl console_rcar_putc
+ .globl console_rcar_flush
- /*
- * The console base is in the data section and not in .bss
- * even though it is zero-init. In particular, this allows
- * the console functions to start using this variable before
- * the runtime memory is initialized for images which do not
- * need to copy the .data section from ROM to RAM.
- */
/* -----------------------------------------------
- * int console_init(unsigned long base_addr,
- * unsigned int uart_clk, unsigned int baud_rate)
- * Function to initialize the console without a
- * C Runtime to print debug information. It saves
- * the console base to the data section.
- * In: x0 - console base address
- * w1 - Uart clock in Hz
+ * int console_rcar_register(
+ * uintptr_t base, uint32_t clk, uint32_t baud,
+ * console_rcar_t *console)
+ * Function to initialize and register a new rcar
+ * console. Storage passed in for the console struct
+ * *must* be persistent (i.e. not from the stack).
+ * In: x0 - UART register base address
+ * w1 - UART clock in Hz
* w2 - Baud rate
- * out: return 1 on success.
- * Clobber list : x1 - x3
+ * x3 - pointer to empty console_rcar_t struct
+ * Out: return 1 on success, 0 on error
+ * Clobber list : x0, x1, x2, x6, x7, x14
* -----------------------------------------------
*/
-func console_init
- b console_core_init
-endfunc console_init
+func console_rcar_register
+ mov x7, x30
+ mov x6, x3
+ cbz x6, register_fail
+ str x0, [x6, #CONSOLE_T_RCAR_BASE]
-func console_uninit
- ret
-endfunc console_uninit
+ bl console_rcar_init
+
+ mov x0, x6
+ mov x30, x7
+ finish_console_register rcar, putc=1, getc=0, flush=1
+
+register_fail:
+ ret x7
+endfunc console_rcar_register
/* -----------------------------------------------
- * int console_core_init(unsigned long base_addr,
+ * int console_rcar_init(unsigned long base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
* C Runtime to print debug information. This
- * function will be accessed by console_init and
- * crash reporting.
+ * function will be accessed by console_rcar_register
+ * and crash reporting.
* In: x0 - console base address
* w1 - Uart clock in Hz
* w2 - Baud rate
@@ -166,7 +168,7 @@
* Clobber list : x1, x2
* -----------------------------------------------
*/
-func console_core_init
+func console_rcar_init
ldr x0, =CPG_BASE
ldr w1, [x0, #CPG_SMSTPCR]
and w1, w1, #~MSTP
@@ -261,33 +263,19 @@
mov x0, #1
ret
-endfunc console_core_init
-
- /* ---------------------------------------------
- * int console_putc(int c)
- * Function to output a character over the
- * console. It returns the character printed on
- * success or -1 on error.
- * In : x0 - character to be printed
- * Out : return -1 on error else return character.
- * Clobber list : x1, x2
- * ---------------------------------------------
- */
-func console_putc
- b console_core_putc
-endfunc console_putc
+endfunc console_rcar_init
/* --------------------------------------------------------
- * int console_core_putc(int c, unsigned int base_addr)
+ * int console_rcar_putc(int c, unsigned int base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : w0 - character to be printed
- * x1 - console base address
+ * x1 - pointer to console_t structure
* Out : return -1 on error else return character.
* Clobber list : x2
* --------------------------------------------------------
*/
-func console_core_putc
+func console_rcar_putc
ldr x1, =SCIF_BASE
cmp w0, #0xA
/* Prepend '\r' to '\n' */
@@ -313,24 +301,11 @@
and w2, w2, #~SCFSR_TEND_MASK
strh w2, [x1, #SCIF_SCFSR]
- ret
-endfunc console_core_putc
-
- /* ---------------------------------------------
- * int console_getc(void)
- * Function to get a character from the console.
- * It returns the character grabbed on success
- * or -1 on error.
- * Clobber list : x0, x1
- * ---------------------------------------------
- */
-func console_getc
- mov w0, #-1
ret
-endfunc console_getc
+endfunc console_rcar_putc
/* ---------------------------------------------
- * int console_flush(void)
+ * int console_rcar_flush(void)
* Function to force a write of all buffered
* data that hasn't been output. It returns 0
* upon successful completion, otherwise it
@@ -338,7 +313,7 @@
* Clobber list : x0, x1
* ---------------------------------------------
*/
-func console_flush
+func console_rcar_flush
ldr x0, =SCIF_BASE
1:
/* Check TEND flag */
@@ -354,4 +329,4 @@
mov w0, #0
ret
-endfunc console_flush
+endfunc console_rcar_flush
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 11fd666..76e6e6f 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -20,7 +20,6 @@
#include <drivers/generic_delay_timer.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp1_clk.h>
-#include <drivers/st/stm32mp1_clkfunc.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include <lib/mmio.h>
@@ -40,6 +39,15 @@
#define HSIDIV_TIMEOUT TIMEOUT_US_200MS
#define OSCRDY_TIMEOUT TIMEOUT_US_1S
+const char *stm32mp_osc_node_label[NB_OSC] = {
+ [_LSI] = "clk-lsi",
+ [_LSE] = "clk-lse",
+ [_HSI] = "clk-hsi",
+ [_HSE] = "clk-hse",
+ [_CSI] = "clk-csi",
+ [_I2S_CKIN] = "i2s_ckin",
+};
+
enum stm32mp1_parent_id {
/* Oscillators are defined in enum stm32mp_osc_id */
@@ -83,7 +91,7 @@
_STGEN_SEL,
_I2C46_SEL,
_SPI6_SEL,
- _USART1_SEL,
+ _UART1_SEL,
_RNG1_SEL,
_UART6_SEL,
_UART24_SEL,
@@ -93,8 +101,8 @@
_SDMMC3_SEL,
_QSPI_SEL,
_FMC_SEL,
- _ASS_SEL,
- _MSS_SEL,
+ _AXIS_SEL,
+ _MCUS_SEL,
_USBPHY_SEL,
_USBO_SEL,
_PARENT_SEL_NB,
@@ -246,13 +254,13 @@
.fixed = (f), \
}
-#define _CLK_PARENT(idx, off, s, m, p) \
- [(idx)] = { \
- .offset = (off), \
- .src = (s), \
- .msk = (m), \
- .parent = (p), \
- .nb_parent = ARRAY_SIZE(p) \
+#define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \
+ [_ ## _label ## _SEL] = { \
+ .offset = _rcc_selr, \
+ .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \
+ .msk = _rcc_selr ## _ ## _label ## SRC_MASK, \
+ .parent = (_parents), \
+ .nb_parent = ARRAY_SIZE(_parents) \
}
#define _CLK_PLL(idx, type, off1, off2, off3, \
@@ -315,6 +323,8 @@
_CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
_CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
+ _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
+
_CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
_CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
_CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
@@ -322,7 +332,7 @@
_CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
_CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
_CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
- _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _USART1_SEL),
+ _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
_CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
_CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5),
_CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5),
@@ -430,25 +440,25 @@
};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
- _CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
- _CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
- _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
- _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
- _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
- _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents),
- _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents),
- _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
- _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents),
- _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents),
- _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents),
- _CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, sdmmc12_parents),
- _CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, sdmmc3_parents),
- _CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
- _CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
- _CLK_PARENT(_ASS_SEL, RCC_ASSCKSELR, 0, 0x3, ass_parents),
- _CLK_PARENT(_MSS_SEL, RCC_MSSCKSELR, 0, 0x3, mss_parents),
- _CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
- _CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
+ _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents),
+ _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents),
+ _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents),
+ _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents),
+ _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents),
+ _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
+ _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
+ _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
+ _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
+ _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents),
+ _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents),
+ _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents),
+ _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
+ _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
+ _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
+ _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents),
+ _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents),
+ _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
+ _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
};
/* Define characteristic of PLL according type */
@@ -648,7 +658,7 @@
}
sel = clk_sel_ref(s);
- p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & sel->msk;
+ p_sel = (mmio_read_32(rcc_base + sel->offset) & sel->msk) >> sel->src;
if (p_sel < sel->nb_parent) {
return (int)sel->parent[p_sel];
}
@@ -1305,7 +1315,11 @@
const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
- mmio_write_32(pllxcr, RCC_PLLNCR_PLLON);
+ /* Preserve RCC_PLLNCR_SSCG_CTRL value */
+ mmio_clrsetbits_32(pllxcr,
+ RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
+ RCC_PLLNCR_DIVREN,
+ RCC_PLLNCR_PLLON);
}
static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output)
@@ -1434,6 +1448,9 @@
RCC_PLLNCSGR_SSCG_MODE_MASK;
mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg);
+
+ mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr,
+ RCC_PLLNCR_SSCG_CTRL);
}
static int stm32mp1_set_clksrc(unsigned int clksrc)
@@ -1516,9 +1533,6 @@
}
}
-#define CNTCVL_OFF 0x008
-#define CNTCVU_OFF 0x00C
-
static void stm32mp1_stgen_config(void)
{
uintptr_t stgen;
diff --git a/drivers/st/clk/stm32mp1_clkfunc.c b/drivers/st/clk/stm32mp1_clkfunc.c
deleted file mode 100644
index 1aa05bf..0000000
--- a/drivers/st/clk/stm32mp1_clkfunc.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <errno.h>
-
-#include <libfdt.h>
-
-#include <platform_def.h>
-
-#include <drivers/st/stm32_gpio.h>
-#include <drivers/st/stm32mp_clkfunc.h>
-#include <drivers/st/stm32mp1_clk.h>
-#include <drivers/st/stm32mp1_clkfunc.h>
-#include <dt-bindings/clock/stm32mp1-clksrc.h>
-
-const char *stm32mp_osc_node_label[NB_OSC] = {
- [_LSI] = "clk-lsi",
- [_LSE] = "clk-lse",
- [_HSI] = "clk-hsi",
- [_HSE] = "clk-hse",
- [_CSI] = "clk-csi",
- [_I2S_CKIN] = "i2s_ckin",
-};
-
-/*
- * Get the frequency of an oscillator from its name in device tree.
- * @param name: oscillator name
- * @param freq: stores the frequency of the oscillator
- * @return: 0 on success, and a negative FDT/ERRNO error code on failure.
- */
-int fdt_osc_read_freq(const char *name, uint32_t *freq)
-{
- int node, subnode;
- void *fdt;
-
- if (fdt_get_address(&fdt) == 0) {
- return -ENOENT;
- }
-
- node = fdt_path_offset(fdt, "/clocks");
- if (node < 0) {
- return -FDT_ERR_NOTFOUND;
- }
-
- fdt_for_each_subnode(subnode, fdt, node) {
- const char *cchar;
- int ret;
-
- cchar = fdt_get_name(fdt, subnode, &ret);
- if (cchar == NULL) {
- return ret;
- }
-
- if (strncmp(cchar, name, (size_t)ret) == 0) {
- const fdt32_t *cuint;
-
- cuint = fdt_getprop(fdt, subnode, "clock-frequency",
- &ret);
- if (cuint == NULL) {
- return ret;
- }
-
- *freq = fdt32_to_cpu(*cuint);
-
- return 0;
- }
- }
-
- /* Oscillator not found, freq=0 */
- *freq = 0;
- return 0;
-}
-
-/*
- * Check the presence of an oscillator property from its id.
- * @param osc_id: oscillator ID
- * @param prop_name: property name
- * @return: true/false regarding search result.
- */
-bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
-{
- int node, subnode;
- void *fdt;
-
- if (fdt_get_address(&fdt) == 0) {
- return false;
- }
-
- if (osc_id >= NB_OSC) {
- return false;
- }
-
- node = fdt_path_offset(fdt, "/clocks");
- if (node < 0) {
- return false;
- }
-
- fdt_for_each_subnode(subnode, fdt, node) {
- const char *cchar;
- int ret;
-
- cchar = fdt_get_name(fdt, subnode, &ret);
- if (cchar == NULL) {
- return false;
- }
-
- if (strncmp(cchar, stm32mp_osc_node_label[osc_id],
- (size_t)ret) != 0) {
- continue;
- }
-
- if (fdt_getprop(fdt, subnode, prop_name, NULL) != NULL) {
- return true;
- }
- }
-
- return false;
-}
-
-/*
- * Get the value of a oscillator property from its ID.
- * @param osc_id: oscillator ID
- * @param prop_name: property name
- * @param dflt_value: default value
- * @return oscillator value on success, default value if property not found.
- */
-uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
- const char *prop_name, uint32_t dflt_value)
-{
- int node, subnode;
- void *fdt;
-
- if (fdt_get_address(&fdt) == 0) {
- return dflt_value;
- }
-
- if (osc_id >= NB_OSC) {
- return dflt_value;
- }
-
- node = fdt_path_offset(fdt, "/clocks");
- if (node < 0) {
- return dflt_value;
- }
-
- fdt_for_each_subnode(subnode, fdt, node) {
- const char *cchar;
- int ret;
-
- cchar = fdt_get_name(fdt, subnode, &ret);
- if (cchar == NULL) {
- return dflt_value;
- }
-
- if (strncmp(cchar, stm32mp_osc_node_label[osc_id],
- (size_t)ret) != 0) {
- continue;
- }
-
- return fdt_read_uint32_default(subnode, prop_name, dflt_value);
- }
-
- return dflt_value;
-}
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index 16acef0..87c8e2b 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -16,6 +16,147 @@
#define DT_STGEN_COMPAT "st,stm32-stgen"
/*
+ * Get the frequency of an oscillator from its name in device tree.
+ * @param name: oscillator name
+ * @param freq: stores the frequency of the oscillator
+ * @return: 0 on success, and a negative FDT/ERRNO error code on failure.
+ */
+int fdt_osc_read_freq(const char *name, uint32_t *freq)
+{
+ int node, subnode;
+ void *fdt;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -ENOENT;
+ }
+
+ node = fdt_path_offset(fdt, "/clocks");
+ if (node < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ fdt_for_each_subnode(subnode, fdt, node) {
+ const char *cchar;
+ int ret;
+
+ cchar = fdt_get_name(fdt, subnode, &ret);
+ if (cchar == NULL) {
+ return ret;
+ }
+
+ if (strncmp(cchar, name, (size_t)ret) == 0) {
+ const fdt32_t *cuint;
+
+ cuint = fdt_getprop(fdt, subnode, "clock-frequency",
+ &ret);
+ if (cuint == NULL) {
+ return ret;
+ }
+
+ *freq = fdt32_to_cpu(*cuint);
+
+ return 0;
+ }
+ }
+
+ /* Oscillator not found, freq=0 */
+ *freq = 0;
+ return 0;
+}
+
+/*
+ * Check the presence of an oscillator property from its id.
+ * @param osc_id: oscillator ID
+ * @param prop_name: property name
+ * @return: true/false regarding search result.
+ */
+bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
+{
+ int node, subnode;
+ void *fdt;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return false;
+ }
+
+ if (osc_id >= NB_OSC) {
+ return false;
+ }
+
+ node = fdt_path_offset(fdt, "/clocks");
+ if (node < 0) {
+ return false;
+ }
+
+ fdt_for_each_subnode(subnode, fdt, node) {
+ const char *cchar;
+ int ret;
+
+ cchar = fdt_get_name(fdt, subnode, &ret);
+ if (cchar == NULL) {
+ return false;
+ }
+
+ if (strncmp(cchar, stm32mp_osc_node_label[osc_id],
+ (size_t)ret) != 0) {
+ continue;
+ }
+
+ if (fdt_getprop(fdt, subnode, prop_name, NULL) != NULL) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/*
+ * Get the value of a oscillator property from its ID.
+ * @param osc_id: oscillator ID
+ * @param prop_name: property name
+ * @param dflt_value: default value
+ * @return oscillator value on success, default value if property not found.
+ */
+uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
+ const char *prop_name, uint32_t dflt_value)
+{
+ int node, subnode;
+ void *fdt;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return dflt_value;
+ }
+
+ if (osc_id >= NB_OSC) {
+ return dflt_value;
+ }
+
+ node = fdt_path_offset(fdt, "/clocks");
+ if (node < 0) {
+ return dflt_value;
+ }
+
+ fdt_for_each_subnode(subnode, fdt, node) {
+ const char *cchar;
+ int ret;
+
+ cchar = fdt_get_name(fdt, subnode, &ret);
+ if (cchar == NULL) {
+ return dflt_value;
+ }
+
+ if (strncmp(cchar, stm32mp_osc_node_label[osc_id],
+ (size_t)ret) != 0) {
+ continue;
+ }
+
+ return fdt_read_uint32_default(subnode, prop_name, dflt_value);
+ }
+
+ return dflt_value;
+}
+
+/*
* Get the RCC node offset from the device tree
* @param fdt: Device tree reference
* @return: Node offset or a negative value on error
diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
deleted file mode 100644
index b115d63..0000000
--- a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
+++ /dev/null
@@ -1,581 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <common/debug.h>
-#include "qos_init_d3.h"
-
-
-#define RCAR_QOS_VERSION "rev.0.05"
-
-#define RCAR_QOS_NONE (3U)
-#define RCAR_QOS_TYPE_DEFAULT (0U)
-
-#define RCAR_DRAM_SPLIT_LINEAR (0U)
-#define RCAR_DRAM_SPLIT_4CH (1U)
-#define RCAR_DRAM_SPLIT_2CH (2U)
-#define RCAR_DRAM_SPLIT_AUTO (3U)
-
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-
-#define DBSC_BASE (0xE6790000U)
-#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
-#define DBSC_AXARB (DBSC_BASE + 0x0800U)
-#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
-#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
-#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
-#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
-#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
-#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
-#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
-#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
-#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
-#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
-#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
-#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
-#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
-#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
-#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
-#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
-#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
-#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
-#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
-#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
-#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
-#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
-#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
-#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
-#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
-#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
-#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
-#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
-#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
-#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
-#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
-#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
-#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
-#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
-#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
-#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
-#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
-#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
-#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
-#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
-#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
-#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
-#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
-#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
-#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
-#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
-#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
-#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
-
-#define AXI_BASE (0xE6784000U)
-#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
-#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
-
-#define MSTAT_BASE (0xE67E0000U)
-#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
-#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
-#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
-#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
-#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
-#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
-#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
-
-#define RALLOC_BASE (0xE67F0000U)
-#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
-#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
-#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
-#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
-#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
-#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
-#define RALLOC_EC (RALLOC_BASE + 0x003CU)
-#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
-#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
-#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
-#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
-#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U)
-#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
-#define RALLOC_TICKDUPL (RALLOC_BASE + 0x0088U)
-
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-static inline void io_write_32(uintptr_t addr, uint32_t value)
-{
- *(volatile uint32_t*)addr = value;
-}
-
-static inline void io_write_64(uintptr_t addr, uint64_t value)
-{
- *(volatile uint64_t*)addr = value;
-}
-
-typedef struct {
- uintptr_t addr;
- uint64_t value;
-} mstat_slot_t;
-
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-static const mstat_slot_t mstat_fix[] = {
- {0x0000U, 0x0000000000000000U},
- {0x0008U, 0x0000000000000000U},
- {0x0010U, 0x0000000000000000U},
- {0x0018U, 0x0000000000000000U},
- {0x0020U, 0x0000000000000000U},
- {0x0028U, 0x0000000000000000U},
- {0x0030U, 0x001004340000FFFFU},
- {0x0038U, 0x001004140000FFFFU},
- {0x0040U, 0x0000000000000000U},
- {0x0048U, 0x0000000000000000U},
- {0x0050U, 0x0000000000000000U},
- {0x0058U, 0x00140B030000FFFFU},
- {0x0060U, 0x001408610000FFFFU},
- {0x0068U, 0x0000000000000000U},
- {0x0070U, 0x0000000000000000U},
- {0x0078U, 0x0000000000000000U},
- {0x0080U, 0x0000000000000000U},
- {0x0088U, 0x001410620000FFFFU},
- {0x0090U, 0x0000000000000000U},
- {0x0098U, 0x0000000000000000U},
- {0x00A0U, 0x000C041C0000FFFFU},
- {0x00A8U, 0x000C04090000FFFFU},
- {0x00B0U, 0x000C04110000FFFFU},
- {0x00B8U, 0x0000000000000000U},
- {0x00C0U, 0x000C041C0000FFFFU},
- {0x00C8U, 0x000C04090000FFFFU},
- {0x00D0U, 0x000C04110000FFFFU},
- {0x00D8U, 0x0000000000000000U},
- {0x00E0U, 0x0000000000000000U},
- {0x00E8U, 0x0000000000000000U},
- {0x00F0U, 0x001018570000FFFFU},
- {0x00F8U, 0x0000000000000000U},
- {0x0100U, 0x0000000000000000U},
- {0x0108U, 0x0000000000000000U},
- {0x0110U, 0x001008570000FFFFU},
- {0x0118U, 0x0000000000000000U},
- {0x0120U, 0x0000000000000000U},
- {0x0128U, 0x0000000000000000U},
- {0x0130U, 0x0000000000000000U},
- {0x0138U, 0x0000000000000000U},
- {0x0140U, 0x0000000000000000U},
- {0x0148U, 0x0000000000000000U},
- {0x0150U, 0x001008520000FFFFU},
- {0x0158U, 0x0000000000000000U},
- {0x0160U, 0x0000000000000000U},
- {0x0168U, 0x0000000000000000U},
- {0x0170U, 0x0000000000000000U},
- {0x0178U, 0x0000000000000000U},
- {0x0180U, 0x0000000000000000U},
- {0x0188U, 0x0000000000000000U},
- {0x0190U, 0x00100CA30000FFFFU},
- {0x0198U, 0x0000000000000000U},
- {0x01A0U, 0x0000000000000000U},
- {0x01A8U, 0x0000000000000000U},
- {0x01B0U, 0x0000000000000000U},
- {0x01B8U, 0x0000000000000000U},
- {0x01C0U, 0x0000000000000000U},
- {0x01C8U, 0x0000000000000000U},
- {0x01D0U, 0x0000000000000000U},
- {0x01D8U, 0x0000000000000000U},
- {0x01E0U, 0x0000000000000000U},
- {0x01E8U, 0x000C04020000FFFFU},
- {0x01F0U, 0x0000000000000000U},
- {0x01F8U, 0x0000000000000000U},
- {0x0200U, 0x0000000000000000U},
- {0x0208U, 0x000C04090000FFFFU},
- {0x0210U, 0x0000000000000000U},
- {0x0218U, 0x0000000000000000U},
- {0x0220U, 0x0000000000000000U},
- {0x0228U, 0x0000000000000000U},
- {0x0230U, 0x0000000000000000U},
- {0x0238U, 0x0000000000000000U},
- {0x0240U, 0x0000000000000000U},
- {0x0248U, 0x0000000000000000U},
- {0x0250U, 0x0000000000000000U},
- {0x0258U, 0x0000000000000000U},
- {0x0260U, 0x0000000000000000U},
- {0x0268U, 0x001410040000FFFFU},
- {0x0270U, 0x001404020000FFFFU},
- {0x0278U, 0x0000000000000000U},
- {0x0280U, 0x0000000000000000U},
- {0x0288U, 0x0000000000000000U},
- {0x0290U, 0x001410040000FFFFU},
- {0x0298U, 0x001404020000FFFFU},
- {0x02A0U, 0x000C04050000FFFFU},
- {0x02A8U, 0x000C04050000FFFFU},
- {0x02B0U, 0x0000000000000000U},
- {0x02B8U, 0x0000000000000000U},
- {0x02C0U, 0x0000000000000000U},
- {0x02C8U, 0x0000000000000000U},
- {0x02D0U, 0x000C04050000FFFFU},
- {0x02D8U, 0x000C04050000FFFFU},
- {0x02E0U, 0x0000000000000000U},
- {0x02E8U, 0x0000000000000000U},
- {0x02F0U, 0x0000000000000000U},
- {0x02F8U, 0x0000000000000000U},
- {0x0300U, 0x0000000000000000U},
- {0x0308U, 0x0000000000000000U},
- {0x0310U, 0x0000000000000000U},
- {0x0318U, 0x0000000000000000U},
- {0x0320U, 0x0000000000000000U},
- {0x0328U, 0x0000000000000000U},
- {0x0330U, 0x0000000000000000U},
- {0x0338U, 0x0000000000000000U},
- {0x0340U, 0x0000000000000000U},
- {0x0348U, 0x0000000000000000U},
- {0x0350U, 0x0000000000000000U},
- {0x0358U, 0x0000000000000000U},
- {0x0360U, 0x0000000000000000U},
- {0x0368U, 0x0000000000000000U},
- {0x0370U, 0x000C04020000FFFFU},
- {0x0378U, 0x000C04020000FFFFU},
- {0x0380U, 0x000C04090000FFFFU},
- {0x0388U, 0x000C04090000FFFFU},
- {0x0390U, 0x0000000000000000U},
-};
-
-static const mstat_slot_t mstat_be[] = {
- {0x0000U, 0x0000000000000000U},
- {0x0008U, 0x0000000000000000U},
- {0x0010U, 0x0000000000000000U},
- {0x0018U, 0x0000000000000000U},
- {0x0020U, 0x0000000000000000U},
- {0x0028U, 0x0000000000000000U},
- {0x0030U, 0x0000000000000000U},
- {0x0038U, 0x0000000000000000U},
- {0x0040U, 0x0000000000000000U},
- {0x0048U, 0x0000000000000000U},
- {0x0050U, 0x0000000000000000U},
- {0x0058U, 0x0000000000000000U},
- {0x0060U, 0x0000000000000000U},
- {0x0068U, 0x0000000000000000U},
- {0x0070U, 0x0000000000000000U},
- {0x0078U, 0x0000000000000000U},
- {0x0080U, 0x0000000000000000U},
- {0x0088U, 0x0000000000000000U},
- {0x0090U, 0x0000000000000000U},
- {0x0098U, 0x0000000000000000U},
- {0x00A0U, 0x0000000000000000U},
- {0x00A8U, 0x0000000000000000U},
- {0x00B0U, 0x0000000000000000U},
- {0x00B8U, 0x0000000000000000U},
- {0x00C0U, 0x0000000000000000U},
- {0x00C8U, 0x0000000000000000U},
- {0x00D0U, 0x0000000000000000U},
- {0x00D8U, 0x0000000000000000U},
- {0x00E0U, 0x0000000000000000U},
- {0x00E8U, 0x0000000000000000U},
- {0x00F0U, 0x0000000000000000U},
- {0x00F8U, 0x0000000000000000U},
- {0x0100U, 0x0000000000000000U},
- {0x0108U, 0x0000000000000000U},
- {0x0110U, 0x0000000000000000U},
- {0x0118U, 0x0000000000000000U},
- {0x0120U, 0x0000000000000000U},
- {0x0128U, 0x0000000000000000U},
- {0x0130U, 0x0000000000000000U},
- {0x0138U, 0x0000000000000000U},
- {0x0140U, 0x0000000000000000U},
- {0x0148U, 0x0000000000000000U},
- {0x0150U, 0x0000000000000000U},
- {0x0158U, 0x0000000000000000U},
- {0x0160U, 0x0000000000000000U},
- {0x0168U, 0x0000000000000000U},
- {0x0170U, 0x0000000000000000U},
- {0x0178U, 0x0000000000000000U},
- {0x0180U, 0x0000000000000000U},
- {0x0188U, 0x0000000000000000U},
- {0x0190U, 0x0000000000000000U},
- {0x0198U, 0x0000000000000000U},
- {0x01A0U, 0x0000000000000000U},
- {0x01A8U, 0x0000000000000000U},
- {0x01B0U, 0x0000000000000000U},
- {0x01B8U, 0x0000000000000000U},
- {0x01C0U, 0x00110090060FA001U},
- {0x01C8U, 0x00110090060FA001U},
- {0x01D0U, 0x0000000000000000U},
- {0x01D8U, 0x0000000000000000U},
- {0x01E0U, 0x0000000000000000U},
- {0x01E8U, 0x0000000000000000U},
- {0x01F0U, 0x0011001006004401U},
- {0x01F8U, 0x0000000000000000U},
- {0x0200U, 0x0000000000000000U},
- {0x0208U, 0x0000000000000000U},
- {0x0210U, 0x0011001006004401U},
- {0x0218U, 0x0011001006009801U},
- {0x0220U, 0x0011001006009801U},
- {0x0228U, 0x0000000000000000U},
- {0x0230U, 0x0011001006009801U},
- {0x0238U, 0x0011001006009801U},
- {0x0240U, 0x0000000000000000U},
- {0x0248U, 0x0000000000000000U},
- {0x0250U, 0x0000000000000000U},
- {0x0258U, 0x0000000000000000U},
- {0x0260U, 0x0000000000000000U},
- {0x0268U, 0x0000000000000000U},
- {0x0270U, 0x0000000000000000U},
- {0x0278U, 0x0000000000000000U},
- {0x0280U, 0x0000000000000000U},
- {0x0288U, 0x0000000000000000U},
- {0x0290U, 0x0000000000000000U},
- {0x0298U, 0x0000000000000000U},
- {0x02A0U, 0x0000000000000000U},
- {0x02A8U, 0x0000000000000000U},
- {0x02B0U, 0x0000000000000000U},
- {0x02B8U, 0x0011001006003401U},
- {0x02C0U, 0x0000000000000000U},
- {0x02C8U, 0x0000000000000000U},
- {0x02D0U, 0x0000000000000000U},
- {0x02D8U, 0x0000000000000000U},
- {0x02E0U, 0x0000000000000000U},
- {0x02E8U, 0x0011001006003401U},
- {0x02F0U, 0x00110090060FA001U},
- {0x02F8U, 0x00110090060FA001U},
- {0x0300U, 0x0000000000000000U},
- {0x0308U, 0x0000000000000000U},
- {0x0310U, 0x0000000000000000U},
- {0x0318U, 0x0012001006003401U},
- {0x0320U, 0x0000000000000000U},
- {0x0328U, 0x0000000000000000U},
- {0x0330U, 0x0000000000000000U},
- {0x0338U, 0x0000000000000000U},
- {0x0340U, 0x0000000000000000U},
- {0x0348U, 0x0000000000000000U},
- {0x0350U, 0x0000000000000000U},
- {0x0358U, 0x00120090060FA001U},
- {0x0360U, 0x00120090060FA001U},
- {0x0368U, 0x0012001006003401U},
- {0x0370U, 0x0000000000000000U},
- {0x0378U, 0x0000000000000000U},
- {0x0380U, 0x0000000000000000U},
- {0x0388U, 0x0000000000000000U},
- {0x0390U, 0x0012001006003401U},
-};
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md=0;
-
- /* BUFCAM settings */
- //DBSC_DBCAM0CNF0 not set
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
- io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0
- //DBSC_DBSCHCNT1 not set
- io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
- io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
-
- md = (*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 19;
-
- switch (md) {
- case 0x0: //MD19=0 : DDR3L-1600, 4GByte(1GByte x4)
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- default: //MD19=1 : DDR3L-1856, 4GByte(1GByte x4)
- /* DDR1856 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
- io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
- io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
- io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
- //DBSC_DBSCHQOS_1_0 not set
- //DBSC_DBSCHQOS_1_1 not set
- //DBSC_DBSCHQOS_1_2 not set
- //DBSC_DBSCHQOS_1_3 not set
- //DBSC_DBSCHQOS_2_0 not set
- //DBSC_DBSCHQOS_2_1 not set
- //DBSC_DBSCHQOS_2_2 not set
- //DBSC_DBSCHQOS_2_3 not set
- //DBSC_DBSCHQOS_3_0 not set
- //DBSC_DBSCHQOS_3_1 not set
- //DBSC_DBSCHQOS_3_2 not set
- //DBSC_DBSCHQOS_3_3 not set
- io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
- io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
- io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
- io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
- //DBSC_DBSCHQOS_5_0 not set
- //DBSC_DBSCHQOS_5_1 not set
- //DBSC_DBSCHQOS_5_2 not set
- //DBSC_DBSCHQOS_5_3 not set
- //DBSC_DBSCHQOS_6_0 not set
- //DBSC_DBSCHQOS_6_1 not set
- //DBSC_DBSCHQOS_6_2 not set
- //DBSC_DBSCHQOS_6_3 not set
- //DBSC_DBSCHQOS_7_0 not set
- //DBSC_DBSCHQOS_7_1 not set
- //DBSC_DBSCHQOS_7_2 not set
- //DBSC_DBSCHQOS_7_3 not set
- //DBSC_DBSCHQOS_8_0 not set
- //DBSC_DBSCHQOS_8_1 not set
- //DBSC_DBSCHQOS_8_2 not set
- //DBSC_DBSCHQOS_8_3 not set
- io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
- io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
- io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
- io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
- //DBSC_DBSCHQOS_10_0 not set
- //DBSC_DBSCHQOS_10_1 not set
- //DBSC_DBSCHQOS_10_2 not set
- //DBSC_DBSCHQOS_10_3 not set
- //DBSC_DBSCHQOS_11_0 not set
- //DBSC_DBSCHQOS_11_1 not set
- //DBSC_DBSCHQOS_11_2 not set
- //DBSC_DBSCHQOS_11_3 not set
- //DBSC_DBSCHQOS_12_0 not set
- //DBSC_DBSCHQOS_12_1 not set
- //DBSC_DBSCHQOS_12_2 not set
- //DBSC_DBSCHQOS_12_3 not set
- io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
- io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
- io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
- io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
- io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
- io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
- io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
- io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
- io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
- io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
-}
-
-void qos_init_d3(void)
-{
- io_write_32(DBSC_DBSYSCNT0, 0x00001234);
-
- dbsc_setting();
-
- /* DRAM Split Address mapping */
-#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
- ERROR("DRAM Split 4ch not supported.(D3)");
- panic();
-#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
- ERROR("DRAM Split 2ch not supported.(D3)");
- panic();
-#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
- ERROR("DRAM Split Auto not supported.(D3)");
- panic();
-#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
-/* NOTICE("BL2: DRAM Split is OFF\n"); */
- /* Split setting(DDR 1ch) */
- io_write_32(AXI_ADSPLCR0, 0x00000000U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- ERROR("DRAM split is an invalid value.(D3)");
- panic();
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
- /* Resource Alloc setting */
- io_write_32(RALLOC_RAS, 0x00000020U);
- io_write_32(RALLOC_FIXTH, 0x000F0005U);
- io_write_32(RALLOC_RAEN, 0x00000001U);
- io_write_32(RALLOC_REGGD, 0x00000000U);
- io_write_64(RALLOC_DANN, 0x0404020002020201U);
- io_write_32(RALLOC_DANT, 0x00100804U);
- io_write_32(RALLOC_EC, 0x00000000U);
- io_write_64(RALLOC_EMS, 0x0000000000000000U);
- io_write_32(RALLOC_FSS, 0x0000000AU);
- io_write_32(RALLOC_INSFC, 0xC7840001U);
- io_write_32(RALLOC_BERR, 0x00000000U);
- io_write_32(RALLOC_EARLYR, 0x00000000U);
- io_write_32(RALLOC_RACNT0, 0x00010003U);
- io_write_32(RALLOC_TICKDUPL, 0x00000000U);
-
- /* GPU setting */
- io_write_32(0xFD812030U, 0x00000000U);
-
- /* MSTAT setting */
- io_write_32(MSTAT_SL_INIT, 0x030500ACU);
- io_write_32(MSTAT_REF_ARS, 0x00780000U);
-
- /* MSTAT SRAM setting */
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
- mstat_fix[i].value);
- io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
- mstat_fix[i].value);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
- mstat_be[i].value);
- io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
- mstat_be[i].value);
- }
- }
-
- /* 3DG bus Leaf setting */
- io_write_32(0xFD820808U, 0x00001234U);
- io_write_32(0xFD820800U, 0x00000000U);
- io_write_32(0xFD821800U, 0x00000000U);
- io_write_32(0xFD822800U, 0x00000000U);
- io_write_32(0xFD823800U, 0x00000000U);
-
- /* RT bus Leaf setting */
- io_write_32(0xF1300800U, 0x00000003U);
- io_write_32(0xF1340800U, 0x00000003U);
- io_write_32(0xFFC50800U, 0x00000000U);
- io_write_32(0xFFC51800U, 0x00000000U);
-
- /* Resource Alloc start */
- io_write_32(RALLOC_RAEN, 0x00000001U);
-
- /* MSTAT start */
- io_write_32(MSTAT_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- /* Resource Alloc setting */
- io_write_32(RALLOC_EC, 0x00000000U);
- /* Resource Alloc start */
- io_write_32(RALLOC_RAEN, 0x00000001U);
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
- io_write_32(DBSC_DBSYSCNT0, 0x00000000);
-}
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
deleted file mode 100644
index db51912..0000000
--- a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "../qos_reg.h"
-#include "qos_init_e3_v10.h"
-
-#define RCAR_QOS_VERSION "rev.0.05"
-
-#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
-#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
-
-#define REF_ARS_ARBSTOPCYCLE_E3 (((SL_INIT_SSLOTCLK_E3) - 5U) << 16U)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_e3_v10_mstat390.h"
-#else
-#include "qos_init_e3_v10_mstat780.h"
-#endif
-
-#endif
-
-static void dbsc_setting(void)
-{
- /* Register write enable */
- io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
-
- /* BUFCAM settings */
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218);
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
- io_write_32(DBSC_DBSCHCNT0, 0x000F0037);
- io_write_32(DBSC_DBSCHSZ0, 0x00000001);
- io_write_32(DBSC_DBSCHRW0, 0x22421111);
-
- /* DDR3 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
- io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
- io_write_32(DBSC_DBSCHQOS02, 0x00000000);
- io_write_32(DBSC_DBSCHQOS03, 0x00000000);
- io_write_32(DBSC_DBSCHQOS40, 0x00000300);
- io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
- io_write_32(DBSC_DBSCHQOS42, 0x00000200);
- io_write_32(DBSC_DBSCHQOS43, 0x00000100);
- io_write_32(DBSC_DBSCHQOS90, 0x00000100);
- io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS93, 0x00000040);
- io_write_32(DBSC_DBSCHQOS130, 0x00000100);
- io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS133, 0x00000040);
- io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
- io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
- io_write_32(DBSC_DBSCHQOS142, 0x00000080);
- io_write_32(DBSC_DBSCHQOS143, 0x00000040);
- io_write_32(DBSC_DBSCHQOS150, 0x00000040);
- io_write_32(DBSC_DBSCHQOS151, 0x00000030);
- io_write_32(DBSC_DBSCHQOS152, 0x00000020);
- io_write_32(DBSC_DBSCHQOS153, 0x00000010);
-
- /* Register write protect */
- io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
-}
-
-void qos_init_e3_v10(void)
-{
- dbsc_setting();
-
- /* DRAM Split Address mapping */
-#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
-#if RCAR_LSI == RCAR_E3
-#error "Don't set DRAM Split 4ch(E3)"
-#else
- ERROR("DRAM Split 4ch not supported.(E3)");
- panic();
-#endif
-#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
-#if RCAR_LSI == RCAR_E3
-#error "Don't set DRAM Split 2ch(E3)"
-#else
- ERROR("DRAM Split 2ch not supported.(E3)");
- panic();
-#endif
-#else
- NOTICE("BL2: DRAM Split is OFF\n");
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
- NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
-#else
- NOTICE("BL2: DRAM refresh interval 7.8 usec\n");
-#endif
-
- io_write_32(QOSCTRL_RAS, 0x00000020U);
- io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
- io_write_32(QOSCTRL_DANT, 0x00100804U);
- io_write_32(QOSCTRL_FSS, 0x0000000AU);
- io_write_32(QOSCTRL_INSFC, 0x06330001U);
- io_write_32(QOSCTRL_EARLYR, 0x00000000U);
- io_write_32(QOSCTRL_RACNT0, 0x00010003U);
-
- io_write_32(QOSCTRL_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
- SL_INIT_SSLOTCLK_E3);
- io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_E3);
-
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
- io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
- io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
- }
- }
-
- /* RT bus Leaf setting */
- io_write_32(RT_ACT0, 0x00000000U);
- io_write_32(RT_ACT1, 0x00000000U);
-
- /* CCI bus Leaf setting */
- io_write_32(CPU_ACT0, 0x00000003U);
- io_write_32(CPU_ACT1, 0x00000003U);
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-
- io_write_32(QOSCTRL_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif
-}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
deleted file mode 100644
index 21aa3df..0000000
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "qos_init_h3_v10.h"
-
-#define RCAR_QOS_VERSION "rev.0.36"
-
-#define RCAR_QOS_NONE (3U)
-#define RCAR_QOS_TYPE_DEFAULT (0U)
-
-#define RCAR_DRAM_SPLIT_LINEAR (0U)
-#define RCAR_DRAM_SPLIT_4CH (1U)
-#define RCAR_DRAM_SPLIT_2CH (2U)
-#define RCAR_DRAM_SPLIT_AUTO (3U)
-
-#define AXI_BASE (0xE6784000U)
-#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
-#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
-#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
-#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
-#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
-#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
-#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
-#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
-#define ADSPLCR0_SWP (0x0CU)
-
-#define MSTAT_BASE (0xE67E0000U)
-#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
-#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
-#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
-#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
-#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
-#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
-#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
-
-#define RALLOC_BASE (0xE67F0000U)
-#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
-#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
-#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
-#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
-#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
-#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
-#define RALLOC_EC (RALLOC_BASE + 0x003CU)
-#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
-#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
-#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-static const mstat_slot_t mstat_fix[] = {
- {0x0000U, 0x0000000000000000UL},
- {0x0008U, 0x0000000000000000UL},
- {0x0010U, 0x0000000000000000UL},
- {0x0018U, 0x0000000000000000UL},
- {0x0020U, 0x0000000000000000UL},
- {0x0028U, 0x0000000000000000UL},
- {0x0030U, 0x0000000000000000UL},
- {0x0038U, 0x0000000000000000UL},
- {0x0040U, 0x00140C050000FFFFUL},
- {0x0048U, 0x0000000000000000UL},
- {0x0050U, 0x0000000000000000UL},
- {0x0058U, 0x001404030000FFFFUL},
- {0x0060U, 0x001408060000FFFFUL},
- {0x0068U, 0x0000000000000000UL},
- {0x0070U, 0x0000000000000000UL},
- {0x0078U, 0x0000000000000000UL},
- {0x0080U, 0x0000000000000000UL},
- {0x0088U, 0x00140C050000FFFFUL},
- {0x0090U, 0x001408060000FFFFUL},
- {0x0098U, 0x001404020000FFFFUL},
- {0x00A0U, 0x0000000000000000UL},
- {0x00A8U, 0x0000000000000000UL},
- {0x00B0U, 0x0000000000000000UL},
- {0x00B8U, 0x0000000000000000UL},
- {0x00C0U, 0x0000000000000000UL},
- {0x00C8U, 0x0000000000000000UL},
- {0x00D0U, 0x0000000000000000UL},
- {0x00D8U, 0x0000000000000000UL},
- {0x00E0U, 0x0000000000000000UL},
- {0x00E8U, 0x0000000000000000UL},
- {0x00F0U, 0x0000000000000000UL},
- {0x00F8U, 0x0000000000000000UL},
- {0x0100U, 0x0000000000000000UL},
- {0x0108U, 0x0000000000000000UL},
- {0x0110U, 0x0000000000000000UL},
- {0x0118U, 0x0000000000000000UL},
- {0x0120U, 0x0000000000000000UL},
- {0x0128U, 0x0000000000000000UL},
- {0x0130U, 0x0000000000000000UL},
- {0x0138U, 0x001004020000FFFFUL},
- {0x0140U, 0x001004020000FFFFUL},
- {0x0148U, 0x001004020000FFFFUL},
- {0x0150U, 0x001008050000FFFFUL},
- {0x0158U, 0x001008050000FFFFUL},
- {0x0160U, 0x001008050000FFFFUL},
- {0x0168U, 0x001008050000FFFFUL},
- {0x0170U, 0x001008050000FFFFUL},
- {0x0178U, 0x001004030000FFFFUL},
- {0x0180U, 0x001004030000FFFFUL},
- {0x0188U, 0x001004030000FFFFUL},
- {0x0190U, 0x001014140000FFFFUL},
- {0x0198U, 0x001014140000FFFFUL},
- {0x01A0U, 0x001008060000FFFFUL},
- {0x01A8U, 0x001008060000FFFFUL},
- {0x01B0U, 0x001008060000FFFFUL},
- {0x01B8U, 0x0000000000000000UL},
- {0x01C0U, 0x0000000000000000UL},
- {0x01C8U, 0x0000000000000000UL},
- {0x01D0U, 0x0000000000000000UL},
- {0x01D8U, 0x0000000000000000UL},
- {0x01E0U, 0x0000000000000000UL},
- {0x01E8U, 0x0000000000000000UL},
- {0x01F0U, 0x0000000000000000UL},
- {0x01F8U, 0x0000000000000000UL},
- {0x0200U, 0x0000000000000000UL},
- {0x0208U, 0x0000000000000000UL},
- {0x0210U, 0x0000000000000000UL},
- {0x0218U, 0x0000000000000000UL},
- {0x0220U, 0x0000000000000000UL},
- {0x0228U, 0x0000000000000000UL},
- {0x0230U, 0x0000000000000000UL},
- {0x0238U, 0x0000000000000000UL},
- {0x0240U, 0x0000000000000000UL},
- {0x0248U, 0x0000000000000000UL},
- {0x0250U, 0x0000000000000000UL},
- {0x0258U, 0x0000000000000000UL},
- {0x0260U, 0x0000000000000000UL},
- {0x0268U, 0x0000000000000000UL},
- {0x0270U, 0x0000000000000000UL},
- {0x0278U, 0x0000000000000000UL},
- {0x0280U, 0x0000000000000000UL},
- {0x0288U, 0x0000000000000000UL},
- {0x0290U, 0x0000000000000000UL},
- {0x0298U, 0x0000000000000000UL},
- {0x02A0U, 0x0000000000000000UL},
- {0x02A8U, 0x0000000000000000UL},
- {0x02B0U, 0x0000000000000000UL},
- {0x02B8U, 0x0000000000000000UL},
- {0x02C0U, 0x0000000000000000UL},
- {0x02C8U, 0x0000000000000000UL},
- {0x02D0U, 0x0000000000000000UL},
- {0x02D8U, 0x0000000000000000UL},
- {0x02E0U, 0x0000000000000000UL},
- {0x02E8U, 0x0000000000000000UL},
- {0x02F0U, 0x0000000000000000UL},
- {0x02F8U, 0x0000000000000000UL},
- {0x0300U, 0x0000000000000000UL},
- {0x0308U, 0x0000000000000000UL},
- {0x0310U, 0x0000000000000000UL},
- {0x0318U, 0x0000000000000000UL},
- {0x0320U, 0x0000000000000000UL},
- {0x0328U, 0x0000000000000000UL},
- {0x0330U, 0x0000000000000000UL},
- {0x0338U, 0x0000000000000000UL},
-};
-
-static const mstat_slot_t mstat_be[] = {
- {0x0000U, 0x001000100C8FFC01UL},
- {0x0008U, 0x001000100C8FFC01UL},
- {0x0010U, 0x001000100C8FFC01UL},
- {0x0018U, 0x001000100C8FFC01UL},
- {0x0020U, 0x001000100C8FFC01UL},
- {0x0028U, 0x001000100C8FFC01UL},
- {0x0030U, 0x001000100C8FFC01UL},
- {0x0038U, 0x001000100C8FFC01UL},
- {0x0040U, 0x0000000000000000UL},
- {0x0048U, 0x0000000000000000UL},
- {0x0050U, 0x001000100C8FFC01UL},
- {0x0058U, 0x0000000000000000UL},
- {0x0060U, 0x0000000000000000UL},
- {0x0068U, 0x001000100C8FFC01UL},
- {0x0070U, 0x001000100C8FFC01UL},
- {0x0078U, 0x001000100C8FFC01UL},
- {0x0080U, 0x001000100C8FFC01UL},
- {0x0088U, 0x0000000000000000UL},
- {0x0090U, 0x0000000000000000UL},
- {0x0098U, 0x0000000000000000UL},
- {0x00A0U, 0x001000100C8FFC01UL},
- {0x00A8U, 0x001000100C8FFC01UL},
- {0x00B0U, 0x001000100C8FFC01UL},
- {0x00B8U, 0x001000100C8FFC01UL},
- {0x00C0U, 0x001000100C8FFC01UL},
- {0x00C8U, 0x001000100C8FFC01UL},
- {0x00D0U, 0x001000100C8FFC01UL},
- {0x00D8U, 0x002000200C8FFC01UL},
- {0x00E0U, 0x002000200C8FFC01UL},
- {0x00E8U, 0x001000100C8FFC01UL},
- {0x00F0U, 0x001000100C8FFC01UL},
- {0x00F8U, 0x001000100C8FFC01UL},
- {0x0100U, 0x0000000000000000UL},
- {0x0108U, 0x002000200C8FFC01UL},
- {0x0110U, 0x001000100C8FFC01UL},
- {0x0118U, 0x001000100C8FFC01UL},
- {0x0120U, 0x0000000000000000UL},
- {0x0128U, 0x002000200C8FFC01UL},
- {0x0130U, 0x001000100C8FFC01UL},
- {0x0138U, 0x0000000000000000UL},
- {0x0140U, 0x0000000000000000UL},
- {0x0148U, 0x0000000000000000UL},
- {0x0150U, 0x0000000000000000UL},
- {0x0158U, 0x0000000000000000UL},
- {0x0160U, 0x0000000000000000UL},
- {0x0168U, 0x0000000000000000UL},
- {0x0170U, 0x0000000000000000UL},
- {0x0178U, 0x0000000000000000UL},
- {0x0180U, 0x0000000000000000UL},
- {0x0188U, 0x0000000000000000UL},
- {0x0190U, 0x0000000000000000UL},
- {0x0198U, 0x0000000000000000UL},
- {0x01A0U, 0x0000000000000000UL},
- {0x01A8U, 0x0000000000000000UL},
- {0x01B0U, 0x0000000000000000UL},
- {0x01B8U, 0x001000100C8FFC01UL},
- {0x01C0U, 0x001000200C8FFC01UL},
- {0x01C8U, 0x001000200C8FFC01UL},
- {0x01D0U, 0x001000200C8FFC01UL},
- {0x01D8U, 0x001000200C8FFC01UL},
- {0x01E0U, 0x001000100C8FFC01UL},
- {0x01E8U, 0x001000100C8FFC01UL},
- {0x01F0U, 0x001000100C8FFC01UL},
- {0x01F8U, 0x001000100C8FFC01UL},
- {0x0200U, 0x001000100C8FFC01UL},
- {0x0208U, 0x001000100C8FFC01UL},
- {0x0210U, 0x001000100C8FFC01UL},
- {0x0218U, 0x001000100C8FFC01UL},
- {0x0220U, 0x001000100C8FFC01UL},
- {0x0228U, 0x001000100C8FFC01UL},
- {0x0230U, 0x001000100C8FFC01UL},
- {0x0238U, 0x001000100C8FFC01UL},
- {0x0240U, 0x001000100C8FFC01UL},
- {0x0248U, 0x001000100C8FFC01UL},
- {0x0250U, 0x001000100C8FFC01UL},
- {0x0258U, 0x001000100C8FFC01UL},
- {0x0260U, 0x001000100C8FFC01UL},
- {0x0268U, 0x001000100C8FFC01UL},
- {0x0270U, 0x001000100C8FFC01UL},
- {0x0278U, 0x001000100C8FFC01UL},
- {0x0280U, 0x001000100C8FFC01UL},
- {0x0288U, 0x001000100C8FFC01UL},
- {0x0290U, 0x001000100C8FFC01UL},
- {0x0298U, 0x001000100C8FFC01UL},
- {0x02A0U, 0x001000100C8FFC01UL},
- {0x02A8U, 0x001000100C8FFC01UL},
- {0x02B0U, 0x001000100C8FFC01UL},
- {0x02B8U, 0x001000100C8FFC01UL},
- {0x02C0U, 0x001000100C8FFC01UL},
- {0x02C8U, 0x001000100C8FFC01UL},
- {0x02D0U, 0x001000100C8FFC01UL},
- {0x02D8U, 0x001000100C8FFC01UL},
- {0x02E0U, 0x001000100C8FFC01UL},
- {0x02E8U, 0x001000100C8FFC01UL},
- {0x02F0U, 0x001000200C8FFC01UL},
- {0x02F8U, 0x001000300C8FFC01UL},
- {0x0300U, 0x0000000000000000UL},
- {0x0308U, 0x001000200C8FFC01UL},
- {0x0310U, 0x001000300C8FFC01UL},
- {0x0318U, 0x0000000000000000UL},
- {0x0320U, 0x001000200C8FFC01UL},
- {0x0328U, 0x001000300C8FFC01UL},
- {0x0330U, 0x001000200C8FFC01UL},
- {0x0338U, 0x001000300C8FFC01UL},
-};
-#endif
-
-void qos_init_h3_v10(void)
-{
- /* DRAM Split Address mapping */
-#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
- (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
- NOTICE("BL2: DRAM Split is 4ch\n");
- io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1BU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR1, 0x00000000U);
- io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
- NOTICE("BL2: DRAM Split is 2ch\n");
- io_write_32(AXI_ADSPLCR0, 0x00000000U);
- io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1BU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR2, 0x00000000U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- NOTICE("BL2: DRAM Split is OFF\n");
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
- /* AR Cache setting */
- io_write_32(0xE67D1000U, 0x00000100U);
- io_write_32(0xE67D1008U, 0x00000100U);
-
- /* Resource Alloc setting */
- io_write_32(RALLOC_RAS, 0x00000040U);
- io_write_32(RALLOC_FIXTH, 0x000F0005U);
- io_write_32(RALLOC_REGGD, 0x00000004U);
- io_write_64(RALLOC_DANN, 0x0202000004040404UL);
- io_write_32(RALLOC_DANT, 0x003C1110U);
- io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
- io_write_64(RALLOC_EMS, 0x0000000000000000UL);
- io_write_32(RALLOC_INSFC, 0xC7840001U);
- io_write_32(RALLOC_BERR, 0x00000000U);
-
- /* MSTAT setting */
- io_write_32(MSTAT_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
- io_write_32(MSTAT_REF_ARS, 0x00330000U);
-
- /* MSTAT SRAM setting */
- for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
- mstat_fix[i].value);
- io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
- mstat_fix[i].value);
- }
- for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
- mstat_be[i].value);
- io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
- mstat_be[i].value);
- }
-
- /* 3DG bus Leaf setting */
- io_write_32(0xFD820808U, 0x00001234U);
- io_write_32(0xFD820800U, 0x0000003FU);
- io_write_32(0xFD821800U, 0x0000003FU);
- io_write_32(0xFD822800U, 0x0000003FU);
- io_write_32(0xFD823800U, 0x0000003FU);
- io_write_32(0xFD824800U, 0x0000003FU);
- io_write_32(0xFD825800U, 0x0000003FU);
- io_write_32(0xFD826800U, 0x0000003FU);
- io_write_32(0xFD827800U, 0x0000003FU);
-
- /* Resource Alloc start */
- io_write_32(RALLOC_RAEN, 0x00000001U);
-
- /* MSTAT start */
- io_write_32(MSTAT_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- /* Resource Alloc setting */
- io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
deleted file mode 100644
index 5b7348c..0000000
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
+++ /dev/null
@@ -1,610 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include <rcar_def.h>
-
-#include "../qos_common.h"
-#include "qos_init_h3_v11.h"
-
-#define RCAR_QOS_VERSION "rev.0.37"
-
-#define RCAR_QOS_NONE (3U)
-#define RCAR_QOS_TYPE_DEFAULT (0U)
-
-#define RCAR_DRAM_SPLIT_LINEAR (0U)
-#define RCAR_DRAM_SPLIT_4CH (1U)
-#define RCAR_DRAM_SPLIT_2CH (2U)
-#define RCAR_DRAM_SPLIT_AUTO (3U)
-
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-
-#define RCAR_PWRSR8 (0xE6180340U) /* A3VP_PWRSR0 */
-#define RCAR_PWRONCR8 (0xE618034CU) /* A3VP_PWRONCR */
-#define RCAR_PWRSR9 (0xE6180380U) /* A3VC_PWRSR0 */
-#define RCAR_PWRONCR9 (0xE618038CU) /* A3VC_PWRONCR */
-#define RCAR_PWRSR10 (0xE61803C0U) /* A2VC_PWRSR0 */
-#define RCAR_PWRONCR10 (0xE61803CCU) /* A2VC_PWRONCR */
-
-#define DBSC_BASE (0xE6790000U)
-#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
-#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
-#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
-#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
-#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
-#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
-#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
-#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
-#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
-#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
-#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
-#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
-#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
-#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
-#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
-#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
-#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
-#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
-#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
-#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
-#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
-#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
-#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
-#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
-#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
-#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
-#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
-#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
-#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
-#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
-#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
-#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
-#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
-#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
-#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
-#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
-#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
-#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
-#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
-#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
-#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
-#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
-#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
-#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
-#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
-#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
-#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
-
-#define AXI_BASE (0xE6784000U)
-#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
-#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
-#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
-#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
-#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
-#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
-#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
-#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
-#define ADSPLCR0_SWP (0x0CU)
-
-#define MSTAT_BASE (0xE67E0000U)
-#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
-#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
-#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
-#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
-#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
-#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
-#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
-
-#define RALLOC_BASE (0xE67F0000U)
-#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
-#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
-#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
-#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
-#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
-#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
-#define RALLOC_EC (RALLOC_BASE + 0x003CU)
-#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
-#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
-#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
-#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-static const mstat_slot_t mstat_fix[] = {
- {0x0000U, 0x0000000000000000UL},
- {0x0008U, 0x0000000000000000UL},
- {0x0010U, 0x0000000000000000UL},
- {0x0018U, 0x0000000000000000UL},
- {0x0020U, 0x0000000000000000UL},
- {0x0028U, 0x0000000000000000UL},
- {0x0030U, 0x001004030000FFFFUL},
- {0x0038U, 0x001008060000FFFFUL},
- {0x0040U, 0x001414090000FFFFUL},
- {0x0048U, 0x0000000000000000UL},
- {0x0050U, 0x001410010000FFFFUL},
- {0x0058U, 0x00140C0C0000FFFFUL},
- {0x0060U, 0x00140C0C0000FFFFUL},
- {0x0068U, 0x0000000000000000UL},
- {0x0070U, 0x001410010000FFFFUL},
- {0x0078U, 0x001008060000FFFFUL},
- {0x0080U, 0x001004020000FFFFUL},
- {0x0088U, 0x001414090000FFFFUL},
- {0x0090U, 0x00140C0C0000FFFFUL},
- {0x0098U, 0x001408080000FFFFUL},
- {0x00A0U, 0x000C08020000FFFFUL},
- {0x00A8U, 0x000C04010000FFFFUL},
- {0x00B0U, 0x000C04010000FFFFUL},
- {0x00B8U, 0x0000000000000000UL},
- {0x00C0U, 0x000C08020000FFFFUL},
- {0x00C8U, 0x000C04010000FFFFUL},
- {0x00D0U, 0x000C04010000FFFFUL},
- {0x00D8U, 0x000C04030000FFFFUL},
- {0x00E0U, 0x000C100F0000FFFFUL},
- {0x00E8U, 0x0000000000000000UL},
- {0x00F0U, 0x001010080000FFFFUL},
- {0x00F8U, 0x001010080000FFFFUL},
- {0x0100U, 0x0000000000000000UL},
- {0x0108U, 0x000C04030000FFFFUL},
- {0x0110U, 0x001010080000FFFFUL},
- {0x0118U, 0x001010080000FFFFUL},
- {0x0120U, 0x0000000000000000UL},
- {0x0128U, 0x000C100E0000FFFFUL},
- {0x0130U, 0x0000000000000000UL},
- {0x0138U, 0x001008050000FFFFUL},
- {0x0140U, 0x001008050000FFFFUL},
- {0x0148U, 0x001008050000FFFFUL},
- {0x0150U, 0x001008050000FFFFUL},
- {0x0158U, 0x001008050000FFFFUL},
- {0x0160U, 0x001008050000FFFFUL},
- {0x0168U, 0x001008050000FFFFUL},
- {0x0170U, 0x001008050000FFFFUL},
- {0x0178U, 0x001004030000FFFFUL},
- {0x0180U, 0x001004030000FFFFUL},
- {0x0188U, 0x001004030000FFFFUL},
- {0x0190U, 0x001014140000FFFFUL},
- {0x0198U, 0x001014140000FFFFUL},
- {0x01A0U, 0x001008050000FFFFUL},
- {0x01A8U, 0x001008050000FFFFUL},
- {0x01B0U, 0x001008050000FFFFUL},
- {0x01B8U, 0x0000000000000000UL},
- {0x01C0U, 0x0000000000000000UL},
- {0x01C8U, 0x0000000000000000UL},
- {0x01D0U, 0x0000000000000000UL},
- {0x01D8U, 0x0000000000000000UL},
- {0x01E0U, 0x0000000000000000UL},
- {0x01E8U, 0x0000000000000000UL},
- {0x01F0U, 0x0000000000000000UL},
- {0x01F8U, 0x0000000000000000UL},
- {0x0200U, 0x0000000000000000UL},
- {0x0208U, 0x0000000000000000UL},
- {0x0210U, 0x0000000000000000UL},
- {0x0218U, 0x0000000000000000UL},
- {0x0220U, 0x0000000000000000UL},
- {0x0228U, 0x0000000000000000UL},
- {0x0230U, 0x0000000000000000UL},
- {0x0238U, 0x0000000000000000UL},
- {0x0240U, 0x0000000000000000UL},
- {0x0248U, 0x0000000000000000UL},
- {0x0250U, 0x0000000000000000UL},
- {0x0258U, 0x0000000000000000UL},
- {0x0260U, 0x0000000000000000UL},
- {0x0268U, 0x001408010000FFFFUL},
- {0x0270U, 0x001404010000FFFFUL},
- {0x0278U, 0x0000000000000000UL},
- {0x0280U, 0x0000000000000000UL},
- {0x0288U, 0x0000000000000000UL},
- {0x0290U, 0x001408010000FFFFUL},
- {0x0298U, 0x001404010000FFFFUL},
- {0x02A0U, 0x000C04010000FFFFUL},
- {0x02A8U, 0x000C04010000FFFFUL},
- {0x02B0U, 0x001404010000FFFFUL},
- {0x02B8U, 0x0000000000000000UL},
- {0x02C0U, 0x0000000000000000UL},
- {0x02C8U, 0x0000000000000000UL},
- {0x02D0U, 0x000C04010000FFFFUL},
- {0x02D8U, 0x000C04010000FFFFUL},
- {0x02E0U, 0x001404010000FFFFUL},
- {0x02E8U, 0x0000000000000000UL},
- {0x02F0U, 0x0000000000000000UL},
- {0x02F8U, 0x0000000000000000UL},
- {0x0300U, 0x0000000000000000UL},
- {0x0308U, 0x0000000000000000UL},
- {0x0310U, 0x0000000000000000UL},
- {0x0318U, 0x0000000000000000UL},
- {0x0320U, 0x0000000000000000UL},
- {0x0328U, 0x0000000000000000UL},
- {0x0330U, 0x0000000000000000UL},
- {0x0338U, 0x0000000000000000UL},
-};
-
-static const mstat_slot_t mstat_be[] = {
- {0x0000U, 0x001200100C89C401UL},
- {0x0008U, 0x001200100C89C401UL},
- {0x0010U, 0x001200100C89C401UL},
- {0x0018U, 0x001200100C89C401UL},
- {0x0020U, 0x001100100C803401UL},
- {0x0028U, 0x001100100C80FC01UL},
- {0x0030U, 0x0000000000000000UL},
- {0x0038U, 0x0000000000000000UL},
- {0x0040U, 0x0000000000000000UL},
- {0x0048U, 0x0000000000000000UL},
- {0x0050U, 0x0000000000000000UL},
- {0x0058U, 0x0000000000000000UL},
- {0x0060U, 0x0000000000000000UL},
- {0x0068U, 0x001100100C803401UL},
- {0x0070U, 0x0000000000000000UL},
- {0x0078U, 0x0000000000000000UL},
- {0x0080U, 0x0000000000000000UL},
- {0x0088U, 0x0000000000000000UL},
- {0x0090U, 0x0000000000000000UL},
- {0x0098U, 0x0000000000000000UL},
- {0x00A0U, 0x0000000000000000UL},
- {0x00A8U, 0x0000000000000000UL},
- {0x00B0U, 0x0000000000000000UL},
- {0x00B8U, 0x001100100C803401UL},
- {0x00C0U, 0x0000000000000000UL},
- {0x00C8U, 0x0000000000000000UL},
- {0x00D0U, 0x0000000000000000UL},
- {0x00D8U, 0x0000000000000000UL},
- {0x00E0U, 0x0000000000000000UL},
- {0x00E8U, 0x001100100C803401UL},
- {0x00F0U, 0x0000000000000000UL},
- {0x00F8U, 0x0000000000000000UL},
- {0x0100U, 0x0000000000000000UL},
- {0x0108U, 0x0000000000000000UL},
- {0x0110U, 0x0000000000000000UL},
- {0x0118U, 0x0000000000000000UL},
- {0x0120U, 0x0000000000000000UL},
- {0x0128U, 0x0000000000000000UL},
- {0x0130U, 0x001100100C803401UL},
- {0x0138U, 0x0000000000000000UL},
- {0x0140U, 0x0000000000000000UL},
- {0x0148U, 0x0000000000000000UL},
- {0x0150U, 0x0000000000000000UL},
- {0x0158U, 0x0000000000000000UL},
- {0x0160U, 0x0000000000000000UL},
- {0x0168U, 0x0000000000000000UL},
- {0x0170U, 0x0000000000000000UL},
- {0x0178U, 0x0000000000000000UL},
- {0x0180U, 0x0000000000000000UL},
- {0x0188U, 0x0000000000000000UL},
- {0x0190U, 0x0000000000000000UL},
- {0x0198U, 0x0000000000000000UL},
- {0x01A0U, 0x0000000000000000UL},
- {0x01A8U, 0x0000000000000000UL},
- {0x01B0U, 0x0000000000000000UL},
- {0x01B8U, 0x001100100C803401UL},
- {0x01C0U, 0x001100800C8FFC01UL},
- {0x01C8U, 0x001100800C8FFC01UL},
- {0x01D0U, 0x001100800C8FFC01UL},
- {0x01D8U, 0x001100800C8FFC01UL},
- {0x01E0U, 0x001100100C80FC01UL},
- {0x01E8U, 0x001200100C80FC01UL},
- {0x01F0U, 0x001100100C80FC01UL},
- {0x01F8U, 0x001100100C803401UL},
- {0x0200U, 0x001100100C80FC01UL},
- {0x0208U, 0x001200100C80FC01UL},
- {0x0210U, 0x001100100C80FC01UL},
- {0x0218U, 0x001100100C825801UL},
- {0x0220U, 0x001100100C825801UL},
- {0x0228U, 0x001100100C803401UL},
- {0x0230U, 0x001100100C825801UL},
- {0x0238U, 0x001100100C825801UL},
- {0x0240U, 0x001200100C8BB801UL},
- {0x0248U, 0x001100200C8FFC01UL},
- {0x0250U, 0x001200100C8BB801UL},
- {0x0258U, 0x001100200C8FFC01UL},
- {0x0260U, 0x001100100C84E401UL},
- {0x0268U, 0x0000000000000000UL},
- {0x0270U, 0x0000000000000000UL},
- {0x0278U, 0x001100100C81F401UL},
- {0x0280U, 0x001100100C803401UL},
- {0x0288U, 0x001100100C803401UL},
- {0x0290U, 0x0000000000000000UL},
- {0x0298U, 0x0000000000000000UL},
- {0x02A0U, 0x0000000000000000UL},
- {0x02A8U, 0x0000000000000000UL},
- {0x02B0U, 0x0000000000000000UL},
- {0x02B8U, 0x001100100C803401UL},
- {0x02C0U, 0x001100100C803401UL},
- {0x02C8U, 0x001100100C803401UL},
- {0x02D0U, 0x0000000000000000UL},
- {0x02D8U, 0x0000000000000000UL},
- {0x02E0U, 0x0000000000000000UL},
- {0x02E8U, 0x001100100C803401UL},
- {0x02F0U, 0x001100300C8FFC01UL},
- {0x02F8U, 0x001100500C8FFC01UL},
- {0x0300U, 0x001100100C803401UL},
- {0x0308U, 0x001100300C8FFC01UL},
- {0x0310U, 0x001100500C8FFC01UL},
- {0x0318U, 0x001200100C803401UL},
- {0x0320U, 0x001100300C8FFC01UL},
- {0x0328U, 0x001100500C8FFC01UL},
- {0x0330U, 0x001100300C8FFC01UL},
- {0x0338U, 0x001100500C8FFC01UL},
-};
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md = 0;
-
- /* BUFCAM settings */
- /* DBSC_DBCAM0CNF0 not set */
- io_write_32(DBSC_DBCAM0CNF1, 0x00044218); /* dbcam0cnf1 */
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
- /* DBSC_DBCAM0CNF3 not set */
- io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */
- io_write_32(DBSC_DBSCHCNT1, 0x00001010); /* dbschcnt1 */
- io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
- io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
-
- md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
- switch (md) {
- case 0x0:
- /* DDR3200 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
- /* DDR2800 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
- /* DDR2400 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
- io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
- io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
- io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
- /* DBSC_DBSCHQOS_1_0 not set */
- /* DBSC_DBSCHQOS_1_1 not set */
- /* DBSC_DBSCHQOS_1_2 not set */
- /* DBSC_DBSCHQOS_1_3 not set */
- /* DBSC_DBSCHQOS_2_0 not set */
- /* DBSC_DBSCHQOS_2_1 not set */
- /* DBSC_DBSCHQOS_2_2 not set */
- /* DBSC_DBSCHQOS_2_3 not set */
- /* DBSC_DBSCHQOS_3_0 not set */
- /* DBSC_DBSCHQOS_3_1 not set */
- /* DBSC_DBSCHQOS_3_2 not set */
- /* DBSC_DBSCHQOS_3_3 not set */
- io_write_32(DBSC_DBSCHQOS_4_0, 0x00000E00);
- io_write_32(DBSC_DBSCHQOS_4_1, 0x00000DFF);
- io_write_32(DBSC_DBSCHQOS_4_2, 0x00000400);
- io_write_32(DBSC_DBSCHQOS_4_3, 0x00000200);
- /* DBSC_DBSCHQOS_5_0 not set */
- /* DBSC_DBSCHQOS_5_1 not set */
- /* DBSC_DBSCHQOS_5_2 not set */
- /* DBSC_DBSCHQOS_5_3 not set */
- /* DBSC_DBSCHQOS_6_0 not set */
- /* DBSC_DBSCHQOS_6_1 not set */
- /* DBSC_DBSCHQOS_6_2 not set */
- /* DBSC_DBSCHQOS_6_3 not set */
- /* DBSC_DBSCHQOS_7_0 not set */
- /* DBSC_DBSCHQOS_7_1 not set */
- /* DBSC_DBSCHQOS_7_2 not set */
- /* DBSC_DBSCHQOS_7_3 not set */
- /* DBSC_DBSCHQOS_8_0 not set */
- /* DBSC_DBSCHQOS_8_1 not set */
- /* DBSC_DBSCHQOS_8_2 not set */
- /* DBSC_DBSCHQOS_8_3 not set */
- io_write_32(DBSC_DBSCHQOS_9_0, 0x00000C00);
- io_write_32(DBSC_DBSCHQOS_9_1, 0x00000BFF);
- io_write_32(DBSC_DBSCHQOS_9_2, 0x00000400);
- io_write_32(DBSC_DBSCHQOS_9_3, 0x00000200);
- /* DBSC_DBSCHQOS_10_0 not set */
- /* DBSC_DBSCHQOS_10_1 not set */
- /* DBSC_DBSCHQOS_10_2 not set */
- /* DBSC_DBSCHQOS_10_3 not set */
- /* DBSC_DBSCHQOS_11_0 not set */
- /* DBSC_DBSCHQOS_11_1 not set */
- /* DBSC_DBSCHQOS_11_2 not set */
- /* DBSC_DBSCHQOS_11_3 not set */
- /* DBSC_DBSCHQOS_12_0 not set */
- /* DBSC_DBSCHQOS_12_1 not set */
- /* DBSC_DBSCHQOS_12_2 not set */
- /* DBSC_DBSCHQOS_12_3 not set */
- io_write_32(DBSC_DBSCHQOS_13_0, 0x00000980);
- io_write_32(DBSC_DBSCHQOS_13_1, 0x0000097F);
- io_write_32(DBSC_DBSCHQOS_13_2, 0x00000300);
- io_write_32(DBSC_DBSCHQOS_13_3, 0x00000180);
- io_write_32(DBSC_DBSCHQOS_14_0, 0x00000800);
- io_write_32(DBSC_DBSCHQOS_14_1, 0x000007FF);
- io_write_32(DBSC_DBSCHQOS_14_2, 0x00000300);
- io_write_32(DBSC_DBSCHQOS_14_3, 0x00000180);
- io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
- io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
- io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
- io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
-}
-
-void qos_init_h3_v11(void)
-{
- dbsc_setting();
-
- /* DRAM Split Address mapping */
-#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
- (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
- NOTICE("BL2: DRAM Split is 4ch\n");
- io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1BU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR1, 0x00000000U);
- io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
- NOTICE("BL2: DRAM Split is 2ch\n");
- io_write_32(AXI_ADSPLCR0, 0x00000000U);
- io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1BU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR2, 0x00000000U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- NOTICE("BL2: DRAM Split is OFF\n");
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
- /* AR Cache setting */
- io_write_32(0xE67D1000U, 0x00000100U);
- io_write_32(0xE67D1008U, 0x00000100U);
-
- /* Resource Alloc setting */
-#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
- io_write_32(RALLOC_RAS, 0x00000020U);
-#else
- io_write_32(RALLOC_RAS, 0x00000040U);
-#endif
- io_write_32(RALLOC_FIXTH, 0x000F0005U);
- io_write_32(RALLOC_REGGD, 0x00000000U);
-#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
- io_write_64(RALLOC_DANN, 0x0101010102020201UL);
- io_write_32(RALLOC_DANT, 0x00181008U);
-#else
- io_write_64(RALLOC_DANN, 0x0101000004040401UL);
- io_write_32(RALLOC_DANT, 0x003C2010U);
-#endif
- io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
- io_write_64(RALLOC_EMS, 0x0000000000000000UL);
- io_write_32(RALLOC_INSFC, 0xC7840001U);
- io_write_32(RALLOC_BERR, 0x00000000U);
- io_write_32(RALLOC_RACNT0, 0x00000000U);
-
- /* MSTAT setting */
- io_write_32(MSTAT_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
- io_write_32(MSTAT_REF_ARS, 0x00330000U);
-
- /* MSTAT SRAM setting */
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
- mstat_fix[i].value);
- io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
- mstat_fix[i].value);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
- mstat_be[i].value);
- io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
- mstat_be[i].value);
- }
- }
-
- /* 3DG bus Leaf setting */
- io_write_32(0xFD820808U, 0x00001234U);
- io_write_32(0xFD820800U, 0x0000003FU);
- io_write_32(0xFD821800U, 0x0000003FU);
- io_write_32(0xFD822800U, 0x0000003FU);
- io_write_32(0xFD823800U, 0x0000003FU);
- io_write_32(0xFD824800U, 0x0000003FU);
- io_write_32(0xFD825800U, 0x0000003FU);
- io_write_32(0xFD826800U, 0x0000003FU);
- io_write_32(0xFD827800U, 0x0000003FU);
-
- /* VIO bus Leaf setting */
- io_write_32(0xFEB89800, 0x00000001U);
- io_write_32(0xFEB8A800, 0x00000001U);
- io_write_32(0xFEB8B800, 0x00000001U);
- io_write_32(0xFEB8C800, 0x00000001U);
-
- /* HSC bus Leaf setting */
- io_write_32(0xE6430800, 0x00000001U);
- io_write_32(0xE6431800, 0x00000001U);
- io_write_32(0xE6432800, 0x00000001U);
- io_write_32(0xE6433800, 0x00000001U);
-
- /* MP bus Leaf setting */
- io_write_32(0xEC620800, 0x00000001U);
- io_write_32(0xEC621800, 0x00000001U);
-
- /* PERIE bus Leaf setting */
- io_write_32(0xE7760800, 0x00000001U);
- io_write_32(0xE7768800, 0x00000001U);
-
- /* PERIW bus Leaf setting */
- io_write_32(0xE6760800, 0x00000001U);
- io_write_32(0xE6768800, 0x00000001U);
-
- /* RT bus Leaf setting */
- io_write_32(0xFFC50800, 0x00000001U);
- io_write_32(0xFFC51800, 0x00000001U);
-
- /* CCI bus Leaf setting */
- {
-
- uint32_t modemr = io_read_32(RCAR_MODEMR);
-
- modemr &= MODEMR_BOOT_CPU_MASK;
-
- if ((modemr == MODEMR_BOOT_CPU_CA57) ||
- (modemr == MODEMR_BOOT_CPU_CA53)) {
- io_write_32(0xF1300800, 0x00000001U);
- io_write_32(0xF1340800, 0x00000001U);
- io_write_32(0xF1380800, 0x00000001U);
- io_write_32(0xF13C0800, 0x00000001U);
- }
- }
-
- /* Resource Alloc start */
- io_write_32(RALLOC_RAEN, 0x00000001U);
-
- /* MSTAT start */
- io_write_32(MSTAT_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- /* Resource Alloc setting */
- io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
deleted file mode 100644
index c7137de..0000000
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "../qos_reg.h"
-#include "qos_init_h3_v20.h"
-
-
-#define RCAR_QOS_VERSION "rev.0.21"
-
-#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
-
-#define QOSWT_WTEN_ENABLE (0x1U)
-
-#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 (SL_INIT_SSLOTCLK_H3_20 - 0x5U)
-
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
-#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-
-#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
-#define WT_BASE_SUB_SLOT_NUM0 (12U)
-#define QOSWT_WTSET0_PERIOD0_H3_20 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
-#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#define QOSWT_WTSET1_PERIOD1_H3_20 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
-#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_h3_v20_mstat195.h"
-#else
-#include "qos_init_h3_v20_mstat390.h"
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_h3_v20_qoswt195.h"
-#else
-#include "qos_init_h3_v20_qoswt390.h"
-#endif
-
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md = 0;
-
- /* Register write enable */
- io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
-
- /* BUFCAM settings */
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
- io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
- io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
- io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
- io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
-
- md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
- switch (md) {
- case 0x0:
- /* DDR3200 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
- /* DDR2800 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
- /* DDR2400 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
- io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
- io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
- io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
- io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
- io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
- io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
- io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
- io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
- io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
- io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
- io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
- io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
- io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
- io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
- io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
- io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
- io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
- io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
- io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
-
- /* Register write protect */
- io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
-}
-
-void qos_init_h3_v20(void)
-{
- dbsc_setting();
-
- /* DRAM Split Address mapping */
-#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
- (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
- NOTICE("BL2: DRAM Split is 4ch\n");
- io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1BU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR1, 0x00000000U);
- io_write_32(AXI_ADSPLCR2, 0x00001054U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
- NOTICE("BL2: DRAM Split is 2ch\n");
- io_write_32(AXI_ADSPLCR0, 0x00000000U);
- io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1BU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR2, 0x00001004U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- NOTICE("BL2: DRAM Split is OFF\n");
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
- NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
-#else
- NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- NOTICE("BL2: Periodic Write DQ Training\n");
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_RAS, 0x00000044U);
- io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
- io_write_32(QOSCTRL_DANT, 0x0020100AU);
- io_write_32(QOSCTRL_INSFC, 0x06330001U);
- io_write_32(QOSCTRL_RACNT0, 0x00010003U);
-
- /* GPU Boost Mode */
- io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
-
- io_write_32(QOSCTRL_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
- SL_INIT_SSLOTCLK_H3_20);
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- io_write_32(QOSCTRL_REF_ARS,
- ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 << 16)));
-#else
- io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
- io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
- io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
- }
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
- io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
- qoswt_fix[i]);
- io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
- qoswt_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
- io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
- io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
- }
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
- }
-
- /* 3DG bus Leaf setting */
- io_write_32(GPU_ACT0, 0x00000000U);
- io_write_32(GPU_ACT1, 0x00000000U);
- io_write_32(GPU_ACT2, 0x00000000U);
- io_write_32(GPU_ACT3, 0x00000000U);
- io_write_32(GPU_ACT4, 0x00000000U);
- io_write_32(GPU_ACT5, 0x00000000U);
- io_write_32(GPU_ACT6, 0x00000000U);
- io_write_32(GPU_ACT7, 0x00000000U);
-
- /* RT bus Leaf setting */
- io_write_32(RT_ACT0, 0x00000000U);
- io_write_32(RT_ACT1, 0x00000000U);
-
- /* CCI bus Leaf setting */
- io_write_32(CPU_ACT0, 0x00000003U);
- io_write_32(CPU_ACT1, 0x00000003U);
- io_write_32(CPU_ACT2, 0x00000003U);
- io_write_32(CPU_ACT3, 0x00000003U);
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- /* re-write training setting */
- io_write_32(QOSWT_WTREF,
- ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
- io_write_32(QOSWT_WTSET0,
- ((QOSWT_WTSET0_PERIOD0_H3_20 << 16) |
- (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
- io_write_32(QOSWT_WTSET1,
- ((QOSWT_WTSET1_PERIOD1_H3_20 << 16) |
- (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
-
- io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
deleted file mode 100644
index ffc9025..0000000
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "../qos_reg.h"
-#include "qos_init_h3_v30.h"
-
-
-#define RCAR_QOS_VERSION "rev.0.11"
-
-#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
-
-#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
-
-#define QOSWT_WTEN_ENABLE (0x1U)
-
-#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 (SL_INIT_SSLOTCLK_H3_30 - 0x5U)
-
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
-#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-
-#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
-#define WT_BASE_SUB_SLOT_NUM0 (12U)
-#define QOSWT_WTSET0_PERIOD0_H3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_30)-1U)
-#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#define QOSWT_WTSET1_PERIOD1_H3_30 (QOSWT_WTSET0_PERIOD0_H3_30)
-#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
-#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_h3_v30_mstat195.h"
-#else
-#include "qos_init_h3_v30_mstat390.h"
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_h3_v30_qoswt195.h"
-#else
-#include "qos_init_h3_v30_qoswt390.h"
-#endif
-
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md = 0;
-
- /* Register write enable */
- io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
-
- /* BUFCAM settings */
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
- io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
- io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
- io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
- io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
-
- md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
- switch (md) {
- case 0x0:
- /* DDR3200 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
- /* DDR2800 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
- /* DDR2400 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
- io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
- io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
- io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
- io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
- io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
- io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
- io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
- io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
- io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
- io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
- io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
- io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
- io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
- io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
- io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
- io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
- io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
- io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
- io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
-
- /* Register write protect */
- io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
-}
-
-void qos_init_h3_v30(void)
-{
- unsigned int split_area;
- dbsc_setting();
-
-#if RCAR_DRAM_LPDDR4_MEMCONF == 0 /* 1GB */
- split_area = 0x1BU;
-#else /* default 2GB */
- split_area = 0x1CU;
-#endif
-
- /* DRAM Split Address mapping */
-#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
- (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
- NOTICE("BL2: DRAM Split is 4ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
-
- io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(split_area)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR1, 0x00000000U);
- io_write_32(AXI_ADSPLCR2, 0x00001054U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
- NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
-
- io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
- io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(split_area)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR2, 0x00001004U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
- NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
- NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
-#else
- NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- NOTICE("BL2: Periodic Write DQ Training\n");
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_RAS, 0x00000044U);
- io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
- io_write_32(QOSCTRL_DANT, 0x0020100AU);
- io_write_32(QOSCTRL_FSS, 0x0000000AU);
- io_write_32(QOSCTRL_INSFC, 0x06330001U);
- io_write_32(QOSCTRL_RACNT0, 0x00010003U);
-
- /* GPU Boost Mode */
- io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
-
- io_write_32(QOSCTRL_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
- SL_INIT_SSLOTCLK_H3_30);
- io_write_32(QOSCTRL_REF_ARS,
- ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 << 16)));
-
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
- io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
- io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
- }
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
- io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
- qoswt_fix[i]);
- io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
- qoswt_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
- io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
- io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
- }
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
- }
-
- /* AXI setting */
- io_write_32(AXI_MMCR, 0x00010008U);
- io_write_32(AXI_TR3CR, 0x00010000U);
- io_write_32(AXI_TR4CR, 0x00010000U);
-
- /* RT bus Leaf setting */
- io_write_32(RT_ACT0, 0x00000000U);
- io_write_32(RT_ACT1, 0x00000000U);
-
- /* CCI bus Leaf setting */
- io_write_32(CPU_ACT0, 0x00000003U);
- io_write_32(CPU_ACT1, 0x00000003U);
- io_write_32(CPU_ACT2, 0x00000003U);
- io_write_32(CPU_ACT3, 0x00000003U);
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- /* re-write training setting */
- io_write_32(QOSWT_WTREF,
- ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
- io_write_32(QOSWT_WTSET0,
- ((QOSWT_WTSET0_PERIOD0_H3_30 << 16) |
- (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
- io_write_32(QOSWT_WTSET1,
- ((QOSWT_WTSET1_PERIOD1_H3_30 << 16) |
- (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
-
- io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
deleted file mode 100644
index 6503b43..0000000
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "../qos_reg.h"
-#include "qos_init_h3n_v30.h"
-
-
-#define RCAR_QOS_VERSION "rev.0.07"
-
-#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
-
-#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
-
-#define QOSWT_WTEN_ENABLE (0x1U)
-
-#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N (SL_INIT_SSLOTCLK_H3N - 0x5U)
-
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
-#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-
-#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
-#define WT_BASE_SUB_SLOT_NUM0 (12U)
-#define QOSWT_WTSET0_PERIOD0_H3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3N)-1U)
-#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#define QOSWT_WTSET1_PERIOD1_H3N (QOSWT_WTSET0_PERIOD0_H3N)
-#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
-#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_h3n_v30_mstat195.h"
-#else
-#include "qos_init_h3n_v30_mstat390.h"
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_h3n_v30_qoswt195.h"
-#else
-#include "qos_init_h3n_v30_qoswt390.h"
-#endif
-
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md = 0;
-
- /* Register write enable */
- io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
-
- /* BUFCAM settings */
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
- io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
- io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
- io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
- io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
-
- md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
- switch (md) {
- case 0x0:
- /* DDR3200 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
- /* DDR2800 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
- /* DDR2400 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123U);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
- io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
- io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
- io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
- io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
- io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
- io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
- io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
- io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
- io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
- io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
- io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
- io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
- io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
- io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
- io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
- io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
- io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
- io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
- io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
- io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
- io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
-
- /* Register write protect */
- io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
-}
-
-void qos_init_h3n_v30(void)
-{
- unsigned int split_area;
- dbsc_setting();
-
- /* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
- split_area = 0x1CU;
-
- /* DRAM Split Address mapping */
-#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
-#if RCAR_LSI == RCAR_H3N
-#error "Don't set DRAM Split 4ch(H3N)"
-#else
- ERROR("DRAM Split 4ch not supported.(H3N)");
- panic();
-#endif
-#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
- (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
- NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
-
- io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
- io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(split_area)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR2, 0x00001004U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
- NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
- NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
-#else
- NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- NOTICE("BL2: Periodic Write DQ Training\n");
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_RAS, 0x00000044U);
- io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
- io_write_32(QOSCTRL_DANT, 0x0020100AU);
- io_write_32(QOSCTRL_FSS, 0x0000000AU);
- io_write_32(QOSCTRL_INSFC, 0x06330001U);
- io_write_32(QOSCTRL_RACNT0, 0x00010003U);
-
- /* GPU Boost Mode */
- io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
-
- io_write_32(QOSCTRL_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
- SL_INIT_SSLOTCLK_H3N);
- io_write_32(QOSCTRL_REF_ARS,
- ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
-
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
- io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
- io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
- }
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
- io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
- qoswt_fix[i]);
- io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
- qoswt_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
- io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
- io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
- }
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
- }
-
- /* AXI setting */
- io_write_32(AXI_MMCR, 0x00010008U);
- io_write_32(AXI_TR3CR, 0x00010000U);
- io_write_32(AXI_TR4CR, 0x00010000U);
-
- /* RT bus Leaf setting */
- io_write_32(RT_ACT0, 0x00000000U);
- io_write_32(RT_ACT1, 0x00000000U);
-
- /* CCI bus Leaf setting */
- io_write_32(CPU_ACT0, 0x00000003U);
- io_write_32(CPU_ACT1, 0x00000003U);
- io_write_32(CPU_ACT2, 0x00000003U);
- io_write_32(CPU_ACT3, 0x00000003U);
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- /* re-write training setting */
- io_write_32(QOSWT_WTREF,
- ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
- io_write_32(QOSWT_WTSET0,
- ((QOSWT_WTSET0_PERIOD0_H3N << 16) |
- (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
- io_write_32(QOSWT_WTSET1,
- ((QOSWT_WTSET1_PERIOD1_H3N << 16) |
- (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
-
- io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
deleted file mode 100644
index c0846d2..0000000
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "qos_init_m3_v10.h"
-
-#define RCAR_QOS_VERSION "rev.0.19"
-
-#define RCAR_QOS_NONE (3U)
-#define RCAR_QOS_TYPE_DEFAULT (0U)
-
-#define RCAR_DRAM_SPLIT_LINEAR (0U)
-#define RCAR_DRAM_SPLIT_4CH (1U)
-#define RCAR_DRAM_SPLIT_2CH (2U)
-#define RCAR_DRAM_SPLIT_AUTO (3U)
-
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-
-#define DBSC_BASE (0xE6790000U)
-#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
-#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
-#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
-#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
-#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
-#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
-#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
-#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
-#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
-#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
-#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
-#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
-#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
-#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
-#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
-#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
-#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
-#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
-#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
-#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
-#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
-#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
-#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
-#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
-#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
-#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
-#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
-#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
-#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
-#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
-#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
-#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
-#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
-#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
-#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
-#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
-#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
-#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
-#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
-#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
-#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
-#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
-#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
-#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
-#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
-#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
-#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
-
-#define AXI_BASE (0xE6784000U)
-#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
-#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
-#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
-#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
-#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
-#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
-#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
-#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
-#define ADSPLCR0_SWP (0x0CU)
-
-#define MSTAT_BASE (0xE67E0000U)
-#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
-#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
-#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
-#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
-#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
-#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
-#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
-
-#define RALLOC_BASE (0xE67F0000U)
-#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
-#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
-#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
-#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
-#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
-#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
-#define RALLOC_EC (RALLOC_BASE + 0x003CU)
-#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
-#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
-#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
-#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
-#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-static const mstat_slot_t mstat_fix[] = {
- {0x0000U, 0x0000000000000000UL},
- {0x0008U, 0x0000000000000000UL},
- {0x0010U, 0x0000000000000000UL},
- {0x0018U, 0x0000000000000000UL},
- {0x0020U, 0x0000000000000000UL},
- {0x0028U, 0x0000000000000000UL},
- {0x0030U, 0x001004030000FFFFUL},
- {0x0038U, 0x001004030000FFFFUL},
- {0x0040U, 0x001414090000FFFFUL},
- {0x0048U, 0x0000000000000000UL},
- {0x0050U, 0x001410010000FFFFUL},
- {0x0058U, 0x00140C090000FFFFUL},
- {0x0060U, 0x00140C090000FFFFUL},
- {0x0068U, 0x0000000000000000UL},
- {0x0070U, 0x001410010000FFFFUL},
- {0x0078U, 0x001004020000FFFFUL},
- {0x0080U, 0x0000000000000000UL},
- {0x0088U, 0x001414090000FFFFUL},
- {0x0090U, 0x001408060000FFFFUL},
- {0x0098U, 0x0000000000000000UL},
- {0x00A0U, 0x000C08020000FFFFUL},
- {0x00A8U, 0x000C04010000FFFFUL},
- {0x00B0U, 0x000C04010000FFFFUL},
- {0x00B8U, 0x0000000000000000UL},
- {0x00C0U, 0x000C08020000FFFFUL},
- {0x00C8U, 0x000C04010000FFFFUL},
- {0x00D0U, 0x000C04010000FFFFUL},
- {0x00D8U, 0x000C04030000FFFFUL},
- {0x00E0U, 0x000C100F0000FFFFUL},
- {0x00E8U, 0x0000000000000000UL},
- {0x00F0U, 0x001010080000FFFFUL},
- {0x00F8U, 0x0000000000000000UL},
- {0x0100U, 0x0000000000000000UL},
- {0x0108U, 0x0000000000000000UL},
- {0x0110U, 0x001010080000FFFFUL},
- {0x0118U, 0x0000000000000000UL},
- {0x0120U, 0x0000000000000000UL},
- {0x0128U, 0x0000000000000000UL},
- {0x0130U, 0x0000000000000000UL},
- {0x0138U, 0x00100C0A0000FFFFUL},
- {0x0140U, 0x0000000000000000UL},
- {0x0148U, 0x0000000000000000UL},
- {0x0150U, 0x00100C0A0000FFFFUL},
- {0x0158U, 0x0000000000000000UL},
- {0x0160U, 0x00100C0A0000FFFFUL},
- {0x0168U, 0x0000000000000000UL},
- {0x0170U, 0x0000000000000000UL},
- {0x0178U, 0x001008050000FFFFUL},
- {0x0180U, 0x0000000000000000UL},
- {0x0188U, 0x0000000000000000UL},
- {0x0190U, 0x001028280000FFFFUL},
- {0x0198U, 0x0000000000000000UL},
- {0x01A0U, 0x00100C0A0000FFFFUL},
- {0x01A8U, 0x0000000000000000UL},
- {0x01B0U, 0x0000000000000000UL},
- {0x01B8U, 0x0000000000000000UL},
- {0x01C0U, 0x0000000000000000UL},
- {0x01C8U, 0x0000000000000000UL},
- {0x01D0U, 0x0000000000000000UL},
- {0x01D8U, 0x0000000000000000UL},
- {0x01E0U, 0x0000000000000000UL},
- {0x01E8U, 0x0000000000000000UL},
- {0x01F0U, 0x0000000000000000UL},
- {0x01F8U, 0x0000000000000000UL},
- {0x0200U, 0x0000000000000000UL},
- {0x0208U, 0x0000000000000000UL},
- {0x0210U, 0x0000000000000000UL},
- {0x0218U, 0x0000000000000000UL},
- {0x0220U, 0x0000000000000000UL},
- {0x0228U, 0x0000000000000000UL},
- {0x0230U, 0x0000000000000000UL},
- {0x0238U, 0x0000000000000000UL},
- {0x0240U, 0x0000000000000000UL},
- {0x0248U, 0x0000000000000000UL},
- {0x0250U, 0x0000000000000000UL},
- {0x0258U, 0x0000000000000000UL},
- {0x0260U, 0x0000000000000000UL},
- {0x0268U, 0x001408010000FFFFUL},
- {0x0270U, 0x001404010000FFFFUL},
- {0x0278U, 0x0000000000000000UL},
- {0x0280U, 0x0000000000000000UL},
- {0x0288U, 0x0000000000000000UL},
- {0x0290U, 0x001408010000FFFFUL},
- {0x0298U, 0x001404010000FFFFUL},
- {0x02A0U, 0x000C04010000FFFFUL},
- {0x02A8U, 0x000C04010000FFFFUL},
- {0x02B0U, 0x001404010000FFFFUL},
- {0x02B8U, 0x0000000000000000UL},
- {0x02C0U, 0x0000000000000000UL},
- {0x02C8U, 0x0000000000000000UL},
- {0x02D0U, 0x000C04010000FFFFUL},
- {0x02D8U, 0x000C04010000FFFFUL},
- {0x02E0U, 0x001404010000FFFFUL},
- {0x02E8U, 0x0000000000000000UL},
- {0x02F0U, 0x0000000000000000UL},
- {0x02F8U, 0x0000000000000000UL},
- {0x0300U, 0x0000000000000000UL},
- {0x0308U, 0x0000000000000000UL},
- {0x0310U, 0x0000000000000000UL},
- {0x0318U, 0x0000000000000000UL},
- {0x0320U, 0x0000000000000000UL},
- {0x0328U, 0x0000000000000000UL},
- {0x0330U, 0x0000000000000000UL},
- {0x0338U, 0x0000000000000000UL},
- {0x0340U, 0x0000000000000000UL},
- {0x0348U, 0x0000000000000000UL},
- {0x0350U, 0x0000000000000000UL},
-};
-
-static const mstat_slot_t mstat_be[] = {
- {0x0000U, 0x001200100C89C401UL},
- {0x0008U, 0x001200100C89C401UL},
- {0x0010U, 0x001200100C89C401UL},
- {0x0018U, 0x001200100C89C401UL},
- {0x0020U, 0x0000000000000000UL},
- {0x0028U, 0x001100100C803401UL},
- {0x0030U, 0x0000000000000000UL},
- {0x0038U, 0x0000000000000000UL},
- {0x0040U, 0x0000000000000000UL},
- {0x0048U, 0x0000000000000000UL},
- {0x0050U, 0x0000000000000000UL},
- {0x0058U, 0x0000000000000000UL},
- {0x0060U, 0x0000000000000000UL},
- {0x0068U, 0x0000000000000000UL},
- {0x0070U, 0x0000000000000000UL},
- {0x0078U, 0x0000000000000000UL},
- {0x0080U, 0x0000000000000000UL},
- {0x0088U, 0x0000000000000000UL},
- {0x0090U, 0x0000000000000000UL},
- {0x0098U, 0x0000000000000000UL},
- {0x00A0U, 0x0000000000000000UL},
- {0x00A8U, 0x0000000000000000UL},
- {0x00B0U, 0x0000000000000000UL},
- {0x00B8U, 0x0000000000000000UL},
- {0x00C0U, 0x0000000000000000UL},
- {0x00C8U, 0x0000000000000000UL},
- {0x00D0U, 0x0000000000000000UL},
- {0x00D8U, 0x0000000000000000UL},
- {0x00E0U, 0x0000000000000000UL},
- {0x00E8U, 0x0000000000000000UL},
- {0x00F0U, 0x0000000000000000UL},
- {0x00F8U, 0x0000000000000000UL},
- {0x0100U, 0x0000000000000000UL},
- {0x0108U, 0x0000000000000000UL},
- {0x0110U, 0x0000000000000000UL},
- {0x0118U, 0x0000000000000000UL},
- {0x0120U, 0x0000000000000000UL},
- {0x0128U, 0x0000000000000000UL},
- {0x0130U, 0x0000000000000000UL},
- {0x0138U, 0x0000000000000000UL},
- {0x0140U, 0x0000000000000000UL},
- {0x0148U, 0x0000000000000000UL},
- {0x0150U, 0x0000000000000000UL},
- {0x0158U, 0x0000000000000000UL},
- {0x0160U, 0x0000000000000000UL},
- {0x0168U, 0x0000000000000000UL},
- {0x0170U, 0x0000000000000000UL},
- {0x0178U, 0x0000000000000000UL},
- {0x0180U, 0x0000000000000000UL},
- {0x0188U, 0x0000000000000000UL},
- {0x0190U, 0x0000000000000000UL},
- {0x0198U, 0x0000000000000000UL},
- {0x01A0U, 0x0000000000000000UL},
- {0x01A8U, 0x0000000000000000UL},
- {0x01B0U, 0x0000000000000000UL},
- {0x01B8U, 0x0000000000000000UL},
- {0x01C0U, 0x001100500C8FFC01UL},
- {0x01C8U, 0x001100500C8FFC01UL},
- {0x01D0U, 0x001100500C8FFC01UL},
- {0x01D8U, 0x001100500C8FFC01UL},
- {0x01E0U, 0x0000000000000000UL},
- {0x01E8U, 0x001200100C803401UL},
- {0x01F0U, 0x001100100C80FC01UL},
- {0x01F8U, 0x0000000000000000UL},
- {0x0200U, 0x0000000000000000UL},
- {0x0208U, 0x001200100C80FC01UL},
- {0x0210U, 0x001100100C80FC01UL},
- {0x0218U, 0x001100100C825801UL},
- {0x0220U, 0x001100100C825801UL},
- {0x0228U, 0x0000000000000000UL},
- {0x0230U, 0x001100100C825801UL},
- {0x0238U, 0x001100100C825801UL},
- {0x0240U, 0x001200100C8BB801UL},
- {0x0248U, 0x001100100C8EA401UL},
- {0x0250U, 0x001200100C8BB801UL},
- {0x0258U, 0x001100100C8EA401UL},
- {0x0260U, 0x001100100C84E401UL},
- {0x0268U, 0x0000000000000000UL},
- {0x0270U, 0x0000000000000000UL},
- {0x0278U, 0x001100100C81F401UL},
- {0x0280U, 0x0000000000000000UL},
- {0x0288U, 0x0000000000000000UL},
- {0x0290U, 0x0000000000000000UL},
- {0x0298U, 0x0000000000000000UL},
- {0x02A0U, 0x0000000000000000UL},
- {0x02A8U, 0x0000000000000000UL},
- {0x02B0U, 0x0000000000000000UL},
- {0x02B8U, 0x001100100C803401UL},
- {0x02C0U, 0x0000000000000000UL},
- {0x02C8U, 0x0000000000000000UL},
- {0x02D0U, 0x0000000000000000UL},
- {0x02D8U, 0x0000000000000000UL},
- {0x02E0U, 0x0000000000000000UL},
- {0x02E8U, 0x001100100C803401UL},
- {0x02F0U, 0x001100300C8FFC01UL},
- {0x02F8U, 0x001100500C8FFC01UL},
- {0x0300U, 0x0000000000000000UL},
- {0x0308U, 0x001100300C8FFC01UL},
- {0x0310U, 0x001100500C8FFC01UL},
- {0x0318U, 0x001200100C803401UL},
- {0x0320U, 0x0000000000000000UL},
- {0x0328U, 0x0000000000000000UL},
- {0x0330U, 0x0000000000000000UL},
- {0x0338U, 0x0000000000000000UL},
- {0x0340U, 0x0000000000000000UL},
- {0x0348U, 0x0000000000000000UL},
- {0x0350U, 0x0000000000000000UL},
-};
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md = 0;
-
- /* BUFCAM settings */
- /* DBSC_DBCAM0CNF0 not set */
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
- io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */
- io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */
- /* DBSC_DBSCHCNT1 not set */
- io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
- io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
-
- md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
- switch (md) {
- case 0x0:
- /* DDR3200 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
- /* DDR2800 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
- /* DDR2400 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
- io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
- io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
- io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
- /* DBSC_DBSCHQOS_1_0 not set */
- /* DBSC_DBSCHQOS_1_1 not set */
- /* DBSC_DBSCHQOS_1_2 not set */
- /* DBSC_DBSCHQOS_1_3 not set */
- /* DBSC_DBSCHQOS_2_0 not set */
- /* DBSC_DBSCHQOS_2_1 not set */
- /* DBSC_DBSCHQOS_2_2 not set */
- /* DBSC_DBSCHQOS_2_3 not set */
- /* DBSC_DBSCHQOS_3_0 not set */
- /* DBSC_DBSCHQOS_3_1 not set */
- /* DBSC_DBSCHQOS_3_2 not set */
- /* DBSC_DBSCHQOS_3_3 not set */
- io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
- io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
- io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
- io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
- /* DBSC_DBSCHQOS_5_0 not set */
- /* DBSC_DBSCHQOS_5_1 not set */
- /* DBSC_DBSCHQOS_5_2 not set */
- /* DBSC_DBSCHQOS_5_3 not set */
- /* DBSC_DBSCHQOS_6_0 not set */
- /* DBSC_DBSCHQOS_6_1 not set */
- /* DBSC_DBSCHQOS_6_2 not set */
- /* DBSC_DBSCHQOS_6_3 not set */
- /* DBSC_DBSCHQOS_7_0 not set */
- /* DBSC_DBSCHQOS_7_1 not set */
- /* DBSC_DBSCHQOS_7_2 not set */
- /* DBSC_DBSCHQOS_7_3 not set */
- /* DBSC_DBSCHQOS_8_0 not set */
- /* DBSC_DBSCHQOS_8_1 not set */
- /* DBSC_DBSCHQOS_8_2 not set */
- /* DBSC_DBSCHQOS_8_3 not set */
- io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
- io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
- io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
- io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
- /* DBSC_DBSCHQOS_10_0 not set */
- /* DBSC_DBSCHQOS_10_1 not set */
- /* DBSC_DBSCHQOS_10_2 not set */
- /* DBSC_DBSCHQOS_10_3 not set */
- /* DBSC_DBSCHQOS_11_0 not set */
- /* DBSC_DBSCHQOS_11_1 not set */
- /* DBSC_DBSCHQOS_11_2 not set */
- /* DBSC_DBSCHQOS_11_3 not set */
- /* DBSC_DBSCHQOS_12_0 not set */
- /* DBSC_DBSCHQOS_12_1 not set */
- /* DBSC_DBSCHQOS_12_2 not set */
- /* DBSC_DBSCHQOS_12_3 not set */
- io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
- io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
- io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
- io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
- io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
- io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
- io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
- io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
- io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
- io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
-}
-
-void qos_init_m3_v10(void)
-{
- dbsc_setting();
-
- /* DRAM Split Address mapping */
-#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
-#if RCAR_LSI == RCAR_M3
-#error "Don't set DRAM Split 4ch(M3)"
-#else
- ERROR("DRAM Split 4ch not supported.(M3)");
- panic();
-#endif
-#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
- (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
- NOTICE("BL2: DRAM Split is 2ch\n");
- io_write_32(AXI_ADSPLCR0, 0x00000000U);
- io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1CU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR2, 0x089A0000U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- NOTICE("BL2: DRAM Split is OFF\n");
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
- /* Resource Alloc setting */
- io_write_32(RALLOC_RAS, 0x00000028U);
- io_write_32(RALLOC_FIXTH, 0x000F0005U);
- io_write_32(RALLOC_REGGD, 0x00000000U);
- io_write_64(RALLOC_DANN, 0x0101010102020201UL);
- io_write_32(RALLOC_DANT, 0x00100804U);
- io_write_32(RALLOC_EC, 0x00000000U);
- io_write_64(RALLOC_EMS, 0x0000000000000000UL);
- io_write_32(RALLOC_FSS, 0x000003e8U);
- io_write_32(RALLOC_INSFC, 0xC7840001U);
- io_write_32(RALLOC_BERR, 0x00000000U);
- io_write_32(RALLOC_RACNT0, 0x00000000U);
-
- /* MSTAT setting */
- io_write_32(MSTAT_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
- io_write_32(MSTAT_REF_ARS, 0x00330000U);
-
- /* MSTAT SRAM setting */
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
- mstat_fix[i].value);
- io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
- mstat_fix[i].value);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
- mstat_be[i].value);
- io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
- mstat_be[i].value);
- }
- }
-
- /* 3DG bus Leaf setting */
- io_write_32(0xFD820808U, 0x00001234U);
- io_write_32(0xFD820800U, 0x00000006U);
- io_write_32(0xFD821800U, 0x00000006U);
- io_write_32(0xFD822800U, 0x00000006U);
- io_write_32(0xFD823800U, 0x00000006U);
- io_write_32(0xFD824800U, 0x00000006U);
- io_write_32(0xFD825800U, 0x00000006U);
- io_write_32(0xFD826800U, 0x00000006U);
- io_write_32(0xFD827800U, 0x00000006U);
-
- /* RT bus Leaf setting */
- io_write_32(0xFFC50800U, 0x00000000U);
- io_write_32(0xFFC51800U, 0x00000000U);
-
- /* Resource Alloc start */
- io_write_32(RALLOC_RAEN, 0x00000001U);
-
- /* MSTAT start */
- io_write_32(MSTAT_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- /* Resource Alloc setting */
- io_write_32(RALLOC_EC, 0x00000000U);
- /* Resource Alloc start */
- io_write_32(RALLOC_RAEN, 0x00000001U);
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
deleted file mode 100644
index cee9dd0..0000000
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "../qos_reg.h"
-#include "qos_init_m3_v11.h"
-
-#define RCAR_QOS_VERSION "rev.0.19"
-
-
-#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
-
-#define QOSWT_WTEN_ENABLE (0x1U)
-
-#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 (SL_INIT_SSLOTCLK_M3_11 - 0x5U)
-
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
-#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-
-#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
-#define WT_BASE_SUB_SLOT_NUM0 (12U)
-#define QOSWT_WTSET0_PERIOD0_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
-#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#define QOSWT_WTSET1_PERIOD1_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
-#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_m3_v11_mstat195.h"
-#else
-#include "qos_init_m3_v11_mstat390.h"
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_m3_v11_qoswt195.h"
-#else
-#include "qos_init_m3_v11_qoswt390.h"
-#endif
-
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md = 0;
-
- /* BUFCAM settings */
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
- io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */
- io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
- io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
- io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
-
- md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
- switch (md) {
- case 0x0:
- /* DDR3200 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
- /* DDR2800 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
- /* DDR2400 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
- io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
- io_write_32(DBSC_DBSCHQOS02, 0x00000000);
- io_write_32(DBSC_DBSCHQOS03, 0x00000000);
- io_write_32(DBSC_DBSCHQOS40, 0x00000300);
- io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
- io_write_32(DBSC_DBSCHQOS42, 0x00000200);
- io_write_32(DBSC_DBSCHQOS43, 0x00000100);
- io_write_32(DBSC_DBSCHQOS90, 0x00000100);
- io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS93, 0x00000040);
- io_write_32(DBSC_DBSCHQOS120, 0x00000040);
- io_write_32(DBSC_DBSCHQOS121, 0x00000030);
- io_write_32(DBSC_DBSCHQOS122, 0x00000020);
- io_write_32(DBSC_DBSCHQOS123, 0x00000010);
- io_write_32(DBSC_DBSCHQOS130, 0x00000100);
- io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS133, 0x00000040);
- io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
- io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
- io_write_32(DBSC_DBSCHQOS142, 0x00000080);
- io_write_32(DBSC_DBSCHQOS143, 0x00000040);
- io_write_32(DBSC_DBSCHQOS150, 0x00000040);
- io_write_32(DBSC_DBSCHQOS151, 0x00000030);
- io_write_32(DBSC_DBSCHQOS152, 0x00000020);
- io_write_32(DBSC_DBSCHQOS153, 0x00000010);
-}
-
-void qos_init_m3_v11(void)
-{
- dbsc_setting();
-
- /* DRAM Split Address mapping */
-#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
-#if RCAR_LSI == RCAR_M3
-#error "Don't set DRAM Split 4ch(M3)"
-#else
- ERROR("DRAM Split 4ch not supported.(M3)");
- panic();
-#endif
-#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
- (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
- NOTICE("BL2: DRAM Split is 2ch\n");
- io_write_32(AXI_ADSPLCR0, 0x00000000U);
- io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1CU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR2, 0x00001004U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- NOTICE("BL2: DRAM Split is OFF\n");
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
- NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
-#else
- NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- NOTICE("BL2: Periodic Write DQ Training\n");
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_RAS, 0x00000044U);
- io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
- io_write_32(QOSCTRL_DANT, 0x0020100AU);
- io_write_32(QOSCTRL_INSFC, 0x06330001U);
- io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */
-
- io_write_32(QOSCTRL_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
- SL_INIT_SSLOTCLK_M3_11);
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- io_write_32(QOSCTRL_REF_ARS,
- ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 << 16)));
-#else
- io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
- io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
- io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
- }
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
- io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
- qoswt_fix[i]);
- io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
- qoswt_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
- io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
- io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
- }
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
- }
-
- /* 3DG bus Leaf setting */
- io_write_32(GPU_ACT_GRD, 0x00001234U);
- io_write_32(GPU_ACT0, 0x00000000U);
- io_write_32(GPU_ACT1, 0x00000000U);
- io_write_32(GPU_ACT2, 0x00000000U);
- io_write_32(GPU_ACT3, 0x00000000U);
-
- /* RT bus Leaf setting */
- io_write_32(RT_ACT0, 0x00000000U);
- io_write_32(RT_ACT1, 0x00000000U);
-
- /* CCI bus Leaf setting */
- io_write_32(CPU_ACT0, 0x00000003U);
- io_write_32(CPU_ACT1, 0x00000003U);
- io_write_32(CPU_ACT2, 0x00000003U);
- io_write_32(CPU_ACT3, 0x00000003U);
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- /* re-write training setting */
- io_write_32(QOSWT_WTREF,
- ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
- io_write_32(QOSWT_WTSET0,
- ((QOSWT_WTSET0_PERIOD0_M3_11 << 16) |
- (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
- io_write_32(QOSWT_WTSET1,
- ((QOSWT_WTSET1_PERIOD1_M3_11 << 16) |
- (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
-
- io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
deleted file mode 100644
index bbdb1fd..0000000
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "../qos_reg.h"
-#include "qos_init_m3_v30.h"
-
-#define RCAR_QOS_VERSION "rev.0.03"
-
-#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
-#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
-
-#define QOSWT_TIME_BANK0 (20000000U) //unit:ns
-
-#define QOSWT_WTEN_ENABLE (0x1U)
-
-#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 (SL_INIT_SSLOTCLK_M3_30 - 0x5U)
-
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
-#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-
-#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
-#define WT_BASE_SUB_SLOT_NUM0 (12U)
-#define QOSWT_WTSET0_PERIOD0_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
-#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#define QOSWT_WTSET1_PERIOD1_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
-#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_m3_v30_mstat195.h"
-#else
-#include "qos_init_m3_v30_mstat390.h"
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_m3_v30_qoswt195.h"
-#else
-#include "qos_init_m3_v30_qoswt390.h"
-#endif
-
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md=0;
-
- /* Register write enable */
- io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
-
- /* BUFCAM settings */
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
- io_write_32(DBSC_DBCAM0CNF3, 0x00000000); //dbcam0cnf3
- io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0
- io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
- io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
-
- md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17;
-
- switch (md) {
- case 0x0:
- /* DDR3200 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4)
- /* DDR2800 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4)
- /* DDR2400 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4)
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
- io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
- io_write_32(DBSC_DBSCHQOS02, 0x00000000);
- io_write_32(DBSC_DBSCHQOS03, 0x00000000);
- io_write_32(DBSC_DBSCHQOS40, 0x00000300);
- io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
- io_write_32(DBSC_DBSCHQOS42, 0x00000200);
- io_write_32(DBSC_DBSCHQOS43, 0x00000100);
- io_write_32(DBSC_DBSCHQOS90, 0x00000100);
- io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS93, 0x00000040);
- io_write_32(DBSC_DBSCHQOS120, 0x00000040);
- io_write_32(DBSC_DBSCHQOS121, 0x00000030);
- io_write_32(DBSC_DBSCHQOS122, 0x00000020);
- io_write_32(DBSC_DBSCHQOS123, 0x00000010);
- io_write_32(DBSC_DBSCHQOS130, 0x00000100);
- io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS133, 0x00000040);
- io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
- io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
- io_write_32(DBSC_DBSCHQOS142, 0x00000080);
- io_write_32(DBSC_DBSCHQOS143, 0x00000040);
- io_write_32(DBSC_DBSCHQOS150, 0x00000040);
- io_write_32(DBSC_DBSCHQOS151, 0x00000030);
- io_write_32(DBSC_DBSCHQOS152, 0x00000020);
- io_write_32(DBSC_DBSCHQOS153, 0x00000010);
-
- /* Register write protect */
- io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
-}
-
-void qos_init_m3_v30(void)
-{
- dbsc_setting();
-
- /* DRAM Split Address mapping */
-#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
- #if RCAR_LSI == RCAR_M3
- #error "Don't set DRAM Split 4ch(M3)"
- #else
- ERROR("DRAM Split 4ch not supported.(M3)");
- panic();
- #endif
-#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
- (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
- NOTICE("BL2: DRAM Split is 2ch\n");
- io_write_32(AXI_ADSPLCR0, 0x00000000U);
- io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
- | ADSPLCR0_SPLITSEL(0xFFU)
- | ADSPLCR0_AREA(0x1DU)
- | ADSPLCR0_SWP);
- io_write_32(AXI_ADSPLCR2, 0x00001004U);
- io_write_32(AXI_ADSPLCR3, 0x00000000U);
-#else
- NOTICE("BL2: DRAM Split is OFF\n");
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
- NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
-#else
- NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- NOTICE("BL2: Periodic Write DQ Training\n");
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_RAS, 0x00000044U);
- io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
- io_write_32(QOSCTRL_DANT, 0x0020100AU);
- io_write_32(QOSCTRL_FSS, 0x0000000AU);
- io_write_32(QOSCTRL_INSFC, 0x06330001U);
- io_write_32(QOSCTRL_EARLYR, 0x00000001U);
- io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */
-
- /* GPU Boost Mode */
- io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
-
- io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30);
- io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16)));
-
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(QOSBW_FIX_QOS_BANK0 + i*8,
- mstat_fix[i]);
- io_write_64(QOSBW_FIX_QOS_BANK1 + i*8,
- mstat_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(QOSBW_BE_QOS_BANK0 + i*8,
- mstat_be[i]);
- io_write_64(QOSBW_BE_QOS_BANK1 + i*8,
- mstat_be[i]);
- }
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
- io_write_64(QOSWT_FIX_WTQOS_BANK0 + i*8,
- qoswt_fix[i]);
- io_write_64(QOSWT_FIX_WTQOS_BANK1 + i*8,
- qoswt_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
- io_write_64(QOSWT_BE_WTQOS_BANK0 + i*8,
- qoswt_be[i]);
- io_write_64(QOSWT_BE_WTQOS_BANK1 + i*8,
- qoswt_be[i]);
- }
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
- }
-
- /* RT bus Leaf setting */
- io_write_32(RT_ACT0, 0x00000000U);
- io_write_32(RT_ACT1, 0x00000000U);
-
- /* CCI bus Leaf setting */
- io_write_32(CPU_ACT0, 0x00000003U);
- io_write_32(CPU_ACT1, 0x00000003U);
- io_write_32(CPU_ACT2, 0x00000003U);
- io_write_32(CPU_ACT3, 0x00000003U);
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- /* re-write training setting */
- io_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
- io_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_M3_30 << 16) | (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
- io_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_M3_30 << 16) | (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
-
- io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
deleted file mode 100644
index bd023e2..0000000
--- a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "../qos_common.h"
-#include "../qos_reg.h"
-#include "qos_init_m3n_v10.h"
-
-#define RCAR_QOS_VERSION "rev.0.09"
-
-#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
-#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
-
-#define REF_ARS_ARBSTOPCYCLE_M3N (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
-
-#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
-
-#define QOSWT_WTEN_ENABLE (0x1U)
-
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
-#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
-
-#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
-#define WT_BASE_SUB_SLOT_NUM0 (12U)
-#define QOSWT_WTSET0_PERIOD0_M3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3N)-1U)
-#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#define QOSWT_WTSET1_PERIOD1_M3N QOSWT_WTSET0_PERIOD0_M3N
-#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
-#define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_m3n_v10_mstat195.h"
-#else
-#include "qos_init_m3n_v10_mstat390.h"
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
-#include "qos_init_m3n_v10_qoswt195.h"
-#else
-#include "qos_init_m3n_v10_qoswt390.h"
-#endif
-
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-#endif
-
-static void dbsc_setting(void)
-{
- uint32_t md = 0;
-
- /* Register write enable */
- io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
-
- /* BUFCAM settings */
- io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
- io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
- io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
- io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
-
- md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
- switch (md) {
- case 0x0:
- /* DDR3200 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
- /* DDR2800 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
- /* DDR2400 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
- /* DDR1600 */
- io_write_32(DBSC_SCFCTST2, 0x012F1123);
- break;
- }
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
- io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
- io_write_32(DBSC_DBSCHQOS02, 0x00000000);
- io_write_32(DBSC_DBSCHQOS03, 0x00000000);
- io_write_32(DBSC_DBSCHQOS40, 0x00000300);
- io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
- io_write_32(DBSC_DBSCHQOS42, 0x00000200);
- io_write_32(DBSC_DBSCHQOS43, 0x00000100);
- io_write_32(DBSC_DBSCHQOS90, 0x00000100);
- io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS93, 0x00000040);
- io_write_32(DBSC_DBSCHQOS130, 0x00000100);
- io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
- io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
- io_write_32(DBSC_DBSCHQOS133, 0x00000040);
- io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
- io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
- io_write_32(DBSC_DBSCHQOS142, 0x00000080);
- io_write_32(DBSC_DBSCHQOS143, 0x00000040);
- io_write_32(DBSC_DBSCHQOS150, 0x00000040);
- io_write_32(DBSC_DBSCHQOS151, 0x00000030);
- io_write_32(DBSC_DBSCHQOS152, 0x00000020);
- io_write_32(DBSC_DBSCHQOS153, 0x00000010);
-
- /* Register write protect */
- io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
-}
-
-void qos_init_m3n_v10(void)
-{
- dbsc_setting();
-
- /* DRAM Split Address mapping */
-#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
-#if RCAR_LSI == RCAR_M3N
-#error "Don't set DRAM Split 4ch(M3N)"
-#else
- ERROR("DRAM Split 4ch not supported.(M3N)");
- panic();
-#endif
-#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
-#if RCAR_LSI == RCAR_M3N
-#error "Don't set DRAM Split 2ch(M3N)"
-#else
- ERROR("DRAM Split 2ch not supported.(M3N)");
- panic();
-#endif
-#else
- NOTICE("BL2: DRAM Split is OFF\n");
-#endif
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
-#if RCAR_REF_INT == RCAR_REF_DEFAULT
- NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
-#else
- NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
-#endif
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- NOTICE("BL2: Periodic Write DQ Training\n");
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_RAS, 0x00000028U);
- io_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
- io_write_32(QOSCTRL_DANT, 0x00100804U);
- io_write_32(QOSCTRL_FSS, 0x0000000AU);
- io_write_32(QOSCTRL_INSFC, 0x06330001U);
- io_write_32(QOSCTRL_EARLYR, 0x00000001U);
- io_write_32(QOSCTRL_RACNT0, 0x00010003U);
-
- io_write_32(QOSCTRL_SL_INIT,
- SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
- SL_INIT_SSLOTCLK_M3N);
- io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_M3N);
-
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
- io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
- io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
- }
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
- io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
- qoswt_fix[i]);
- io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
- qoswt_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
- io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
- io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
- }
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
- }
-
- /* RT bus Leaf setting */
- io_write_32(RT_ACT0, 0x00000000U);
- io_write_32(RT_ACT1, 0x00000000U);
-
- /* CCI bus Leaf setting */
- io_write_32(CPU_ACT0, 0x00000003U);
- io_write_32(CPU_ACT1, 0x00000003U);
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- /* re-write training setting */
- io_write_32(QOSWT_WTREF,
- ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
- io_write_32(QOSWT_WTSET0,
- ((QOSWT_WTSET0_PERIOD0_M3N << 16) |
- (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
- io_write_32(QOSWT_WTSET1,
- ((QOSWT_WTSET1_PERIOD1_M3N << 16) |
- (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
-
- io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-
- io_write_32(QOSCTRL_STATQC, 0x00000001U);
-#else
- NOTICE("BL2: QoS is None\n");
-
- io_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c b/drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
deleted file mode 100644
index 2700b37..0000000
--- a/drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <common/debug.h>
-#include "qos_init_v3m.h"
-
-#define RCAR_QOS_VERSION "rev.0.01"
-
-#define RCAR_QOS_NONE (3U)
-#define RCAR_QOS_TYPE_DEFAULT (0U)
-
-#define RCAR_DRAM_SPLIT_LINEAR (0U)
-#define RCAR_DRAM_SPLIT_4CH (1U)
-#define RCAR_DRAM_SPLIT_2CH (2U)
-
-#define DBSC_BASE (0xE6790000U)
-#define DBSC_AXARB (DBSC_BASE + 0x0800U)
-
-#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
-#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
-#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
-#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
-#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
-#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
-#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
-#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
-#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
-#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
-#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
-#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
-#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
-#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
-#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
-#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
-#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
-#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
-#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
-#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
-#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
-#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
-#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
-#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
-#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
-#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
-#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
-#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
-#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
-#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
-#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
-#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
-#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
-#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
-#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
-#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
-#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
-#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
-#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
-#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
-#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
-#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
-#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
-#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
-#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
-#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
-#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
-#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
-#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
-#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
-
-#define AXI_BASE (0xE6784000U)
-#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
-#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
-#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
-#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
-#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
-#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
-#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
-#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
-#define ADSPLCR0_SWP (0x0CU)
-
-#define MSTAT_BASE (0xE67E0000U)
-#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
-#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
-#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
-#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
-#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
-#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
-#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
-
-#define RALLOC_BASE (0xE67F0000U)
-#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
-#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
-#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
-#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
-#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
-#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
-#define RALLOC_EC (RALLOC_BASE + 0x003CU)
-#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
-#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
-#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
-#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
-
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-
-static inline void io_write_32(uintptr_t addr, uint32_t value)
-{
- *(volatile uint32_t*)addr = value;
-}
-
-static inline void io_write_64(uintptr_t addr, uint64_t value)
-{
- *(volatile uint64_t*)addr = value;
-}
-
-
-typedef struct {
- uintptr_t addr;
- uint64_t value;
-} mstat_slot_t;
-
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
-static const mstat_slot_t mstat_fix[] = {
- {0x0000U, 0x000000000000FFFFU},
- {0x0008U, 0x000000000000FFFFU},
- {0x0010U, 0x000000000000FFFFU},
- {0x0018U, 0x000000000000FFFFU},
- {0x0020U, 0x001414090000FFFFU},
- {0x0028U, 0x000C00000000FFFFU},
- {0x0030U, 0x001008040000FFFFU},
- {0x0038U, 0x001004040000FFFFU},
- {0x0040U, 0x001004040000FFFFU},
- {0x0048U, 0x000000000000FFFFU},
- {0x0050U, 0x001004040000FFFFU},
- {0x0058U, 0x001004040000FFFFU},
- {0x0060U, 0x000000000000FFFFU},
- {0x0068U, 0x001404040000FFFFU},
- {0x0070U, 0x001008030000FFFFU},
- {0x0078U, 0x001004030000FFFFU},
- {0x0080U, 0x001004030000FFFFU},
- {0x0088U, 0x000000000000FFFFU},
- {0x0090U, 0x001004040000FFFFU},
- {0x0098U, 0x001004040000FFFFU},
- {0x00A0U, 0x000000000000FFFFU},
- {0x00A8U, 0x000000000000FFFFU},
- {0x00B0U, 0x000000000000FFFFU},
- {0x00B8U, 0x000000000000FFFFU},
- {0x00C0U, 0x000000000000FFFFU},
- {0x00C8U, 0x000000000000FFFFU},
- {0x00D0U, 0x000000000000FFFFU},
- {0x00D8U, 0x000000000000FFFFU},
- {0x00E0U, 0x001404020000FFFFU},
- {0x00E8U, 0x000000000000FFFFU},
- {0x00F0U, 0x000000000000FFFFU},
- {0x00F8U, 0x000000000000FFFFU},
- {0x0100U, 0x000000000000FFFFU},
- {0x0108U, 0x000C04020000FFFFU},
- {0x0110U, 0x000000000000FFFFU},
- {0x0118U, 0x001404020000FFFFU},
- {0x0120U, 0x000000000000FFFFU},
- {0x0128U, 0x000000000000FFFFU},
- {0x0130U, 0x000000000000FFFFU},
- {0x0138U, 0x000000000000FFFFU},
- {0x0140U, 0x000000000000FFFFU},
- {0x0148U, 0x000000000000FFFFU},
-};
-
-static const mstat_slot_t mstat_be[] = {
- {0x0000U, 0x00100020447FFC01U},
- {0x0008U, 0x00100020447FFC01U},
- {0x0010U, 0x00100040447FFC01U},
- {0x0018U, 0x00100040447FFC01U},
- {0x0020U, 0x0000000000000000U},
- {0x0028U, 0x0000000000000000U},
- {0x0030U, 0x0000000000000000U},
- {0x0038U, 0x0000000000000000U},
- {0x0040U, 0x0000000000000000U},
- {0x0048U, 0x0000000000000000U},
- {0x0050U, 0x0000000000000000U},
- {0x0058U, 0x0000000000000000U},
- {0x0060U, 0x0000000000000000U},
- {0x0068U, 0x0000000000000000U},
- {0x0070U, 0x0000000000000000U},
- {0x0078U, 0x0000000000000000U},
- {0x0080U, 0x0000000000000000U},
- {0x0088U, 0x0000000000000000U},
- {0x0090U, 0x0000000000000000U},
- {0x0098U, 0x0000000000000000U},
- {0x00A0U, 0x00100010447FFC01U},
- {0x00A8U, 0x00100010447FFC01U},
- {0x00B0U, 0x00100010447FFC01U},
- {0x00B8U, 0x00100010447FFC01U},
- {0x00C0U, 0x00100010447FFC01U},
- {0x00C8U, 0x00100010447FFC01U},
- {0x00D0U, 0x0000000000000000U},
- {0x00D8U, 0x00100010447FFC01U},
- {0x00E0U, 0x0000000000000000U},
- {0x00E8U, 0x00100010447FFC01U},
- {0x00F0U, 0x00100010447FFC01U},
- {0x00F8U, 0x00100010447FFC01U},
- {0x0100U, 0x00100010447FFC01U},
- {0x0108U, 0x0000000000000000U},
- {0x0110U, 0x00100010447FFC01U},
- {0x0118U, 0x0000000000000000U},
- {0x0120U, 0x00100010447FFC01U},
- {0x0128U, 0x00100010447FFC01U},
- {0x0130U, 0x00100010447FFC01U},
- {0x0138U, 0x00100010447FFC01U},
- {0x0140U, 0x00100020447FFC01U},
- {0x0148U, 0x00100020447FFC01U},
-};
-#endif
-
-static void dbsc_setting(void)
-{
-
- /* BUFCAM settings */
- //DBSC_DBCAM0CNF0 not set
- io_write_32(DBSC_DBCAM0CNF1, 0x00044218); //dbcam0cnf1
- io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
- //io_write_32(DBSC_DBCAM0CNF3, 0x00000007); //dbcam0cnf3
- io_write_32(DBSC_DBSCHCNT0, 0x080F003F); //dbschcnt0
- io_write_32(DBSC_DBSCHCNT1, 0x00001010); //dbschcnt0
-
- io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
- io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
- io_write_32(DBSC_DBSCHRW1, 0x00180034); //dbschrw1
- io_write_32(DBSC_SCFCTST0,0x180B1708);
- io_write_32(DBSC_SCFCTST1,0x0808070C);
- io_write_32(DBSC_SCFCTST2,0x012F1123);
-
- /* QoS Settings */
- io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
- io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
- io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
- io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
- //DBSC_DBSCHQOS_1_0 not set
- //DBSC_DBSCHQOS_1_1 not set
- //DBSC_DBSCHQOS_1_2 not set
- //DBSC_DBSCHQOS_1_3 not set
- //DBSC_DBSCHQOS_2_0 not set
- //DBSC_DBSCHQOS_2_1 not set
- //DBSC_DBSCHQOS_2_2 not set
- //DBSC_DBSCHQOS_2_3 not set
- //DBSC_DBSCHQOS_3_0 not set
- //DBSC_DBSCHQOS_3_1 not set
- //DBSC_DBSCHQOS_3_2 not set
- //DBSC_DBSCHQOS_3_3 not set
- io_write_32(DBSC_DBSCHQOS_4_0, 0x0000F000);
- io_write_32(DBSC_DBSCHQOS_4_1, 0x0000EFFF);
- io_write_32(DBSC_DBSCHQOS_4_2, 0x0000B000);
- io_write_32(DBSC_DBSCHQOS_4_3, 0x00000000);
- //DBSC_DBSCHQOS_5_0 not set
- //DBSC_DBSCHQOS_5_1 not set
- //DBSC_DBSCHQOS_5_2 not set
- //DBSC_DBSCHQOS_5_3 not set
- //DBSC_DBSCHQOS_6_0 not set
- //DBSC_DBSCHQOS_6_1 not set
- //DBSC_DBSCHQOS_6_2 not set
- //DBSC_DBSCHQOS_6_3 not set
- //DBSC_DBSCHQOS_7_0 not set
- //DBSC_DBSCHQOS_7_1 not set
- //DBSC_DBSCHQOS_7_2 not set
- //DBSC_DBSCHQOS_7_3 not set
- //DBSC_DBSCHQOS_8_0 not set
- //DBSC_DBSCHQOS_8_1 not set
- //DBSC_DBSCHQOS_8_2 not set
- //DBSC_DBSCHQOS_8_3 not set
- io_write_32(DBSC_DBSCHQOS_9_0, 0x0000F000);
- io_write_32(DBSC_DBSCHQOS_9_1, 0x0000EFFF);
- io_write_32(DBSC_DBSCHQOS_9_2, 0x0000D000);
- io_write_32(DBSC_DBSCHQOS_9_3, 0x00000000);
- //DBSC_DBSCHQOS_10_0 not set
- //DBSC_DBSCHQOS_10_1 not set
- //DBSC_DBSCHQOS_10_2 not set
- //DBSC_DBSCHQOS_10_3 not set
- //DBSC_DBSCHQOS_11_0 not set
- //DBSC_DBSCHQOS_11_1 not set
- //DBSC_DBSCHQOS_11_2 not set
- //DBSC_DBSCHQOS_11_3 not set
- //DBSC_DBSCHQOS_12_0 not set
- //DBSC_DBSCHQOS_12_1 not set
- //DBSC_DBSCHQOS_12_2 not set
- //DBSC_DBSCHQOS_12_3 not set
- io_write_32(DBSC_DBSCHQOS_13_0, 0x0000F000);
- io_write_32(DBSC_DBSCHQOS_13_1, 0x0000EFFF);
- io_write_32(DBSC_DBSCHQOS_13_2, 0x0000E800);
- io_write_32(DBSC_DBSCHQOS_13_3, 0x00007000);
- io_write_32(DBSC_DBSCHQOS_14_0, 0x0000F000);
- io_write_32(DBSC_DBSCHQOS_14_1, 0x0000EFFF);
- io_write_32(DBSC_DBSCHQOS_14_2, 0x0000E800);
- io_write_32(DBSC_DBSCHQOS_14_3, 0x0000B000);
- io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
- io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
- io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
- io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
-}
-
-void qos_init_v3m(void)
-{
-return;
-
- dbsc_setting();
-
-#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
-#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
- NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
-#endif
-
- /* Resource Alloc setting */
- io_write_32(RALLOC_RAS, 0x00000020U);
- io_write_32(RALLOC_FIXTH, 0x000F0005U);
- io_write_32(RALLOC_REGGD, 0x00000004U);
- io_write_64(RALLOC_DANN, 0x0202020104040200U);
- io_write_32(RALLOC_DANT, 0x00201008U);
- io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */
- io_write_64(RALLOC_EMS, 0x0000000000000000U);
- io_write_32(RALLOC_INSFC, 0x63C20001U);
- io_write_32(RALLOC_BERR, 0x00000000U);
-
- /* MSTAT setting */
- io_write_32(MSTAT_SL_INIT, 0x0305007DU);
- io_write_32(MSTAT_REF_ARS, 0x00330000U);
-
- /* MSTAT SRAM setting */
- {
- uint32_t i;
-
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
- mstat_fix[i].value);
- io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
- mstat_fix[i].value);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
- mstat_be[i].value);
- io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
- mstat_be[i].value);
- }
- }
-
- /* AXI-IF arbitration setting */
- io_write_32(DBSC_AXARB, 0x18010000U);
-
- /* Resource Alloc start */
- io_write_32(RALLOC_RAEN, 0x00000001U);
-
- /* MSTAT start */
- io_write_32(MSTAT_STATQC, 0x00000001U);
-
-#else
- NOTICE("BL2: QoS is None\n");
-#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
-}
diff --git a/drivers/staging/renesas/rcar/qos/qos.mk b/drivers/staging/renesas/rcar/qos/qos.mk
deleted file mode 100644
index d00e622..0000000
--- a/drivers/staging/renesas/rcar/qos/qos.mk
+++ /dev/null
@@ -1,106 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_AUTO})
-# E3, H3N not available for LSI_AUTO
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
-else ifdef RCAR_LSI_CUT_COMPAT
- ifeq (${RCAR_LSI},${RCAR_H3})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
- endif
- ifeq (${RCAR_LSI},${RCAR_H3N})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
- endif
- ifeq (${RCAR_LSI},${RCAR_M3})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
- endif
- ifeq (${RCAR_LSI},${RCAR_M3N})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
- endif
- ifeq (${RCAR_LSI},${RCAR_V3M})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
- endif
- ifeq (${RCAR_LSI},${RCAR_E3})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
- endif
- ifeq (${RCAR_LSI},${RCAR_D3})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
- endif
-else
- ifeq (${RCAR_LSI},${RCAR_H3})
- ifeq (${LSI_CUT},10)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
- else ifeq (${LSI_CUT},11)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
- else ifeq (${LSI_CUT},20)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
- else ifeq (${LSI_CUT},30)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
- else
-# LSI_CUT 30 or later
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
- endif
- endif
- ifeq (${RCAR_LSI},${RCAR_H3N})
- ifeq (${LSI_CUT},30)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
- else
-# LSI_CUT 30 or later
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
- endif
- endif
- ifeq (${RCAR_LSI},${RCAR_M3})
- ifeq (${LSI_CUT},10)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
- else ifeq (${LSI_CUT},11)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
- else ifeq (${LSI_CUT},13)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
- else ifeq (${LSI_CUT},30)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
- else
-# LSI_CUT 30 or later
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
- endif
- endif
- ifeq (${RCAR_LSI},${RCAR_M3N})
- ifeq (${LSI_CUT},10)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
- else
-# LSI_CUT 10 or later
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
- endif
- endif
- ifeq (${RCAR_LSI},${RCAR_V3M})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
- endif
- ifeq (${RCAR_LSI},${RCAR_E3})
- ifeq (${LSI_CUT},10)
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
- else
-# LSI_CUT 10 or later
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
- endif
- endif
- ifeq (${RCAR_LSI},${RCAR_D3})
- BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_d3.c
- endif
-endif
-
-BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c
diff --git a/drivers/staging/renesas/rcar/qos/qos_common.h b/drivers/staging/renesas/rcar/qos/qos_common.h
deleted file mode 100644
index c3a83ac..0000000
--- a/drivers/staging/renesas/rcar/qos/qos_common.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef QOS_COMMON_H
-#define QOS_COMMON_H
-
-#define RCAR_REF_DEFAULT (0U)
-
-/* define used for get_refperiod. */
-/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
-/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
-#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
-#define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
-#else /* REF option */
-#define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
-#endif
-
-#if (RCAR_LSI == RCAR_E3)
-/* define used for E3 */
-#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_E3 (0xAFU) /* 175 */
-#else /* REF 7.8usec */
-#define SUB_SLOT_CYCLE_E3 (0x15EU) /* 350 */
-#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-
-#define OPERATING_FREQ_E3 (266U) /* MHz */
-#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
-/* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
-/* define used for M3N */
-#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
-#define SUB_SLOT_CYCLE_M3N (0x7EU) /* 126 */
-#else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_M3N (0xFCU) /* 252 */
-#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-
-#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
-#define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
-/* define used for H3 */
-#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
-#define SUB_SLOT_CYCLE_H3_20 (0x7EU) /* 126 */
-#else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_H3_20 (0xFCU) /* 252 */
-#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-
-#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
-#define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
-
-/* define used for H3 Cut 30 */
-#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
-#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U)
-#define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
-
-#endif
-
-#if (RCAR_LSI == RCAR_H3N)
-/* define used for H3N */
-#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
-#define SUB_SLOT_CYCLE_H3N (0x7EU) /* 126 */
-#else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_H3N (0xFCU) /* 252 */
-#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-
-#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
-#define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
-
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
-/* define used for M3 */
-#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
-#define SUB_SLOT_CYCLE_M3_11 (0x7EU) /* 126 */
-#define SUB_SLOT_CYCLE_M3_30 (0x7EU) /* 126 */
-#else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_M3_11 (0xFCU) /* 252 */
-#define SUB_SLOT_CYCLE_M3_30 (0xFCU) /* 252 */
-#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-
-#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
-#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 -1U)
-#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
-#define QOSWT_WTSET0_CYCLE_M3_30 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
-#endif
-
-#define OPERATING_FREQ (400U) /* MHz */
-#define BASE_SUB_SLOT_NUM (0x6U)
-#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
-
-#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
-
-#define SL_INIT_REFFSSLOT (0x3U << 24U)
-#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
-#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U)
-
-static inline void io_write_32(uintptr_t addr, uint32_t value)
-{
- *(volatile uint32_t *)addr = value;
-}
-
-static inline uint32_t io_read_32(uintptr_t addr)
-{
- return *(volatile uint32_t *)addr;
-}
-
-static inline void io_write_64(uintptr_t addr, uint64_t value)
-{
- *(volatile uint64_t *)addr = value;
-}
-
-typedef struct {
- uintptr_t addr;
- uint64_t value;
-} mstat_slot_t;
-
-extern uint32_t qos_init_ddr_ch;
-extern uint8_t qos_init_ddr_phyvalid;
-
-#endif /* QOS_COMMON_H */
diff --git a/drivers/staging/renesas/rcar/qos/qos_reg.h b/drivers/staging/renesas/rcar/qos/qos_reg.h
deleted file mode 100644
index 759816f..0000000
--- a/drivers/staging/renesas/rcar/qos/qos_reg.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef QOS_REG_H
-#define QOS_REG_H
-
-#define RCAR_QOS_NONE (3U)
-#define RCAR_QOS_TYPE_DEFAULT (0U)
-
-#define RCAR_DRAM_SPLIT_LINEAR (0U)
-#define RCAR_DRAM_SPLIT_4CH (1U)
-#define RCAR_DRAM_SPLIT_2CH (2U)
-#define RCAR_DRAM_SPLIT_AUTO (3U)
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-
-#define DBSC_BASE (0xE6790000U)
-#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
-#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
-#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
-#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
-#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
-#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
-#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
-#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
-#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
-
-#define AXI_BASE (0xE6784000U)
-#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
-#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
-#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
-#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
-#define AXI_MMCR (AXI_BASE + 0x0300U)
-#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
-#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
-#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
-#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
-#define ADSPLCR0_SWP (0x0CU)
-
-#define AXI_TR3CR (0xE67D100CU)
-#define AXI_TR4CR (0xE67D1014U)
-
-#define QOS_BASE0 (0xE67E0000U)
-#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
-#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
-#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
-#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
-#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
-#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
-#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
-
-#define QOS_BASE1 (0xE67F0000U)
-#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
-#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
-#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
-#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
-#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
-#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
-#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
-
-#define GPU_ACT_GRD (0xFD820808U)
-#define GPU_ACT0 (0xFD820800U)
-#define GPU_ACT1 (0xFD821800U)
-#define GPU_ACT2 (0xFD822800U)
-#define GPU_ACT3 (0xFD823800U)
-#define GPU_ACT4 (0xFD824800U)
-#define GPU_ACT5 (0xFD825800U)
-#define GPU_ACT6 (0xFD826800U)
-#define GPU_ACT7 (0xFD827800U)
-
-#define RT_ACT0 (0xFFC50800U)
-#define RT_ACT1 (0xFFC51800U)
-
-#define CPU_ACT0 (0xF1300800U)
-#define CPU_ACT1 (0xF1340800U)
-#define CPU_ACT2 (0xF1380800U)
-#define CPU_ACT3 (0xF13C0800U)
-
-#define RCAR_REWT_TRAINING_DISABLE (0U)
-#define RCAR_REWT_TRAINING_ENABLE (1U)
-
-#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
-#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
-#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
-#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
-#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
-#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
-#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
-#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
-
-#endif /* QOS_REG_H */
diff --git a/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
index 16b8cf6..11e8f2b 100644
--- a/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-/* STM32MP157C DK1/DK2 BOARD configuration
+ *
+ * STM32MP157C DK1/DK2 BOARD configuration
* 1x DDR3L 4Gb, 16-bit, 533MHz.
* Reference used NT5CC256M16DP-DI from NANYA
*
@@ -16,8 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41"
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
@@ -90,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
@@ -109,11 +108,11 @@
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
-#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
-#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
diff --git a/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
index 82e7104..4b70b60 100644
--- a/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-/* STM32MP157C ED1 BOARD configuration
+ *
+ * STM32MP157C ED1 BOARD configuration
* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
* Reference used NT5CC256M16DP-DI from NANYA
*
@@ -17,8 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.41"
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000
@@ -91,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi
index c7553ca..8e480b2 100644
--- a/fdts/stm32mp157-pinctrl.dtsi
+++ b/fdts/stm32mp157-pinctrl.dtsi
@@ -214,21 +214,6 @@
};
};
- sdmmc1_dir_pins_b: sdmmc1-dir-1 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 12, AF8)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
@@ -286,6 +271,19 @@
};
};
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
+ bias-disable;
+ };
+ };
+
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@@ -300,6 +298,21 @@
bias-disable;
};
};
+
+ usart3_pins_b: usart3-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
+ bias-disable;
+ };
+ };
};
pinctrl_z: pin-controller-z@54004000 {
diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts
index 68188be..b17d501 100644
--- a/fdts/stm32mp157a-dk1.dts
+++ b/fdts/stm32mp157a-dk1.dts
@@ -15,6 +15,8 @@
aliases {
serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
};
chosen {
@@ -146,6 +148,12 @@
status = "okay";
};
+&pwr {
+ pwr-regulators {
+ vdd-supply = <&vdd>;
+ };
+};
+
&rng1 {
status = "okay";
};
@@ -170,6 +178,18 @@
status = "okay";
};
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "disabled";
+};
+
+&usart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usart3_pins_b>;
+ status = "disabled";
+};
+
/* ATF Specific */
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
@@ -281,3 +301,11 @@
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
};
};
+
+&bsec {
+ board_id: board_id@ec {
+ reg = <0xec 0x4>;
+ status = "okay";
+ secure-status = "okay";
+ };
+};
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index 820e413..ed55725 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -42,7 +42,7 @@
st,main-control-register = <0x04>;
st,vin-control-register = <0xc0>;
- st,usb-control-register = <0x30>;
+ st,usb-control-register = <0x20>;
regulators {
compatible = "st,stpmic1-regulators";
@@ -143,6 +143,12 @@
status = "okay";
};
+&pwr {
+ pwr-regulators {
+ vdd-supply = <&vdd>;
+ };
+};
+
&rng1 {
status = "okay";
};
@@ -302,4 +308,10 @@
};
};
-/delete-node/ &clk_csi;
+&bsec {
+ board_id: board_id@ec {
+ reg = <0xec 0x4>;
+ status = "okay";
+ secure-status = "okay";
+ };
+};
diff --git a/fdts/stm32mp157c-security.dtsi b/fdts/stm32mp157c-security.dtsi
index 59119c5..f7e55b3 100644
--- a/fdts/stm32mp157c-security.dtsi
+++ b/fdts/stm32mp157c-security.dtsi
@@ -26,9 +26,12 @@
status = "okay";
secure-status = "okay";
};
- board_id: board_id@ec {
- reg = <0xec 0x4>;
- status = "okay";
- secure-status = "okay";
- };
+};
+
+&sdmmc1 {
+ compatible = "st,stm32-sdmmc2";
+};
+
+&sdmmc2 {
+ compatible = "st,stm32-sdmmc2";
};
diff --git a/fdts/stm32mp157c.dtsi b/fdts/stm32mp157c.dtsi
index 0ec7ecb..0942a91 100644
--- a/fdts/stm32mp157c.dtsi
+++ b/fdts/stm32mp157c.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -70,6 +70,16 @@
interrupt-parent = <&intc>;
ranges;
+ timers12: timer@40006000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40006000 0x400>;
+ clocks = <&rcc TIM12_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+
usart2: serial@4000e000 {
compatible = "st,stm32h7-uart";
reg = <0x4000e000 0x400>;
@@ -127,8 +137,19 @@
status = "disabled";
};
+ timers15: timer@44006000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x44006000 0x400>;
+ clocks = <&rcc TIM15_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+
sdmmc3: sdmmc@48004000 {
- compatible = "st,stm32-sdmmc2";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>, <0x48005000 0x400>;
clocks = <&rcc SDMMC3_K>;
clock-names = "apb_pclk";
@@ -139,6 +160,16 @@
status = "disabled";
};
+ usbotg_hs: usb-otg@49000000 {
+ compatible = "st,stm32mp1-hsotg", "snps,dwc2";
+ reg = <0x49000000 0x10000>;
+ clocks = <&rcc USBO_K>;
+ clock-names = "otg";
+ resets = <&rcc USBO_R>;
+ reset-names = "dwc2";
+ status = "disabled";
+ };
+
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
@@ -170,6 +201,30 @@
};
};
+ syscfg: syscon@50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ clocks = <&rcc SYSCFG>;
+ };
+
+ cryp1: cryp@54001000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54001000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
+ status = "disabled";
+ };
+
+ hash1: hash@54002000 {
+ compatible = "st,stm32f756-hash";
+ reg = <0x54002000 0x400>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc HASH1>;
+ resets = <&rcc HASH1_R>;
+ status = "disabled";
+ };
+
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
@@ -202,7 +257,8 @@
};
sdmmc1: sdmmc@58005000 {
- compatible = "st,stm32-sdmmc2";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
@@ -214,7 +270,8 @@
};
sdmmc2: sdmmc@58007000 {
- compatible = "st,stm32-sdmmc2";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 44044d4..0db4145 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -81,6 +81,10 @@
* Generic timer memory mapped registers & offsets
******************************************************************************/
#define CNTCR_OFF U(0x000)
+/* Counter Count Value Lower register */
+#define CNTCVL_OFF U(0x008)
+/* Counter Count Value Upper register */
+#define CNTCVU_OFF U(0x00C)
#define CNTFID_OFF U(0x020)
#define CNTCR_EN (U(1) << 0)
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index d23d89e..502b868 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -99,6 +99,7 @@
* Generic timer memory mapped registers & offsets
******************************************************************************/
#define CNTCR_OFF U(0x000)
+#define CNTCV_OFF U(0x008)
#define CNTFID_OFF U(0x020)
#define CNTCR_EN (U(1) << 0)
diff --git a/include/drivers/auth/auth_mod.h b/include/drivers/auth/auth_mod.h
index 39f5372..6c48124 100644
--- a/include/drivers/auth/auth_mod.h
+++ b/include/drivers/auth/auth_mod.h
@@ -40,11 +40,10 @@
/* Macro to register a CoT defined as an array of auth_img_desc_t pointers */
#define REGISTER_COT(_cot) \
- const auth_img_desc_t **const cot_desc_ptr = \
- (const auth_img_desc_t **const)_cot; \
+ const auth_img_desc_t *const *const cot_desc_ptr = (_cot); \
unsigned int auth_img_flags[MAX_NUMBER_IDS]
-extern const auth_img_desc_t **const cot_desc_ptr;
+extern const auth_img_desc_t *const *const cot_desc_ptr;
extern unsigned int auth_img_flags[MAX_NUMBER_IDS];
#endif /* TRUSTED_BOARD_BOOT */
diff --git a/include/drivers/renesas/rcar/console/console.h b/include/drivers/renesas/rcar/console/console.h
new file mode 100644
index 0000000..5bc10b7
--- /dev/null
+++ b/include/drivers/renesas/rcar/console/console.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RCAR_PRINTF_H
+#define RCAR_PRINTF_H
+
+#define CONSOLE_T_RCAR_BASE CONSOLE_T_DRVDATA
+
+#ifndef __ASSEMBLY__
+
+#include <stdint.h>
+
+typedef struct {
+ console_t console;
+ uintptr_t base;
+} console_rcar_t;
+
+/*
+ * Initialize a new rcar console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ */
+int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_rcar_t *console);
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* RCAR_PRINTF_H */
diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h
index 7afa5ad..1ebd39f 100644
--- a/include/drivers/st/stm32mp1_clk.h
+++ b/include/drivers/st/stm32mp1_clk.h
@@ -9,6 +9,19 @@
#include <arch_helpers.h>
+enum stm32mp_osc_id {
+ _HSI,
+ _HSE,
+ _CSI,
+ _LSI,
+ _LSE,
+ _I2S_CKIN,
+ NB_OSC,
+ _UNKNOWN_OSC_ID = 0xFF
+};
+
+extern const char *stm32mp_osc_node_label[NB_OSC];
+
int stm32mp1_clk_probe(void);
int stm32mp1_clk_init(void);
diff --git a/include/drivers/st/stm32mp1_clkfunc.h b/include/drivers/st/stm32mp1_clkfunc.h
deleted file mode 100644
index f303937..0000000
--- a/include/drivers/st/stm32mp1_clkfunc.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef STM32MP1_CLKFUNC_H
-#define STM32MP1_CLKFUNC_H
-
-#include <stdbool.h>
-
-#include <libfdt.h>
-
-enum stm32mp_osc_id {
- _HSI,
- _HSE,
- _CSI,
- _LSI,
- _LSE,
- _I2S_CKIN,
- NB_OSC,
- _UNKNOWN_OSC_ID = 0xFF
-};
-
-extern const char *stm32mp_osc_node_label[NB_OSC];
-
-int fdt_osc_read_freq(const char *name, uint32_t *freq);
-bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name);
-uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
- const char *prop_name,
- uint32_t dflt_value);
-
-#endif /* STM32MP1_CLKFUNC_H */
diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h
index eaa853d..4b4aac8 100644
--- a/include/drivers/st/stm32mp1_rcc.h
+++ b/include/drivers/st/stm32mp1_rcc.h
@@ -480,4 +480,82 @@
/* Values of RCC_PWRLPDLYCR register */
#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0)
+/* RCC_ASSCKSELR register fields */
+#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0)
+#define RCC_ASSCKSELR_AXISSRC_SHIFT 0
+
+/* RCC_MSSCKSELR register fields */
+#define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0)
+#define RCC_MSSCKSELR_MCUSSRC_SHIFT 0
+
+/* RCC_I2C46CKSELR register fields */
+#define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0)
+#define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0
+
+/* RCC_SPI6CKSELR register fields */
+#define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0)
+#define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0
+
+/* RCC_UART1CKSELR register fields */
+#define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0)
+#define RCC_UART1CKSELR_UART1SRC_SHIFT 0
+
+/* RCC_RNG1CKSELR register fields */
+#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0)
+#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0
+
+/* RCC_STGENCKSELR register fields */
+#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0)
+#define RCC_STGENCKSELR_STGENSRC_SHIFT 0
+
+/* RCC_I2C12CKSELR register fields */
+#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0)
+#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0
+
+/* RCC_I2C35CKSELR register fields */
+#define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0)
+#define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0
+
+/* RCC_UART6CKSELR register fields */
+#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0)
+#define RCC_UART6CKSELR_UART6SRC_SHIFT 0
+
+/* RCC_UART24CKSELR register fields */
+#define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0)
+#define RCC_UART24CKSELR_UART24SRC_SHIFT 0
+
+/* RCC_UART35CKSELR register fields */
+#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0)
+#define RCC_UART35CKSELR_UART35SRC_SHIFT 0
+
+/* RCC_UART78CKSELR register fields */
+#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0)
+#define RCC_UART78CKSELR_UART78SRC_SHIFT 0
+
+/* RCC_SDMMC12CKSELR register fields */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0)
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0
+
+/* RCC_SDMMC3CKSELR register fields */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0)
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0
+
+/* RCC_ETHCKSELR register fields */
+#define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0)
+#define RCC_ETHCKSELR_ETHSRC_SHIFT 0
+
+/* RCC_QSPICKSELR register fields */
+#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0)
+#define RCC_QSPICKSELR_QSPISRC_SHIFT 0
+
+/* RCC_FMCCKSELR register fields */
+#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0)
+#define RCC_FMCCKSELR_FMCSRC_SHIFT 0
+
+/* RCC_USBCKSELR register fields */
+#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0)
+#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0
+#define RCC_USBCKSELR_USBOSRC_MASK BIT(4)
+#define RCC_USBCKSELR_USBOSRC_SHIFT 4
+
#endif /* STM32MP1_RCC_H */
diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h
index 5beb06b..0769167 100644
--- a/include/drivers/st/stm32mp_clkfunc.h
+++ b/include/drivers/st/stm32mp_clkfunc.h
@@ -11,6 +11,14 @@
#include <libfdt.h>
+#include <platform_def.h>
+
+int fdt_osc_read_freq(const char *name, uint32_t *freq);
+bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name);
+uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
+ const char *prop_name,
+ uint32_t dflt_value);
+
int fdt_get_rcc_node(void *fdt);
uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name,
diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S
index d840da8..96b63cf 100644
--- a/lib/cpus/aarch64/neoverse_e1.S
+++ b/lib/cpus/aarch64/neoverse_e1.S
@@ -21,6 +21,21 @@
#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Neoverse-E1.
+ * Shall clobber: x0-x19
+ * -------------------------------------------------
+ */
+func neoverse_e1_reset_func
+ mov x19, x30
+
+#if ERRATA_DSU_936184
+ bl errata_dsu_936184_wa
+#endif
+
+ ret x19
+endfunc neoverse_e1_reset_func
+
func neoverse_e1_cpu_pwr_dwn
mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
@@ -34,6 +49,18 @@
* Errata printing function for Neoverse N1. Must follow AAPCS.
*/
func neoverse_e1_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184
+
+ ldp x8, x30, [sp], #16
ret
endfunc neoverse_e1_errata_report
#endif
@@ -50,5 +77,5 @@
endfunc neoverse_e1_cpu_reg_dump
declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \
- CPU_NO_RESET_FUNC, \
+ neoverse_e1_reset_func, \
neoverse_e1_cpu_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index d685b7e..8afc4a2 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -146,6 +146,11 @@
msr CPUAMCNTENSET_EL0, x0
isb
#endif
+
+#if ERRATA_DSU_936184
+ bl errata_dsu_936184_wa
+#endif
+
ret x19
endfunc neoverse_n1_reset_func
@@ -181,6 +186,7 @@
*/
report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
+ report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
ldp x8, x30, [sp], #16
ret
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index f20f515..585079b 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -38,6 +38,12 @@
# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
COLD_BOOT_SINGLE_CPU := 1
+# Do not enable SPE (not supported on ARM v8.0).
+ENABLE_SPE_FOR_LOWER_ELS := 0
+
+# Do not enable SVE (not supported on ARM v8.0).
+ENABLE_SVE_FOR_NS := 0
+
# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
@@ -56,3 +62,6 @@
# We are short on memory, so save 3.5KB by not having an extra coherent page.
USE_COHERENT_MEM := 0
+
+# This platform is single-cluster and does not require coherency setup.
+WARMBOOT_ENABLE_DCACHE_EARLY := 1
diff --git a/plat/arm/common/sp_min/arm_sp_min.mk b/plat/arm/common/sp_min/arm_sp_min.mk
index edab884..dbd451c 100644
--- a/plat/arm/common/sp_min/arm_sp_min.mk
+++ b/plat/arm/common/sp_min/arm_sp_min.mk
@@ -1,15 +1,16 @@
#
-# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# SP MIN source files common to ARM standard platforms
-# Skip building BL1 and BL2 if RESET_TO_SP_MIN flag is set.
+# Skip building BL1, BL2 and BL2U if RESET_TO_SP_MIN flag is set.
ifeq (${RESET_TO_SP_MIN},1)
BL1_SOURCES =
BL2_SOURCES =
+ BL2U_SOURCES =
endif
BL32_SOURCES += plat/arm/common/arm_pm.c \
@@ -17,4 +18,3 @@
plat/arm/common/sp_min/arm_sp_min_setup.c \
plat/common/aarch32/platform_mp_stack.S \
plat/common/plat_psci_common.c
-
diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/rcar/aarch64/plat_helpers.S
index ae0d675..61dd622 100644
--- a/plat/renesas/rcar/aarch64/plat_helpers.S
+++ b/plat/renesas/rcar/aarch64/plat_helpers.S
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,7 +20,7 @@
.globl plat_crash_console_init
.globl plat_crash_console_putc
- .globl plat_crash_console_flush
+ .globl plat_crash_console_flush
.globl plat_invalidate_icache
.globl plat_report_exception
.globl plat_secondary_reset
@@ -28,6 +28,10 @@
.globl plat_my_core_pos
.extern rcar_log_init
+ .extern console_rcar_init
+ .extern console_rcar_putc
+ .extern console_rcar_flush
+
#if IMAGE_BL2
#define INT_ID_MASK (0x3ff)
.extern bl2_interrupt_error_type
@@ -258,7 +262,7 @@
mov sp, x2
str x1, [sp, #-16]!
str x30, [sp, #-16]!
- bl console_core_init
+ bl console_rcar_init
ldr x30, [sp], #16
ldr x1, [sp], #16
mov sp, x1
@@ -280,7 +284,7 @@
str x3, [sp, #-16]!
str x4, [sp, #-16]!
str x5, [sp, #-16]!
- bl console_core_putc
+ bl console_rcar_putc
ldr x5, [sp], #16
ldr x4, [sp], #16
ldr x3, [sp], #16
@@ -292,11 +296,10 @@
/* ---------------------------------------------
* int plat_crash_console_flush()
- *
* ---------------------------------------------
*/
func plat_crash_console_flush
- b console_flush
+ b console_rcar_flush
endfunc plat_crash_console_flush
/* --------------------------------------------------------------------
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index a21d6ab..3c9b56f 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -686,8 +686,7 @@
if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
boot_cpu == MODEMR_BOOT_CPU_CA53) {
rcar_pfc_init();
- /* console configuration (platform specific) done in driver */
- console_init(0, 0, 0);
+ rcar_console_boot_init();
}
plat_rcar_gic_driver_init();
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c
index add3e34..4fff233 100644
--- a/plat/renesas/rcar/bl31_plat_setup.c
+++ b/plat/renesas/rcar/bl31_plat_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -79,9 +79,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- /* dummy config: the actual console configuration (platform specific)
- is done in the driver (scif.c) */
- console_init(1, 0, 0);
+ rcar_console_runtime_init();
NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
diff --git a/plat/renesas/rcar/include/rcar_private.h b/plat/renesas/rcar/include/rcar_private.h
index def3276..a76c023 100644
--- a/plat/renesas/rcar/include/rcar_private.h
+++ b/plat/renesas/rcar/include/rcar_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -99,4 +99,9 @@
void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit);
void cpg_write(uintptr_t regadr, uint32_t regval);
+void rcar_console_boot_init(void);
+void rcar_console_boot_end(void);
+void rcar_console_runtime_init(void);
+void rcar_console_runtime_end(void);
+
#endif /* RCAR_PRIVATE_H */
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 85cbe07..17fdc0d 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -12,6 +12,7 @@
GENERATE_COT := 1
BL2_AT_EL3 := 1
ENABLE_SVE_FOR_NS := 0
+MULTI_CONSOLE_API := 1
CRASH_REPORTING := 1
HANDLE_EA_EL3_FIRST := 1
@@ -348,12 +349,12 @@
ERRATA_A57_813419 := 1
include drivers/staging/renesas/rcar/ddr/ddr.mk
-include drivers/staging/renesas/rcar/qos/qos.mk
+include drivers/renesas/rcar/qos/qos.mk
include drivers/staging/renesas/rcar/pfc/pfc.mk
include lib/libfdt/libfdt.mk
PLAT_INCLUDES := -Idrivers/staging/renesas/rcar/ddr \
- -Idrivers/staging/renesas/rcar/qos \
+ -Idrivers/renesas/rcar/qos \
-Idrivers/renesas/rcar/iic_dvfs \
-Idrivers/renesas/rcar/board \
-Idrivers/renesas/rcar/cpld/ \
diff --git a/plat/renesas/rcar/rcar_common.c b/plat/renesas/rcar/rcar_common.c
index b83df8b..d24d71a 100644
--- a/plat/renesas/rcar/rcar_common.c
+++ b/plat/renesas/rcar/rcar_common.c
@@ -67,3 +67,38 @@
panic();
}
+
+#include <drivers/renesas/rcar/console/console.h>
+
+static console_rcar_t rcar_boot_console;
+static console_rcar_t rcar_runtime_console;
+
+void rcar_console_boot_init(void)
+{
+ int ret;
+
+ ret = console_rcar_register(0, 0, 0, &rcar_boot_console);
+ if (!ret)
+ panic();
+
+ console_set_scope(&rcar_boot_console.console, CONSOLE_FLAG_BOOT);
+}
+
+void rcar_console_boot_end(void)
+{
+}
+
+void rcar_console_runtime_init(void)
+{
+ int ret;
+
+ ret = console_rcar_register(1, 0, 0, &rcar_runtime_console);
+ if (!ret)
+ panic();
+
+ console_set_scope(&rcar_boot_console.console, CONSOLE_FLAG_RUNTIME);
+}
+
+void rcar_console_runtime_end(void)
+{
+}
diff --git a/plat/st/common/include/stm32mp_dt.h b/plat/st/common/include/stm32mp_dt.h
index 3415b05..74b01b3 100644
--- a/plat/st/common/include/stm32mp_dt.h
+++ b/plat/st/common/include/stm32mp_dt.h
@@ -36,11 +36,12 @@
void dt_fill_device_info(struct dt_node_info *info, int node);
int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
int dt_get_stdout_uart_info(struct dt_node_info *info);
-int dt_get_stdout_node_offset(void);
uint32_t dt_get_ddr_size(void);
uintptr_t dt_get_ddrctrl_base(void);
uintptr_t dt_get_ddrphyc_base(void);
uintptr_t dt_get_pwr_base(void);
+uint32_t dt_get_pwr_vdd_voltage(void);
+uintptr_t dt_get_syscfg_base(void);
const char *dt_get_board_model(void);
#endif /* STM32MP_DT_H */
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 2aba41e..f95c788 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -98,17 +98,6 @@
return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
}
-unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
-{
- if (bank == GPIO_BANK_Z) {
- return GPIOZ;
- }
-
- assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
-
- return GPIOA + (bank - GPIO_BANK_A);
-}
-
uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index e64433b..17da490 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -146,6 +146,52 @@
}
/*******************************************************************************
+ * This function gets the stdout path node.
+ * It reads the value indicated inside the device tree.
+ * Returns node offset on success and a negative FDT error code on failure.
+ ******************************************************************************/
+static int dt_get_stdout_node_offset(void)
+{
+ int node;
+ const char *cchar;
+
+ node = fdt_path_offset(fdt, "/secure-chosen");
+ if (node < 0) {
+ node = fdt_path_offset(fdt, "/chosen");
+ if (node < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+ }
+
+ cchar = fdt_getprop(fdt, node, "stdout-path", NULL);
+ if (cchar == NULL) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ node = -FDT_ERR_NOTFOUND;
+ if (strchr(cchar, (int)':') != NULL) {
+ const char *name;
+ char *str = (char *)cchar;
+ int len = 0;
+
+ while (strncmp(":", str, 1)) {
+ len++;
+ str++;
+ }
+
+ name = fdt_get_alias_namelen(fdt, cchar, len);
+
+ if (name != NULL) {
+ node = fdt_path_offset(fdt, name);
+ }
+ } else {
+ node = fdt_path_offset(fdt, cchar);
+ }
+
+ return node;
+}
+
+/*******************************************************************************
* This function gets the stdout pin configuration information from the DT.
* And then calls the sub-function to treat it and set GPIO registers.
* Returns 0 on success and a negative FDT error code on failure.
@@ -232,49 +278,6 @@
}
/*******************************************************************************
- * This function gets the stdout path node.
- * It reads the value indicated inside the device tree.
- * Returns node if success, and a negative value else.
- ******************************************************************************/
-int dt_get_stdout_node_offset(void)
-{
- int node;
- const char *cchar;
-
- node = fdt_path_offset(fdt, "/chosen");
- if (node < 0) {
- return -FDT_ERR_NOTFOUND;
- }
-
- cchar = fdt_getprop(fdt, node, "stdout-path", NULL);
- if (cchar == NULL) {
- return -FDT_ERR_NOTFOUND;
- }
-
- node = -FDT_ERR_NOTFOUND;
- if (strchr(cchar, (int)':') != NULL) {
- const char *name;
- char *str = (char *)cchar;
- int len = 0;
-
- while (strncmp(":", str, 1)) {
- len++;
- str++;
- }
-
- name = fdt_get_alias_namelen(fdt, cchar, len);
-
- if (name != NULL) {
- node = fdt_path_offset(fdt, name);
- }
- } else {
- node = fdt_path_offset(fdt, cchar);
- }
-
- return node;
-}
-
-/*******************************************************************************
* This function gets DDR size information from the DT.
* Returns value in bytes on success, and 0 on failure.
******************************************************************************/
@@ -350,6 +353,68 @@
return 0;
}
+ cuint = fdt_getprop(fdt, node, "reg", NULL);
+ if (cuint == NULL) {
+ return 0;
+ }
+
+ return fdt32_to_cpu(*cuint);
+}
+
+/*******************************************************************************
+ * This function gets PWR VDD regulator voltage information from the DT.
+ * Returns value in microvolts on success, and 0 on failure.
+ ******************************************************************************/
+uint32_t dt_get_pwr_vdd_voltage(void)
+{
+ int node, pwr_regulators_node;
+ const fdt32_t *cuint;
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT);
+ if (node < 0) {
+ INFO("%s: Cannot read PWR node in DT\n", __func__);
+ return 0;
+ }
+
+ pwr_regulators_node = fdt_subnode_offset(fdt, node, "pwr-regulators");
+ if (node < 0) {
+ INFO("%s: Cannot read pwr-regulators node in DT\n", __func__);
+ return 0;
+ }
+
+ cuint = fdt_getprop(fdt, pwr_regulators_node, "vdd-supply", NULL);
+ if (cuint == NULL) {
+ return 0;
+ }
+
+ node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
+ if (node < 0) {
+ return 0;
+ }
+
+ cuint = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL);
+ if (cuint == NULL) {
+ return 0;
+ }
+
+ return fdt32_to_cpu(*cuint);
+}
+
+/*******************************************************************************
+ * This function gets SYSCFG base address information from the DT.
+ * Returns value on success, and 0 on failure.
+ ******************************************************************************/
+uintptr_t dt_get_syscfg_base(void)
+{
+ int node;
+ const fdt32_t *cuint;
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_SYSCFG_COMPAT);
+ if (node < 0) {
+ INFO("%s: Cannot read SYSCFG node in DT\n", __func__);
+ return 0;
+ }
+
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index b54486e..27d298e 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -15,6 +15,7 @@
#include <common/desc_image_load.h>
#include <drivers/delay_timer.h>
#include <drivers/generic_delay_timer.h>
+#include <drivers/st/bsec.h>
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32mp_reset.h>
@@ -211,6 +212,10 @@
;
}
+ if (bsec_probe() != 0) {
+ panic();
+ }
+
/* Reset backup domain on cold boot cases */
if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
@@ -236,6 +241,8 @@
panic();
}
+ stm32mp1_syscfg_init();
+
result = dt_get_stdout_uart_info(&dt_uart_info);
if ((result <= 0) ||
diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index 49a2bdf..e38fca0 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -17,4 +17,8 @@
void stm32mp1_gic_pcpu_init(void);
void stm32mp1_gic_init(void);
+void stm32mp1_syscfg_init(void);
+void stm32mp1_syscfg_enable_io_compensation(void);
+void stm32mp1_syscfg_disable_io_compensation(void);
+
#endif /* STM32MP1_PRIVATE_H */
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 4796e91..f6bf9f3 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -49,14 +49,12 @@
PLAT_BL_COMMON_SOURCES += lib/cpus/aarch32/cortex_a7.S
-PLAT_BL_COMMON_SOURCES += ${LIBFDT_SRCS} \
- drivers/arm/tzc/tzc400.c \
+PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/st/bsec/bsec.c \
drivers/st/clk/stm32mp_clkfunc.c \
drivers/st/clk/stm32mp1_clk.c \
- drivers/st/clk/stm32mp1_clkfunc.c \
drivers/st/ddr/stm32mp1_ddr_helpers.c \
drivers/st/gpio/stm32_gpio.c \
drivers/st/i2c/stm32_i2c.c \
@@ -66,7 +64,8 @@
plat/st/common/stm32mp_dt.c \
plat/st/stm32mp1/stm32mp1_context.c \
plat/st/stm32mp1/stm32mp1_helper.S \
- plat/st/stm32mp1/stm32mp1_security.c
+ plat/st/stm32mp1/stm32mp1_security.c \
+ plat/st/stm32mp1/stm32mp1_syscfg.c
BL2_SOURCES += drivers/io/io_block.c \
drivers/io/io_dummy.c \
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index cff7ddb..94c4c5b 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -111,7 +111,7 @@
#endif
/* DTB initialization value */
-#define STM32MP_DTB_SIZE U(0x00004000) /* 16Ko for DTB */
+#define STM32MP_DTB_SIZE U(0x00005000) /* 20Ko for DTB */
#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
STM32MP_DTB_SIZE)
@@ -223,11 +223,11 @@
#define STM32MP_SDMMC2_BASE U(0x58007000)
#define STM32MP_SDMMC3_BASE U(0x48004000)
-#define STM32MP_MMC_INIT_FREQ 400000 /*400 KHz*/
-#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/
-#define STM32MP_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/
-#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/
-#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/
+#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
+#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
+#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
+#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
+#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
/*******************************************************************************
* STM32MP1 BSEC / OTP
@@ -239,11 +239,15 @@
/* OTP offsets */
#define DATA0_OTP U(0)
+#define HW2_OTP U(18)
/* OTP mask */
/* DATA0 */
#define DATA0_OTP_SECURED BIT(6)
+/* HW2 OTP */
+#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
+
/*******************************************************************************
* STM32MP1 TAMP
******************************************************************************/
@@ -277,5 +281,6 @@
******************************************************************************/
#define DT_PWR_COMPAT "st,stm32mp1-pwr"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
+#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
#endif /* STM32MP1_DEF_H */
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 20eb88e..340c7fb 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -4,6 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
+
#include <platform_def.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
@@ -53,3 +55,14 @@
enable_mmu_svc_mon(0);
}
+
+unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
+{
+ if (bank == GPIO_BANK_Z) {
+ return GPIOZ;
+ }
+
+ assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+
+ return GPIOA + (bank - GPIO_BANK_A);
+}
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
new file mode 100644
index 0000000..2fd06f3
--- /dev/null
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/st/bsec.h>
+#include <drivers/st/stpmic1.h>
+#include <lib/mmio.h>
+
+#include <stm32mp_dt.h>
+#include <stm32mp1_private.h>
+
+/*
+ * SYSCFG REGISTER OFFSET (base relative)
+ */
+#define SYSCFG_BOOTR 0x00U
+#define SYSCFG_IOCTRLSETR 0x18U
+#define SYSCFG_ICNR 0x1CU
+#define SYSCFG_CMPCR 0x20U
+#define SYSCFG_CMPENSETR 0x24U
+
+/*
+ * SYSCFG_BOOTR Register
+ */
+#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
+#define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4)
+#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
+/*
+ * SYSCFG_IOCTRLSETR Register
+ */
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
+
+/*
+ * SYSCFG_ICNR Register
+ */
+#define SYSCFG_ICNR_AXI_M9 BIT(9)
+
+/*
+ * SYSCFG_CMPCR Register
+ */
+#define SYSCFG_CMPCR_SW_CTRL BIT(1)
+#define SYSCFG_CMPCR_READY BIT(8)
+#define SYSCFG_CMPCR_RANSRC GENMASK(19, 16)
+#define SYSCFG_CMPCR_RANSRC_SHIFT 16
+#define SYSCFG_CMPCR_RAPSRC GENMASK(23, 20)
+#define SYSCFG_CMPCR_ANSRC_SHIFT 24
+
+/*
+ * SYSCFG_CMPENSETR Register
+ */
+#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
+
+void stm32mp1_syscfg_init(void)
+{
+ uint32_t bootr;
+ uint32_t otp = 0;
+ uint32_t vdd_voltage;
+ uintptr_t syscfg_base = dt_get_syscfg_base();
+
+ /*
+ * Interconnect update : select master using the port 1.
+ * LTDC = AXI_M9.
+ */
+ mmio_write_32(syscfg_base + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
+
+ /* Disable Pull-Down for boot pin connected to VDD */
+ bootr = mmio_read_32(syscfg_base + SYSCFG_BOOTR) &
+ SYSCFG_BOOTR_BOOT_MASK;
+ mmio_clrsetbits_32(syscfg_base + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
+ bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
+
+ /*
+ * High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
+ * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
+ * It could be disabled for low frequencies or if AFMUX is selected
+ * but the function is not used, typically for TRACE.
+ * If high speed low voltage pad mode is node enable, platform will
+ * over consume.
+ *
+ * WARNING:
+ * Enabling High Speed mode while VDD > 2.7V
+ * with the OTP product_below_2v5 (OTP 18, BIT 13)
+ * erroneously set to 1 can damage the SoC!
+ * => TF-A enables the low power mode only if VDD < 2.7V (in DT)
+ * but this value needs to be consistent with board design.
+ */
+ if (bsec_read_otp(&otp, HW2_OTP) != BSEC_OK) {
+ panic();
+ }
+
+ otp = otp & HW2_OTP_PRODUCT_BELOW_2V5;
+
+ /* Get VDD supply */
+ vdd_voltage = dt_get_pwr_vdd_voltage();
+
+ /* Check if VDD is Low Voltage */
+ if (vdd_voltage == 0U) {
+ WARN("VDD unknown");
+ } else if (vdd_voltage < 2700000U) {
+ mmio_write_32(syscfg_base + SYSCFG_IOCTRLSETR,
+ SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
+ SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
+ SYSCFG_IOCTRLSETR_HSLVEN_ETH |
+ SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
+ SYSCFG_IOCTRLSETR_HSLVEN_SPI);
+
+ if (otp == 0U) {
+ INFO("Product_below_2v5=0: HSLVEN protected by HW\n");
+ }
+ } else {
+ if (otp != 0U) {
+ ERROR("Product_below_2v5=1:\n");
+ ERROR("\tHSLVEN update is destructive,\n");
+ ERROR("\tno update as VDD > 2.7V\n");
+ panic();
+ }
+ }
+
+ stm32mp1_syscfg_enable_io_compensation();
+}
+
+void stm32mp1_syscfg_enable_io_compensation(void)
+{
+ uintptr_t syscfg_base = dt_get_syscfg_base();
+
+ /*
+ * Activate automatic I/O compensation.
+ * Warning: need to ensure CSI enabled and ready in clock driver.
+ * Enable non-secure clock, we assume non-secure is suspended.
+ */
+ stm32mp1_clk_enable_non_secure(SYSCFG);
+
+ mmio_setbits_32(syscfg_base + SYSCFG_CMPENSETR,
+ SYSCFG_CMPENSETR_MPU_EN);
+
+ while ((mmio_read_32(syscfg_base + SYSCFG_CMPCR) &
+ SYSCFG_CMPCR_READY) == 0U) {
+ ;
+ }
+
+ mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+}
+
+void stm32mp1_syscfg_disable_io_compensation(void)
+{
+ uintptr_t syscfg_base = dt_get_syscfg_base();
+ uint32_t value;
+
+ /*
+ * Deactivate automatic I/O compensation.
+ * Warning: CSI is disabled automatically in STOP if not
+ * requested for other usages and always OFF in STANDBY.
+ * Disable non-secure SYSCFG clock, we assume non-secure is suspended.
+ */
+ value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) >>
+ SYSCFG_CMPCR_ANSRC_SHIFT;
+
+ mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR,
+ SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
+
+ value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) |
+ (value << SYSCFG_CMPCR_RANSRC_SHIFT);
+
+ mmio_write_32(syscfg_base + SYSCFG_CMPCR, value);
+
+ mmio_setbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+
+ mmio_clrbits_32(syscfg_base + SYSCFG_CMPENSETR,
+ SYSCFG_CMPENSETR_MPU_EN);
+
+ stm32mp1_clk_disable_non_secure(SYSCFG);
+}