plat/sgi: define default list of memory regions for dmc620 tzc
Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
platforms. The default DMC-620 TZC memory regions are defined
considering the support for secure paritition as well.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db
diff --git a/plat/arm/board/rde1edge/rde1edge_security.c b/plat/arm/board/rde1edge/rde1edge_security.c
index 2123e09..35f81d1 100644
--- a/plat/arm/board/rde1edge/rde1edge_security.c
+++ b/plat/arm/board/rde1edge/rde1edge_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
+#include <sgi_dmc620_tzc_regions.h>
uintptr_t rde1edge_dmc_base[] = {
RDE1EDGE_DMC620_BASE0,
@@ -20,11 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
- {
- .region_base = ARM_AP_TZC_DRAM1_BASE,
- .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
- .sec_attr = TZC_DMC620_REGION_S_RDWR
- }
+ CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
diff --git a/plat/arm/board/rdn1edge/rdn1edge_security.c b/plat/arm/board/rdn1edge/rdn1edge_security.c
index ffa8935..4943532 100644
--- a/plat/arm/board/rdn1edge/rdn1edge_security.c
+++ b/plat/arm/board/rdn1edge/rdn1edge_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
+#include <sgi_dmc620_tzc_regions.h>
uintptr_t rdn1edge_dmc_base[] = {
RDN1EDGE_DMC620_BASE0,
@@ -20,11 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
- {
- .region_base = ARM_AP_TZC_DRAM1_BASE,
- .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
- .sec_attr = TZC_DMC620_REGION_S_RDWR
- }
+ CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
diff --git a/plat/arm/board/sgi575/sgi575_security.c b/plat/arm/board/sgi575/sgi575_security.c
index 440f18d..17d07d1 100644
--- a/plat/arm/board/sgi575/sgi575_security.c
+++ b/plat/arm/board/sgi575/sgi575_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
-#include <plat/arm/common/plat_arm.h>
+#include <sgi_dmc620_tzc_regions.h>
uintptr_t sgi575_dmc_base[] = {
SGI575_DMC620_BASE0,
@@ -21,11 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
- {
- .region_base = ARM_AP_TZC_DRAM1_BASE,
- .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
- .sec_attr = TZC_DMC620_REGION_S_RDWR
- }
+ CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
diff --git a/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h
new file mode 100644
index 0000000..e939163
--- /dev/null
+++ b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_DMC620_TZC_REGIONS_H
+#define SGI_DMC620_TZC_REGIONS_H
+
+#include <drivers/arm/tzc_dmc620.h>
+
+#if SPM_MM
+#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
+ { \
+ .region_base = ARM_AP_TZC_DRAM1_BASE, \
+ .region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \
+ .sec_attr = TZC_DMC620_REGION_S_RDWR \
+ }, { \
+ .region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \
+ .region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \
+ .sec_attr = TZC_DMC620_REGION_S_NS_RDWR \
+ }, { \
+ .region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \
+ .region_top = ARM_AP_TZC_DRAM1_END, \
+ .sec_attr = TZC_DMC620_REGION_S_RDWR \
+ }
+#else
+#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
+ { \
+ .region_base = ARM_AP_TZC_DRAM1_BASE, \
+ .region_top = ARM_AP_TZC_DRAM1_END, \
+ .sec_attr = TZC_DMC620_REGION_S_RDWR \
+ }
+#endif /* SPM_MM */
+
+#endif /* SGI_DMC620_TZC_REGIONS_H */