tree 66beeeba3d7772d536498010cc41bf2b77c45734
parent 4c7fa50c245d23db1507d617b6ccda7aed3b083f
author Varun Wadekar <vwadekar@nvidia.com> 1474666096 -0700
committer Varun Wadekar <vwadekar@nvidia.com> 1491581751 -0700

Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.

Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"

The following CPU registers have to be set by the non-secure driver
before issuing the SMC:

X1 = MPIDR of the target core
X2 = MIDR of the target core

Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>