AArch32: Enable GIC and TZC support

This patch modifies GICv3 and TZC drivers to add AArch32 support.
No modifications are required for the GICv2 driver for AArch32 support.
The TZC driver assumes that the secure world is running in Little-Endian
mode to do 64 bit manipulations. Assertions are present to validate the
assumption.

Note: The legacy GICv3 driver is not supported for AArch32.

Change-Id: Id1bc75a9f5dafb9715c9500ca77b4606eb1e2458
diff --git a/drivers/arm/tzc/tzc_dmc500.c b/drivers/arm/tzc/tzc_dmc500.c
index b2f0bf6..24e587c 100644
--- a/drivers/arm/tzc/tzc_dmc500.c
+++ b/drivers/arm/tzc/tzc_dmc500.c
@@ -211,7 +211,7 @@
 	 * Do address range check based on DMC-TZ configuration. A 43bit address
 	 * is the max and expected case.
 	 */
-	assert(((region_top <= (UINT64_MAX >> (64 - 43))) &&
+	assert(((region_top <= _tzc_get_max_top_addr(43)) &&
 		(region_base < region_top)));
 
 	/* region_base and (region_top + 1) must be 4KB aligned */