plat: marvell: ap807: use correct address for MCIx4 register
The AP807 uses different register offset for MCIx4 register, reflect it
in the code.
Change-Id: Ic7e44fede3c69083e8629741e7c440b1ae08c35f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
diff --git a/drivers/marvell/mochi/ap807_setup.c b/drivers/marvell/mochi/ap807_setup.c
index 864c923..132fffc 100644
--- a/drivers/marvell/mochi/ap807_setup.c
+++ b/drivers/marvell/mochi/ap807_setup.c
@@ -31,6 +31,11 @@
#define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
#define DVM_48BIT_VA_ENABLE (1 << 21)
+
+/* SoC RFU / IHBx4 Control */
+#define MCIX4_807_REG_START_ADDR_REG(unit_id) (MVEBU_RFU_BASE + \
+ 0x4258 + (unit_id * 0x4))
+
/* Secure MoChi incoming access */
#define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738)
#define SEC_MOCHI_IN_ACC_IHB0_EN (1)
@@ -124,7 +129,7 @@
uint32_t mci;
for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++)
- mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci),
+ mmio_write_32(MCIX4_807_REG_START_ADDR_REG(mci),
MVEBU_MCI_REG_BASE_REMAP(mci) >>
MCI_REMAP_OFF_SHIFT);
}