feat(intel): add build option for boot source
Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.
Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.
Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 72ffbe2..f787ebc 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -15,7 +15,6 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
-#define BOOT_SOURCE BOOT_SOURCE_SDMMC
/* 1 = Flush cache, 0 = No cache flush.
* Default for Agilex is No cache flush.
* For Agilex FP8, set to Flush cache.
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index 21cc6a3..9ff8039 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -87,6 +87,24 @@
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+# Configs for Boot Source
+SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
+SOCFPGA_BOOT_SOURCE_QSPI ?= 0
+SOCFPGA_BOOT_SOURCE_NAND ?= 0
+
+$(eval $(call assert_booleans,\
+ $(sort \
+ SOCFPGA_BOOT_SOURCE_SDMMC \
+ SOCFPGA_BOOT_SOURCE_QSPI \
+ SOCFPGA_BOOT_SOURCE_NAND \
+)))
+$(eval $(call add_defines,\
+ $(sort \
+ SOCFPGA_BOOT_SOURCE_SDMMC \
+ SOCFPGA_BOOT_SOURCE_QSPI \
+ SOCFPGA_BOOT_SOURCE_NAND \
+)))
+
# Configs for VAB Authentication
SOCFPGA_SECURE_VAB_AUTH := 0
$(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH))
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index ab6e2bc..31d28f2 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -16,7 +16,6 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5
-#define BOOT_SOURCE BOOT_SOURCE_SDMMC
/* 1 = Flush cache, 0 = No cache flush.
* Default for Agilex5 is Cache flush.
*/
diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk
index 4bb90d5..172b554 100644
--- a/plat/intel/soc/agilex5/platform.mk
+++ b/plat/intel/soc/agilex5/platform.mk
@@ -113,6 +113,24 @@
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+# Configs for Boot Source
+SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
+SOCFPGA_BOOT_SOURCE_QSPI ?= 0
+SOCFPGA_BOOT_SOURCE_NAND ?= 0
+
+$(eval $(call assert_booleans,\
+ $(sort \
+ SOCFPGA_BOOT_SOURCE_SDMMC \
+ SOCFPGA_BOOT_SOURCE_QSPI \
+ SOCFPGA_BOOT_SOURCE_NAND \
+)))
+$(eval $(call add_defines,\
+ $(sort \
+ SOCFPGA_BOOT_SOURCE_SDMMC \
+ SOCFPGA_BOOT_SOURCE_QSPI \
+ SOCFPGA_BOOT_SOURCE_NAND \
+)))
+
# Configs for VAB Authentication
SOCFPGA_SECURE_VAB_AUTH := 0
$(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH))
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 0788ab8..f3fb1a4 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -22,6 +22,18 @@
#define PLAT_SOCFPGA_AGILEX5 4
#define SIMICS_RUN 1
#define MAX_IO_MTD_DEVICES U(1)
+/* Boot Source configuration
+ * TODO: Shall consider "assert_numeric" in the future
+ */
+#if SOCFPGA_BOOT_SOURCE_NAND
+#define BOOT_SOURCE BOOT_SOURCE_NAND
+#elif SOCFPGA_BOOT_SOURCE_SDMMC
+#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+#elif SOCFPGA_BOOT_SOURCE_QSPI
+#define BOOT_SOURCE BOOT_SOURCE_QSPI
+#else
+#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+#endif
/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
#define PLAT_CPU_RELEASE_ADDR 0xffd12210
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index a0d4180..fbe18c3 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -24,8 +24,8 @@
BOOT_SOURCE_FPGA = 0,
BOOT_SOURCE_SDMMC,
BOOT_SOURCE_NAND,
- BOOT_SOURCE_RSVD,
- BOOT_SOURCE_QSPI
+ BOOT_SOURCE_QSPI,
+ BOOT_SOURCE_RSVD
} boot_source_type;
/*******************************************************************************
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index c5e66c7..cbaccfd 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -15,7 +15,6 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
-#define BOOT_SOURCE BOOT_SOURCE_SDMMC
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk
index 29fd0eb..4770f8d 100644
--- a/plat/intel/soc/n5x/platform.mk
+++ b/plat/intel/soc/n5x/platform.mk
@@ -1,5 +1,6 @@
#
-# Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+# Copyright (c) 2024, Altera Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -46,8 +47,30 @@
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c
+# Don't have the Linux kernel as a BL33 image by default
+ARM_LINUX_KERNEL_AS_BL33 := 0
+$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+# Configs for Boot Source
+SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
+SOCFPGA_BOOT_SOURCE_QSPI ?= 0
+SOCFPGA_BOOT_SOURCE_NAND ?= 0
+
+$(eval $(call assert_booleans,\
+ $(sort \
+ SOCFPGA_BOOT_SOURCE_SDMMC \
+ SOCFPGA_BOOT_SOURCE_QSPI \
+ SOCFPGA_BOOT_SOURCE_NAND \
+)))
+$(eval $(call add_defines,\
+ $(sort \
+ SOCFPGA_BOOT_SOURCE_SDMMC \
+ SOCFPGA_BOOT_SOURCE_QSPI \
+ SOCFPGA_BOOT_SOURCE_NAND \
+)))
+
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index cd4c163..35b92c5 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -14,7 +14,6 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
-#define BOOT_SOURCE BOOT_SOURCE_SDMMC
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 0a33c3d..4cd7032 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -78,8 +78,30 @@
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c
+# Don't have the Linux kernel as a BL33 image by default
+ARM_LINUX_KERNEL_AS_BL33 := 0
+$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+# Configs for Boot Source
+SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
+SOCFPGA_BOOT_SOURCE_QSPI ?= 0
+SOCFPGA_BOOT_SOURCE_NAND ?= 0
+
+$(eval $(call assert_booleans,\
+ $(sort \
+ SOCFPGA_BOOT_SOURCE_SDMMC \
+ SOCFPGA_BOOT_SOURCE_QSPI \
+ SOCFPGA_BOOT_SOURCE_NAND \
+)))
+$(eval $(call add_defines,\
+ $(sort \
+ SOCFPGA_BOOT_SOURCE_SDMMC \
+ SOCFPGA_BOOT_SOURCE_QSPI \
+ SOCFPGA_BOOT_SOURCE_NAND \
+)))
+
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
USE_COHERENT_MEM := 1