refactor(neoverse-rd): rewrite CSS and RoS device mmap macros
The CSS and RoS peripherals memory map macros have incorrect memory base
address and region size values. That is, the existing mmap definitions
are -
CSS peripherals mmap - Base address (0x20000000) and size (0x20000000)
RoS peripherals mmap - Base address (0x40000000) and size (0x40000000)
The corrected peripherals memory map definitions are -
CSS peripherals mmap - Base address (0x20000000) and size (0x40000000)
RoS peripherals mmap - Base address (0x60000000) and size (0x20000000)
While these macros are being updated, it is a good opportunity to rename
them appropriately. That is, the new macros are named as
NRD_CSS_PERIPH_MMAP - for mmap macro for CSS peripherals memory region
NRD_ROS_PERIPH_MMAP - for mmap macro for RoS peripherals memory region
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic2d12d7904922660a03efe6bc83ca8df2eb5a8d4
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
index e5a7466..74428dd 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
@@ -22,8 +22,8 @@
#define SOC_CSS_UART_SIZE UL(0x10000)
/* CSS peripherals */
-#define NRD_DEVICE_BASE UL(0x20000000)
-#define NRD_DEVICE_SIZE UL(0x20000000)
+#define NRD_CSS_PERIPH_BASE UL(0x20000000)
+#define NRD_CSS_PERIPH_SIZE UL(0x40000000)
/* Secure Watchdog */
#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
index ddf5dc2..bd54656 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
@@ -55,11 +55,11 @@
* MMU mappings
******************************************************************************/
-#define NRD_MAP_DEVICE(n) \
+#define NRD_CSS_PERIPH_MMAP(n) \
MAP_REGION_FLAT( \
NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
- NRD_DEVICE_BASE, \
- NRD_DEVICE_SIZE, \
+ NRD_CSS_PERIPH_BASE, \
+ NRD_CSS_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
index 42a9826..16db3ca 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
@@ -40,8 +40,8 @@
#if defined(IMAGE_BL31)
# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
-# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
-# define MAX_XLAT_TABLES (8 + ((NRD_CHIP_COUNT - 1) * 3))
+# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 3))
# define PLAT_SP_IMAGE_MMAP_REGIONS (12)
# define PLAT_SP_IMAGE_MAX_XLAT_TABLES (14)
# else
@@ -60,7 +60,7 @@
* multichip platforms peripherals also fall into address space with width
* > 40 bits.
*/
-# define MAX_XLAT_TABLES (7 + ((NRD_CHIP_COUNT - 1) * 2))
+# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 2))
#elif !USE_ROMLIB
# define PLAT_ARM_MMAP_ENTRIES (11)
# define MAX_XLAT_TABLES (7)
@@ -127,7 +127,7 @@
*
*/
#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE (0x20000 + ((NRD_CHIP_COUNT - 1) * \
+# define PLAT_ARM_MAX_BL2_SIZE (0x28000 + ((NRD_CHIP_COUNT - 1) * \
0x2000))
#else
# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((NRD_CHIP_COUNT - 1) * \
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
index e12bbb5..b4d3ec2 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
@@ -16,6 +16,10 @@
* ROS configs
******************************************************************************/
+/* RoS Peripherals */
+#define NRD_ROS_PERIPH_BASE UL(0x60000000)
+#define NRD_ROS_PERIPH_SIZE UL(0x20000000)
+
/* System Reg */
#define CSS_SYSTEMREG_DEVICE_BASE UL(0x1C010000)
#define CSS_SYSTEMREG_DEVICE_SIZE UL(0x00010000)
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
index 5f3c376..701ac77 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
@@ -18,11 +18,11 @@
* MMU mapping
******************************************************************************/
-#define PLAT_ARM_SECURE_MAP_DEVICE(n) \
+#define NRD_ROS_PERIPH_MMAP(n) \
MAP_REGION_FLAT( \
NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
- SOC_CSS_DEVICE_BASE, \
- SOC_CSS_DEVICE_SIZE, \
+ NRD_ROS_PERIPH_BASE, \
+ NRD_ROS_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define PLAT_ARM_SECURE_MAP_SYSTEMREG \
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat1.c b/plat/arm/board/neoverse_rd/common/nrd_plat1.c
index eb96944..2f57f3b 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat1.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat1.c
@@ -32,8 +32,8 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
NRD_MAP_FLASH0_RO,
- NRD_MAP_DEVICE(0),
- PLAT_ARM_SECURE_MAP_DEVICE(0),
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PERIPH_MMAP(0),
{0}
};
#endif
@@ -44,17 +44,17 @@
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
- NRD_MAP_DEVICE(0),
- PLAT_ARM_SECURE_MAP_DEVICE(0),
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PERIPH_MMAP(0),
ARM_MAP_NS_DRAM1,
#if NRD_CHIP_COUNT > 1
- NRD_MAP_DEVICE(1),
+ NRD_CSS_PERIPH_MMAP(1),
#endif
#if NRD_CHIP_COUNT > 2
- NRD_MAP_DEVICE(2),
+ NRD_CSS_PERIPH_MMAP(2),
#endif
#if NRD_CHIP_COUNT > 3
- NRD_MAP_DEVICE(3),
+ NRD_CSS_PERIPH_MMAP(3),
#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
@@ -72,11 +72,11 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
- NRD_MAP_DEVICE(0),
+ NRD_CSS_PERIPH_MMAP(0),
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
- PLAT_ARM_SECURE_MAP_DEVICE(0),
+ NRD_ROS_PERIPH_MMAP(0),
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
@@ -88,7 +88,6 @@
PLAT_ARM_SECURE_MAP_SYSTEMREG,
PLAT_ARM_SECURE_MAP_NOR2,
SOC_PLATFORM_SECURE_UART,
- PLAT_ARM_SECURE_MAP_DEVICE(0),
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
ARM_SP_IMAGE_RW_MMAP,
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
index 5f84d0c..cbed1a2 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
@@ -14,8 +14,8 @@
#if defined(IMAGE_BL31)
static const mmap_region_t rdn1edge_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- NRD_MAP_DEVICE(1),
- PLAT_ARM_SECURE_MAP_DEVICE(1)
+ NRD_CSS_PERIPH_MMAP(1),
+ NRD_ROS_PERIPH_MMAP(1)
};
static struct gic600_multichip_data rdn1e1_multichip_data __init = {
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
index e537257..4e1ace0 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
@@ -14,17 +14,17 @@
#if defined(IMAGE_BL31)
static const mmap_region_t rdv1mc_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- NRD_MAP_DEVICE(1),
- PLAT_ARM_SECURE_MAP_DEVICE(1),
+ NRD_CSS_PERIPH_MMAP(1),
+ NRD_ROS_PERIPH_MMAP(1),
#if (NRD_CHIP_COUNT > 2)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
- NRD_MAP_DEVICE(2),
- PLAT_ARM_SECURE_MAP_DEVICE(2),
+ NRD_CSS_PERIPH_MMAP(2),
+ NRD_ROS_PERIPH_MMAP(2),
#endif
#if (NRD_CHIP_COUNT > 3)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
- NRD_MAP_DEVICE(3),
- PLAT_ARM_SECURE_MAP_DEVICE(3)
+ NRD_CSS_PERIPH_MMAP(3),
+ NRD_ROS_PERIPH_MMAP(3)
#endif
};