Merge changes I93de2db1,I880f88b1,I02e2fc75,I48908413,Ie7de9a9f, ... into integration
* changes:
feat(st-ddr): add STM32MP2 driver
refactor(st-ddr): create generic services
refactor(st-ddr): remove name from stm32mp_ddr_reg_desc
refactor(st-ddr): add definition for timeouts and delays
feat(st): add stm32mp_is_wakeup_from_standby()
feat(stm32mp2): add RETRAM map/unmap capability
feat(stm32mp2): add helper to get DDRDBG base address
feat(stm32mp2): handle DDR power supplies
feat(stm32mp1): handle DDR power supplies
diff --git a/Makefile b/Makefile
index e9e0f59..179e07a 100644
--- a/Makefile
+++ b/Makefile
@@ -32,6 +32,12 @@
################################################################################
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
+include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
+
+# To be able to set platform specific defaults
+ifneq ($(PLAT_DEFAULTS_MAKEFILE_FULL),)
+include ${PLAT_DEFAULTS_MAKEFILE_FULL}
+endif
################################################################################
# Configure the toolchains used to build TF-A and its tools
@@ -42,7 +48,6 @@
# Assertions enabled for DEBUG builds by default
ENABLE_ASSERTIONS := ${DEBUG}
ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION}
-PLAT := ${DEFAULT_PLAT}
################################################################################
# Checkpatch script options
@@ -407,7 +412,6 @@
################################################################################
# Generic definitions
################################################################################
-include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
ifeq (${BUILD_BASE},)
BUILD_BASE := ./build
@@ -1712,7 +1716,7 @@
${FIPTOOL}: FORCE
ifdef UNIX_MK
- $(q)${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${FIPTOOLPATH} all
+ $(q)${MAKE} PLAT=${PLAT} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${FIPTOOLPATH} all
else
# Clear the MAKEFLAGS as we do not want
# to pass the gnumake flags to nmake.
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index db0eafc..a8a0061 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -19,7 +19,8 @@
ifeq (${ARCH},aarch64)
BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
- lib/el3_runtime/aarch64/context.S
+ lib/el3_runtime/aarch64/context.S \
+ lib/cpus/errata_common.c
endif
ifeq (${TRUSTED_BOARD_BOOT},1)
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 5230cdc..fda43dc 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -843,6 +843,9 @@
- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4
+ CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 42b1ec4..de2da2f 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -27,7 +27,7 @@
Program Min supported version
======================== =====================
Arm Compiler 6.18
-Arm GNU Compiler 13.2
+Arm GNU Compiler 13.3
Clang/LLVM 11.0.0
Device Tree Compiler 1.4.7
GNU make 3.81
@@ -51,7 +51,7 @@
AArch64 builds, the respective targets required are ``arm-none-eabi`` and
``aarch64-none-elf``.
-Testing has been performed with version 13.2.Rel1 (gcc 13.2) of the Arm
+Testing has been performed with version 13.3.Rel1 (gcc 13.3) of the Arm
GNU compiler, which can be installed from the `Arm Developer website`_.
In addition, a native compiler is required to build supporting tools.
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
index 84e76f7..e54d581 100644
--- a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
+++ b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
@@ -13,6 +13,11 @@
#define ARM_DFS_BASE_ADDR (0x40054000UL)
#define CGM0_BASE_ADDR (0x40030000UL)
#define CGM1_BASE_ADDR (0x40034000UL)
+#define DDRPLL_BASE_ADDR (0x40044000UL)
+#define MC_ME_BASE_ADDR (0x40088000UL)
+#define MC_RGM_BASE_ADDR (0x40078000UL)
+#define RDC_BASE_ADDR (0x40080000UL)
+#define MC_CGM5_BASE_ADDR (0x40068000UL)
/* FXOSC */
#define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL)
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-mc-me.h b/drivers/nxp/clk/s32cc/include/s32cc-mc-me.h
new file mode 100644
index 0000000..8249fc5
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/include/s32cc-mc-me.h
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2020-2021, 2023-2024 NXP
+ */
+#ifndef S32CC_MC_ME_H
+#define S32CC_MC_ME_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+int mc_me_enable_partition(uintptr_t mc_me, uintptr_t mc_rgm, uintptr_t rdc,
+ uint32_t part);
+void mc_me_enable_part_cofb(uintptr_t mc_me, uint32_t partition_n, uint32_t block,
+ bool check_status);
+
+#endif /* S32CC_MC_ME_H */
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h b/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
index 5ff55fb..d6234da 100644
--- a/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
+++ b/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
@@ -8,5 +8,7 @@
#include <stdint.h>
void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value);
+void mc_rgm_release_part(uintptr_t rgm, uint32_t part);
+void mc_rgm_wait_part_deassert(uintptr_t rgm, uint32_t part);
#endif /* MC_RGM_H */
diff --git a/drivers/nxp/clk/s32cc/mc_me.c b/drivers/nxp/clk/s32cc/mc_me.c
new file mode 100644
index 0000000..04d0425
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/mc_me.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <inttypes.h>
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <s32cc-mc-me.h>
+#include <s32cc-mc-rgm.h>
+
+#define MC_ME_MAX_PARTITIONS (4U)
+
+#define MC_ME_CTL_KEY(MC_ME) ((MC_ME) + 0x0UL)
+#define MC_ME_CTL_KEY_KEY (0x5AF0U)
+#define MC_ME_CTL_KEY_INVERTEDKEY (0xA50FU)
+
+#define MC_ME_PRTN_N(MC_ME, PART) ((MC_ME) + 0x100UL + ((PART) * 0x200UL))
+#define MC_ME_PRTN_N_PCONF(MC_ME, PART) (MC_ME_PRTN_N(MC_ME, PART))
+#define MC_ME_PRTN_N_PCE BIT_32(0)
+#define MC_ME_PRTN_N_OSSE BIT_32(2)
+#define MC_ME_PRTN_N_PUPD(MC_ME, PART) (MC_ME_PRTN_N(MC_ME, PART) + 0x4UL)
+#define MC_ME_PRTN_N_PCUD BIT_32(0)
+#define MC_ME_PRTN_N_OSSUD BIT_32(2)
+#define MC_ME_PRTN_N_STAT(MC_ME, PART) (MC_ME_PRTN_N(MC_ME, PART) + 0x8UL)
+#define MC_ME_PRTN_N_PCS BIT_32(0)
+#define MC_ME_PRTN_N_COFB0_STAT(MC_ME, PART) \
+ (MC_ME_PRTN_N(MC_ME, PART) + 0x10UL)
+#define MC_ME_PRTN_N_COFB0_CLKEN(MC_ME, PART) \
+ (MC_ME_PRTN_N(MC_ME, PART) + 0x30UL)
+#define MC_ME_PRTN_N_REQ(PART) BIT_32(PART)
+
+#define RDC_RD_CTRL(RDC, PART) ((RDC) + ((PART) * 0x4UL))
+#define RDC_CTRL_UNLOCK BIT_32(31)
+#define RDC_RD_INTERCONNECT_DISABLE BIT_32(3)
+
+#define RDC_RD_N_STATUS(RDC, PART) ((RDC) + ((PART) * 0x4UL) + 0x80UL)
+#define RDC_RD_INTERCONNECT_DISABLE_STAT \
+ BIT_32(4)
+
+static bool is_interconnect_disabled(uintptr_t rdc, uint32_t part)
+{
+ return ((mmio_read_32(RDC_RD_N_STATUS(rdc, part)) &
+ RDC_RD_INTERCONNECT_DISABLE_STAT) != 0U);
+}
+
+static void enable_interconnect(uintptr_t rdc, uint32_t part)
+{
+ /* Unlock RDC register write */
+ mmio_setbits_32(RDC_RD_CTRL(rdc, part), RDC_CTRL_UNLOCK);
+
+ /* Clear corresponding RDC_RD_INTERCONNECT bit */
+ mmio_clrbits_32(RDC_RD_CTRL(rdc, part), RDC_RD_INTERCONNECT_DISABLE);
+
+ /* Wait until the interface gets enabled */
+ while (is_interconnect_disabled(rdc, part)) {
+ }
+
+ /* Lock RDC register write */
+ mmio_clrbits_32(RDC_RD_CTRL(rdc, part), RDC_CTRL_UNLOCK);
+}
+
+static int mc_me_check_partition_nb_valid(uint32_t part)
+{
+ if (part >= MC_ME_MAX_PARTITIONS) {
+ ERROR("Invalid partition %" PRIu32 "\n", part);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void part_pconf_write_pce(uintptr_t mc_me, uint32_t pce_bit,
+ uint32_t part)
+{
+ mmio_clrsetbits_32(MC_ME_PRTN_N_PCONF(mc_me, part), MC_ME_PRTN_N_PCE,
+ pce_bit & MC_ME_PRTN_N_PCE);
+}
+
+static void mc_me_apply_hw_changes(uintptr_t mc_me)
+{
+ mmio_write_32(MC_ME_CTL_KEY(mc_me), MC_ME_CTL_KEY_KEY);
+ mmio_write_32(MC_ME_CTL_KEY(mc_me), MC_ME_CTL_KEY_INVERTEDKEY);
+}
+
+static void part_pupd_update_and_wait(uintptr_t mc_me, uint32_t part,
+ uint32_t mask)
+{
+ uint32_t pconf, stat;
+
+ mmio_setbits_32(MC_ME_PRTN_N_PUPD(mc_me, part), mask);
+
+ mc_me_apply_hw_changes(mc_me);
+
+ /* wait for the updates to apply */
+ pconf = mmio_read_32(MC_ME_PRTN_N_PCONF(mc_me, part));
+ do {
+ stat = mmio_read_32(MC_ME_PRTN_N_STAT(mc_me, part));
+ } while ((stat & mask) != (pconf & mask));
+}
+
+static void part_pconf_write_osse(uintptr_t mc_me, uint32_t osse_bit,
+ uint32_t part)
+{
+ mmio_clrsetbits_32(MC_ME_PRTN_N_PCONF(mc_me, part), MC_ME_PRTN_N_OSSE,
+ (osse_bit & MC_ME_PRTN_N_OSSE));
+}
+
+int mc_me_enable_partition(uintptr_t mc_me, uintptr_t mc_rgm, uintptr_t rdc,
+ uint32_t part)
+{
+ uint32_t part_stat;
+ int ret;
+
+ /* Partition 0 is already enabled by BootROM */
+ if (part == 0U) {
+ return 0;
+ }
+
+ ret = mc_me_check_partition_nb_valid(part);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Enable a partition only if it's disabled */
+ part_stat = mmio_read_32(MC_ME_PRTN_N_STAT(mc_me, part));
+ if ((MC_ME_PRTN_N_PCS & part_stat) != 0U) {
+ return 0;
+ }
+
+ part_pconf_write_pce(mc_me, MC_ME_PRTN_N_PCE, part);
+ part_pupd_update_and_wait(mc_me, part, MC_ME_PRTN_N_PCUD);
+
+ enable_interconnect(rdc, part);
+
+ /* Release partition reset */
+ mc_rgm_release_part(mc_rgm, part);
+
+ /* Clear OSSE bit */
+ part_pconf_write_osse(mc_me, 0, part);
+
+ part_pupd_update_and_wait(mc_me, part, MC_ME_PRTN_N_OSSUD);
+
+ mc_rgm_wait_part_deassert(mc_rgm, part);
+
+ return 0;
+}
+
+void mc_me_enable_part_cofb(uintptr_t mc_me, uint32_t partition_n, uint32_t block,
+ bool check_status)
+{
+ uint32_t block_mask = MC_ME_PRTN_N_REQ(block);
+ uintptr_t cofb_stat_addr;
+
+ mmio_setbits_32(MC_ME_PRTN_N_COFB0_CLKEN(mc_me, partition_n),
+ block_mask);
+
+ mmio_setbits_32(MC_ME_PRTN_N_PCONF(mc_me, partition_n),
+ MC_ME_PRTN_N_PCE);
+
+ part_pupd_update_and_wait(mc_me, partition_n, MC_ME_PRTN_N_PCUD);
+
+ cofb_stat_addr = MC_ME_PRTN_N_COFB0_STAT(mc_me, partition_n);
+ if (check_status) {
+ while ((mmio_read_32(cofb_stat_addr) & block_mask) == 0U) {
+ }
+ }
+}
diff --git a/drivers/nxp/clk/s32cc/mc_rgm.c b/drivers/nxp/clk/s32cc/mc_rgm.c
index cbf4022..c66b013 100644
--- a/drivers/nxp/clk/s32cc/mc_rgm.c
+++ b/drivers/nxp/clk/s32cc/mc_rgm.c
@@ -7,7 +7,10 @@
#include <lib/utils_def.h>
#include <s32cc-mc-rgm.h>
-#define MC_RGM_PRST(MC_RGM, PER) ((MC_RGM) + 0x40UL + ((PER) * 0x8UL))
+#define MC_RGM_PRST(RGM, PER) ((RGM) + 0x40UL + ((PER) * 0x8UL))
+#define MC_RGM_PRST_PERIPH_N_RST(PER) BIT_32(PER)
+#define MC_RGM_PSTAT(RGM, PER) ((RGM) + 0x140UL + ((PER) * 0x8UL))
+#define MC_RGM_PSTAT_PERIPH(PER) BIT_32(PER)
/* ERR051700
* Releasing more than one Software Resettable Domain (SRD)
@@ -63,3 +66,19 @@
mmio_write_32(MC_RGM_PRST(rgm, part), value);
}
#endif /* ERRATA_S32_051700 */
+
+void mc_rgm_release_part(uintptr_t rgm, uint32_t part)
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(MC_RGM_PRST(rgm, part));
+ reg &= ~MC_RGM_PRST_PERIPH_N_RST(0);
+ mc_rgm_periph_reset(rgm, part, reg);
+}
+
+void mc_rgm_wait_part_deassert(uintptr_t rgm, uint32_t part)
+{
+ while ((mmio_read_32(MC_RGM_PSTAT(rgm, part)) &
+ MC_RGM_PSTAT_PERIPH(0)) != 0U) {
+ }
+}
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk.mk b/drivers/nxp/clk/s32cc/s32cc_clk.mk
index 2a9a376..602179e 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk.mk
+++ b/drivers/nxp/clk/s32cc/s32cc_clk.mk
@@ -10,6 +10,7 @@
CLK_SOURCES := \
${PLAT_DRIVERS_PATH}/clk/s32cc/mc_rgm.c \
+ ${PLAT_DRIVERS_PATH}/clk/s32cc/mc_me.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_modules.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_utils.c \
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index 14b03d9..9b57607 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -4,15 +4,14 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
-
-#include <s32cc-clk-regs.h>
-
#include <common/debug.h>
#include <drivers/clk.h>
#include <lib/mmio.h>
#include <s32cc-clk-ids.h>
#include <s32cc-clk-modules.h>
+#include <s32cc-clk-regs.h>
#include <s32cc-clk-utils.h>
+#include <s32cc-mc-me.h>
#define MAX_STACK_DEPTH (40U)
@@ -26,6 +25,11 @@
uintptr_t armdfs_base;
uintptr_t cgm0_base;
uintptr_t cgm1_base;
+ uintptr_t cgm5_base;
+ uintptr_t ddrpll_base;
+ uintptr_t mc_me;
+ uintptr_t mc_rgm;
+ uintptr_t rdc;
};
static int update_stack_depth(unsigned int *depth)
@@ -47,6 +51,11 @@
.armdfs_base = ARM_DFS_BASE_ADDR,
.cgm0_base = CGM0_BASE_ADDR,
.cgm1_base = CGM1_BASE_ADDR,
+ .cgm5_base = MC_CGM5_BASE_ADDR,
+ .ddrpll_base = DDRPLL_BASE_ADDR,
+ .mc_me = MC_ME_BASE_ADDR,
+ .mc_rgm = MC_RGM_BASE_ADDR,
+ .rdc = RDC_BASE_ADDR,
};
return &driver;
@@ -86,6 +95,9 @@
case S32CC_PERIPH_PLL:
*base = drv->periphpll_base;
break;
+ case S32CC_DDR_PLL:
+ *base = drv->ddrpll_base;
+ break;
case S32CC_ARM_DFS:
*base = drv->armdfs_base;
break;
@@ -95,6 +107,9 @@
case S32CC_CGM1:
*base = drv->cgm1_base;
break;
+ case S32CC_CGM5:
+ *base = drv->cgm5_base;
+ break;
case S32CC_FIRC:
break;
case S32CC_SIRC:
@@ -140,9 +155,10 @@
unsigned int depth)
{
const struct s32cc_osc *osc = s32cc_obj2osc(module);
+ unsigned int ldepth = depth;
int ret = 0;
- ret = update_stack_depth(&depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -321,11 +337,12 @@
const struct s32cc_pll *pll = s32cc_obj2pll(module);
const struct s32cc_clkmux *mux;
uintptr_t pll_addr = UL(0x0);
+ unsigned int ldepth = depth;
unsigned long sclk_freq;
uint32_t sclk_id;
int ret;
- ret = update_stack_depth(&depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -421,11 +438,12 @@
{
const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
uintptr_t pll_addr = 0x0ULL;
+ unsigned int ldepth = depth;
const struct s32cc_pll *pll;
uint32_t dc;
int ret;
- ret = update_stack_depth(&depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -562,10 +580,11 @@
unsigned int depth)
{
const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+ unsigned int ldepth = depth;
const struct s32cc_clk *clk;
int ret = 0;
- ret = update_stack_depth(&depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -585,6 +604,7 @@
/* PLL mux will be enabled by PLL setup */
case S32CC_ARM_PLL:
case S32CC_PERIPH_PLL:
+ case S32CC_DDR_PLL:
break;
case S32CC_CGM1:
ret = enable_cgm_mux(mux, drv);
@@ -592,6 +612,9 @@
case S32CC_CGM0:
ret = enable_cgm_mux(mux, drv);
break;
+ case S32CC_CGM5:
+ ret = enable_cgm_mux(mux, drv);
+ break;
default:
ERROR("Unknown mux parent type: %d\n", mux->module);
ret = -EINVAL;
@@ -616,9 +639,10 @@
const struct s32cc_clk_drv *drv,
unsigned int depth)
{
+ unsigned int ldepth = depth;
int ret = 0;
- ret = update_stack_depth(&depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -782,13 +806,14 @@
unsigned int depth)
{
const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
+ unsigned int ldepth = depth;
const struct s32cc_pll *pll;
const struct s32cc_dfs *dfs;
uintptr_t dfs_addr = 0UL;
uint32_t mfi, mfn;
int ret = 0;
- ret = update_stack_depth(&depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -821,6 +846,86 @@
const struct s32cc_clk_drv *drv,
unsigned int depth);
+static int enable_part(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ const struct s32cc_part *part = s32cc_obj2part(module);
+ uint32_t part_no = part->partition_id;
+
+ if ((drv->mc_me == 0UL) || (drv->mc_rgm == 0UL) || (drv->rdc == 0UL)) {
+ return -EINVAL;
+ }
+
+ return mc_me_enable_partition(drv->mc_me, drv->mc_rgm, drv->rdc, part_no);
+}
+
+static int enable_part_block(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ const struct s32cc_part_block *block = s32cc_obj2partblock(module);
+ const struct s32cc_part *part = block->part;
+ uint32_t part_no = part->partition_id;
+ unsigned int ldepth = depth;
+ uint32_t cofb;
+ int ret;
+
+ ret = update_stack_depth(&ldepth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if ((block->block >= s32cc_part_block0) &&
+ (block->block <= s32cc_part_block15)) {
+ cofb = (uint32_t)block->block - (uint32_t)s32cc_part_block0;
+ mc_me_enable_part_cofb(drv->mc_me, part_no, cofb, block->status);
+ } else {
+ ERROR("Unknown partition block type: %d\n", block->block);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct s32cc_clk_obj *
+get_part_block_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_part_block *block = s32cc_obj2partblock(module);
+
+ return &block->part->desc;
+}
+
+static int enable_module_with_refcount(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth);
+
+static int enable_part_block_link(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module);
+ struct s32cc_part_block *block = link->block;
+ unsigned int ldepth = depth;
+ int ret;
+
+ ret = update_stack_depth(&ldepth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Move the enablement algorithm to partition tree */
+ return enable_module_with_refcount(&block->desc, drv, ldepth);
+}
+
+static struct s32cc_clk_obj *
+get_part_block_link_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module);
+
+ return link->parent;
+}
+
static int no_enable(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
unsigned int depth)
@@ -832,24 +937,25 @@
const struct s32cc_clk_drv *drv, bool leaf_node,
unsigned int depth)
{
+ unsigned int ldepth = depth;
int ret = 0;
if (mod == NULL) {
return 0;
}
- ret = update_stack_depth(&depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
/* Refcount will be updated as part of the recursivity */
if (leaf_node) {
- return en_cb(mod, drv, depth);
+ return en_cb(mod, drv, ldepth);
}
if (mod->refcount == 0U) {
- ret = en_cb(mod, drv, depth);
+ ret = en_cb(mod, drv, ldepth);
}
if (ret == 0) {
@@ -866,7 +972,7 @@
unsigned int depth)
{
struct s32cc_clk_obj *parent = get_module_parent(module);
- static const enable_clk_t enable_clbs[8] = {
+ static const enable_clk_t enable_clbs[12] = {
[s32cc_clk_t] = no_enable,
[s32cc_osc_t] = enable_osc,
[s32cc_pll_t] = enable_pll,
@@ -875,11 +981,15 @@
[s32cc_shared_clkmux_t] = enable_mux,
[s32cc_dfs_t] = enable_dfs,
[s32cc_dfs_div_t] = enable_dfs_div,
+ [s32cc_part_t] = enable_part,
+ [s32cc_part_block_t] = enable_part_block,
+ [s32cc_part_block_link_t] = enable_part_block_link,
};
+ unsigned int ldepth = depth;
uint32_t index;
int ret = 0;
- ret = update_stack_depth(&depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -904,13 +1014,13 @@
parent = get_module_parent(module);
ret = exec_cb_with_refcount(enable_module, parent, drv,
- false, depth);
+ false, ldepth);
if (ret != 0) {
return ret;
}
ret = exec_cb_with_refcount(enable_clbs[index], module, drv,
- true, depth);
+ true, ldepth);
if (ret != 0) {
return ret;
}
@@ -1238,7 +1348,7 @@
static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module)
{
- static const get_parent_clb_t parents_clbs[8] = {
+ static const get_parent_clb_t parents_clbs[12] = {
[s32cc_clk_t] = get_clk_parent,
[s32cc_osc_t] = get_no_parent,
[s32cc_pll_t] = get_pll_parent,
@@ -1247,6 +1357,9 @@
[s32cc_shared_clkmux_t] = get_mux_parent,
[s32cc_dfs_t] = get_dfs_parent,
[s32cc_dfs_div_t] = get_dfs_div_parent,
+ [s32cc_part_t] = get_no_parent,
+ [s32cc_part_block_t] = get_part_block_parent,
+ [s32cc_part_block_link_t] = get_part_block_link_parent,
};
uint32_t index;
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
index 17ded0e..71055ab 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
@@ -10,6 +10,9 @@
#define S32CC_A53_MIN_FREQ (48UL * MHZ)
#define S32CC_A53_MAX_FREQ (1000UL * MHZ)
+/* Partitions */
+static struct s32cc_part part0 = S32CC_PART(0);
+
/* Oscillators */
static struct s32cc_osc fxosc =
S32CC_OSC_INIT(S32CC_FXOSC);
@@ -139,7 +142,40 @@
static struct s32cc_clk periph_pll_phi3_clk =
S32CC_FREQ_MODULE_CLK(periph_pll_phi3_div, 0, 133333333);
+/* DDR PLL */
+static struct s32cc_clkmux ddr_pll_mux =
+ S32CC_CLKMUX_INIT(S32CC_DDR_PLL, 0, 2,
+ S32CC_CLK_FIRC,
+ S32CC_CLK_FXOSC, 0, 0, 0);
+static struct s32cc_clk ddr_pll_mux_clk =
+ S32CC_MODULE_CLK(ddr_pll_mux);
+static struct s32cc_pll ddrpll =
+ S32CC_PLL_INIT(ddr_pll_mux_clk, S32CC_DDR_PLL, 1);
+static struct s32cc_clk ddr_pll_vco_clk =
+ S32CC_FREQ_MODULE_CLK(ddrpll, 1300 * MHZ, 1600 * MHZ);
+
-static struct s32cc_clk *s32cc_hw_clk_list[22] = {
+static struct s32cc_pll_out_div ddr_pll_phi0_div =
+ S32CC_PLL_OUT_DIV_INIT(ddrpll, 0);
+static struct s32cc_clk ddr_pll_phi0_clk =
+ S32CC_FREQ_MODULE_CLK(ddr_pll_phi0_div, 0, 800 * MHZ);
+
+/* MC_CGM5 */
+static struct s32cc_clkmux cgm5_mux0 =
+ S32CC_SHARED_CLKMUX_INIT(S32CC_CGM5, 0, 2,
+ S32CC_CLK_FIRC,
+ S32CC_CLK_DDR_PLL_PHI0,
+ 0, 0, 0);
+static struct s32cc_clk cgm5_mux0_clk = S32CC_MODULE_CLK(cgm5_mux0);
+
+/* DDR clock */
+static struct s32cc_part_block part0_block1 =
+ S32CC_PART_BLOCK(&part0, s32cc_part_block1);
+static struct s32cc_part_block_link ddr_block_link =
+ S32CC_PART_BLOCK_LINK(cgm5_mux0_clk, &part0_block1);
+static struct s32cc_clk ddr_clk =
+ S32CC_FREQ_MODULE_CLK(ddr_block_link, 0, 800 * MHZ);
+
+static struct s32cc_clk *s32cc_hw_clk_list[37] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
[S32CC_CLK_ID(S32CC_CLK_SIRC)] = &sirc_clk,
@@ -150,6 +186,8 @@
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_DFS1)] = &arm_dfs1_clk,
/* PERIPH PLL */
[S32CC_CLK_ID(S32CC_CLK_PERIPH_PLL_PHI3)] = &periph_pll_phi3_clk,
+ /* DDR PLL */
+ [S32CC_CLK_ID(S32CC_CLK_DDR_PLL_PHI0)] = &ddr_pll_phi0_clk,
};
static struct s32cc_clk_array s32cc_hw_clocks = {
@@ -158,7 +196,7 @@
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
-static struct s32cc_clk *s32cc_arch_clk_list[18] = {
+static struct s32cc_clk *s32cc_arch_clk_list[22] = {
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
@@ -184,6 +222,13 @@
/* Linflex */
[S32CC_CLK_ID(S32CC_CLK_LINFLEX)] = &linflex_clk,
[S32CC_CLK_ID(S32CC_CLK_LINFLEX_BAUD)] = &linflex_baud_clk,
+ /* DDR PLL */
+ [S32CC_CLK_ID(S32CC_CLK_DDR_PLL_MUX)] = &ddr_pll_mux_clk,
+ [S32CC_CLK_ID(S32CC_CLK_DDR_PLL_VCO)] = &ddr_pll_vco_clk,
+ /* MC_CGM5 */
+ [S32CC_CLK_ID(S32CC_CLK_MC_CGM5_MUX0)] = &cgm5_mux0_clk,
+ /* DDR */
+ [S32CC_CLK_ID(S32CC_CLK_DDR)] = &ddr_clk,
};
static struct s32cc_clk_array s32cc_arch_clocks = {
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 3f6d3d7..02b9df9 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -16,6 +16,8 @@
#define S32CC_XBAR_2X_FREQ (800U * MHZ)
#define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ
+#define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ)
+#define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ)
static int setup_fxosc(void)
{
@@ -139,6 +141,45 @@
return ret;
}
+static int setup_ddr_pll(void)
+{
+ int ret;
+
+ ret = clk_set_parent(S32CC_CLK_DDR_PLL_MUX, S32CC_CLK_FXOSC);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_DDR_PLL_VCO, S32CC_DDR_PLL_VCO_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_DDR_PLL_PHI0, S32CC_DDR_PLL_PHI0_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
+static int enable_ddr_clk(void)
+{
+ int ret;
+
+ ret = clk_set_parent(S32CC_CLK_MC_CGM5_MUX0, S32CC_CLK_DDR_PLL_PHI0);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_DDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
int s32cc_init_early_clks(void)
{
int ret;
@@ -175,5 +216,15 @@
return ret;
}
+ ret = setup_ddr_pll();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = enable_ddr_clk();
+ if (ret != 0) {
+ return ret;
+ }
+
return ret;
}
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
index de633ae..d34dc22 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
@@ -95,4 +95,12 @@
#define S32CC_CLK_LINFLEX_BAUD S32CC_ARCH_CLK(16)
#define S32CC_CLK_LINFLEX S32CC_ARCH_CLK(17)
+/* DDR PLL */
+#define S32CC_CLK_DDR_PLL_MUX S32CC_ARCH_CLK(18)
+#define S32CC_CLK_DDR_PLL_VCO S32CC_ARCH_CLK(19)
+
+/* DDR clock */
+#define S32CC_CLK_MC_CGM5_MUX0 S32CC_ARCH_CLK(20)
+#define S32CC_CLK_DDR S32CC_ARCH_CLK(21)
+
#endif /* S32CC_CLK_IDS_H */
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
index a6d58cc..4837f79 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
@@ -22,6 +22,9 @@
s32cc_clkmux_t,
s32cc_shared_clkmux_t,
s32cc_fixed_div_t,
+ s32cc_part_t,
+ s32cc_part_block_t,
+ s32cc_part_block_link_t,
};
enum s32cc_clk_source {
@@ -33,6 +36,8 @@
S32CC_PERIPH_PLL,
S32CC_CGM0,
S32CC_CGM1,
+ S32CC_DDR_PLL,
+ S32CC_CGM5,
};
struct s32cc_clk_obj {
@@ -208,6 +213,76 @@
#define S32CC_CHILD_CLK(PARENT, MIN_F, MAX_F) \
S32CC_FREQ_CLK(NULL, &(PARENT), MIN_F, MAX_F)
+struct s32cc_part {
+ struct s32cc_clk_obj desc;
+ uint32_t partition_id;
+};
+
+#define S32CC_PART(PART_NUM) \
+{ \
+ .desc = { \
+ .type = s32cc_part_t, \
+ }, \
+ .partition_id = (PART_NUM), \
+}
+
+enum s32cc_part_block_type {
+ s32cc_part_block0,
+ s32cc_part_block1,
+ s32cc_part_block2,
+ s32cc_part_block3,
+ s32cc_part_block4,
+ s32cc_part_block5,
+ s32cc_part_block6,
+ s32cc_part_block7,
+ s32cc_part_block8,
+ s32cc_part_block9,
+ s32cc_part_block10,
+ s32cc_part_block11,
+ s32cc_part_block12,
+ s32cc_part_block13,
+ s32cc_part_block14,
+ s32cc_part_block15,
+};
+
+struct s32cc_part_block {
+ struct s32cc_clk_obj desc;
+ struct s32cc_part *part;
+ enum s32cc_part_block_type block;
+ bool status;
+};
+
+#define S32CC_PART_BLOCK_STATUS(PART_META, BLOCK_TYPE, STATUS) \
+{ \
+ .desc = { \
+ .type = s32cc_part_block_t, \
+ }, \
+ .part = (PART_META), \
+ .block = (BLOCK_TYPE), \
+ .status = (STATUS), \
+}
+
+#define S32CC_PART_BLOCK(PARENT, BLOCK_TYPE) \
+ S32CC_PART_BLOCK_STATUS(PARENT, BLOCK_TYPE, true)
+
+#define S32CC_PART_BLOCK_NO_STATUS(PARENT, BLOCK_TYPE) \
+ S32CC_PART_BLOCK_STATUS(PARENT, BLOCK_TYPE, false)
+
+struct s32cc_part_block_link {
+ struct s32cc_clk_obj desc;
+ struct s32cc_clk_obj *parent;
+ struct s32cc_part_block *block;
+};
+
+#define S32CC_PART_BLOCK_LINK(PARENT, BLOCK) \
+{ \
+ .desc = { \
+ .type = s32cc_part_block_link_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .block = (BLOCK), \
+}
+
static inline struct s32cc_osc *s32cc_obj2osc(const struct s32cc_clk_obj *mod)
{
uintptr_t osc_addr;
@@ -294,4 +369,30 @@
return (struct s32cc_dfs_div *)dfs_div_addr;
}
+static inline struct s32cc_part *s32cc_obj2part(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t part_addr;
+
+ part_addr = ((uintptr_t)mod) - offsetof(struct s32cc_part, desc);
+ return (struct s32cc_part *)part_addr;
+}
+
+static inline struct s32cc_part_block *
+s32cc_obj2partblock(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t part_blk_addr;
+
+ part_blk_addr = ((uintptr_t)mod) - offsetof(struct s32cc_part_block, desc);
+ return (struct s32cc_part_block *)part_blk_addr;
+}
+
+static inline struct s32cc_part_block_link *
+s32cc_obj2partblocklink(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t blk_link;
+
+ blk_link = ((uintptr_t)mod) - offsetof(struct s32cc_part_block_link, desc);
+ return (struct s32cc_part_block_link *)blk_link;
+}
+
#endif /* S32CC_CLK_MODULES_H */
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index ca79991..7a97ed1 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -50,6 +50,11 @@
unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
+
+#if ERRATA_A75_764081
+long check_erratum_cortex_a75_764081(long cpu_rev);
+#endif /* ERRATA_A75_764081 */
+
#endif /* __ASSEMBLER__ */
#endif /* CORTEX_A75_H */
diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h
index b16170c..f701216 100644
--- a/include/lib/cpus/aarch64/cortex_x4.h
+++ b/include/lib/cpus/aarch64/cortex_x4.h
@@ -26,6 +26,7 @@
/*******************************************************************************
* CPU Auxiliary control register specific definitions
******************************************************************************/
+#define CORTEX_X4_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
#define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index ef1b02b..2c31515 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -35,6 +35,15 @@
void print_errata_status(void);
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void);
+#else
+static inline bool errata_a75_764081_applies(void)
+{
+ return false;
+}
+#endif
+
#if ERRATA_A520_2938996 || ERRATA_X4_2726228
unsigned int check_if_affected_core(void);
#endif
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 9115303..152c81f 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -10,6 +10,8 @@
#include <cpuamu.h>
#include <cpu_macros.S>
+.global check_erratum_cortex_a75_764081
+
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 75b2766..8820de5 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -75,6 +75,14 @@
check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
+workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789
+ sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14)
+ sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13)
+ sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52)
+workaround_reset_end cortex_x4, ERRATUM(3076789)
+
+check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1)
+
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 2cbbdd2..4c20785 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -843,6 +843,10 @@
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2897503
+# Flag to apply erratum 3076789 workaround on reset. This erratum applies
+# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_X4_3076789
+
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 9801245..a4515a9 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <cortex_a520.h>
#include <cortex_x4.h>
+#include <cortex_a75.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -28,3 +29,14 @@
return ERRATA_NOT_APPLIES;
}
#endif
+
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void)
+{
+ long rev_var = cpu_get_rev_var();
+ if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
+ return true;
+ }
+ return false;
+}
+#endif /* ERRATA_A75_764081 */
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 218ad11..6210356 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -89,13 +89,13 @@
| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
}
-#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used then set
* SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_elx |= SCTLR_IESB_BIT;
+ }
/* Store the initialised SCTLR_EL1 value in the cpu_context */
write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx);
@@ -1070,14 +1070,16 @@
if ((scr_el3 & SCR_HCE_BIT) != 0U) {
/* Initialize SCTLR_EL2 register with reset value. */
sctlr_el2 = SCTLR_EL2_RES1;
-#if ERRATA_A75_764081
+
/*
* If workaround of errata 764081 for Cortex-A75
* is used then set SCTLR_EL2.IESB to enable
* Implicit Error Synchronization Barrier.
*/
- sctlr_el2 |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_el2 |= SCTLR_IESB_BIT;
+ }
+
write_sctlr_el2(sctlr_el2);
} else {
/*
diff --git a/make_helpers/plat_helpers.mk b/make_helpers/plat_helpers.mk
index a7ae9a2..bc02a20 100644
--- a/make_helpers/plat_helpers.mk
+++ b/make_helpers/plat_helpers.mk
@@ -11,6 +11,7 @@
ifndef PLAT_HELPERS_MK
PLAT_HELPERS_MK := $(lastword $(MAKEFILE_LIST))
+ PLAT:= ${DEFAULT_PLAT}
ifeq (${PLAT},)
$(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform")
endif
@@ -18,15 +19,18 @@
# TF_PLATFORM_ROOT can be overridden for when building tools directly
TF_PLATFORM_ROOT ?= plat/
PLAT_MAKEFILE := platform.mk
+ PLAT_DEFAULTS_MAKEFILE := platform_defaults.mk
# Generate the platforms list by recursively searching for all directories
# under /plat containing a PLAT_MAKEFILE. Append each platform with a `|`
# char and strip out the final '|'.
ALL_PLATFORM_MK_FILES := $(call rwildcard,${TF_PLATFORM_ROOT},${PLAT_MAKEFILE})
+ ALL_PLATFORM_MK_DEF_FILES := $(call rwildcard,${TF_PLATFORM_ROOT},${PLAT_DEFAULTS_MAKEFILE})
ALL_PLATFORM_DIRS := $(patsubst %/,%,$(dir ${ALL_PLATFORM_MK_FILES}))
ALL_PLATFORMS := $(sort $(notdir ${ALL_PLATFORM_DIRS}))
PLAT_MAKEFILE_FULL := $(filter %/${PLAT}/${PLAT_MAKEFILE},${ALL_PLATFORM_MK_FILES})
+ PLAT_DEFAULTS_MAKEFILE_FULL := $(filter %/${PLAT}/${PLAT_DEFAULTS_MAKEFILE},${ALL_PLATFORM_MK_DEF_FILES})
PLATFORM_LIST := $(subst ${space},|,${ALL_PLATFORMS})
ifeq ($(PLAT_MAKEFILE_FULL),)
$(error "Error: Invalid platform. The following platforms are available: ${PLATFORM_LIST}")
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index e878863..970fca9 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -74,6 +74,10 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ (void)arg0;
+ (void)arg1;
+ (void)arg2;
+ (void)arg3;
uint32_t uart_clock;
int32_t rc;
@@ -206,6 +210,7 @@
static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
+ (void)id;
uint32_t intr_id;
uint32_t i;
interrupt_type_handler_t handler = NULL;
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
index 2094c65..ca76b6a 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -10,6 +10,7 @@
#include <platform_def.h>
#include "ncore_ccu.h"
+#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"
#include "socfpga_system_manager.h"
@@ -17,6 +18,486 @@
#define SMMU_DMI 1
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ncore_ccu_reg_t ncore_ccu_modules[] = {
+ {"caiu0@1c000000", 0x1C000000, 0x00001000},
+ {"ncaiu0@1c001000", 0x1C001000, 0x00001000},
+ {"ncaiu1@1c002000", 0x1C002000, 0x00001000},
+ {"ncaiu2@1c003000", 0x1C003000, 0x00001000},
+ {"ncaiu3@1c004000", 0x1C004000, 0x00001000},
+ {"dce0@1c005000", 0x1C005000, 0x00001000},
+ {"dce1@1c006000", 0x1C006000, 0x00001000},
+ {"dmi0@1c007000", 0x1C007000, 0x00001000},
+ {"dmi1@1c008000", 0x1C008000, 0x00001000},
+ {"noc_fw_l4_per@10d21000", 0x10D21000, 0x0000008C},
+ {"noc_fw_l4_sys@10d21100", 0x10D21100, 0x00000098},
+ {"noc_fw_lwsoc2fpga@10d21300", 0x10D21300, 0x00000004},
+ {"noc_fw_soc2fpga@10d21200", 0x10D21200, 0x00000004},
+ {"noc_fw_tcu@10d21400", 0x10D21400, 0x00000004}
+ };
+
+ncore_ccu_t ccu_caiu0[] = {
+ /* CAIUAMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* CAIUMIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DII1_MPFEREGS */
+ {0x00000414, 0x00018000, 0xFFFFFFFF},
+ {0x00000418, 0x00000000, 0x000000FF},
+ {0x00000410, 0xC0E00200, 0xC1F03E1F},
+ /* DII2_GICREGS */
+ {0x00000424, 0x0001D000, 0xFFFFFFFF},
+ {0x00000428, 0x00000000, 0x000000FF},
+ {0x00000420, 0xC0800400, 0xC1F03E1F},
+ /* NCAIU0_LWSOC2FPGA */
+ {0x00000444, 0x00020000, 0xFFFFFFFF},
+ {0x00000448, 0x00000000, 0x000000FF},
+ {0x00000440, 0xC1100006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_1G */
+ {0x00000454, 0x00040000, 0xFFFFFFFF},
+ {0x00000458, 0x00000000, 0x000000FF},
+ {0x00000450, 0xC1200006, 0xC1F03E1F},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_16G */
+ {0x00000474, 0x00400000, 0xFFFFFFFF},
+ {0x00000478, 0x00000000, 0x000000FF},
+ {0x00000470, 0xC1600006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_256G */
+ {0x00000494, 0x04000000, 0xFFFFFFFF},
+ {0x00000498, 0x00000000, 0x000000FF},
+ {0x00000490, 0xC1A00006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_ncaiu0[] = {
+ /* NCAIU0AMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* NCAIU0MIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* PSS */
+ {0x00000404, 0x00010000, 0xFFFFFFFF},
+ {0x00000408, 0x00000000, 0x000000FF},
+ {0x00000400, 0xC0F00000, 0xC1F03E1F},
+ /* DII1_MPFEREGS */
+ {0x00000414, 0x00018000, 0xFFFFFFFF},
+ {0x00000418, 0x00000000, 0x000000FF},
+ {0x00000410, 0xC0E00200, 0xC1F03E1F},
+ /* NCAIU0_LWSOC2FPGA */
+ {0x00000444, 0x00020000, 0xFFFFFFFF},
+ {0x00000448, 0x00000000, 0x000000FF},
+ {0x00000440, 0xC1100006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_1G */
+ {0x00000454, 0x00040000, 0xFFFFFFFF},
+ {0x00000458, 0x00000000, 0x000000FF},
+ {0x00000450, 0xC1200006, 0xC1F03E1F},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_16G */
+ {0x00000474, 0x00400000, 0xFFFFFFFF},
+ {0x00000478, 0x00000000, 0x000000FF},
+ {0x00000470, 0xC1600006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_256G */
+ {0x00000494, 0x04000000, 0xFFFFFFFF},
+ {0x00000498, 0x00000000, 0x000000FF},
+ {0x00000490, 0xC1A00006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_ncaiu1[] = {
+ /* NCAIU1AMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* NCAIU1MIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_ncaiu2[] = {
+ /* NCAIU2AMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* NCAIU2MIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_ncaiu3[] = {
+ /* NCAIU3AMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* NCAIU3MIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DII1_MPFEREGS */
+ {0x00000414, 0x00018000, 0xFFFFFFFF},
+ {0x00000418, 0x00000000, 0x000000FF},
+ {0x00000410, 0xC0E00200, 0xC1F03E1F},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_dce0[] = {
+ /* DCEUAMIGR0 */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* DCEUMIFSR0 */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_dce1[] = {
+ /* DCEUAMIGR1 */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* DCEUMIFSR1 */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_dmi0[] = {
+ /* DMIUSMCTCR */
+ {0x00000300, 0x00000001, 0x00000003},
+ {0x00000300, 0x00000003, 0x00000003}
+ };
+
+ncore_ccu_t ccu_dmi1[] = {
+ /* DMIUSMCTCR */
+ {0x00000300, 0x00000001, 0x00000003},
+ {0x00000300, 0x00000003, 0x00000003}
+ };
+
+ncore_ccu_t ccu_noc_fw_l4_per[] = {
+ /* NAND */
+ {0x00000000, 0x01010001, 0x01010001},
+ /* USB0 */
+ {0x0000000C, 0x01010001, 0x01010001},
+ /* USB1 */
+ {0x00000010, 0x01010001, 0x01010001},
+ /* SPI_MAIN0 */
+ {0x0000001C, 0x01010301, 0x01010301},
+ /* SPI_MAIN1 */
+ {0x00000020, 0x01010301, 0x01010301},
+ /* SPI_SECONDARY0 */
+ {0x00000024, 0x01010301, 0x01010301},
+ /* SPI_SECONDARY1 */
+ {0x00000028, 0x01010301, 0x01010301},
+ /* EMAC0 */
+ {0x0000002C, 0x01010001, 0x01010001},
+ /* EMAC1 */
+ {0x00000030, 0x01010001, 0x01010001},
+ /* EMAC2 */
+ {0x00000034, 0x01010001, 0x01010001},
+ /* SDMMC */
+ {0x00000040, 0x01010001, 0x01010001},
+ /* GPIO0 */
+ {0x00000044, 0x01010301, 0x01010301},
+ /* GPIO1 */
+ {0x00000048, 0x01010301, 0x01010301},
+ /* I2C0 */
+ {0x00000050, 0x01010301, 0x01010301},
+ /* I2C1 */
+ {0x00000054, 0x01010301, 0x01010301},
+ /* I2C2 */
+ {0x00000058, 0x01010301, 0x01010301},
+ /* I2C3 */
+ {0x0000005C, 0x01010301, 0x01010301},
+ /* I2C4 */
+ {0x00000060, 0x01010301, 0x01010301},
+ /* SP_TIMER0 */
+ {0x00000064, 0x01010301, 0x01010301},
+ /* SP_TIMER1 */
+ {0x00000068, 0x01010301, 0x01010301},
+ /* UART0 */
+ {0x0000006C, 0x01010301, 0x01010301},
+ /* UART1 */
+ {0x00000070, 0x01010301, 0x01010301},
+ /* I3C0 */
+ {0x00000074, 0x01010301, 0x01010301},
+ /* I3C1 */
+ {0x00000078, 0x01010301, 0x01010301},
+ /* DMA0 */
+ {0x0000007C, 0x01010001, 0x01010001},
+ /* DMA1 */
+ {0x00000080, 0x01010001, 0x01010001},
+ /* COMBO_PHY */
+ {0x00000084, 0x01010001, 0x01010001},
+ /* NAND_SDMA */
+ {0x00000088, 0x01010301, 0x01010301}
+ };
+
+ncore_ccu_t ccu_noc_fw_l4_sys[] = {
+ /* DMA_ECC */
+ {0x00000008, 0x01010001, 0x01010001},
+ /* EMAC0RX_ECC */
+ {0x0000000C, 0x01010001, 0x01010001},
+ /* EMAC0TX_ECC */
+ {0x00000010, 0x01010001, 0x01010001},
+ /* EMAC1RX_ECC */
+ {0x00000014, 0x01010001, 0x01010001},
+ /* EMAC1TX_ECC */
+ {0x00000018, 0x01010001, 0x01010001},
+ /* EMAC2RX_ECC */
+ {0x0000001C, 0x01010001, 0x01010001},
+ /* EMAC2TX_ECC */
+ {0x00000020, 0x01010001, 0x01010001},
+ /* NAND_ECC */
+ {0x0000002C, 0x01010001, 0x01010001},
+ /* NAND_READ_ECC */
+ {0x00000030, 0x01010001, 0x01010001},
+ /* NAND_WRITE_ECC */
+ {0x00000034, 0x01010001, 0x01010001},
+ /* OCRAM_ECC */
+ {0x00000038, 0x01010001, 0x01010001},
+ /* SDMMC_ECC */
+ {0x00000040, 0x01010001, 0x01010001},
+ /* USB0_ECC */
+ {0x00000044, 0x01010001, 0x01010001},
+ /* USB1_CACHEECC */
+ {0x00000048, 0x01010001, 0x01010001},
+ /* CLOCK_MANAGER */
+ {0x0000004C, 0x01010001, 0x01010001},
+ /* IO_MANAGER */
+ {0x00000054, 0x01010001, 0x01010001},
+ /* RESET_MANAGER */
+ {0x00000058, 0x01010001, 0x01010001},
+ /* SYSTEM_MANAGER */
+ {0x0000005C, 0x01010001, 0x01010001},
+ /* OSC0_TIMER */
+ {0x00000060, 0x01010301, 0x01010301},
+ /* OSC1_TIMER0*/
+ {0x00000064, 0x01010301, 0x01010301},
+ /* WATCHDOG0 */
+ {0x00000068, 0x01010301, 0x01010301},
+ /* WATCHDOG1 */
+ {0x0000006C, 0x01010301, 0x01010301},
+ /* WATCHDOG2 */
+ {0x00000070, 0x01010301, 0x01010301},
+ /* WATCHDOG3 */
+ {0x00000074, 0x01010301, 0x01010301},
+ /* DAP */
+ {0x00000078, 0x03010001, 0x03010001},
+ /* WATCHDOG4 */
+ {0x0000007C, 0x01010301, 0x01010301},
+ /* POWER_MANAGER */
+ {0x00000080, 0x01010001, 0x01010001},
+ /* USB1_RXECC */
+ {0x00000084, 0x01010001, 0x01010001},
+ /* USB1_TXECC */
+ {0x00000088, 0x01010001, 0x01010001},
+ /* L4_NOC_PROBES */
+ {0x00000090, 0x01010001, 0x01010001},
+ /* L4_NOC_QOS */
+ {0x00000094, 0x01010001, 0x01010001}
+ };
+
+ncore_ccu_t ccu_noc_fw_lwsoc2fpga[] = {
+ /* LWSOC2FPGA_CSR */
+ {0x00000000, 0x0FFE0301, 0x0FFE0301}
+ };
+
+ncore_ccu_t ccu_noc_fw_soc2fpga[] = {
+ /* SOC2FPGA_CSR */
+ {0x00000000, 0x0FFE0301, 0x0FFE0301}
+ };
+
+ncore_ccu_t ccu_noc_fw_tcu[] = {
+ /* TCU_CSR */
+ {0x00000000, 0x01010001, 0x01010001}
+ };
+
+uint32_t init_ncore_ccu(void)
+{
+ ncore_ccu_t *ccu_module_table = NULL;
+ uint32_t base;
+ uint32_t size;
+ uint32_t val;
+ uint32_t offset;
+ uint32_t mask;
+ uint32_t set_mask = 0U;
+ uint32_t reg = 0U;
+
+ for (int index = 0; index < ARRAY_SIZE(ncore_ccu_modules); index++) {
+ base = ncore_ccu_modules[index].base;
+ size = ncore_ccu_modules[index].size;
+
+ switch (index) {
+ case 0:
+ ccu_module_table = ccu_caiu0;
+ size = (sizeof(ccu_caiu0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 1:
+ ccu_module_table = ccu_ncaiu0;
+ size = (sizeof(ccu_ncaiu0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 2:
+ ccu_module_table = ccu_ncaiu1;
+ size = (sizeof(ccu_ncaiu1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 3:
+ ccu_module_table = ccu_ncaiu2;
+ size = (sizeof(ccu_ncaiu2) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 4:
+ ccu_module_table = ccu_ncaiu3;
+ size = (sizeof(ccu_ncaiu3) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 5:
+ ccu_module_table = ccu_dce0;
+ size = (sizeof(ccu_dce0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 6:
+ ccu_module_table = ccu_dce1;
+ size = (sizeof(ccu_dce1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 7:
+ ccu_module_table = ccu_dmi0;
+ size = (sizeof(ccu_dmi0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 8:
+ ccu_module_table = ccu_dmi1;
+ size = (sizeof(ccu_dmi1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 9:
+ ccu_module_table = ccu_noc_fw_l4_per;
+ size = (sizeof(ccu_noc_fw_l4_per) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 10:
+ ccu_module_table = ccu_noc_fw_l4_sys;
+ size = (sizeof(ccu_noc_fw_l4_sys) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 11:
+ ccu_module_table = ccu_noc_fw_lwsoc2fpga;
+ size = (sizeof(ccu_noc_fw_lwsoc2fpga) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 12:
+ ccu_module_table = ccu_noc_fw_soc2fpga;
+ size = (sizeof(ccu_noc_fw_soc2fpga) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 13:
+ ccu_module_table = ccu_noc_fw_tcu;
+ size = (sizeof(ccu_noc_fw_tcu) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ default:
+ break;
+ }
+
+ VERBOSE("CCU node base addr 0x%x, name %s, size 0x%x and module table %p\n",
+ base, ncore_ccu_modules[index].name, size, (uint32_t *)ccu_module_table);
+
+ /*
+ * First element: offset
+ * Second element: val
+ * Third element: mask
+ */
+ for (int i = 0; i < size; i++) {
+ offset = ccu_module_table[i].offset;
+ val = ccu_module_table[i].val;
+
+ /* Reads the masking bit value from the list */
+ mask = ccu_module_table[i].mask;
+
+ if (mask != 0) {
+ if (mask == 0xFFFFFFFF) {
+ reg = base + offset;
+ mmio_write_32((uintptr_t)reg, val);
+ } else {
+ /* Mask the value with the masking bits */
+ set_mask = val & mask;
+ reg = base + offset;
+
+ /* Clears and sets specific bits in the register */
+ mmio_clrsetbits_32((uintptr_t)reg, mask, set_mask);
+ }
+ }
+
+ }
+
+ }
+
+ return 0;
+}
+#endif
static coh_ss_id_t subsystem_id;
void get_subsystem_id(void)
@@ -29,6 +510,7 @@
subsystem_id.num_directory = directory;
subsystem_id.num_coh_agent = coh_agent;
}
+
uint32_t directory_init(void)
{
uint32_t dir_sf_mtn, dir_sf_en;
@@ -42,7 +524,7 @@
/* Poll Active Bit */
ret = poll_active_bit(dir);
if (ret != 0) {
- ERROR("Timeout during active bit polling");
+ ERROR("Timeout during active bit polling\n");
return -ETIMEDOUT;
}
/* Disable snoop filter, a bit per snoop filter */
@@ -51,6 +533,7 @@
}
return 0;
}
+
uint32_t coherent_agent_intfc_init(void)
{
uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
@@ -65,11 +548,12 @@
ca_type = CACHING_AGENT_TYPE(ca_id);
if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM)
mmio_setbits_32(NCORE_CCU_CSR(NCORE_CSADSER0),
- BIT(ca));
+ BIT(ca));
}
}
return 0;
}
+
uint32_t poll_active_bit(uint32_t dir)
{
uint32_t timeout = 80000;
@@ -81,6 +565,7 @@
}
return -1;
}
+
void bypass_ocram_firewall(void)
{
mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
@@ -92,6 +577,7 @@
mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
+
void ncore_enable_ocram_firewall(void)
{
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
@@ -103,6 +589,8 @@
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
+
+#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
uint32_t init_ncore_ccu(void)
{
uint32_t status;
@@ -112,6 +600,7 @@
bypass_ocram_firewall();
return status;
}
+#endif
void setup_smmu_stream_id(void)
{
@@ -130,7 +619,6 @@
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN0), TSN0);
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN1), TSN1);
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN2), TSN2);
-
/* Enabled Stream ctrl register for Agilex5 */
mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA0), ENABLE_STREAMID);
mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA1), ENABLE_STREAMID);
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
index 6cdbeb8..e00c4b7 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
@@ -9,192 +9,206 @@
#include <stdbool.h>
#include <stdint.h>
+#include "socfpga_plat_def.h"
+
#ifndef CCU_ACTIVATE_COH_FPGA
-#define CCU_ACTIVATE_COH_FPGA 0
+#define CCU_ACTIVATE_COH_FPGA 0
#endif
-// Address map for ccu init
-#define addr_CAIUIDR1 (0x1C000000)
-#define addr_GRBUNRRUCR (0x1c0ffff8)
-#define base_addr_NRS_CAIU0 (0x1c000000)
-#define base_addr_NRS_NCAIU0 (0x1c001000)
-#define base_addr_NRS_NCAIU1 (0x1c002000)
-#define base_addr_NRS_NCAIU2 (0x1c003000)
-#define base_addr_NRS_NCAIU3 (0x1c004000)
-#define base_addr_NRS_DCE0 (0x1c005000)
-#define base_addr_NRS_DCE1 (0x1c006000)
-//#define base_addr_NRS_DMI0 (0x1c007000)
-//#define base_addr_NRS_DMI1 (0x1c008000)
-//DMI
-#define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR 0x1C007300
-#define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR 0x1C008300
-//DSU
-#define ALT_CCU_DSU_CAIUAMIGR_ADDR 0x1C0003C0
-#define ALT_CCU_DSU_CAIUMIFSR_ADDR 0x1C0003C4
-#define ALT_CCU_DSU_CAIUGPRBLR1_ADDR 0x1C000414
-#define ALT_CCU_DSU_CAIUGPRBHR1_ADDR 0x1C000418
-#define ALT_CCU_DSU_CAIUGPRAR1_ADDR 0x1C000410
-#define ALT_CCU_DSU_CAIUGPRBLR2_ADDR 0x1C000424
-#define ALT_CCU_DSU_CAIUGPRBHR2_ADDR 0x1C000428
-#define ALT_CCU_DSU_CAIUGPRAR2_ADDR 0x1C000420
-#define ALT_CCU_DSU_CAIUGPRBLR4_ADDR 0x1C000444
-#define ALT_CCU_DSU_CAIUGPRBHR4_ADDR 0x1C000448
-#define ALT_CCU_DSU_CAIUGPRAR4_ADDR 0x1C000440
-#define ALT_CCU_DSU_CAIUGPRBLR5_ADDR 0x1C000454
-#define ALT_CCU_DSU_CAIUGPRBHR5_ADDR 0x1C000458
-#define ALT_CCU_DSU_CAIUGPRAR5_ADDR 0x1C000450
-#define ALT_CCU_DSU_CAIUGPRBLR6_ADDR 0x1C000464
-#define ALT_CCU_DSU_CAIUGPRBHR6_ADDR 0x1C000468
-#define ALT_CCU_DSU_CAIUGPRAR6_ADDR 0x1C000460
-#define ALT_CCU_DSU_CAIUGPRBLR7_ADDR 0x1C000474
-#define ALT_CCU_DSU_CAIUGPRBHR7_ADDR 0x1C000478
-#define ALT_CCU_DSU_CAIUGPRAR7_ADDR 0x1C000470
-#define ALT_CCU_DSU_CAIUGPRBLR8_ADDR 0x1C000484
-#define ALT_CCU_DSU_CAIUGPRBHR8_ADDR 0x1C000488
-#define ALT_CCU_DSU_CAIUGPRAR8_ADDR 0x1C000480
-#define ALT_CCU_DSU_CAIUGPRBLR9_ADDR 0x1C000494
-#define ALT_CCU_DSU_CAIUGPRBHR9_ADDR 0x1C000498
-#define ALT_CCU_DSU_CAIUGPRAR9_ADDR 0x1C000490
-#define ALT_CCU_DSU_CAIUGPRBLR10_ADDR 0x1C0004A4
-#define ALT_CCU_DSU_CAIUGPRBHR10_ADDR 0x1C0004A8
-#define ALT_CCU_DSU_CAIUGPRAR10_ADDR 0x1C0004A0
-//GIC
-#define ALT_CCU_GIC_M_XAIUAMIGR_ADDR 0x1C0023C0
-#define ALT_CCU_GIC_M_XAIUMIFSR_ADDR 0x1C0023C4
-#define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR 0x1C002414
-#define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR 0x1C002418
-#define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR 0x1C002410
-#define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR 0x1C002464
-#define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR 0x1C002468
-#define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR 0x1C002460
-#define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR 0x1C002484
-#define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR 0x1C002488
-#define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR 0x1C002480
-#define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR 0x1C0024A4
-#define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR 0x1C0024A8
-#define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR 0x1C0024A0
-//FPGA2SOC
-#define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR 0x1C0013C0
-#define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR 0x1C0013C4
-#define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR 0x1C001414
-#define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR 0x1C001418
-#define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR 0x1C001410
-#define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR 0x1C001464
-#define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR 0x1C001468
-#define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR 0x1C001460
-#define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR 0x1C001484
-#define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR 0x1C001488
-#define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR 0x1C001480
-#define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR 0x1C0014A4
-#define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR 0x1C0014A8
-#define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR 0x1C0014A0
-//TCU
-#define ALT_CCU_TCU_BASE 0x1C003000
-#define ALT_CCU_TCU_XAIUAMIGR_ADDR ALT_CCU_TCU_BASE + 0x03C0
-#define ALT_CCU_TCU_XAIUMIFSR_ADDR ALT_CCU_TCU_BASE + 0x03C4
-#define ALT_CCU_TCU_XAIUGPRBLR0_ADDR ALT_CCU_TCU_BASE + 0x0404
-#define ALT_CCU_TCU_XAIUGPRBHR0_ADDR ALT_CCU_TCU_BASE + 0x0408
-#define ALT_CCU_TCU_XAIUGPRAR0_ADDR ALT_CCU_TCU_BASE + 0x0400
-#define ALT_CCU_TCU_XAIUGPRBLR1_ADDR ALT_CCU_TCU_BASE + 0x0414
-#define ALT_CCU_TCU_XAIUGPRBHR1_ADDR ALT_CCU_TCU_BASE + 0x0418
-#define ALT_CCU_TCU_XAIUGPRAR1_ADDR ALT_CCU_TCU_BASE + 0x0410
-#define ALT_CCU_TCU_XAIUGPRBLR2_ADDR ALT_CCU_TCU_BASE + 0x0424
-#define ALT_CCU_TCU_XAIUGPRBHR2_ADDR ALT_CCU_TCU_BASE + 0x0428
-#define ALT_CCU_TCU_XAIUGPRAR2_ADDR ALT_CCU_TCU_BASE + 0x0420
-#define ALT_CCU_TCU_XAIUGPRBLR6_ADDR 0x1C003464
-#define ALT_CCU_TCU_XAIUGPRBHR6_ADDR 0x1C003468
-#define ALT_CCU_TCU_XAIUGPRAR6_ADDR 0x1C003460
-#define ALT_CCU_TCU_XAIUGPRBLR8_ADDR 0x1C003484
-#define ALT_CCU_TCU_XAIUGPRBHR8_ADDR 0x1C003488
-#define ALT_CCU_TCU_XAIUGPRAR8_ADDR 0x1C003480
-#define ALT_CCU_TCU_XAIUGPRBLR10_ADDR 0x1C0034A4
-#define ALT_CCU_TCU_XAIUGPRBHR10_ADDR 0x1C0034A8
-#define ALT_CCU_TCU_XAIUGPRAR10_ADDR 0x1C0034A0
-//IOM
-#define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR 0x1C0043C0
-#define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR 0x1C0013C4
-#define ALT_CCU_IOM_XAIUGPRBLR1_ADDR 0x1C001414
-#define ALT_CCU_IOM_XAIUGPRBHR1_ADDR 0x1C001418
-#define ALT_CCU_IOM_XAIUGPRAR1_ADDR 0x1C001410
-#define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR 0x1C001464
-#define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR 0x1C001468
-#define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR 0x1C001460
-#define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR 0x1C001484
-#define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR 0x1C001488
-#define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR 0x1C001480
-#define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR 0x1C0014A4
-#define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR 0x1C0014A8
-#define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR 0x1C0014A0
-//DCE
-#define ALT_CCU_DCE0_DCEUAMIGR_ADDR 0x1C0053C0
-#define ALT_CCU_DCE0_DCEUMIFSR_ADDR 0x1C0053C4
-#define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR 0x1C005464
-#define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR 0x1C005468
-#define ALT_CCU_DCE0_DCEUGPRAR6_ADDR 0x1C005460
-#define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR 0x1C005484
-#define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR 0x1C005488
-#define ALT_CCU_DCE0_DCEUGPRAR8_ADDR 0x1C005480
-#define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR 0x1C0054A4
-#define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR 0x1C0054A8
-#define ALT_CCU_DCE0_DCEUGPRAR10_ADDR 0x1C0054A0
-#define ALT_CCU_DCE1_DCEUAMIGR_ADDR 0x1C0063C0
-#define ALT_CCU_DCE1_DCEUMIFSR_ADDR 0x1C0063C4
-#define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR 0x1C006464
-#define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR 0x1C006468
-#define ALT_CCU_DCE1_DCEUGPRAR6_ADDR 0x1C006460
-#define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR 0x1C006484
-#define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR 0x1C006488
-#define ALT_CCU_DCE1_DCEUGPRAR8_ADDR 0x1C006480
-#define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR 0x1C0064A4
-#define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR 0x1C0064A8
-#define ALT_CCU_DCE1_DCEUGPRAR10_ADDR 0x1C0064A0
-#define offset_NRS_GPRAR0 (0x400)
-#define offset_NRS_GPRBLR0 (0x404)
-#define offset_NRS_GPRBHR0 (0x408)
-#define offset_NRS_GPRAR1 (0x410)
-#define offset_NRS_GPRBLR1 (0x414)
-#define offset_NRS_GPRBHR1 (0x418)
-#define offset_NRS_GPRAR2 (0x420)
-#define offset_NRS_GPRBLR2 (0x424)
-#define offset_NRS_GPRBHR2 (0x428)
-#define offset_NRS_GPRAR3 (0x430)
-#define offset_NRS_GPRBLR3 (0x434)
-#define offset_NRS_GPRBHR3 (0x438)
-#define offset_NRS_GPRAR4 (0x440)
-#define offset_NRS_GPRBLR4 (0x444)
-#define offset_NRS_GPRBHR4 (0x448)
-#define offset_NRS_GPRAR5 (0x450)
-#define offset_NRS_GPRBLR5 (0x454)
-#define offset_NRS_GPRBHR5 (0x458)
-#define offset_NRS_GPRAR6 (0x460)
-#define offset_NRS_GPRBLR6 (0x464)
-#define offset_NRS_GPRBHR6 (0x468)
-#define offset_NRS_GPRAR7 (0x470)
-#define offset_NRS_GPRBLR7 (0x474)
-#define offset_NRS_GPRBHR7 (0x478)
-#define offset_NRS_GPRAR8 (0x480)
-#define offset_NRS_GPRBLR8 (0x484)
-#define offset_NRS_GPRBHR8 (0x488)
-#define offset_NRS_GPRAR9 (0x490)
-#define offset_NRS_GPRBLR9 (0x494)
-#define offset_NRS_GPRBHR9 (0x498)
-#define offset_NRS_GPRAR10 (0x4a0)
-#define offset_NRS_GPRBLR10 (0x4a4)
-#define offset_NRS_GPRBHR10 (0x4a8)
-#define offset_NRS_AMIGR (0x3c0)
-#define offset_NRS_MIFSR (0x3c4)
-#define offset_NRS_DMIUSMCTCR (0x300)
-#define base_addr_DII0_PSSPERIPHS (0x10000)
-#define base_addr_DII0_LWHPS2FPGA (0x20000)
-#define base_addr_DII0_HPS2FPGA_1G (0x40000)
-#define base_addr_DII0_HPS2FPGA_15G (0x400000)
-#define base_addr_DII0_HPS2FPGA_240G (0x4000000)
-#define base_addr_DII1_MPFEREGS (0x18000)
-#define base_addr_DII2_GICREGS (0x1D000)
-#define base_addr_DII3_OCRAM (0x0)
-#define base_addr_BHR (0x0)
-#define base_addr_DMI_SDRAM_2G (0x80000)
-#define base_addr_DMI_SDRAM_30G (0x800000)
-#define base_addr_DMI_SDRAM_480G (0x8000000)
+
+/* Macros */
+#define CCU_OFFSET_VAL_MASK 3U
+#define CCU_WORD_BYTE 4U
+
+// Address Map for CCU Init
+#define addr_CAIUIDR1 SOCFPGA_CCU_NOC_REG_BASE + 0x00000
+#define addr_GRBUNRRUCR SOCFPGA_CCU_NOC_REG_BASE + 0xFFFF8
+#define base_addr_NRS_CAIU0 SOCFPGA_CCU_NOC_REG_BASE + 0x00000
+#define base_addr_NRS_NCAIU0 SOCFPGA_CCU_NOC_REG_BASE + 0x01000
+#define base_addr_NRS_NCAIU1 SOCFPGA_CCU_NOC_REG_BASE + 0x02000
+#define base_addr_NRS_NCAIU2 SOCFPGA_CCU_NOC_REG_BASE + 0x03000
+#define base_addr_NRS_NCAIU3 SOCFPGA_CCU_NOC_REG_BASE + 0x04000
+#define base_addr_NRS_DCE0 SOCFPGA_CCU_NOC_REG_BASE + 0x05000
+#define base_addr_NRS_DCE1 SOCFPGA_CCU_NOC_REG_BASE + 0x06000
+//#define base_addr_NRS_DMI0 SOCFPGA_CCU_NOC_REG_BASE + 0x07000
+//#define base_addr_NRS_DMI1 SOCFPGA_CCU_NOC_REG_BASE + 0x08000
+
+/* DMI */
+#define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x7300
+#define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x8300
+
+/* DSU */
+#define ALT_CCU_DSU_CAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3C0
+#define ALT_CCU_DSU_CAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3C4
+#define ALT_CCU_DSU_CAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x414
+#define ALT_CCU_DSU_CAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x418
+#define ALT_CCU_DSU_CAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x410
+#define ALT_CCU_DSU_CAIUGPRBLR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x424
+#define ALT_CCU_DSU_CAIUGPRBHR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x428
+#define ALT_CCU_DSU_CAIUGPRAR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x420
+#define ALT_CCU_DSU_CAIUGPRBLR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x444
+#define ALT_CCU_DSU_CAIUGPRBHR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x448
+#define ALT_CCU_DSU_CAIUGPRAR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x440
+#define ALT_CCU_DSU_CAIUGPRBLR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x454
+#define ALT_CCU_DSU_CAIUGPRBHR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x458
+#define ALT_CCU_DSU_CAIUGPRAR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x450
+#define ALT_CCU_DSU_CAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x464
+#define ALT_CCU_DSU_CAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x468
+#define ALT_CCU_DSU_CAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x460
+#define ALT_CCU_DSU_CAIUGPRBLR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x474
+#define ALT_CCU_DSU_CAIUGPRBHR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x478
+#define ALT_CCU_DSU_CAIUGPRAR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x470
+#define ALT_CCU_DSU_CAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x484
+#define ALT_CCU_DSU_CAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x488
+#define ALT_CCU_DSU_CAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x480
+#define ALT_CCU_DSU_CAIUGPRBLR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x494
+#define ALT_CCU_DSU_CAIUGPRBHR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x498
+#define ALT_CCU_DSU_CAIUGPRAR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x490
+#define ALT_CCU_DSU_CAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A4
+#define ALT_CCU_DSU_CAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A8
+#define ALT_CCU_DSU_CAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A0
+
+/* GIC */
+#define ALT_CCU_GIC_M_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x23C0
+#define ALT_CCU_GIC_M_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x23C4
+#define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2414
+#define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2418
+#define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2410
+#define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2464
+#define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2468
+#define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2460
+#define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2484
+#define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2488
+#define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2480
+#define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A4
+#define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A8
+#define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A0
+
+/* FPGA2SOC */
+#define ALT_CCU_FPGA2SOC_BASE SOCFPGA_CCU_NOC_REG_BASE + 0x1000
+#define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C0
+#define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C4
+#define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1414
+#define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1418
+#define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1410
+#define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1464
+#define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1468
+#define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1460
+#define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1484
+#define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1488
+#define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1480
+#define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A4
+#define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A8
+#define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A0
+
+/* TCU */
+#define ALT_CCU_TCU_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x33C0
+#define ALT_CCU_TCU_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x33C4
+#define ALT_CCU_TCU_XAIUGPRBLR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3404
+#define ALT_CCU_TCU_XAIUGPRBHR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3408
+#define ALT_CCU_TCU_XAIUGPRAR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3400
+#define ALT_CCU_TCU_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3414
+#define ALT_CCU_TCU_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3418
+#define ALT_CCU_TCU_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3410
+#define ALT_CCU_TCU_XAIUGPRBLR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3424
+#define ALT_CCU_TCU_XAIUGPRBHR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3428
+#define ALT_CCU_TCU_XAIUGPRAR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3420
+#define ALT_CCU_TCU_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3464
+#define ALT_CCU_TCU_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3468
+#define ALT_CCU_TCU_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3460
+#define ALT_CCU_TCU_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3484
+#define ALT_CCU_TCU_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3488
+#define ALT_CCU_TCU_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3480
+#define ALT_CCU_TCU_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A4
+#define ALT_CCU_TCU_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A8
+#define ALT_CCU_TCU_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A0
+
+/* IOM */
+#define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x43C0
+#define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C4
+#define ALT_CCU_IOM_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1414
+#define ALT_CCU_IOM_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1418
+#define ALT_CCU_IOM_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1410
+#define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1464
+#define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1468
+#define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1460
+#define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1484
+#define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1488
+#define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1480
+#define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A4
+#define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A8
+#define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A0
+
+/* DCE */
+#define ALT_CCU_DCE0_DCEUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x53C0
+#define ALT_CCU_DCE0_DCEUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x53C4
+#define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5464
+#define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5468
+#define ALT_CCU_DCE0_DCEUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5460
+#define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5484
+#define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5488
+#define ALT_CCU_DCE0_DCEUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5480
+#define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A4
+#define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A8
+#define ALT_CCU_DCE0_DCEUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A0
+#define ALT_CCU_DCE1_DCEUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x63C0
+#define ALT_CCU_DCE1_DCEUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x63C4
+#define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6464
+#define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6468
+#define ALT_CCU_DCE1_DCEUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6460
+#define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6484
+#define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6488
+#define ALT_CCU_DCE1_DCEUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6480
+#define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A4
+#define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A8
+#define ALT_CCU_DCE1_DCEUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A0
+#define offset_NRS_GPRAR0 0x400
+#define offset_NRS_GPRBLR0 0x404
+#define offset_NRS_GPRBHR0 0x408
+#define offset_NRS_GPRAR1 0x410
+#define offset_NRS_GPRBLR1 0x414
+#define offset_NRS_GPRBHR1 0x418
+#define offset_NRS_GPRAR2 0x420
+#define offset_NRS_GPRBLR2 0x424
+#define offset_NRS_GPRBHR2 0x428
+#define offset_NRS_GPRAR3 0x430
+#define offset_NRS_GPRBLR3 0x434
+#define offset_NRS_GPRBHR3 0x438
+#define offset_NRS_GPRAR4 0x440
+#define offset_NRS_GPRBLR4 0x444
+#define offset_NRS_GPRBHR4 0x448
+#define offset_NRS_GPRAR5 0x450
+#define offset_NRS_GPRBLR5 0x454
+#define offset_NRS_GPRBHR5 0x458
+#define offset_NRS_GPRAR6 0x460
+#define offset_NRS_GPRBLR6 0x464
+#define offset_NRS_GPRBHR6 0x468
+#define offset_NRS_GPRAR7 0x470
+#define offset_NRS_GPRBLR7 0x474
+#define offset_NRS_GPRBHR7 0x478
+#define offset_NRS_GPRAR8 0x480
+#define offset_NRS_GPRBLR8 0x484
+#define offset_NRS_GPRBHR8 0x488
+#define offset_NRS_GPRAR9 0x490
+#define offset_NRS_GPRBLR9 0x494
+#define offset_NRS_GPRBHR9 0x498
+#define offset_NRS_GPRAR10 0x4A0
+#define offset_NRS_GPRBLR10 0x4A4
+#define offset_NRS_GPRBHR10 0x4A8
+#define offset_NRS_AMIGR 0x3C0
+#define offset_NRS_MIFSR 0x3C4
+#define offset_NRS_DMIUSMCTCR 0x300
+#define base_addr_DII0_PSSPERIPHS 0x10000
+#define base_addr_DII0_LWHPS2FPGA 0x20000
+#define base_addr_DII0_HPS2FPGA_1G 0x40000
+#define base_addr_DII0_HPS2FPGA_15G 0x400000
+#define base_addr_DII0_HPS2FPGA_240G 0x4000000
+#define base_addr_DII1_MPFEREGS 0x18000
+#define base_addr_DII2_GICREGS 0x1D000
+#define base_addr_DII3_OCRAM 0x0
+#define base_addr_BHR 0x0
+#define base_addr_DMI_SDRAM_2G 0x80000
+#define base_addr_DMI_SDRAM_30G 0x800000
+#define base_addr_DMI_SDRAM_480G 0x8000000
// ((0x0<<9) | (0xf<<20) | (0x1<<30) | (0x1<<31))
#define wr_DII0_PSSPERIPHS 0xC0F00000
// ((0x0<<9) | (0x11<<20) | (0x1<<30) | (0x1<<31))
@@ -228,54 +242,46 @@
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31))
#define wr_DMI_SDRAM_30G 0x81700006
// ((0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31))
-#define wr_DMI_SDRAM_240G_ORDERED 0x81a00000
+#define wr_DMI_SDRAM_240G_ORDERED 0x81A00000
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31))
-#define wr_DMI_SDRAM_240G 0x81a00006
+#define wr_DMI_SDRAM_240G 0x81A00006
// ((0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31))
-#define wr_DMI_SDRAM_480G_ORDERED 0x81b00000
+#define wr_DMI_SDRAM_480G_ORDERED 0x81B00000
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31))
-#define wr_DMI_SDRAM_480G 0x81b00006
+#define wr_DMI_SDRAM_480G 0x81B00006
typedef enum CCU_REGION_SECURITY_e {
- //
- // Allow secure accesses only.
- //
+ /* Allow secure accesses only. */
CCU_REGION_SECURITY_SECURE_ONLY,
- //
- // Allow non-secure accesses only.
- //
+
+ /* Allow non-secure accesses only. */
CCU_REGION_SECURITY_NON_SECURE_ONLY,
- //
- // Allow accesses of any security state.
- //
+
+ /* Allow accesses of any security state. */
CCU_REGION_SECURITY_DONT_CARE
} CCU_REGION_SECURITY_t;
+
typedef enum CCU_REGION_PRIVILEGE_e {
- //
- // Allow privileged accesses only.
- //
+ /* Allow privileged accesses only. */
CCU_REGION_PRIVILEGE_PRIVILEGED_ONLY,
- //
- // Allow unprivileged accesses only.
- //
+ /* Allow unprivileged accesses only. */
CCU_REGION_PRIVILEGE_NON_PRIVILEGED_ONLY,
- //
- // Allow accesses of any privilege.
- //
+ /* Allow accesses of any privilege. */
CCU_REGION_PRIVILEGE_DONT_CARE
} CCU_REGION_PRIVILEGE_t;
-//
-// Initializes the CCU by enabling all regions except RAM 1 - 5.
-// This is needed because of an RTL change around 2016.02.24.
-//
-// Runtime measurement:
-// - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32)
-// - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf)
-//
-// Runtime history:
-// - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32)
-// - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf)
-//
+
+/*
+ * Initializes the CCU by enabling all regions except RAM 1 - 5.
+ * This is needed because of an RTL change around 2016.02.24.
+ *
+ * Runtime measurement:
+ * - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32)
+ * - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf)
+ *
+ * Runtime history:
+ * - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32)
+ * - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf)
+ */
int ccu_hps_init(void);
typedef enum ccu_hps_ram_region_e {
@@ -287,19 +293,21 @@
ccu_hps_ram_region_ramspace5 = 5,
} ccu_hps_ram_region_t;
-// Disables a RAM (OCRAM) region with the given ID.
+/* Disables a RAM (OCRAM) region with the given ID. */
int ccu_hps_ram_region_disable(int id);
-// Enables a RAM (OCRAM) region with the given ID.
+/* Enables a RAM (OCRAM) region with the given ID. */
int ccu_hps_ram_region_enable(int id);
-// Attempts to remap a RAM (OCRAM) region with the given ID to span the given
-// start and end address. It also assigns the security and privilege policy.
-// Regions must be a power-of-two size with a minimum size of 64B.
+/*
+ * Attempts to remap a RAM (OCRAM) region with the given ID to span the given
+ * start and end address. It also assigns the security and privilege policy.
+ * Regions must be a power-of-two size with a minimum size of 64B.
+ */
int ccu_hps_ram_region_remap(int id, uintptr_t start, uintptr_t end,
-CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
+ CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
-// Verifies that all enabled RAM (OCRAM) regions does not overlap.
+/* Verifies that all enabled RAM (OCRAM) regions does not overlap. */
int ccu_hps_ram_validate(void);
typedef enum ccu_hps_mem_region_e {
@@ -312,19 +320,21 @@
ccu_hps_mem_region_memspace1e = 6,
} ccu_hps_mem_region_t;
-// Disables mem0 (DDR) region with the given ID.
+/* Disables mem0 (DDR) region with the given ID. */
int ccu_hps_mem0_region_disable(int id);
-// Enables mem0 (DDR) region with the given ID.
+/* Enables mem0 (DDR) region with the given ID. */
int ccu_hps_mem0_region_enable(int id);
-// Attempts to remap mem0 (DDR) region with the given ID to span the given
-// start and end address. It also assigns the security nad privlege policy.
-// Regions must be a power-of-two in size with a minimum size of 64B.
+/*
+ * Attempts to remap mem0 (DDR) region with the given ID to span the given
+ * start and end address. It also assigns the security nad privlege policy.
+ * Regions must be a power-of-two in size with a minimum size of 64B.
+ */
int ccu_hps_mem0_region_remap(int id, uintptr_t start, uintptr_t end,
-CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
+ CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
-// Verifies that all enabled mem0 (DDR) regions does not overlap.
+/* Verifies that all enabled mem0 (DDR) regions does not overlap. */
int ccu_hps_mem0_validate(void);
typedef enum ccu_hps_ios_region_e {
@@ -342,14 +352,23 @@
ccu_hps_ios_region_iospace2c = 11,
} ccu_hps_ios_region_t;
-// Disables the IOS (IO Slave) region with the given ID.
+/* Disables the IOS (IO Slave) region with the given ID. */
int ccu_hps_ios_region_disable(int id);
-// Enables the IOS (IO Slave) region with the given ID.
+/* Enables the IOS (IO Slave) region with the given ID. */
int ccu_hps_ios_region_enable(int id);
+typedef struct ncore_ccu_reg {
+ char name[50];
+ uint32_t base;
+ uint32_t size;
+ } ncore_ccu_reg_t;
-#define NCORE_CCU_OFFSET 0xf7000000
+typedef struct ncore_ccu {
+ uint32_t offset;
+ uint32_t val;
+ uint32_t mask;
+ } ncore_ccu_t;
/* Coherent Sub-System Address Map */
#define NCORE_CAIU_OFFSET 0x00000
@@ -358,43 +377,49 @@
#define NCORE_NCBU_SIZE 0x01000
#define NCORE_DIRU_OFFSET 0x80000
#define NCORE_DIRU_SIZE 0x01000
-#define NCORE_CMIU_OFFSET 0xc0000
+#define NCORE_CMIU_OFFSET 0xC0000
#define NCORE_CMIU_SIZE 0x01000
-#define NCORE_CSR_OFFSET 0xff000
+#define NCORE_CSR_OFFSET 0xFF000
#define NCORE_CSADSERO 0x00040
-#define NCORE_CSUIDR 0x00ff8
-#define NCORE_CSIDR 0x00ffc
+#define NCORE_CSUIDR 0x00FF8
+#define NCORE_CSIDR 0x00FFC
+
/* Directory Unit Register Map */
#define NCORE_DIRUSFER 0x00010
#define NCORE_DIRUMRHER 0x00070
#define NCORE_DIRUSFMCR 0x00080
#define NCORE_DIRUSFMAR 0x00084
+
/* Coherent Agent Interface Unit Register Map */
-#define NCORE_CAIUIDR 0x00ffc
+#define NCORE_CAIUIDR 0x00FFC
+
/* Snoop Enable Register */
#define NCORE_DIRUCASER0 0x00040
#define NCORE_DIRUCASER1 0x00044
#define NCORE_DIRUCASER2 0x00048
-#define NCORE_DIRUCASER3 0x0004c
+#define NCORE_DIRUCASER3 0x0004C
#define NCORE_CSADSER0 0x00040
#define NCORE_CSADSER1 0x00044
#define NCORE_CSADSER2 0x00048
-#define NCORE_CSADSER3 0x0004c
+#define NCORE_CSADSER3 0x0004C
+
/* Protocols Definition */
#define ACE_W_DVM 0
#define ACE_L_W_DVM 1
#define ACE_WO_DVM 2
#define ACE_L_WO_DVM 3
-/* Bypass OC Ram Firewall */
+
+/* Bypass OCRAM Firewall */
#define NCORE_FW_OCRAM_BLK_BASE 0x100200
#define NCORE_FW_OCRAM_BLK_CGF1 0x04
#define NCORE_FW_OCRAM_BLK_CGF2 0x08
-#define NCORE_FW_OCRAM_BLK_CGF3 0x0c
+#define NCORE_FW_OCRAM_BLK_CGF3 0x0C
#define NCORE_FW_OCRAM_BLK_CGF4 0x10
#define OCRAM_PRIVILEGED_MASK BIT(29)
#define OCRAM_SECURE_MASK BIT(30)
+
/* Macros */
-#define NCORE_CCU_REG(base) (NCORE_CCU_OFFSET + (base))
+#define NCORE_CCU_REG(base) (SOCFPGA_CCU_NOC_REG_BASE + (base))
#define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\
+ (reg))
#define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\
@@ -407,14 +432,14 @@
+ NCORE_CAIU_SIZE * (x))
#define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\
+ (reg))
-#define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24)
-#define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16)
-#define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8)
-#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0)
-#define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18)
+#define CSUIDR_NUM_CMI(x) (((x) & 0x3F000000) >> 24)
+#define CSUIDR_NUM_DIR(x) (((x) & 0x003F0000) >> 16)
+#define CSUIDR_NUM_NCB(x) (((x) & 0x00003F00) >> 8)
+#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007F) >> 0)
+#define CSIDR_NUM_SF(x) (((x) & 0x007C0000) >> 18)
#define SNOOP_FILTER_ID(x) (((x) << 16))
#define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15)
-#define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16)
+#define CACHING_AGENT_TYPE(x) (((x) & 0xF0000) >> 16)
typedef struct coh_ss_id {
uint8_t num_coh_mem;
diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
index 434cd88..6265928 100644
--- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
+++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
@@ -70,6 +70,9 @@
uint64_t x3, uint64_t x4, const void *cookie,
void *handle, uint64_t flags)
{
+ (void) x4;
+ (void) flags;
+ (void) cookie;
int32_t ret;
uint32_t ipi_local_id;
uint32_t ipi_remote_id;
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index 193c5dc..861c5b3 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -79,6 +79,10 @@
static uint64_t cpu_pwrdwn_req_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
+ (void)id;
+ (void)flags;
+ (void)handle;
+ (void)cookie;
uint32_t cpu_id = plat_my_core_pos();
VERBOSE("Powering down CPU %d\n", cpu_id);
@@ -123,6 +127,9 @@
static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
void *cookie)
{
+ (void)flags;
+ (void)handle;
+ (void)cookie;
uint32_t payload[4] = {0};
enum pm_ret_status ret;
int ipi_status, i;
@@ -546,6 +553,7 @@
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle, uint64_t flags)
{
+ (void)cookie;
uintptr_t ret;
uint32_t pm_arg[PAYLOAD_ARG_CNT] = {0};
uint32_t security_flag = NON_SECURE_FLAG;
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 57377a9..58589ad 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -69,6 +69,10 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ (void)arg0;
+ (void)arg1;
+ (void)arg2;
+ (void)arg3;
uint64_t tfa_handoff_addr;
uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE;
enum pm_ret_status ret_status;
@@ -171,6 +175,7 @@
static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
+ (void)id;
uint32_t intr_id;
uint32_t i;
interrupt_type_handler_t handler = NULL;
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index 5af2b1d..ebde49f 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -82,6 +82,11 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ (void)arg0;
+ (void)arg1;
+ (void)arg2;
+ (void)arg3;
+
#if !(TFA_NO_PM)
uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0};
uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE;
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 50d4240..ede3a21 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -72,6 +72,10 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ (void)arg0;
+ (void)arg1;
+ (void)arg2;
+ (void)arg3;
uint64_t tfa_handoff_addr;
setup_console();
diff --git a/plat/xilinx/zynqmp/custom_sip_svc.c b/plat/xilinx/zynqmp/custom_sip_svc.c
index b9664af..c61c92c 100644
--- a/plat/xilinx/zynqmp/custom_sip_svc.c
+++ b/plat/xilinx/zynqmp/custom_sip_svc.c
@@ -12,6 +12,12 @@
uint64_t x3, uint64_t x4, void *cookie,
void *handle, uint64_t flags)
{
+ (void)x1;
+ (void)x2;
+ (void)x3;
+ (void)x4;
+ (void)cookie;
+ (void)flags;
WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 66f011a..daf3e61 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -268,6 +268,7 @@
uint32_t state,
uintptr_t address)
{
+ (void)nid;
uint32_t payload[PAYLOAD_ARG_CNT];
uint32_t cpuid = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpuid);
@@ -1514,6 +1515,7 @@
void pm_query_data(enum pm_query_ids qid, uint32_t arg1, uint32_t arg2,
uint32_t arg3, uint32_t *data)
{
+ (void)arg3;
switch (qid) {
case PM_QID_CLOCK_GET_NAME:
pm_clock_get_name(arg1, (char *)data);
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index bf17ea4..65b2426 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -281,6 +281,9 @@
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle, uint64_t flags)
{
+ (void)x4;
+ (void)cookie;
+ (void)flags;
enum pm_ret_status ret;
uint32_t payload[PAYLOAD_ARG_CNT];