feat(nxp-clk): add objects needed for DDR clock
The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.
Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
index 32287cf..d34dc22 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
@@ -99,4 +99,8 @@
#define S32CC_CLK_DDR_PLL_MUX S32CC_ARCH_CLK(18)
#define S32CC_CLK_DDR_PLL_VCO S32CC_ARCH_CLK(19)
+/* DDR clock */
+#define S32CC_CLK_MC_CGM5_MUX0 S32CC_ARCH_CLK(20)
+#define S32CC_CLK_DDR S32CC_ARCH_CLK(21)
+
#endif /* S32CC_CLK_IDS_H */
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
index 26d2782..4837f79 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
@@ -37,6 +37,7 @@
S32CC_CGM0,
S32CC_CGM1,
S32CC_DDR_PLL,
+ S32CC_CGM5,
};
struct s32cc_clk_obj {