Merge changes from topic "hm/errata-fw" into integration
* changes:
refactor(cpus): add Cortex-A17 errata framework information
fix(fvp): resolve broken workaround reference
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index 6207066..e3a7ebf 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -24,3 +24,8 @@
sphinx:
configuration: docs/conf.py
+
+# Auxiliary formats to export to (in addition to the default HTML output).
+formats:
+ - pdf
+
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 851ac47..7336b91 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -152,92 +152,6 @@
b handle_lower_el_sync_ea
.endm
-
- /* ---------------------------------------------------------------------
- * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
- * interrupts.
- * ---------------------------------------------------------------------
- */
- .macro handle_interrupt_exception label
-
- /*
- * Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * Also save PMCR_EL0 and set the PSTATE to a known state.
- */
- bl prepare_el3_entry
-
-#if ENABLE_PAUTH
- /* Load and program APIAKey firmware key */
- bl pauth_load_bl31_apiakey
-#endif
-
- /* Save the EL3 system registers needed to return from this exception */
- mrs x0, spsr_el3
- mrs x1, elr_el3
- stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
-
- /* Switch to the runtime stack i.e. SP_EL0 */
- ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
- mov x20, sp
- msr spsel, #MODE_SP_EL0
- mov sp, x2
-
- /*
- * Find out whether this is a valid interrupt type.
- * If the interrupt controller reports a spurious interrupt then return
- * to where we came from.
- */
- bl plat_ic_get_pending_interrupt_type
- cmp x0, #INTR_TYPE_INVAL
- b.eq interrupt_exit_\label
-
- /*
- * Get the registered handler for this interrupt type.
- * A NULL return value could be 'cause of the following conditions:
- *
- * a. An interrupt of a type was routed correctly but a handler for its
- * type was not registered.
- *
- * b. An interrupt of a type was not routed correctly so a handler for
- * its type was not registered.
- *
- * c. An interrupt of a type was routed correctly to EL3, but was
- * deasserted before its pending state could be read. Another
- * interrupt of a different type pended at the same time and its
- * type was reported as pending instead. However, a handler for this
- * type was not registered.
- *
- * a. and b. can only happen due to a programming error. The
- * occurrence of c. could be beyond the control of Trusted Firmware.
- * It makes sense to return from this exception instead of reporting an
- * error.
- */
- bl get_interrupt_type_handler
- cbz x0, interrupt_exit_\label
- mov x21, x0
-
- mov x0, #INTR_ID_UNAVAILABLE
-
- /* Set the current security state in the 'flags' parameter */
- mrs x2, scr_el3
- ubfx x1, x2, #0, #1
-
- /* Restore the reference to the 'handle' i.e. SP_EL3 */
- mov x2, x20
-
- /* x3 will point to a cookie (not used now) */
- mov x3, xzr
-
- /* Call the interrupt type handler */
- blr x21
-
-interrupt_exit_\label:
- /* Return from exception, possibly in a different security state */
- b el3_exit
-
- .endm
-
-
vector_base runtime_exceptions
/* ---------------------------------------------------------------------
@@ -342,14 +256,14 @@
save_x30
apply_at_speculative_wa
check_and_unmask_ea
- handle_interrupt_exception irq_aarch64
+ b handle_interrupt_exception
end_vector_entry irq_aarch64
vector_entry fiq_aarch64
save_x30
apply_at_speculative_wa
check_and_unmask_ea
- handle_interrupt_exception fiq_aarch64
+ b handle_interrupt_exception
end_vector_entry fiq_aarch64
vector_entry serror_aarch64
@@ -385,14 +299,14 @@
save_x30
apply_at_speculative_wa
check_and_unmask_ea
- handle_interrupt_exception irq_aarch32
+ b handle_interrupt_exception
end_vector_entry irq_aarch32
vector_entry fiq_aarch32
save_x30
apply_at_speculative_wa
check_and_unmask_ea
- handle_interrupt_exception fiq_aarch32
+ b handle_interrupt_exception
end_vector_entry fiq_aarch32
vector_entry serror_aarch32
@@ -611,6 +525,90 @@
endfunc sync_exception_handler
/* ---------------------------------------------------------------------
+ * This function handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
+ * interrupts.
+ *
+ * Note that x30 has been explicitly saved and can be used here
+ * ---------------------------------------------------------------------
+ */
+func handle_interrupt_exception
+ /*
+ * Save general purpose and ARMv8.3-PAuth registers (if enabled).
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
+ */
+ bl prepare_el3_entry
+
+#if ENABLE_PAUTH
+ /* Load and program APIAKey firmware key */
+ bl pauth_load_bl31_apiakey
+#endif
+
+ /* Save the EL3 system registers needed to return from this exception */
+ mrs x0, spsr_el3
+ mrs x1, elr_el3
+ stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
+
+ /* Switch to the runtime stack i.e. SP_EL0 */
+ ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
+ mov x20, sp
+ msr spsel, #MODE_SP_EL0
+ mov sp, x2
+
+ /*
+ * Find out whether this is a valid interrupt type.
+ * If the interrupt controller reports a spurious interrupt then return
+ * to where we came from.
+ */
+ bl plat_ic_get_pending_interrupt_type
+ cmp x0, #INTR_TYPE_INVAL
+ b.eq interrupt_exit
+
+ /*
+ * Get the registered handler for this interrupt type.
+ * A NULL return value could be 'cause of the following conditions:
+ *
+ * a. An interrupt of a type was routed correctly but a handler for its
+ * type was not registered.
+ *
+ * b. An interrupt of a type was not routed correctly so a handler for
+ * its type was not registered.
+ *
+ * c. An interrupt of a type was routed correctly to EL3, but was
+ * deasserted before its pending state could be read. Another
+ * interrupt of a different type pended at the same time and its
+ * type was reported as pending instead. However, a handler for this
+ * type was not registered.
+ *
+ * a. and b. can only happen due to a programming error. The
+ * occurrence of c. could be beyond the control of Trusted Firmware.
+ * It makes sense to return from this exception instead of reporting an
+ * error.
+ */
+ bl get_interrupt_type_handler
+ cbz x0, interrupt_exit
+ mov x21, x0
+
+ mov x0, #INTR_ID_UNAVAILABLE
+
+ /* Set the current security state in the 'flags' parameter */
+ mrs x2, scr_el3
+ ubfx x1, x2, #0, #1
+
+ /* Restore the reference to the 'handle' i.e. SP_EL3 */
+ mov x2, x20
+
+ /* x3 will point to a cookie (not used now) */
+ mov x3, xzr
+
+ /* Call the interrupt type handler */
+ blr x21
+
+interrupt_exit:
+ /* Return from exception, possibly in a different security state */
+ b el3_exit
+endfunc handle_interrupt_exception
+
+ /* ---------------------------------------------------------------------
* The following code handles exceptions caused by BRK instructions.
* Following a BRK instruction, the only real valid cause of action is
* to print some information and panic, as the code that caused it is
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index ecbefdd..df0cfc0 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -527,6 +527,10 @@
IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed
in r0p2.
+- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2
+ CPU, this affects all configurations. This needs to be enabled for revisions
+ r0p0 and r0p1. It has been fixed in r0p2.
+
For Cortex-A710, the following errata build flags are defined :
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 3d648c4..879ddda 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2636,19 +2636,17 @@
architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included
and unconditionally enabled by TF-A build system.
-- Passed to compiler via "-march" option to generate binary target : Tell the
- compiler to emit instructions upto ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR``
+- ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` are passed to a march.mk build utility
+ this will try to come up with an appropriate -march value to be passed to compiler
+ by probing the compiler and checking what's supported by the compiler and what's best
+ that can be used. But if platform provides a ``MARCH_DIRECTIVE`` then it will used
+ directly and compiler probing will be skipped.
The build system requires that the platform provides a valid numeric value based on
CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture.
Subsequent Arm Architecture versions also support extensions which were introduced
in previous versions.
-**TO-DO** : Its planned to decouple the two functionalities and introduce a new macro
-for compiler usage. The requirement for this decoupling arises becasue TF-A code
-always provides support for the latest and greatest architecture features but this
-is not the case for the target compiler.
-
.. seealso:: :ref:`Build Options`
For details on the Architecture Extension and available features, please refer
@@ -2738,7 +2736,7 @@
.. code:: make
- MARCH_DIRECTIVE := -mach=armv7-a
+ MARCH_DIRECTIVE := -march=armv7-a
Code Structure
--------------
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 47fd450..c410a8e 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -727,6 +727,13 @@
This option defaults to 0.
+- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build
+ options to the compiler. An example usage:
+
+ .. code:: make
+
+ MARCH_DIRECTIVE := -march=armv8.5-a
+
- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
specifies the file that contains the Non-Trusted World private key in PEM
format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index 61b5763..9f996bd 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -194,10 +194,12 @@
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dpu_aclk>;
- hdmi-transmitter@70 {
+ hdmi_tx: hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
video-ports = <0x234501>;
+ #sound-dai-cells = <0>;
+ audio-ports = <2 0x03>;
port {
tda998x_0_input: endpoint {
remote-endpoint = <&dp_pl0_out0>;
@@ -255,6 +257,52 @@
};
};
};
+
+ iofpga_i2s: xlnx-i2s@1c150000 {
+ #sound-dai-cells = <0>;
+ compatible = "xlnx,i2s-transmitter-1.0";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1c150000 0x0 0x10000>;
+ xlnx,dwidth = <0x18>;
+ xlnx,num-channels = <1>;
+ };
+
+ audio_formatter: audio-formatter@1c100000 {
+ compatible = "xlnx,audio-formatter-1.0";
+ reg = <0x0 0x1c000000 0x0 0x10000>;
+ #sound-dai-cells = <0>;
+ interrupt-names = "irq_mm2s";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "s_axi_lite_aclk", "aud_mclk", "m_axis_mm2s_aclk";
+ clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&audio_master>;
+ simple-audio-card,frame-master = <&audio_master>;
+ audio_master: simple-audio-card,cpu {
+ sound-dai = <&iofpga_i2s>;
+ clocks = <&i2s_audclk>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi_tx>;
+ };
+
+ simple-audio-card,plat {
+ sound-dai = <&audio_formatter>;
+ };
+ };
+
+ i2s_audclk: i2s_audclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ clock-output-names = "iofpga:i2s_audclk";
+ };
};
&gic {
diff --git a/fdts/morello.dtsi b/fdts/morello.dtsi
index 20640c5..7f39d75 100644
--- a/fdts/morello.dtsi
+++ b/fdts/morello.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,6 +88,13 @@
clock-output-names = "apb_pclk";
};
+ soc_refclk85mhz: refclk85mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <85000000>;
+ clock-output-names = "iofpga:aclk";
+ };
+
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index dd2c0a6..da4ee7f 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -197,11 +197,11 @@
#define SDCR_SPD_LEGACY U(0x0)
#define SDCR_SPD_DISABLE U(0x2)
#define SDCR_SPD_ENABLE U(0x3)
-#define SDCR_SCCD_BIT (U(1) << 23)
-#define SDCR_TTRF_BIT (U(1) << 19)
#define SDCR_SPME_BIT (U(1) << 17)
-#define SDCR_RESET_VAL U(0x0)
+#define SDCR_TTRF_BIT (U(1) << 19)
+#define SDCR_SCCD_BIT (U(1) << 23)
#define SDCR_MTPME_BIT (U(1) << 28)
+#define SDCR_RESET_VAL U(0x0)
/* HSCTLR definitions */
#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 698fad4..b19e8af 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -596,7 +596,7 @@
#define MDCR_SBRBE_MASK ULL(0x3)
#define MDCR_NSTB(x) ((x) << 24)
#define MDCR_NSTB_EL1 ULL(0x3)
-#define MDCR_NSTBE (ULL(1) << 26)
+#define MDCR_NSTBE_BIT (ULL(1) << 26)
#define MDCR_MTPME_BIT (ULL(1) << 28)
#define MDCR_TDCC_BIT (ULL(1) << 27)
#define MDCR_SCCD_BIT (ULL(1) << 23)
@@ -612,6 +612,7 @@
#define MDCR_SPD32_ENABLE ULL(0x3)
#define MDCR_NSPB(x) ((x) << 12)
#define MDCR_NSPB_EL1 ULL(0x3)
+#define MDCR_NSPBE_BIT (ULL(1) << 11)
#define MDCR_TDOSA_BIT (ULL(1) << 10)
#define MDCR_TDA_BIT (ULL(1) << 9)
#define MDCR_TPM_BIT (ULL(1) << 6)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 6360461..fa9310e 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -115,33 +115,11 @@
* MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
* debug registers, other than those registers that are controlled by
* MDCR_EL3.TDOSA.
- *
- * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
- * accesses to all Performance Monitors registers do not trap to EL3.
- *
- * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer
- * owning security state is Secure state. If FEAT_TRBE is implemented,
- * accesses to Trace Buffer control registers at EL2 and EL1 in any
- * security state generates trap exceptions to EL3.
- * If FEAT_TRBE is not implemented, these bits are RES0.
- *
- * MDCR_EL3.TTRF: Set to one so that access to trace filter control
- * registers in non-monitor mode generate EL3 trap exception,
- * unless the access generates a higher priority exception when trace
- * filter control(FEAT_TRF) is implemented.
- * When FEAT_TRF is not implemented, this bit is RES0.
- * ---------------------------------------------------------------------
*/
mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
MDCR_SPD32(MDCR_SPD32_DISABLE)) & \
- ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT | \
- MDCR_NSTB(MDCR_NSTB_EL1) | MDCR_NSTBE | MDCR_TTRF_BIT))
+ ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT))
- mrs x1, id_aa64dfr0_el1
- ubfx x1, x1, #ID_AA64DFR0_TRACEFILT_SHIFT, #ID_AA64DFR0_TRACEFILT_LENGTH
- cbz x1, 1f
- orr x0, x0, #MDCR_TTRF_BIT
-1:
msr mdcr_el3, x0
/* ---------------------------------------------------------------------
@@ -158,15 +136,6 @@
* CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1,
* CPTR_EL2, CPACR, or HCPTR do not trap to EL3.
*
- * CPTR_EL3.TTA: Set to one so that accesses to the trace system
- * registers trap to EL3 from all exception levels and security
- * states when system register trace is implemented.
- * When system register trace is not implemented, this bit is RES0 and
- * hence set to zero.
- *
- * CPTR_EL3.TTA: Set to zero so that System register accesses to the
- * trace registers do not trap to EL3.
- *
* CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
* by Advanced SIMD, floating-point or SVE instructions (if implemented)
* do not trap to EL3.
@@ -181,12 +150,7 @@
* to EL3 by default.
*/
- mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
- mrs x1, id_aa64dfr0_el1
- ubfx x1, x1, #ID_AA64DFR0_TRACEVER_SHIFT, #ID_AA64DFR0_TRACEVER_LENGTH
- cbz x1, 1f
- orr x0, x0, #TTA_BIT
-1:
+ mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT))
msr cptr_el3, x0
/*
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h
index 6af85a8..337aac3 100644
--- a/include/lib/cpus/aarch64/cortex_a510.h
+++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,11 +14,13 @@
******************************************************************************/
#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
+#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1)
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2)
-#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38)
+#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38)
+#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3)
/*******************************************************************************
* CPU Power Control register specific definitions
@@ -30,6 +32,12 @@
* Complex auxiliary control register specific definitions
******************************************************************************/
#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25)
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2)
/*******************************************************************************
* Auxiliary control register specific definitions
@@ -37,5 +45,11 @@
#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17)
#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1)
-#endif /* CORTEX_A510_H */
\ No newline at end of file
+#endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 404b7f9..d945d7c 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -444,6 +444,19 @@
.endm
/*
+ * BFI : Inserts bitfield into a system register.
+ *
+ * BFI{cond} Rd, Rn, #lsb, #width
+ */
+.macro sysreg_bitfield_insert _reg:req, _src:req, _lsb:req, _width:req
+ /* Source value for BFI */
+ mov x1, #\_src
+ mrs x0, \_reg
+ bfi x0, x1, #\_lsb, #\_width
+ msr \_reg, x0
+.endm
+
+/*
* Apply erratum
*
* _cpu:
diff --git a/include/lib/extensions/sys_reg_trace.h b/include/lib/extensions/sys_reg_trace.h
index d9f7f1b..beda88a 100644
--- a/include/lib/extensions/sys_reg_trace.h
+++ b/include/lib/extensions/sys_reg_trace.h
@@ -13,6 +13,7 @@
#if __aarch64__
void sys_reg_trace_enable(cpu_context_t *context);
+void sys_reg_trace_disable(cpu_context_t *context);
void sys_reg_trace_init_el2_unused(void);
#else
void sys_reg_trace_init_el3(void);
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S
index 6e3ff81..89b238a 100644
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,6 +44,8 @@
bx lr
endfunc check_errata_819472
+add_erratum_entry cortex_a53, ERRATUM(819472), ERRATA_A53_819472
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A53 Errata #824069.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -59,6 +61,8 @@
bx lr
endfunc check_errata_824069
+add_erratum_entry cortex_a53, ERRATUM(824069), ERRATA_A53_824069
+
/* --------------------------------------------------
* Errata Workaround for Cortex A53 Errata #826319.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -89,6 +93,8 @@
b cpu_rev_var_ls
endfunc check_errata_826319
+add_erratum_entry cortex_a53, ERRATUM(826319), ERRATA_A53_826319
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A53 Errata #827319.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -104,6 +110,8 @@
bx lr
endfunc check_errata_827319
+add_erratum_entry cortex_a53, ERRATUM(827319), ERRATA_A53_827319
+
/* ---------------------------------------------------------------------
* Disable the cache non-temporal hint.
*
@@ -142,6 +150,9 @@
b cpu_rev_var_ls
endfunc check_errata_disable_non_temporal_hint
+add_erratum_entry cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT, \
+ disable_non_temporal_hint
+
/* --------------------------------------------------
* Errata Workaround for Cortex A53 Errata #855873.
*
@@ -176,6 +187,8 @@
b cpu_rev_var_hs
endfunc check_errata_855873
+add_erratum_entry cortex_a53, ERRATUM(855873), ERRATA_A53_855873
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A53.
* Shall clobber: r0-r6
@@ -284,31 +297,7 @@
b cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A53. Must follow AAPCS.
- */
-func cortex_a53_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A53_819472, cortex_a53, 819472
- report_errata ERRATA_A53_824069, cortex_a53, 824069
- report_errata ERRATA_A53_826319, cortex_a53, 826319
- report_errata ERRATA_A53_827319, cortex_a53, 827319
- report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
- report_errata ERRATA_A53_855873, cortex_a53, 855873
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a53_errata_report
-#endif
+errata_report_shim cortex_a53
declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
cortex_a53_reset_func, \
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index e10ebb0..6fce24e 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -21,110 +21,15 @@
#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #1922240.
- * This applies only to revision r0p0 (fixed in r0p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_1922240_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1922240
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240
/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- mov x1, #3
- bfi x0, x1, #10, #2
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_1922240_wa
-
-func check_errata_1922240
- /* Applies to r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1922240
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2288014.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0. (fixed in r1p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2288014_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2288014
- cbz x0, 1f
-
- /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- mov x1, #1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2288014_wa
-
-func check_errata_2288014
- /* Applies to r1p0 and below */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2288014
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2042739.
- * This applies only to revisions r0p0, r0p1 and r0p2.
- * (fixed in r0p3)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2042739_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2042739
- cbz x0, 1f
-
- /* Apply the workaround by disabling ReadPreferUnique. */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2042739_wa
+ sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \
+ CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(1922240)
-func check_errata_2042739
- /* Applies to revisions r0p0 - r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2042739
+check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2041909.
- * This applies only to revision r0p2 and it is fixed in
- * r0p3. The issue is also present in r0p0 and r0p1 but
- * there is no workaround in those revisions.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x2, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2041909_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2041909
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909
/* Apply workaround */
mov x0, xzr
msr S3_6_C15_C4_0, x0
@@ -140,39 +45,55 @@
mov x0, #0x3F1
movk x0, #0x110, lsl #16
msr S3_6_C15_C4_1, x0
- isb
+workaround_reset_end cortex_a510, ERRATUM(2041909)
+
+check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2)
+
+workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739
+ /* Apply the workaround by disabling ReadPreferUnique. */
+ sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \
+ CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2042739)
-1:
- ret x17
-endfunc errata_cortex_a510_2041909_wa
+check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
-func check_errata_2041909
- /* Applies only to revision r0p2 */
- mov x1, #0x02
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2041909
+workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
+ /*
+ * Force L2 allocation of transient lines by setting
+ * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
+ */
+ mrs x0, CORTEX_A510_CPUECTLR_EL1
+ mov x1, #1
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
+ msr CORTEX_A510_CPUECTLR_EL1, x0
+workaround_reset_end cortex_a510, ERRATUM(2172148)
+
+check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950
+ /* Set bit 18 in CPUACTLR_EL1 */
+ sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
+ CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH
+
+ /* Set bit 25 in CMPXACTLR_EL1 */
+ sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
+ CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH
+
+workaround_reset_end cortex_a510, ERRATUM(2218950)
+
+check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0)
/* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2250311.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
* This workaround is not a typical errata fix. MPMM
* is disabled here, but this conflicts with the BL31
* MPMM support. So in addition to simply disabling
* the feature, a flag is set in the MPMM library
* indicating that it should not be enabled even if
* ENABLE_MPMM=1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
-func errata_cortex_a510_2250311_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2250311
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311
/* Disable MPMM */
mrs x0, CPUMPMMCR_EL3
bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
@@ -182,227 +103,68 @@
/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
bl mpmm_errata_disable
#endif
-
-1:
- ret x17
-endfunc errata_cortex_a510_2250311_wa
-
-func check_errata_2250311
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2250311
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2218950.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2218950_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2218950
- cbz x0, 1f
-
- /* Source register for BFI */
- mov x1, #1
-
- /* Set bit 18 in CPUACTLR_EL1 */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
- /* Set bit 25 in CMPXACTLR_EL1 */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- bfi x0, x1, #25, #1
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2218950_wa
+workaround_reset_end cortex_a510, ERRATUM(2250311)
-func check_errata_2218950
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2218950
+check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2172148.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2172148_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2172148
- cbz x0, 1f
-
- /*
- * Force L2 allocation of transient lines by setting
- * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
- */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #1
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2172148_wa
-
-func check_errata_2172148
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2172148
+workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014
+ /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
+ sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \
+ CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2288014)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2347730.
- * This applies to revisions r0p0 - r0p3, r1p0, r1p1.
- * It is fixed in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_cortex_a510_2347730_wa
- mov x17, x30
- bl check_errata_2347730
- cbz x0, 1f
+check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
+workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
/*
* Set CPUACTLR_EL1[17] to 1'b1, which disables
* specific microarchitectural clock gating
* behaviour.
*/
- mrs x1, CORTEX_A510_CPUACTLR_EL1
- orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17
- msr CORTEX_A510_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_a510_2347730_wa
-
-func check_errata_2347730
- /* Applies to revisions r1p1 and lower. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2347730
+ sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17
+workaround_reset_end cortex_a510, ERRATUM(2347730)
- /*---------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2371937.
- * This applies to revisions r1p1 and lower, and is
- * fixed in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- *---------------------------------------------------
- */
-func errata_cortex_a510_2371937_wa
- mov x17, x30
- bl check_errata_2371937
- cbz x0, 1f
+check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1)
+workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937
/*
* Cacheable atomic operations can be forced
* to be executed near by setting
* IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found
* in [40:38] of CPUECTLR_EL1.
*/
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR
- bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3
- msr CORTEX_A510_CPUECTLR_EL1, x0
-1:
- ret x17
-endfunc errata_cortex_a510_2371937_wa
-
-func check_errata_2371937
- /* Applies to r1p1 and lower */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2371937
-
- /* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2666669
- * This applies to revisions r1p1 and lower, and is fixed
- * in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ------------------------------------------------------
- */
-func errata_cortex_a510_2666669_wa
- mov x17, x30
- bl check_errata_2666669
- cbz x0, 1f
-
- /*
- * Workaround will set IMP_CPUACTLR_EL1[38]
- * to 0b1.
- */
- mrs x1, CORTEX_A510_CPUACTLR_EL1
- orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38
- msr CORTEX_A510_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_a510_2666669_wa
+ sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \
+ CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2371937)
-func check_errata_2666669
- /* Applies to r1p1 and lower */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2666669
+check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1)
-/* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Erratum 2684597.
- * This erratum applies to revision r0p0, r0p1, r0p2,
- * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
- * is fixed in r1p3.
- * Shall clobber: x0-x17
- * ------------------------------------------------------
- */
- .globl errata_cortex_a510_2684597_wa
-func errata_cortex_a510_2684597_wa
- mov x17, x30
- /* Ensure this errata is only applied to Cortex-A510 cores */
- jump_if_cpu_midr CORTEX_A510_MIDR, 1f
- b 2f
+workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669
+ sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38
+workaround_reset_end cortex_a510, ERRATUM(2666669)
-1:
- /* Check workaround compatibility. */
- mov x0, x18
- bl check_errata_2684597
- cbz x0, 2f
+check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1)
+.global erratum_cortex_a510_2684597_wa
+workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR
/*
* Many assemblers do not yet understand the "tsb csync" mnemonic,
* so use the equivalent hint instruction.
*/
hint #18 /* tsb csync */
-2:
- ret x17
-endfunc errata_cortex_a510_2684597_wa
-/* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Erratum 2684597.
- * This erratum applies to revision r0p0, r0p1, r0p2,
- * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
- * is fixed in r1p3.
- * Shall clobber: x0-x17
- * ------------------------------------------------------
+workaround_runtime_end cortex_a510, ERRATUM(2684597)
+
+check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
+
+/*
+ * ERRATA_DSU_2313941 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a510
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func check_errata_2684597
- /* Applies to revision < r1p3 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2684597
+.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -413,112 +175,17 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A510_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A510_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a510_core_pwr_dwn
- /*
- * Errata printing function for Cortex-A510. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a510_errata_report
- stp x8, x30, [sp, #-16]!
+errata_report_shim cortex_a510
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A510_1922240, cortex_a510, 1922240
- report_errata ERRATA_A510_2041909, cortex_a510, 2041909
- report_errata ERRATA_A510_2042739, cortex_a510, 2042739
- report_errata ERRATA_A510_2172148, cortex_a510, 2172148
- report_errata ERRATA_A510_2218950, cortex_a510, 2218950
- report_errata ERRATA_A510_2250311, cortex_a510, 2250311
- report_errata ERRATA_A510_2288014, cortex_a510, 2288014
- report_errata ERRATA_A510_2347730, cortex_a510, 2347730
- report_errata ERRATA_A510_2371937, cortex_a510, 2371937
- report_errata ERRATA_A510_2666669, cortex_a510, 2666669
- report_errata ERRATA_A510_2684597, cortex_a510, 2684597
- report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a510_errata_report
-#endif
-
-func cortex_a510_reset_func
- mov x19, x30
-
+cpu_reset_func_start cortex_a510
/* Disable speculative loads */
msr SSBS, xzr
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_A510_1922240
- mov x0, x18
- bl errata_cortex_a510_1922240_wa
-#endif
-
-#if ERRATA_A510_2288014
- mov x0, x18
- bl errata_cortex_a510_2288014_wa
-#endif
-
-#if ERRATA_A510_2042739
- mov x0, x18
- bl errata_cortex_a510_2042739_wa
-#endif
-
-#if ERRATA_A510_2041909
- mov x0, x18
- bl errata_cortex_a510_2041909_wa
-#endif
-
-#if ERRATA_A510_2250311
- mov x0, x18
- bl errata_cortex_a510_2250311_wa
-#endif
-
-#if ERRATA_A510_2218950
- mov x0, x18
- bl errata_cortex_a510_2218950_wa
-#endif
-
-#if ERRATA_A510_2371937
- mov x0, x18
- bl errata_cortex_a510_2371937_wa
-#endif
-
-#if ERRATA_A510_2172148
- mov x0, x18
- bl errata_cortex_a510_2172148_wa
-#endif
-
-#if ERRATA_A510_2347730
- mov x0, x18
- bl errata_cortex_a510_2347730_wa
-#endif
-
-#if ERRATA_A510_2666669
- mov x0, x18
- bl errata_cortex_a510_2666669_wa
-#endif
-
- isb
- ret x19
-endfunc cortex_a510_reset_func
+cpu_reset_func_end cortex_a510
/* ---------------------------------------------
* This function provides Cortex-A510 specific
diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S
index ac6583e..85d1894 100644
--- a/lib/cpus/aarch64/cortex_a65ae.S
+++ b/lib/cpus/aarch64/cortex_a65ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,49 +22,26 @@
#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-/* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A65.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a65ae_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
+ /*
+ * ERRATA_DSU_936184 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a65ae
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184
+.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
- ret x19
-endfunc cortex_a65ae_reset_func
+cpu_reset_func_start cortex_a65ae
+cpu_reset_func_end cortex_a65ae
func cortex_a65ae_cpu_pwr_dwn
- mrs x0, CORTEX_A65AE_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A65AE_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a65ae_cpu_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A65AE. Must follow AAPCS.
- */
-func cortex_a65ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a65ae_errata_report
-#endif
+errata_report_shim cortex_a65ae
.section .rodata.cortex_a65ae_regs, "aS"
cortex_a65ae_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index 497bd52..816a58f 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -26,20 +26,7 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2002765.
- * This applies to revisions r0p0, r1p0, and r2p0 and
- * is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2002765_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2002765
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
ldr x0, =0x6
msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0xF3A08002
@@ -48,119 +35,24 @@
msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x40000001003ff
msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
- isb
-
-1:
- ret x17
-endfunc errata_cortex_x2_2002765_wa
-
-func check_errata_2002765
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2002765
+workaround_reset_end cortex_x2, ERRATUM(2002765)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2058056.
- * This applies to revisions r0p0, r1p0, and r2p0 and
- * is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2058056_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2058056
- cbz x0, 1f
-
- mrs x1, CORTEX_X2_CPUECTLR2_EL1
- mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
- msr CORTEX_X2_CPUECTLR2_EL1, x1
+check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0)
-1:
- ret x17
-endfunc errata_cortex_x2_2058056_wa
+workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096
+ sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end cortex_x2, ERRATUM(2017096)
-func check_errata_2058056
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2058056
+check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2083908.
- * This applies to revision r2p0 and is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x2, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2083908_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2083908
- cbz x0, 1f
+workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056
+ sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
+ CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
+workaround_reset_end cortex_x2, ERRATUM(2058056)
- /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
- mrs x1, CORTEX_X2_CPUACTLR5_EL1
- orr x1, x1, #BIT(13)
- msr CORTEX_X2_CPUACTLR5_EL1, x1
-
-1:
- ret x17
-endfunc errata_cortex_x2_2083908_wa
+check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 0)
-func check_errata_2083908
- /* Applies to r2p0 */
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2083908
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2017096.
- * This applies only to revisions r0p0, r1p0 and r2p0
- * and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2017096_wa
- /* Compare x0 against revision r0p0 to r2p0 */
- mov x17, x30
- bl check_errata_2017096
- cbz x0, 1f
- mrs x1, CORTEX_X2_CPUECTLR_EL1
- orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
- msr CORTEX_X2_CPUECTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_x2_2017096_wa
-
-func check_errata_2017096
- /* Applies to r0p0, r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2017096
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2081180.
- * This applies to revision r0p0, r1p0 and r2p0
- * and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2081180_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2081180
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
/* Apply instruction patching sequence */
ldr x0, =0x3
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
@@ -178,34 +70,26 @@
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x10002001003F3
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_x2_2081180_wa
+workaround_reset_end cortex_x2, ERRATUM(2081180)
-func check_errata_2081180
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2081180
+check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata 2216384.
- * This applies to revisions r0p0, r1p0, and r2p0
- * and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2216384_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2216384
- cbz x0, 1f
+workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908
+ /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
+ sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13)
+workaround_reset_end cortex_x2, ERRATUM(2083908)
+
+check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
+
+workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715
+ /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
+ sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_x2, ERRATUM(2147715)
+
+check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
- mrs x1, CORTEX_X2_CPUACTLR5_EL1
- orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
- msr CORTEX_X2_CPUACTLR5_EL1, x1
+workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384
+ sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
/* Apply instruction patching sequence */
ldr x0, =0x5
@@ -216,138 +100,52 @@
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
- isb
-
-1:
- ret x17
-endfunc errata_x2_2216384_wa
+workaround_reset_end cortex_x2, ERRATUM(2216384)
-func check_errata_2216384
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2216384
+check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* ---------------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2147715.
- * This applies only to revisions r2p0 and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------
- */
-func errata_x2_2147715_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2147715
- cbz x0, 1f
-
- /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
- mrs x1, CORTEX_X2_CPUACTLR_EL1
- orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22
- msr CORTEX_X2_CPUACTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_x2_2147715_wa
-
-func check_errata_2147715
- /* Applies to r2p0 */
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2147715
-
- /* ---------------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2282622.
- * This applies to revision r0p0, r1p0, r2p0 and r2p1.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------------
- */
-func errata_x2_2282622_wa
- /* Compare x0 against revision r2p1 */
- mov x17, x30
- bl check_errata_2282622
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622
/* Apply the workaround */
- mrs x1, CORTEX_X2_CPUACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_X2_CPUACTLR2_EL1, x1
+ sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_x2, ERRATUM(2282622)
-1:
- ret x17
-endfunc errata_x2_2282622_wa
+check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
-func check_errata_2282622
- /* Applies to r0p0, r1p0, r2p0 and r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2282622
+workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
+ /* Set bit 40 in CPUACTLR2_EL1 */
+ sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_x2, ERRATUM(2371105)
- /* -------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2371105.
- * This applies to revisions <= r2p0 and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_x2_2371105_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2371105
- cbz x0, 1f
+check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0)
- /* Set bit 40 in CPUACTLR2_EL1 */
- mrs x1, CORTEX_X2_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40
- msr CORTEX_X2_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_x2_2371105_wa
+workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_reset_end cortex_x2, ERRATUM(2768515)
-func check_errata_2371105
- /* Applies to <= r2p0. */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2371105
+check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata #2768515
- * This applies to revisions <= r2p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
+workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-X2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func errata_x2_2768515_wa
- mov x17, x30
- bl check_errata_2768515
- cbz x0, 1f
+ override_vector_table wa_cve_vbar_cortex_x2
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x2, CVE(2022, 23960)
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_x2_2768515_wa
+check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-func check_errata_2768515
- /* Applies to all revisions <= r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2768515
+/*
+ * ERRATA_DSU_2313941 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_x2
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -358,122 +156,24 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_X2_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X2_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
#if ERRATA_X2_2768515
mov x15, x30
bl cpu_get_rev_var
- bl errata_x2_2768515_wa
+ bl erratum_cortex_x2_2768515_wa
mov x30, x15
#endif /* ERRATA_X2_2768515 */
isb
ret
endfunc cortex_x2_core_pwr_dwn
- /*
- * Errata printing function for Cortex X2. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_x2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X2_2002765, cortex_x2, 2002765
- report_errata ERRATA_X2_2017096, cortex_x2, 2017096
- report_errata ERRATA_X2_2058056, cortex_x2, 2058056
- report_errata ERRATA_X2_2081180, cortex_x2, 2081180
- report_errata ERRATA_X2_2083908, cortex_x2, 2083908
- report_errata ERRATA_X2_2147715, cortex_x2, 2147715
- report_errata ERRATA_X2_2216384, cortex_x2, 2216384
- report_errata ERRATA_X2_2282622, cortex_x2, 2282622
- report_errata ERRATA_X2_2371105, cortex_x2, 2371105
- report_errata ERRATA_X2_2768515, cortex_x2, 2768515
- report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960
- report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x2_errata_report
-#endif
-
-func cortex_x2_reset_func
- mov x19, x30
+errata_report_shim cortex_x2
+cpu_reset_func_start cortex_x2
/* Disable speculative loads */
msr SSBS, xzr
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_X2_2002765
- mov x0, x18
- bl errata_cortex_x2_2002765_wa
-#endif
-
-#if ERRATA_X2_2058056
- mov x0, x18
- bl errata_cortex_x2_2058056_wa
-#endif
-
-#if ERRATA_X2_2083908
- mov x0, x18
- bl errata_cortex_x2_2083908_wa
-#endif
-
-#if ERRATA_X2_2017096
- mov x0, x18
- bl errata_x2_2017096_wa
-#endif
-
-#if ERRATA_X2_2081180
- mov x0, x18
- bl errata_x2_2081180_wa
-#endif
-
-#if ERRATA_X2_2216384
- mov x0, x18
- bl errata_x2_2216384_wa
-#endif
-
-#if ERRATA_X2_2147715
- mov x0, x18
- bl errata_x2_2147715_wa
-#endif
-
-#if ERRATA_X2_2282622
- mov x0, x18
- bl errata_x2_2282622_wa
-#endif
-
-#if ERRATA_X2_2371105
- mov x0, x18
- bl errata_x2_2371105_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-X2 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_x2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_x2_reset_func
+cpu_reset_func_end cortex_x2
/* ---------------------------------------------
* This function provides Cortex X2 specific
diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S
index 96b63cf..45bd8d3 100644
--- a/lib/cpus/aarch64/neoverse_e1.S
+++ b/lib/cpus/aarch64/neoverse_e1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,20 +21,18 @@
#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* -------------------------------------------------
- * The CPU Ops reset function for Neoverse-E1.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func neoverse_e1_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
+/*
+ * ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S and applies to neoverse_e1.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184
+.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa
+add_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
- ret x19
-endfunc neoverse_e1_reset_func
+cpu_reset_func_start neoverse_e1
+cpu_reset_func_end neoverse_e1
func neoverse_e1_cpu_pwr_dwn
mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
@@ -44,27 +42,7 @@
ret
endfunc neoverse_e1_cpu_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N1. Must follow AAPCS.
- */
-func neoverse_e1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_e1_errata_report
-#endif
-
+errata_report_shim neoverse_e1
.section .rodata.neoverse_e1_regs, "aS"
neoverse_e1_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 2cf94c7..36a7ee7 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,20 +27,17 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1043202.
- * This applies to revision r0p0 and r1p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
+/*
+ * ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S and applies to Neoverse N1.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func errata_n1_1043202_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1043202
- cbz x0, 1f
+.equ check_erratum_neoverse_n1_936184, check_errata_dsu_936184
+.equ erratum_neoverse_n1_936184_wa, errata_dsu_936184_wa
+add_erratum_entry neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
+workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
@@ -50,314 +47,72 @@
msr CPUPMR_EL3, x0
ldr x0, =0x800200071
msr CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_n1_1043202_wa
+workaround_reset_end neoverse_n1, ERRATUM(1043202)
-func check_errata_1043202
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1043202
+check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0)
-/* --------------------------------------------------
- * Disable speculative loads if Neoverse N1 supports
- * SSBS.
- *
- * Shall clobber: x0.
- * --------------------------------------------------
- */
-func neoverse_n1_disable_speculative_loads
- /* Check if the PE implements SSBS */
- mrs x0, id_aa64pfr1_el1
- tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
- b.eq 1f
+workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
+workaround_reset_end neoverse_n1, ERRATUM(1073348)
- /* Disable speculative loads */
- msr SSBS, xzr
+check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0)
-1:
- ret
-endfunc neoverse_n1_disable_speculative_loads
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1073348
- * This applies to revision r0p0 and r1p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1073348_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1073348
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1073348_wa
-
-func check_errata_1073348
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1073348
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1130799
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1130799_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1130799
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1130799_wa
-
-func check_errata_1130799
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1130799
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1165347
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1165347_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1165347
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1165347_wa
+workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
+workaround_reset_end neoverse_n1, ERRATUM(1130799)
-func check_errata_1165347
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1165347
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1207823
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1207823_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1207823
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1207823_wa
+check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0)
-func check_errata_1207823
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1207823
+workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
+workaround_reset_end neoverse_n1, ERRATUM(1165347)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1220197
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1220197_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1220197
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
- msr NEOVERSE_N1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1220197_wa
+check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0)
-func check_errata_1220197
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1220197
+workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
+workaround_reset_end neoverse_n1, ERRATUM(1207823)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1257314
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1257314_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1257314
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR3_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
- msr NEOVERSE_N1_CPUACTLR3_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1257314_wa
+check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0)
-func check_errata_1257314
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1257314
+workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK
+workaround_reset_end neoverse_n1, ERRATUM(1220197)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1262606
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1262606_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1262606
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1262606_wa
+check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0)
-func check_errata_1262606
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262606
+workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
+workaround_reset_end neoverse_n1, ERRATUM(1257314)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1262888
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1262888_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1262888
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
- msr NEOVERSE_N1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1262888_wa
+check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0)
-func check_errata_1262888
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262888
+workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1262606)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1275112
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1275112_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1275112
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1275112_wa
+check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0)
-func check_errata_1275112
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1275112
+workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
+workaround_reset_end neoverse_n1, ERRATUM(1262888)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1315703.
- * This applies to revision <= r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1315703_wa
- /* Compare x0 against revision r3p1 */
- mov x17, x30
- bl check_errata_1315703
- cbz x0, 1f
+check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0)
- mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
- msr NEOVERSE_N1_CPUACTLR2_EL1, x0
+workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1275112)
-1:
- ret x17
-endfunc errata_n1_1315703_wa
+check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0)
-func check_errata_1315703
- /* Applies to everything <= r3p0. */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1315703
+workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
+workaround_reset_end neoverse_n1, ERRATUM(1315703)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1542419.
- * This applies to revisions r3p0 - r4p0 of Neoverse N1
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1542419_wa
- /* Compare x0 against revision r3p0 and r4p0 */
- mov x17, x30
- bl check_errata_1542419
- cbz x0, 1f
+check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0)
+workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
@@ -368,67 +123,17 @@
ldr x0, =0x08000020007D
msr CPUPCR_EL3, x0
isb
-1:
- ret x17
-endfunc errata_n1_1542419_wa
+workaround_reset_end neoverse_n1, ERRATUM(1542419)
-func check_errata_1542419
- /* Applies to everything r3p0 - r4p0. */
- mov x1, #0x30
- mov x2, #0x40
- b cpu_rev_var_range
-endfunc check_errata_1542419
+check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1868343.
- * This applies to revision <= r4p0 of Neoverse N1.
- * This workaround is the same as the workaround for
- * errata 1262606 and 1275112 but applies to a wider
- * revision range.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1868343_wa
- /*
- * Compare x0 against revision r4p0
- */
- mov x17, x30
- bl check_errata_1868343
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_n1_1868343_wa
+workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1868343)
-func check_errata_1868343
- /* Applies to everything <= r4p0 */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1868343
+check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1946160.
- * This applies to revisions r3p0, r3p1, r4p0, and
- * r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
- * and r2p0 but there is no fix in these revisions.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1946160_wa
- /*
- * Compare x0 against r3p0 - r4p1
- */
- mov x17, x30
- bl check_errata_1946160
- cbz x0, 1f
-
+workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -437,7 +142,6 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
mov x0, #4
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800082
@@ -446,7 +150,6 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
mov x0, #5
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800200
@@ -455,147 +158,62 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
isb
-1:
- ret x17
-endfunc errata_n1_1946160_wa
+workaround_reset_end neoverse_n1, ERRATUM(1946160)
-func check_errata_1946160
- /* Applies to r3p0 - r4p1. */
- mov x1, #0x30
- mov x2, #0x41
- b cpu_rev_var_range
-endfunc check_errata_1946160
+check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #2743102
- * This applies to revisions <= r4p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_n1_2743102_wa
- mov x17, x30
- bl check_errata_2743102
- cbz x0, 1f
-
+workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_n1_2743102_wa
+workaround_runtime_end neoverse_n1, ERRATUM(2743102)
-func check_errata_2743102
- /* Applies to all revisions <= r4p1 */
- mov x1, #0x41
- b cpu_rev_var_ls
-endfunc check_errata_2743102
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func neoverse_n1_reset_func
- mov x19, x30
+check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1)
- bl neoverse_n1_disable_speculative_loads
-
- /* Forces all cacheable atomic instructions to be near */
- mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
- msr NEOVERSE_N1_CPUACTLR2_EL1, x0
- isb
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_N1_1043202
- mov x0, x18
- bl errata_n1_1043202_wa
-#endif
-
-#if ERRATA_N1_1073348
- mov x0, x18
- bl errata_n1_1073348_wa
-#endif
-
-#if ERRATA_N1_1130799
- mov x0, x18
- bl errata_n1_1130799_wa
-#endif
-
-#if ERRATA_N1_1165347
- mov x0, x18
- bl errata_n1_1165347_wa
-#endif
-
-#if ERRATA_N1_1207823
- mov x0, x18
- bl errata_n1_1207823_wa
-#endif
-
-#if ERRATA_N1_1220197
- mov x0, x18
- bl errata_n1_1220197_wa
-#endif
-
-#if ERRATA_N1_1257314
- mov x0, x18
- bl errata_n1_1257314_wa
-#endif
-
-#if ERRATA_N1_1262606
- mov x0, x18
- bl errata_n1_1262606_wa
-#endif
+workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-N1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_n1
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_n1, CVE(2022, 23960)
-#if ERRATA_N1_1262888
- mov x0, x18
- bl errata_n1_1262888_wa
-#endif
+check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_N1_1275112
- mov x0, x18
- bl errata_n1_1275112_wa
-#endif
+/* --------------------------------------------------
+ * Disable speculative loads if Neoverse N1 supports
+ * SSBS.
+ *
+ * Shall clobber: x0.
+ * --------------------------------------------------
+ */
+func neoverse_n1_disable_speculative_loads
+ /* Check if the PE implements SSBS */
+ mrs x0, id_aa64pfr1_el1
+ tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
+ b.eq 1f
-#if ERRATA_N1_1315703
- mov x0, x18
- bl errata_n1_1315703_wa
-#endif
+ /* Disable speculative loads */
+ msr SSBS, xzr
-#if ERRATA_N1_1542419
- mov x0, x18
- bl errata_n1_1542419_wa
-#endif
+1:
+ ret
+endfunc neoverse_n1_disable_speculative_loads
-#if ERRATA_N1_1868343
- mov x0, x18
- bl errata_n1_1868343_wa
-#endif
+cpu_reset_func_start neoverse_n1
+ bl neoverse_n1_disable_speculative_loads
-#if ERRATA_N1_1946160
- mov x0, x18
- bl errata_n1_1946160_wa
-#endif
+ /* Forces all cacheable atomic instructions to be near */
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
+ isb
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
- msr actlr_el3, x0
-
+ sysreg_bit_set actlr_el3, NEOVERSE_N1_ACTLR_AMEN_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
- msr actlr_el2, x0
-
+ sysreg_bit_set actlr_el2, NEOVERSE_N1_ACTLR_AMEN_BIT
/* Enable group0 counters */
mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
msr CPUAMCNTENSET_EL0, x0
@@ -603,27 +221,9 @@
#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some system may have External LLC, core needs to be made aware */
- mrs x0, NEOVERSE_N1_CPUECTLR_EL1
- orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
- msr NEOVERSE_N1_CPUECTLR_EL1, x0
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-N1 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_n1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_n1_reset_func
+cpu_reset_func_end neoverse_n1
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -634,55 +234,15 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
- msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
-#if ERRATA_N1_2743102
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n1_2743102_wa
- mov x30, x15
-#endif /* ERRATA_N1_2743102 */
+ sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
+
+ apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
+
isb
ret
endfunc neoverse_n1_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N1. Must follow AAPCS.
- */
-func neoverse_n1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
- report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
- report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
- report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
- report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
- report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
- report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
- report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
- report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
- report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
- report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
- report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
- report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
- report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
- report_errata ERRATA_N1_2743102, neoverse_n1, 2743102
- report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
- report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_n1_errata_report
-#endif
+errata_report_shim neoverse_n1
/*
* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index 4ea887f..6e00e5e 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -38,6 +38,12 @@
mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
+#if ERRATA_V2_2801372
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_neoverse_v2_2801372_wa
+ mov x30, x15
+#endif /* ERRATA_V2_2801372 */
isb
ret
endfunc neoverse_v2_core_pwr_dwn
@@ -51,6 +57,30 @@
ret
endfunc check_errata_cve_2022_23960
+ /* ----------------------------------------------------
+ * Errata Workaround for Neoverse V2 Errata #2801372
+ * This applies to revisions <= r0p1 and is fixed in r0p2.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ----------------------------------------------------
+ */
+func errata_neoverse_v2_2801372_wa
+ mov x17, x30
+ bl check_errata_2801372
+ cbz x0, 1f
+
+ /* dsb before isb of power down sequence */
+ dsb sy
+1:
+ ret x17
+endfunc errata_neoverse_v2_2801372_wa
+
+func check_errata_2801372
+ /* Applies to all revisions <= r0p1 */
+ mov x1, #0x01
+ b cpu_rev_var_ls
+endfunc check_errata_2801372
+
func neoverse_v2_reset_func
/* Disable speculative loads */
msr SSBS, xzr
@@ -82,6 +112,7 @@
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
+ report_errata ERRATA_V2_2801372, neoverse_v2, 2801372
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index e16c8e4..4a80bce 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -782,6 +782,10 @@
# erratum applies to revisions r0p0, rop1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2719103
+# Flag to apply erratum 2801372 workaround for all configurations.
+# This erratum applies to revisions r0p0, r0p1. Fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_V2_2801372
+
# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_A715_2701951
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index d9ff0b6..9d717bb 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -562,6 +562,20 @@
#endif /* IMAGE_BL31 */
}
+/* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */
+static __unused void enable_pauth_el2(void)
+{
+ u_register_t hcr_el2 = read_hcr_el2();
+ /*
+ * For Armv8.3 pointer authentication feature, disable traps to EL2 when
+ * accessing key registers or using pointer authentication instructions
+ * from lower ELs.
+ */
+ hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
+
+ write_hcr_el2(hcr_el2);
+}
+
/*******************************************************************************
* Enable architecture extensions in-place at EL2 on first entry to Non-secure
* world when EL2 is empty and unused.
@@ -602,6 +616,10 @@
if (is_feat_sme_supported()) {
sme_init_el2_unused();
}
+
+#if ENABLE_PAUTH
+ enable_pauth_el2();
+#endif /* ENABLE_PAUTH */
#endif /* IMAGE_BL31 */
}
@@ -644,6 +662,11 @@
sme_disable(ctx);
}
}
+
+ /* NS can access this but Secure shouldn't */
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_disable(ctx);
+ }
#endif /* IMAGE_BL31 */
}
@@ -672,6 +695,109 @@
cm_setup_context(ctx, ep);
}
+/* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */
+static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx)
+{
+ u_register_t hcr_el2 = HCR_RESET_VAL;
+ u_register_t mdcr_el2;
+ u_register_t scr_el3;
+
+ scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
+
+ /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */
+ if ((scr_el3 & SCR_RW_BIT) != 0U) {
+ hcr_el2 |= HCR_RW_BIT;
+ }
+
+ write_hcr_el2(hcr_el2);
+
+ /*
+ * Initialise CPTR_EL2 setting all fields rather than relying on the hw.
+ * All fields have architecturally UNKNOWN reset values.
+ */
+ write_cptr_el2(CPTR_EL2_RESET_VAL);
+
+ /*
+ * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on
+ * reset and are set to zero except for field(s) listed below.
+ *
+ * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of
+ * Non-secure EL0 and EL1 accesses to the physical timer registers.
+ *
+ * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of
+ * Non-secure EL0 and EL1 accesses to the physical counter registers.
+ */
+ write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
+
+ /*
+ * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally
+ * UNKNOWN value.
+ */
+ write_cntvoff_el2(0);
+
+ /*
+ * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1
+ * respectively.
+ */
+ write_vpidr_el2(read_midr_el1());
+ write_vmpidr_el2(read_mpidr_el1());
+
+ /*
+ * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset.
+ *
+ * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address
+ * translation is disabled, cache maintenance operations depend on the
+ * VMID.
+ *
+ * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is
+ * disabled.
+ */
+ write_vttbr_el2(VTTBR_RESET_VAL &
+ ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) |
+ (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
+
+ /*
+ * Initialise MDCR_EL2, setting all fields rather than relying on hw.
+ * Some fields are architecturally UNKNOWN on reset.
+ *
+ * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System
+ * register accesses to the Debug ROM registers are not trapped to EL2.
+ *
+ * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register
+ * accesses to the powerdown debug registers are not trapped to EL2.
+ *
+ * MDCR_EL2.TDA: Set to zero so that System register accesses to the
+ * debug registers do not trap to EL2.
+ *
+ * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to
+ * EL2.
+ */
+ mdcr_el2 = MDCR_EL2_RESET_VAL &
+ ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT |
+ MDCR_EL2_TDE_BIT);
+
+ write_mdcr_el2(mdcr_el2);
+
+ /*
+ * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset.
+ *
+ * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or
+ * EL1 accesses to System registers do not trap to EL2.
+ */
+ write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
+
+ /*
+ * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on
+ * reset.
+ *
+ * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer
+ * and prevent timer interrupts.
+ */
+ write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT));
+
+ manage_extensions_nonsecure_el2_unused();
+}
+
/*******************************************************************************
* Prepare the CPU system registers for first entry into realm, secure, or
* normal world.
@@ -683,9 +809,8 @@
******************************************************************************/
void cm_prepare_el3_exit(uint32_t security_state)
{
- u_register_t sctlr_elx, scr_el3, mdcr_el2;
+ u_register_t sctlr_elx, scr_el3;
cpu_context_t *ctx = cm_get_context(security_state);
- uint64_t hcr_el2 = 0U;
assert(ctx != NULL);
@@ -722,121 +847,7 @@
#endif
write_sctlr_el2(sctlr_elx);
} else if (el2_implemented != EL_IMPL_NONE) {
- /*
- * EL2 present but unused, need to disable safely.
- * SCTLR_EL2 can be ignored in this case.
- *
- * Set EL2 register width appropriately: Set HCR_EL2
- * field to match SCR_EL3.RW.
- */
- if ((scr_el3 & SCR_RW_BIT) != 0U)
- hcr_el2 |= HCR_RW_BIT;
-
- /*
- * For Armv8.3 pointer authentication feature, disable
- * traps to EL2 when accessing key registers or using
- * pointer authentication instructions from lower ELs.
- */
- hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
-
- write_hcr_el2(hcr_el2);
-
- /*
- * Initialise CPTR_EL2 setting all fields rather than
- * relying on the hw. All fields have architecturally
- * UNKNOWN reset values.
- */
- write_cptr_el2(CPTR_EL2_RESET_VAL);
-
- /*
- * Initialise CNTHCTL_EL2. All fields are
- * architecturally UNKNOWN on reset and are set to zero
- * except for field(s) listed below.
- *
- * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to
- * Hyp mode of Non-secure EL0 and EL1 accesses to the
- * physical timer registers.
- *
- * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
- * Hyp mode of Non-secure EL0 and EL1 accesses to the
- * physical counter registers.
- */
- write_cnthctl_el2(CNTHCTL_RESET_VAL |
- EL1PCEN_BIT | EL1PCTEN_BIT);
-
- /*
- * Initialise CNTVOFF_EL2 to zero as it resets to an
- * architecturally UNKNOWN value.
- */
- write_cntvoff_el2(0);
-
- /*
- * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
- * MPIDR_EL1 respectively.
- */
- write_vpidr_el2(read_midr_el1());
- write_vmpidr_el2(read_mpidr_el1());
-
- /*
- * Initialise VTTBR_EL2. All fields are architecturally
- * UNKNOWN on reset.
- *
- * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
- * 2 address translation is disabled, cache maintenance
- * operations depend on the VMID.
- *
- * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
- * translation is disabled.
- */
- write_vttbr_el2(VTTBR_RESET_VAL &
- ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
- | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
-
- /*
- * Initialise MDCR_EL2, setting all fields rather than
- * relying on hw. Some fields are architecturally
- * UNKNOWN on reset.
- *
- * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
- * EL1 System register accesses to the Debug ROM
- * registers are not trapped to EL2.
- *
- * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
- * System register accesses to the powerdown debug
- * registers are not trapped to EL2.
- *
- * MDCR_EL2.TDA: Set to zero so that System register
- * accesses to the debug registers do not trap to EL2.
- *
- * MDCR_EL2.TDE: Set to zero so that debug exceptions
- * are not routed to EL2.
- */
- mdcr_el2 = ((MDCR_EL2_RESET_VAL) &
- ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
- MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT));
-
- write_mdcr_el2(mdcr_el2);
-
- /*
- * Initialise HSTR_EL2. All fields are architecturally
- * UNKNOWN on reset.
- *
- * HSTR_EL2.T<n>: Set all these fields to zero so that
- * Non-secure EL0 or EL1 accesses to System registers
- * do not trap to EL2.
- */
- write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
- /*
- * Initialise CNTHP_CTL_EL2. All fields are
- * architecturally UNKNOWN on reset.
- *
- * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
- * physical timer and prevent timer interrupts.
- */
- write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
- ~(CNTHP_CTL_ENABLE_BIT));
-
- manage_extensions_nonsecure_el2_unused();
+ init_nonsecure_el2_unused(ctx);
}
}
diff --git a/lib/extensions/pmuv3/aarch64/pmuv3.c b/lib/extensions/pmuv3/aarch64/pmuv3.c
index fda71aa..61fc47d 100644
--- a/lib/extensions/pmuv3/aarch64/pmuv3.c
+++ b/lib/extensions/pmuv3/aarch64/pmuv3.c
@@ -82,9 +82,12 @@
* 0 | 1 | enabled | disabled
* 1 | 1 | enabled | disabled only for counters 0 to
* MDCR_EL2.HPMN - 1. Enabled for the rest
+ *
+ * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
+ * accesses to all Performance Monitors registers do not trap to EL3.
*/
mdcr_el3 = (mdcr_el3 | MDCR_SCCD_BIT | MDCR_MCCD_BIT) &
- ~(MDCR_MPMX_BIT | MDCR_SPME_BIT);
+ ~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT);
mdcr_el3 = mtpmu_disable_el3(mdcr_el3);
write_mdcr_el3(mdcr_el3);
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index 236b102..2c25a9d 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -26,10 +26,13 @@
uint64_t v;
/*
- * MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
+ * MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
* and disabled in secure state. Accesses to SPE registers at
* S-EL1 generate trap exceptions to EL3.
*
+ * MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
+ * When FEAT_RME is not implemented, this field is RES0.
+ *
* MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
* register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
* Setting this bit to 1 doesn't have any effect on it when
@@ -37,6 +40,7 @@
*/
v = read_mdcr_el3();
v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
+ v &= ~(MDCR_NSPBE_BIT);
write_mdcr_el3(v);
}
diff --git a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
index 4b57f67..1349566 100644
--- a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
+++ b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
@@ -12,16 +12,26 @@
void sys_reg_trace_enable(cpu_context_t *ctx)
{
- uint64_t val;
+ /*
+ * CPTR_EL3.TTA: Set to zero so that System register accesses to the
+ * trace registers do not trap to EL3.
+ */
+ uint64_t val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
+
+ val &= ~(TTA_BIT);
+ write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val);
+}
- /* Retrieve CPTR_EL3 value from the given context 'ctx',
- * and update CPTR_EL3.TTA bit to 0.
- * This function is called while switching context to NS to
- * allow system trace register access to NS-EL2 and NS-EL1
- * when NS-EL2 is implemented but not used.
+void sys_reg_trace_disable(cpu_context_t *ctx)
+{
+ /*
+ * CPTR_EL3.TTA: Set to one so that System register accesses to the
+ * trace registers trap to EL3, unless it is trapped by CPACR.TRCDIS,
+ * CPACR_EL1.TTA, or CPTR_EL2.TTA
*/
- val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
- val &= ~TTA_BIT;
+ uint64_t val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
+
+ val |= TTA_BIT;
write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val);
}
diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c
index 461ea73..d4fbdfb 100644
--- a/lib/extensions/trbe/trbe.c
+++ b/lib/extensions/trbe/trbe.c
@@ -24,13 +24,18 @@
u_register_t val;
/*
+ * MDCR_EL3.NSTBE = 0b0
+ * Trace Buffer owning Security state is Non-secure state. If FEAT_RME
+ * is not implemented, this field is RES0.
+ *
* MDCR_EL3.NSTB = 0b11
- * Allow access of trace buffer control registers from NS-EL1
- * and NS-EL2, tracing is prohibited in Secure and Realm state
- * (if implemented).
+ * Allow access of trace buffer control registers from NS-EL1 and
+ * NS-EL2, tracing is prohibited in Secure and Realm state (if
+ * implemented).
*/
val = read_mdcr_el3();
val |= MDCR_NSTB(MDCR_NSTB_EL1);
+ val &= ~(MDCR_NSTBE_BIT);
write_mdcr_el3(val);
}
diff --git a/lib/extensions/trf/aarch32/trf.c b/lib/extensions/trf/aarch32/trf.c
index e13b4db..321c089 100644
--- a/lib/extensions/trf/aarch32/trf.c
+++ b/lib/extensions/trf/aarch32/trf.c
@@ -16,9 +16,9 @@
/*
* Allow access of trace filter control registers from
- * non-monitor mode
+ * non-monitor mode.
*/
val = read_sdcr();
- val &= ~SDCR_TTRF_BIT;
+ val &= ~(SDCR_TTRF_BIT);
write_sdcr(val);
}
diff --git a/lib/extensions/trf/aarch64/trf.c b/lib/extensions/trf/aarch64/trf.c
index f681b28..83fbf85 100644
--- a/lib/extensions/trf/aarch64/trf.c
+++ b/lib/extensions/trf/aarch64/trf.c
@@ -14,12 +14,16 @@
u_register_t val;
/*
+ * MDCR_EL3.STE = b0
+ * Trace prohibited in Secure state unless overridden by the
+ * IMPLEMENTATION DEFINED authentication interface.
+ *
* MDCR_EL3.TTRF = b0
* Allow access of trace filter control registers from NS-EL2
* and NS-EL1 when NS-EL2 is implemented but not used
*/
val = read_mdcr_el3();
- val &= ~MDCR_TTRF_BIT;
+ val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
write_mdcr_el3(val);
}
diff --git a/lib/psci/aarch64/runtime_errata.S b/lib/psci/aarch64/runtime_errata.S
index 8d46691..89e3e12 100644
--- a/lib/psci/aarch64/runtime_errata.S
+++ b/lib/psci/aarch64/runtime_errata.S
@@ -20,7 +20,7 @@
mov x18, x0
#if ERRATA_A510_2684597
- bl errata_cortex_a510_2684597_wa
+ bl erratum_cortex_a510_2684597_wa
#endif
ret x19
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 8aa0cce..70bf77e 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -1037,6 +1037,13 @@
psci_cpu_suspend_finish(cpu_idx, &state_info);
/*
+ * Generic management: Now we just need to retrieve the
+ * information that we had stashed away during the cpu_on
+ * call to set this cpu on its way.
+ */
+ cm_prepare_el3_exit_ns();
+
+ /*
* Set the requested and target state of this CPU and all the higher
* power domains which are ancestors of this CPU to run.
*/
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 76eb50c..1f619ae 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -225,11 +225,4 @@
/* Populate the mpidr field within the cpu node array */
/* This needs to be done only once */
psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK;
-
- /*
- * Generic management: Now we just need to retrieve the
- * information that we had stashed away during the cpu_on
- * call to set this cpu on its way.
- */
- cm_prepare_el3_exit_ns();
}
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index d93e60d..cb12b83 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -367,11 +367,4 @@
psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL);
PUBLISH_EVENT(psci_suspend_pwrdown_finish);
-
- /*
- * Generic management: Now we just need to retrieve the
- * information that we had stashed away during the suspend
- * call to set this cpu on its way.
- */
- cm_prepare_el3_exit_ns();
}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 99dd6c7..df04617 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -205,14 +205,18 @@
#endif
/*
- * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth.
+ * Set the maximum size of BL2 to be close to half of the Trusted SRAM.
+ * Maximum size of BL2 increases as Trusted SRAM size increases.
*/
#if CRYPTO_SUPPORT
#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB
-# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION)
+# define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \
+ (2 * PAGE_SIZE) - \
+ FVP_BL2_ROMLIB_OPTIMIZATION)
#else
-# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION)
+# define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \
+ (3 * PAGE_SIZE) - \
+ FVP_BL2_ROMLIB_OPTIMIZATION)
#endif
#elif ARM_BL31_IN_DRAM
/* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 7df150e..e790f92 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -222,7 +222,8 @@
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
- lib/cpus/aarch32/cortex_a57.S
+ lib/cpus/aarch32/cortex_a57.S \
+ lib/cpus/aarch32/cortex_a53.S
endif
BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk
index aa2fe86..67413c6 100644
--- a/plat/brcm/board/stingray/platform.mk
+++ b/plat/brcm/board/stingray/platform.mk
@@ -210,7 +210,8 @@
BL2_SOURCES += plat/${SOC_DIR}/driver/ihost_pll_config.c \
plat/${SOC_DIR}/src/bl2_setup.c \
- plat/${SOC_DIR}/driver/swreg.c
+ plat/${SOC_DIR}/driver/swreg.c \
+ lib/cpus/aarch64/cpu_helpers.S
ifeq (${USE_DDR},yes)
PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ddr/soc/include
diff --git a/plat/imx/imx8m/imx8m_ccm.c b/plat/imx/imx8m/imx8m_ccm.c
new file mode 100644
index 0000000..10a00c9
--- /dev/null
+++ b/plat/imx/imx8m/imx8m_ccm.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2023, Pengutronix. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define UCR1 0x80
+#define UCR1_UARTEN BIT(0)
+#define DOMAIN0_RUNNING(d) (((d) & 0x3) != 0)
+
+static struct imx_uart {
+ unsigned int ccm_reg;
+ unsigned int uart_base;
+} imx8m_uart_info[] = {
+ { /* UART 1 */
+ .ccm_reg = 0x4490,
+ .uart_base = 0x30860000,
+ }, { /* UART 2 */
+ .ccm_reg = 0x44a0,
+ .uart_base = 0x30890000,
+ }, { /* UART 3 */
+ .ccm_reg = 0x44b0,
+ .uart_base = 0x30880000,
+ }, { /* UART 4 */
+ .ccm_reg = 0x44c0,
+ .uart_base = 0x30a60000,
+ }
+};
+
+unsigned int imx8m_uart_get_base(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8m_uart_info); i++) {
+ uint32_t val;
+
+ /*
+ * At least check that the clock-gate is ungated before we
+ * access the UART register.
+ */
+ val = mmio_read_32(IMX_CCM_BASE + imx8m_uart_info[i].ccm_reg);
+ if (DOMAIN0_RUNNING(val)) {
+ val = mmio_read_32(imx8m_uart_info[i].uart_base + UCR1);
+ if (val & UCR1_UARTEN) {
+ return imx8m_uart_info[i].uart_base;
+ }
+ }
+ }
+
+ /*
+ * We should return an error and inform the user but we can't do it
+ * this early.
+ */
+ return 0;
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index 67bfd36..8e66361 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -27,6 +27,7 @@
#include <imx_uart.h>
#include <imx_rdc.h>
#include <imx8m_caam.h>
+#include <imx8m_ccm.h>
#include <imx8m_csu.h>
#include <plat_imx8.h>
@@ -130,6 +131,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ unsigned int console_base = 0U;
static console_t console;
int i;
@@ -144,7 +146,14 @@
imx_csu_init(csu_cfg);
- console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+#if IMX_BOOT_UART_BASE
+ console_base = IMX_BOOT_UART_BASE;
+#endif
+ if (console_base == 0U) {
+ console_base = imx8m_uart_get_base();
+ }
+
+ console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
/* This console is only used for boot stage */
console_set_scope(&console, CONSOLE_FLAG_BOOT);
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 24582f8..2462517 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -37,6 +37,7 @@
plat/imx/imx8m/imx_rdc.c \
plat/imx/imx8m/imx8m_csu.c \
plat/imx/imx8m/imx8m_caam.c \
+ plat/imx/imx8m/imx8m_ccm.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c \
plat/imx/imx8m/imx8mm/imx8mm_psci.c \
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index eff198d..aeb1cbf 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -25,6 +25,7 @@
#include <imx_uart.h>
#include <imx_rdc.h>
#include <imx8m_caam.h>
+#include <imx8m_ccm.h>
#include <imx8m_csu.h>
#include <platform_def.h>
#include <plat_imx8.h>
@@ -121,6 +122,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ unsigned int console_base = 0U;
static console_t console;
unsigned int val;
int i;
@@ -141,7 +143,14 @@
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
- console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+#if IMX_BOOT_UART_BASE
+ console_base = IMX_BOOT_UART_BASE;
+#endif
+ if (console_base == 0U) {
+ console_base = imx8m_uart_get_base();
+ }
+
+ console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
/* This console is only used for boot stage */
console_set_scope(&console, CONSOLE_FLAG_BOOT);
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index 1c0ad4f..4651610 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -31,6 +31,7 @@
plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx_rdc.c \
plat/imx/imx8m/imx8m_caam.c \
+ plat/imx/imx8m/imx8m_ccm.c \
plat/imx/imx8m/imx8m_csu.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c \
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
index 4c31fa2..e25668b 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -25,6 +25,7 @@
#include <imx_uart.h>
#include <imx_rdc.h>
#include <imx8m_caam.h>
+#include <imx8m_ccm.h>
#include <imx8m_csu.h>
#include <platform_def.h>
#include <plat_imx8.h>
@@ -117,6 +118,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ unsigned int console_base = 0U;
static console_t console;
unsigned int val;
unsigned int i;
@@ -137,7 +139,14 @@
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
- console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+#if IMX_BOOT_UART_BASE
+ console_base = IMX_BOOT_UART_BASE;
+#endif
+ if (console_base == 0U) {
+ console_base = imx8m_uart_get_base();
+ }
+
+ console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
/* This console is only used for boot stage */
console_set_scope(&console, CONSOLE_FLAG_BOOT);
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 1102316..21836d9 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -32,6 +32,7 @@
plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx_rdc.c \
plat/imx/imx8m/imx8m_caam.c \
+ plat/imx/imx8m/imx8m_ccm.c \
plat/imx/imx8m/imx8m_csu.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c \
diff --git a/plat/imx/imx8m/include/imx8m_ccm.h b/plat/imx/imx8m/include/imx8m_ccm.h
new file mode 100644
index 0000000..acbd135
--- /dev/null
+++ b/plat/imx/imx8m/include/imx8m_ccm.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2023, Pengutronix. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX8M_CCM_H
+#define IMX8M_CCM_H
+
+unsigned int imx8m_uart_get_base(void);
+
+#endif /* IMX8M_CCM_H */
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index bc176c6..d7f501b 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -399,7 +399,8 @@
.cpu_errata_list = {
[0] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
ERRATA_NON_ARM_INTERCONNECT},
- [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [1] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
+ [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_V2_H_INC */
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index c80b524..a929ea2 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -128,6 +128,11 @@
sve_enable(ctx);
}
+ /* NS can access this but Realm shouldn't */
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_disable(ctx);
+ }
+
pmuv3_enable(ctx);
}
diff --git a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
index 5c3d580..5263c04 100644
--- a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
+++ b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
@@ -743,10 +743,12 @@
/*
* Overflow is impossible: the arithmetic happens in at least 64-bit
* precision, but all of the operands are bounded by UINT32_MAX, and
- * ((2^32 - 1)^2 + (2^32 - 1) + (2^32 - 1)) = ((2^32 - 1) * (2^32 + 1))
+ * ((2^32 - 1) * (2^32 - 1) + (2^32 - 1) + (2^32 - 1))
+ * = ((2^32 - 1) * ((2^32 - 1) + 1 + 1))
+ * = ((2^32 - 1) * (2^32 + 1))
* = (2^64 - 1).
*/
- CASSERT(sizeof(desc->emad_count == 4), assert_emad_count_max_too_large);
+ CASSERT(sizeof(desc->emad_count) == 4, assert_emad_count_max_too_large);
emad_end = (desc->emad_count * (unsigned long long)emad_size) +
(unsigned long long)sizeof(struct ffa_comp_mrd) +
(unsigned long long)emad_offset;