fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only
After resume from APD power down, XRDC is initialized by S400 but
the PAC2 and MSC0-2 are not configured, so only DBD owner can access
the resources.
We have to move GPIO restore after TFA XRDC reinit and configure
PDAC for PCC5 before enabling eDMA2 MP clock
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I82748de080151b0bdf1cace092b7892a1e402a27
diff --git a/plat/imx/imx8ulp/apd_context.c b/plat/imx/imx8ulp/apd_context.c
index b484a66..54b8795 100644
--- a/plat/imx/imx8ulp/apd_context.c
+++ b/plat/imx/imx8ulp/apd_context.c
@@ -558,12 +558,13 @@
iomuxc_restore();
- gpio_restore(apd_gpio_ctx, APD_GPIO_CTRL_NUM);
-
tpm5_restore();
xrdc_reinit();
+ /* Restore GPIO after xrdc_reinit, otherwise MSCs are invalid */
+ gpio_restore(apd_gpio_ctx, APD_GPIO_CTRL_NUM);
+
/* restore the gic config */
plat_gic_restore(proc_num, &imx_gicv3_ctx);
diff --git a/plat/imx/imx8ulp/xrdc/xrdc_core.c b/plat/imx/imx8ulp/xrdc/xrdc_core.c
index 2e6d31c..d022e4c 100644
--- a/plat/imx/imx8ulp/xrdc/xrdc_core.c
+++ b/plat/imx/imx8ulp/xrdc/xrdc_core.c
@@ -303,6 +303,9 @@
int xrdc_apply_lpav_config(void)
{
+ /* Configure PAC2 to allow to access PCC5 */
+ xrdc_config_pac(2, 39, 0xe00000);
+
/* Enable the eDMA2 MP clock for MDA16 access */
mmio_write_32(IMX_PCC5_BASE + 0x0, 0xc0000000);
return xrdc_apply_config(xrdc_check_lpav);