Merge pull request #484 from jcastillo-arm/jc/tf-issues/337
cert_create: update help message
diff --git a/Makefile b/Makefile
index 500b0fc..add2e9f 100644
--- a/Makefile
+++ b/Makefile
@@ -457,34 +457,34 @@
endif
ifeq (${NEED_BL2},yes)
-$(if ${BL2}, $(eval $(call MAKE_TOOL_ARGS,2,${BL2},in_fip)),\
- $(eval $(call MAKE_BL,2,in_fip)))
+$(if ${BL2}, $(eval $(call MAKE_TOOL_ARGS,2,${BL2},tb-fw)),\
+ $(eval $(call MAKE_BL,2,tb-fw)))
endif
ifeq (${NEED_BL31},yes)
BL31_SOURCES += ${SPD_SOURCES}
-$(if ${BL31}, $(eval $(call MAKE_TOOL_ARGS,31,${BL31},in_fip)),\
- $(eval $(call MAKE_BL,31,in_fip)))
+$(if ${BL31}, $(eval $(call MAKE_TOOL_ARGS,31,${BL31},soc-fw)),\
+ $(eval $(call MAKE_BL,31,soc-fw)))
endif
# If a BL32 image is needed but neither BL32 nor BL32_SOURCES is defined, the
# build system will call FIP_ADD_IMG to print a warning message and abort the
# process. Note that the dependency on BL32 applies to the FIP only.
ifeq (${NEED_BL32},yes)
-$(if ${BL32}, $(eval $(call MAKE_TOOL_ARGS,32,${BL32},in_fip)),\
- $(if ${BL32_SOURCES}, $(eval $(call MAKE_BL,32,in_fip)),\
- $(eval $(call FIP_ADD_IMG,BL32,--bl32))))
+$(if ${BL32}, $(eval $(call MAKE_TOOL_ARGS,32,${BL32},tos-fw)),\
+ $(if ${BL32_SOURCES}, $(eval $(call MAKE_BL,32,tos-fw)),\
+ $(eval $(call FIP_ADD_IMG,BL32,--tos-fw))))
endif
# Add the BL33 image if required by the platform
ifeq (${NEED_BL33},yes)
-$(eval $(call FIP_ADD_IMG,BL33,--bl33))
+$(eval $(call FIP_ADD_IMG,BL33,--nt-fw))
endif
ifeq (${NEED_BL2U},yes)
BL2U_PATH := $(if ${BL2U},${BL2U},$(call IMG_BIN,2u))
$(if ${BL2U}, ,$(eval $(call MAKE_BL,2u)))
-$(eval $(call FWU_FIP_ADD_PAYLOAD,${BL2U_PATH},--bl2u))
+$(eval $(call FWU_FIP_ADD_PAYLOAD,${BL2U_PATH},--ap-fwu-cfg))
endif
locate-checkpatch:
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index 5b6923a..7ae1de3 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -8,7 +8,7 @@
3. [EL3 runtime services framework](#3--el3-runtime-services-framework)
4. [Power State Coordination Interface](#4--power-state-coordination-interface)
5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers)
-6. [Crash Reporting in BL31](#6--crash-reporting-in-bl3-1)
+6. [Crash Reporting in BL31](#6--crash-reporting-in-bl31)
7. [Guidelines for Reset Handlers](#7--guidelines-for-reset-handlers)
8. [CPU specific operations framework](#8--cpu-specific-operations-framework)
9. [Memory layout of BL images](#9-memory-layout-of-bl-images)
@@ -988,11 +988,11 @@
`reset_func()`, `core_pwr_dwn()`, `cluster_pwr_dwn()` and `cpu_reg_dump()`.
The CPU specific files in `lib/cpus` export a `cpu_ops` data structure with
-suitable handlers for that CPU. For example, `lib/cpus/cortex_a53.S` exports
-the `cpu_ops` for Cortex-A53 CPU. According to the platform configuration,
-these CPU specific files must must be included in the build by the platform
-makefile. The generic CPU specific operations framework code exists in
-`lib/cpus/aarch64/cpu_helpers.S`.
+suitable handlers for that CPU. For example, `lib/cpus/aarch64/cortex_a53.S`
+exports the `cpu_ops` for Cortex-A53 CPU. According to the platform
+configuration, these CPU specific files must be included in the build by
+the platform makefile. The generic CPU specific operations framework code exists
+in `lib/cpus/aarch64/cpu_helpers.S`.
### CPU specific Reset Handling
@@ -1020,12 +1020,12 @@
retrieved during power down sequences.
The PSCI service, upon receiving a power down request, determines the highest
-affinity level at which to execute power down sequence for a particular CPU and
+power level at which to execute power down sequence for a particular CPU and
invokes the corresponding 'prepare' power down handler in the CPU specific
-operations framework. For example, when a CPU executes a power down for affinity
+operations framework. For example, when a CPU executes a power down for power
level 0, the `prepare_core_pwr_dwn()` retrieves the `cpu_ops` pointer from the
per-CPU data and the corresponding `core_pwr_dwn()` is invoked. Similarly when
-a CPU executes power down at affinity level 1, the `prepare_cluster_pwr_dwn()`
+a CPU executes power down at power level 1, the `prepare_cluster_pwr_dwn()`
retrieves the `cpu_ops` pointer and the corresponding `cluster_pwr_dwn()` is
invoked.
@@ -1454,8 +1454,8 @@
images. The platform policy can be modified to allow additional images.
-11. Use of coherent memory in Trusted Firmware
-----------------------------------------------
+11. Use of coherent memory in Trusted Firmware
+-----------------------------------------------
There might be loss of coherency when physical memory with mismatched
shareability, cacheability and memory attributes is accessed by multiple CPUs
@@ -1739,5 +1739,5 @@
[Porting Guide]: ./porting-guide.md
[Reset Design]: ./reset-design.md
[INTRG]: ./interrupt-framework-design.md
-[CPUBM]: ./cpu-specific-build-macros.md.md
+[CPUBM]: ./cpu-specific-build-macros.md
[Firmware Update]: ./firmware-update.md
diff --git a/docs/firmware-update.md b/docs/firmware-update.md
index 419ac85..97df8cf 100644
--- a/docs/firmware-update.md
+++ b/docs/firmware-update.md
@@ -3,11 +3,11 @@
Contents :
-1. [Introduction](#1-introduction)
-2. [FWU Overview](#2-fwu-overview)
-3. [Image Identification](#3-image-identification)
-4. [FWU State Machine](#4-fwu-state-machine)
-5. [SMC Interface](#5-smc-interface)
+1. [Introduction](#1--introduction)
+2. [FWU Overview](#2--fwu-overview)
+3. [Image Identification](#3--image-identification)
+4. [FWU State Machine](#4--fwu-state-machine)
+5. [BL1 SMC Interface](#5--bl1-smc-interface)
- - - - - - - - - - - - - - - - - -
@@ -35,8 +35,8 @@
the TBBR.
-2. FWU Overview
----------------
+2. FWU Overview
+----------------
The FWU boot flow is primarily mediated by BL1. Since BL1 executes in ROM, and
it is usually desirable to minimize the amount of ROM code, the design allows
@@ -73,8 +73,8 @@
-3. Image Identification
------------------------
+3. Image Identification
+------------------------
Each FWU image and certificate is identified by a unique ID, defined by the
platform, which BL1 uses to fetch an image descriptor (`image_desc_t`) via a
@@ -135,7 +135,7 @@
5. BL1 SMC Interface
------------------
+---------------------
### BL1_SMC_CALL_COUNT
diff --git a/docs/interrupt-framework-design.md b/docs/interrupt-framework-design.md
index 060bbf2..e50d175 100644
--- a/docs/interrupt-framework-design.md
+++ b/docs/interrupt-framework-design.md
@@ -10,7 +10,7 @@
- [Valid Routing Models](#113-valid-routing-models)
+ [Secure-EL1 Interrupts](#1131-secure-el1-interrupts)
+ [Non-secure Interrupts](#1132-non-secure-interrupts)
- + [EL3 interrupts](#1133-el3_interrupts)
+ + [EL3 interrupts](#1133-el3-interrupts)
- [Mapping of Interrupt Type to Signal](#114-mapping-of-interrupt-type-to-signal)
+ [Effect of mapping of several interrupt types to one signal](#1141-effect-of-mapping-of-several-interrupt-types-to-one-signal)
- [Assumptions in Interrupt Management Framework](#12-assumptions-in-interrupt-management-framework)
diff --git a/docs/user-guide.md b/docs/user-guide.md
index 435a903..3337f88 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -495,7 +495,7 @@
# fip_create --help to print usage information
# fip_create <fip_name> <images to add> [--dump to show result]
./tools/fip_create/fip_create fip.bin --dump \
- --bl2 build/<platform>/debug/bl2.bin --bl31 build/<platform>/debug/bl31.bin
+ --tb-fw build/<platform>/debug/bl2.bin --soc-fw build/<platform>/debug/bl31.bin
Firmware Image Package ToC:
---------------------------
@@ -520,7 +520,7 @@
# Change the BL2 from Debug to Release version
./tools/fip_create/fip_create fip.bin --dump \
- --bl2 build/<platform>/release/bl2.bin
+ --tb-fw build/<platform>/release/bl2.bin
Firmware Image Package ToC:
---------------------------
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index bc381d5..5186f16 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -55,6 +55,5 @@
BL1_SOURCES += ${MBEDTLS_COMMON_SOURCES}
BL2_SOURCES += ${MBEDTLS_COMMON_SOURCES}
-DISABLE_PEDANTIC := 1
endif
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index 6a898dd..1a96e8f 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -174,7 +174,7 @@
/* Digest info should be an MBEDTLS_ASN1_SEQUENCE */
p = (unsigned char *)digest_info_ptr;
- end = (unsigned char *)(digest_info_ptr + digest_info_len);
+ end = p + digest_info_len;
rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED |
MBEDTLS_ASN1_SEQUENCE);
if (rc != 0) {
diff --git a/drivers/console/console.S b/drivers/console/console.S
index 40a6db9..b772363 100644
--- a/drivers/console/console.S
+++ b/drivers/console/console.S
@@ -79,6 +79,7 @@
mov x0, #0
adrp x3, console_base
str x0, [x3, :lo12:console_base]
+ ret
endfunc console_uninit
/* ---------------------------------------------
diff --git a/include/bl31/runtime_svc.h b/include/bl31/runtime_svc.h
index 30ba29f..87f2dd2 100644
--- a/include/bl31/runtime_svc.h
+++ b/include/bl31/runtime_svc.h
@@ -89,12 +89,12 @@
#define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \
static const rt_svc_desc_t __svc_desc_ ## _name \
__attribute__ ((section("rt_svc_descs"), used)) = { \
- _start, \
- _end, \
- _type, \
- #_name, \
- _setup, \
- _smch }
+ .start_oen = _start, \
+ .end_oen = _end, \
+ .call_type = _type, \
+ .name = #_name, \
+ .init = _setup, \
+ .handle = _smch }
/*
* Compile time assertions related to the 'rt_svc_desc' structure to:
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 0ec7a8d..e5e6717 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -202,8 +202,9 @@
* switching exception levels. The only two mechanisms to do so are
* ERET & SMC. Security state is indicated using bit zero of header
* attribute
- * NOTE: BL1 expects entrypoint followed by spsr while processing
- * SMC to jump to BL31 from the start of entry_point_info
+ * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
+ * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
+ * processing SMC to jump to BL31.
*****************************************************************************/
typedef struct entry_point_info {
param_header_t h;
@@ -232,13 +233,13 @@
typedef struct image_desc {
/* Contains unique image id for the image. */
unsigned int image_id;
- image_info_t image_info;
- entry_point_info_t ep_info;
/*
* This member contains Image state information.
* Refer IMAGE_STATE_XXX defined above.
*/
unsigned int state;
+ image_info_t image_info;
+ entry_point_info_t ep_info;
} image_desc_t;
/*******************************************************************************
diff --git a/include/drivers/auth/auth_mod.h b/include/drivers/auth/auth_mod.h
index 0f19b5c..4ed4684 100644
--- a/include/drivers/auth/auth_mod.h
+++ b/include/drivers/auth/auth_mod.h
@@ -48,8 +48,8 @@
*/
typedef struct auth_img_desc_s {
unsigned int img_id;
- const struct auth_img_desc_s *parent;
img_type_t img_type;
+ const struct auth_img_desc_s *parent;
auth_method_desc_t img_auth_methods[AUTH_METHOD_NUM];
auth_param_desc_t authenticated_data[COT_MAX_VERIFIED_PARAMS];
} auth_img_desc_t;
@@ -65,7 +65,7 @@
#define REGISTER_COT(_cot) \
const auth_img_desc_t *const cot_desc_ptr = \
(const auth_img_desc_t *const)&_cot[0]; \
- unsigned int auth_img_flags[sizeof(_cot)/sizeof(_cot[0])];
+ unsigned int auth_img_flags[sizeof(_cot)/sizeof(_cot[0])]
#endif /* TRUSTED_BOARD_BOOT */
diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h
new file mode 100644
index 0000000..4288b9f
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CORTEX_A35_H__
+#define __CORTEX_A35_H__
+
+/* Cortex-A35 Main ID register for revision 0 */
+#define CORTEX_A35_MIDR 0x410FD040
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ * CPUECTLR_EL1 is an implementation-specific register.
+ ******************************************************************************/
+#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
+#define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6)
+
+#endif /* __CORTEX_A35_H__ */
diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S
new file mode 100644
index 0000000..6a447c0
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a35.S
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <bl_common.h>
+#include <cortex_a35.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+ /* ---------------------------------------------
+ * Disable L1 data cache and unified L2 cache
+ * ---------------------------------------------
+ */
+func cortex_a35_disable_dcache
+ mrs x1, sctlr_el3
+ bic x1, x1, #SCTLR_C_BIT
+ msr sctlr_el3, x1
+ isb
+ ret
+endfunc cortex_a35_disable_dcache
+
+ /* ---------------------------------------------
+ * Disable intra-cluster coherency
+ * ---------------------------------------------
+ */
+func cortex_a35_disable_smp
+ mrs x0, CORTEX_A35_CPUECTLR_EL1
+ bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
+ msr CORTEX_A35_CPUECTLR_EL1, x0
+ isb
+ dsb sy
+ ret
+endfunc cortex_a35_disable_smp
+
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A35.
+ * Clobbers: x0
+ * -------------------------------------------------
+ */
+func cortex_a35_reset_func
+ /* ---------------------------------------------
+ * As a bare minimum enable the SMP bit if it is
+ * not already set.
+ * ---------------------------------------------
+ */
+ mrs x0, CORTEX_A35_CPUECTLR_EL1
+ tst x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
+ b.ne skip_smp_setup
+ orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
+ msr CORTEX_A35_CPUECTLR_EL1, x0
+skip_smp_setup:
+ isb
+ ret
+endfunc cortex_a35_reset_func
+
+func cortex_a35_core_pwr_dwn
+ mov x18, x30
+
+ /* ---------------------------------------------
+ * Turn off caches.
+ * ---------------------------------------------
+ */
+ bl cortex_a35_disable_dcache
+
+ /* ---------------------------------------------
+ * Flush L1 caches.
+ * ---------------------------------------------
+ */
+ mov x0, #DCCISW
+ bl dcsw_op_level1
+
+ /* ---------------------------------------------
+ * Come out of intra cluster coherency
+ * ---------------------------------------------
+ */
+ mov x30, x18
+ b cortex_a35_disable_smp
+endfunc cortex_a35_core_pwr_dwn
+
+func cortex_a35_cluster_pwr_dwn
+ mov x18, x30
+
+ /* ---------------------------------------------
+ * Turn off caches.
+ * ---------------------------------------------
+ */
+ bl cortex_a35_disable_dcache
+
+ /* ---------------------------------------------
+ * Flush L1 caches.
+ * ---------------------------------------------
+ */
+ mov x0, #DCCISW
+ bl dcsw_op_level1
+
+ /* ---------------------------------------------
+ * Disable the optional ACP.
+ * ---------------------------------------------
+ */
+ bl plat_disable_acp
+
+ /* ---------------------------------------------
+ * Flush L2 caches.
+ * ---------------------------------------------
+ */
+ mov x0, #DCCISW
+ bl dcsw_op_level2
+
+ /* ---------------------------------------------
+ * Come out of intra cluster coherency
+ * ---------------------------------------------
+ */
+ mov x30, x18
+ b cortex_a35_disable_smp
+endfunc cortex_a35_cluster_pwr_dwn
+
+ /* ---------------------------------------------
+ * This function provides cortex_a35 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a35_regs, "aS"
+cortex_a35_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a35_cpu_reg_dump
+ adr x6, cortex_a35_regs
+ mrs x8, CORTEX_A35_CPUECTLR_EL1
+ ret
+endfunc cortex_a35_cpu_reg_dump
+
+declare_cpu_ops cortex_a35, CORTEX_A35_MIDR
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 00fb92c..d6a4e3a 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -126,7 +126,7 @@
# FWU_FIP_ADD_PAYLOAD appends the command line arguments required by the FIP tool
# to package a new FWU payload. Optionally, it adds the dependency on this payload
# $(1) = payload filename (e.g. ns_bl2u.bin)
-# $(2) = command line option for the specified payload (e.g. --ns_bl2u)
+# $(2) = command line option for the specified payload (e.g. --fwu)
# $(3) = fip target dependency (optional) (e.g. ns_bl2u)
define FWU_FIP_ADD_PAYLOAD
$(eval $(if $(3),FWU_FIP_DEPS += $(3)))
@@ -285,16 +285,16 @@
# each BL image. Arguments:
# $(1) = BL stage (2, 30, 31, 32, 33)
# $(2) = Binary file
-# $(3) = In FIP (false if empty)
+# $(3) = FIP command line option (if empty, image will not be included in the FIP)
define MAKE_TOOL_ARGS
- $(if $(3),$(eval $(call FIP_ADD_PAYLOAD,$(2),--bl$(1),bl$(1))))
+ $(if $(3),$(eval $(call FIP_ADD_PAYLOAD,$(2),--$(3),bl$(1))))
endef
# MAKE_BL macro defines the targets and options to build each BL image.
# Arguments:
# $(1) = BL stage (2, 2u, 30, 31, 32, 33)
-# $(2) = In FIP (false if empty)
+# $(2) = FIP command line option (if empty, image will not be included in the FIP)
define MAKE_BL
$(eval BUILD_DIR := ${BUILD_PLAT}/bl$(1))
$(eval BL_SOURCES := $(BL$(call uppercase,$(1))_SOURCES))
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index cb5f5d7..22df6d7 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -64,6 +64,7 @@
BL1_SOURCES += drivers/io/io_semihosting.c \
lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a35.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/semihosting/semihosting.c \
@@ -87,6 +88,7 @@
plat/arm/board/fvp/fvp_security.c
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a35.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/arm/board/fvp/fvp_bl31_setup.c \
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 4ac12d9..0748f92 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -140,7 +140,7 @@
BL2_SOURCES += ${AUTH_SOURCES}
- $(eval $(call FWU_FIP_ADD_IMG,NS_BL2U,--ns_bl2u))
+ $(eval $(call FWU_FIP_ADD_IMG,NS_BL2U,--fwu))
MBEDTLS_KEY_ALG := ${KEY_ALG}
diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk
index aabcb46..6a8773d 100644
--- a/plat/arm/css/common/css_common.mk
+++ b/plat/arm/css/common/css_common.mk
@@ -52,7 +52,7 @@
plat/arm/css/common/css_topology.c
ifneq (${TRUSTED_BOARD_BOOT},0)
-$(eval $(call FWU_FIP_ADD_IMG,SCP_BL2U,--scp_bl2u))
+$(eval $(call FWU_FIP_ADD_IMG,SCP_BL2U,--scp-fwu-cfg))
endif
ifneq (${RESET_TO_BL31},0)
@@ -61,7 +61,7 @@
endif
# Subsystems require a SCP_BL2 image
-$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp_bl2))
+$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
# Enable option to detect whether the SCP ROM firmware in use predates version
# 1.7.0 and therefore, is incompatible.
diff --git a/tools/cert_create/include/cert.h b/tools/cert_create/include/cert.h
index d38353a..6b1ae95 100644
--- a/tools/cert_create/include/cert.h
+++ b/tools/cert_create/include/cert.h
@@ -77,7 +77,7 @@
/* Macro to register the certificates used in the CoT */
#define REGISTER_COT(_certs) \
cert_t *certs = &_certs[0]; \
- const unsigned int num_certs = sizeof(_certs)/sizeof(_certs[0]);
+ const unsigned int num_certs = sizeof(_certs)/sizeof(_certs[0])
/* Exported variables */
extern cert_t *certs;
diff --git a/tools/cert_create/include/ext.h b/tools/cert_create/include/ext.h
index 52092b5..82a4bcb 100644
--- a/tools/cert_create/include/ext.h
+++ b/tools/cert_create/include/ext.h
@@ -93,7 +93,7 @@
/* Macro to register the extensions used in the CoT */
#define REGISTER_EXTENSIONS(_ext) \
ext_t *extensions = &_ext[0]; \
- const unsigned int num_extensions = sizeof(_ext)/sizeof(_ext[0]);
+ const unsigned int num_extensions = sizeof(_ext)/sizeof(_ext[0])
/* Exported variables */
extern ext_t *extensions;
diff --git a/tools/cert_create/include/key.h b/tools/cert_create/include/key.h
index 2171679..f60997f 100644
--- a/tools/cert_create/include/key.h
+++ b/tools/cert_create/include/key.h
@@ -80,7 +80,7 @@
/* Macro to register the keys used in the CoT */
#define REGISTER_KEYS(_keys) \
key_t *keys = &_keys[0]; \
- const unsigned int num_keys = sizeof(_keys)/sizeof(_keys[0]);
+ const unsigned int num_keys = sizeof(_keys)/sizeof(_keys[0])
/* Exported variables */
extern key_t *keys;
diff --git a/tools/fip_create/fip_create.c b/tools/fip_create/fip_create.c
index f0d0791..19afc74 100644
--- a/tools/fip_create/fip_create.c
+++ b/tools/fip_create/fip_create.c
@@ -56,23 +56,23 @@
/* The images used depends on the platform. */
static entry_lookup_list_t toc_entry_lookup_list[] = {
{ "SCP Firmware Updater Configuration FWU SCP_BL2U", UUID_TRUSTED_UPDATE_FIRMWARE_SCP_BL2U,
- "scp_bl2u", NULL, FLAG_FILENAME },
+ "scp-fwu-cfg", NULL, FLAG_FILENAME },
{ "AP Firmware Updater Configuration BL2U", UUID_TRUSTED_UPDATE_FIRMWARE_BL2U,
- "bl2u", NULL, FLAG_FILENAME },
+ "ap-fwu-cfg", NULL, FLAG_FILENAME },
{ "Firmware Updater NS_BL2U", UUID_TRUSTED_UPDATE_FIRMWARE_NS_BL2U,
- "ns_bl2u", NULL, FLAG_FILENAME },
+ "fwu", NULL, FLAG_FILENAME },
{ "Non-Trusted Firmware Updater certificate", UUID_TRUSTED_FWU_CERT,
"fwu-cert", NULL, FLAG_FILENAME},
{ "Trusted Boot Firmware BL2", UUID_TRUSTED_BOOT_FIRMWARE_BL2,
- "bl2", NULL, FLAG_FILENAME },
+ "tb-fw", NULL, FLAG_FILENAME },
{ "SCP Firmware SCP_BL2", UUID_SCP_FIRMWARE_SCP_BL2,
- "scp_bl2", NULL, FLAG_FILENAME},
+ "scp-fw", NULL, FLAG_FILENAME},
{ "EL3 Runtime Firmware BL31", UUID_EL3_RUNTIME_FIRMWARE_BL31,
- "bl31", NULL, FLAG_FILENAME},
+ "soc-fw", NULL, FLAG_FILENAME},
{ "Secure Payload BL32 (Trusted OS)", UUID_SECURE_PAYLOAD_BL32,
- "bl32", NULL, FLAG_FILENAME},
+ "tos-fw", NULL, FLAG_FILENAME},
{ "Non-Trusted Firmware BL33", UUID_NON_TRUSTED_FIRMWARE_BL33,
- "bl33", NULL, FLAG_FILENAME},
+ "nt-fw", NULL, FLAG_FILENAME},
/* Key Certificates */
{ "Root Of Trust key certificate", UUID_ROT_KEY_CERT,
"rot-cert", NULL, FLAG_FILENAME },