Merge changes I2f4961fe,I0039c724,Iaa3076c1,Ic19973a8 into integration
* changes:
feat(bl32): print entry point before exiting SP_MIN
fix(bl32): avoid clearing argument registers in RESET_TO_SP_MIN case
fix(bl32): always include arm_arch_svc in SP_MIN
fix(services): disable workaround discovery on aarch32 for now
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index f102967..693dd4b 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,11 +62,8 @@
* The Cold boot/Reset entrypoint for SP_MIN
*/
func sp_min_entrypoint
-#if !RESET_TO_SP_MIN
/* ---------------------------------------------------------------
- * Preceding bootloader has populated r0 with a pointer to a
- * 'bl_params_t' structure & r1 with a pointer to platform
- * specific structure
+ * Stash the previous bootloader arguments r0 - r3 for later use.
* ---------------------------------------------------------------
*/
mov r9, r0
@@ -74,6 +71,7 @@
mov r11, r2
mov r12, r3
+#if !RESET_TO_SP_MIN
/* ---------------------------------------------------------------------
* For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
* sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
@@ -91,11 +89,6 @@
_init_c_runtime=1 \
_exception_vectors=sp_min_vector_table \
_pie_fixup_size=FIXUP_SIZE
-
- /* ---------------------------------------------------------------------
- * Relay the previous bootloader's arguments to the platform layer
- * ---------------------------------------------------------------------
- */
#else
/* ---------------------------------------------------------------------
* For RESET_TO_SP_MIN systems which have a programmable reset address,
@@ -111,24 +104,16 @@
_init_c_runtime=1 \
_exception_vectors=sp_min_vector_table \
_pie_fixup_size=FIXUP_SIZE
-
- /* ---------------------------------------------------------------------
- * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
- * to run so there's no argument to relay from a previous bootloader.
- * Zero the arguments passed to the platform layer to reflect that.
- * ---------------------------------------------------------------------
- */
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
-
#endif /* RESET_TO_SP_MIN */
#if SP_MIN_WITH_SECURE_FIQ
route_fiq_to_sp_min r4
#endif
+ /* ---------------------------------------------------------------------
+ * Relay the previous bootloader's arguments to the platform layer
+ * ---------------------------------------------------------------------
+ */
mov r0, r9
mov r1, r10
mov r2, r11
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index 0b7bc57..065468c 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -17,6 +17,7 @@
bl32/sp_min/aarch32/entrypoint.S \
common/runtime_svc.c \
plat/common/aarch32/plat_sp_min_common.c\
+ services/arm_arch_svc/arm_arch_svc_setup.c \
services/std_svc/std_svc_setup.c \
${PSCI_LIB_SOURCES}
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index f050160..26cf207 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -134,6 +134,7 @@
assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
INFO("SP_MIN: Preparing exit to normal world\n");
+ print_entry_point_info(next_image_info);
psci_prepare_next_non_secure_ctx(next_image_info);
smc_set_next_ctx(NON_SECURE);
diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
index f5184e7..9695c9b 100644
--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
+++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
@@ -48,6 +48,3 @@
BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
plat/st/stm32mp1/services/stm32mp1_svc_setup.c \
plat/st/stm32mp1/stm32mp1_scmi.c
-
-# Arm Archtecture services
-BL32_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index bb042c7..57d211e 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,8 @@
return SMC_ARCH_CALL_SUCCESS;
case SMCCC_ARCH_SOC_ID:
return plat_is_smccc_feature_available(arg1);
+#ifdef __aarch64__
+ /* Workaround checks are currently only implemented for aarch64 */
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
@@ -88,6 +90,7 @@
}
return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
#endif
+#endif /* __aarch64__ */
/* Fallthrough */
@@ -128,6 +131,7 @@
SMC_RET1(handle, smccc_arch_features(x1));
case SMCCC_ARCH_SOC_ID:
SMC_RET1(handle, smccc_arch_id(x1));
+#ifdef __aarch64__
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
/*
@@ -156,6 +160,7 @@
*/
SMC_RET0(handle);
#endif
+#endif /* __aarch64__ */
default:
WARN("Unimplemented Arm Architecture Service Call: 0x%x \n",
smc_fid);