Merge pull request #1663 from sudeep-holla/scpi_build_fix
plat: juno: fix build for !CSS_USE_SCMI_DRIVER
diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c
index b9304dc..9bfb309 100644
--- a/bl1/aarch64/bl1_context_mgmt.c
+++ b/bl1/aarch64/bl1_context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,9 +49,9 @@
* Ensure that the build flag to save AArch32 system registers in CPU
* context is not set for AArch64-only platforms.
*/
- if (EL_IMPLEMENTED(1) == EL_IMPL_A64ONLY) {
+ if (el_implemented(1) == EL_IMPL_A64ONLY) {
ERROR("EL1 supports AArch64-only. Please set build flag "
- "CTX_INCLUDE_AARCH32_REGS = 0");
+ "CTX_INCLUDE_AARCH32_REGS = 0\n");
panic();
}
#endif
@@ -76,7 +76,7 @@
DISABLE_ALL_EXCEPTIONS);
} else {
/* Use EL2 if supported; else use EL1. */
- if (EL_IMPLEMENTED(2)) {
+ if (el_implemented(2) != EL_IMPL_NONE) {
next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
} else {
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 62bea01..77b59ed 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -159,9 +159,9 @@
* Ensure that the build flag to save AArch32 system registers in CPU
* context is not set for AArch64-only platforms.
*/
- if (EL_IMPLEMENTED(1) == EL_IMPL_A64ONLY) {
+ if (el_implemented(1) == EL_IMPL_A64ONLY) {
ERROR("EL1 supports AArch64-only. Please set build flag "
- "CTX_INCLUDE_AARCH32_REGS = 0");
+ "CTX_INCLUDE_AARCH32_REGS = 0\n");
panic();
}
#endif
diff --git a/include/common/ep_info.h b/include/common/ep_info.h
index bf3f782..db2355a 100644
--- a/include/common/ep_info.h
+++ b/include/common/ep_info.h
@@ -30,7 +30,7 @@
#define PARAM_EP_SECURITY_MASK U(0x1)
/* Secure or Non-secure image */
-#define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK)
+#define GET_SECURITY_STATE(x) ((x) & PARAM_EP_SECURITY_MASK)
#define SET_SECURITY_STATE(x, security) \
((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security))
diff --git a/include/drivers/arm/tzc_common.h b/include/drivers/arm/tzc_common.h
index dac79aa..4b81547 100644
--- a/include/drivers/arm/tzc_common.h
+++ b/include/drivers/arm/tzc_common.h
@@ -73,10 +73,10 @@
/* Macros for allowing Non-Secure access to a region based on NSAID */
#define TZC_REGION_ACCESS_RD(nsaid) \
- ((U(1) << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \
+ ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
TZC_REGION_ACCESS_RD_EN_SHIFT)
#define TZC_REGION_ACCESS_WR(nsaid) \
- ((U(1) << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \
+ ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
TZC_REGION_ACCESS_WR_EN_SHIFT)
#define TZC_REGION_ACCESS_RDWR(nsaid) \
(TZC_REGION_ACCESS_RD(nsaid) | \
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h
index 5d9c1c1..03f0e86 100644
--- a/include/lib/aarch32/arch_helpers.h
+++ b/include/lib/aarch32/arch_helpers.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __ARCH_HELPERS_H__
-#define __ARCH_HELPERS_H__
+#ifndef ARCH_HELPERS_H
+#define ARCH_HELPERS_H
#include <arch.h> /* for additional register definitions */
#include <cdefs.h>
@@ -381,4 +381,4 @@
#define write_icc_sgi0r_el1(_v) \
write64_icc_sgi0r_el1(_v)
-#endif /* __ARCH_HELPERS_H__ */
+#endif /* ARCH_HELPERS_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index d90061f..61f9830 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -4,11 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __ARCH_HELPERS_H__
-#define __ARCH_HELPERS_H__
+#ifndef ARCH_HELPERS_H
+#define ARCH_HELPERS_H
#include <arch.h> /* for additional register definitions */
#include <cdefs.h> /* For __dead2 */
+#include <stdbool.h>
#include <stdint.h>
#include <string.h>
@@ -363,12 +364,22 @@
}
/*
- * Check if an EL is implemented from AA64PFR0 register fields. 'el' argument
- * must be one of 1, 2 or 3.
+ * Check if an EL is implemented from AA64PFR0 register fields.
*/
-#define EL_IMPLEMENTED(el) \
- ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL##el##_SHIFT) \
- & ID_AA64PFR0_ELX_MASK)
+static inline uint64_t el_implemented(unsigned int el)
+{
+ if (el > 3U) {
+ return EL_IMPL_NONE;
+ } else {
+ unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
+
+ return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
+ }
+}
+
+#if !ERROR_DEPRECATED
+#define EL_IMPLEMENTED(_el) el_implemented(_el)
+#endif
/* Previously defined accesor functions with incomplete register names */
@@ -389,4 +400,4 @@
#define read_cpacr() read_cpacr_el1()
#define write_cpacr(_v) write_cpacr_el1(_v)
-#endif /* __ARCH_HELPERS_H__ */
+#endif /* ARCH_HELPERS_H */
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index c80082e..2d1612e 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __BAKERY_LOCK_H__
-#define __BAKERY_LOCK_H__
+#ifndef BAKERY_LOCK_H
+#define BAKERY_LOCK_H
#include <platform_def.h>
@@ -13,21 +13,39 @@
#ifndef __ASSEMBLY__
#include <cdefs.h>
+#include <stdbool.h>
#include <stdint.h>
+#include <utils_def.h>
/*****************************************************************************
- * Internal helper macros used by the bakery lock implementation.
+ * Internal helpers used by the bakery lock implementation.
****************************************************************************/
+
/* Convert a ticket to priority */
-#define PRIORITY(t, pos) (((t) << 8) | (pos))
+static inline unsigned int bakery_get_priority(unsigned int t, unsigned int pos)
+{
+ return (t << 8) | pos;
+}
+
+#define CHOOSING_TICKET U(0x1)
+#define CHOSEN_TICKET U(0x0)
-#define CHOOSING_TICKET 0x1
-#define CHOSEN_TICKET 0x0
+static inline bool bakery_is_choosing(unsigned int info)
+{
+ return (info & 1U) == CHOOSING_TICKET;
+}
-#define bakery_is_choosing(info) (info & 0x1)
-#define bakery_ticket_number(info) ((info >> 1) & 0x7FFF)
-#define make_bakery_data(choosing, number) \
- (((choosing & 0x1) | (number << 1)) & 0xFFFF)
+static inline unsigned int bakery_ticket_number(unsigned int info)
+{
+ return (info >> 1) & 0x7FFFU;
+}
+
+static inline uint16_t make_bakery_data(unsigned int choosing, unsigned int num)
+{
+ unsigned int val = (choosing & 0x1U) | (num << 1);
+
+ return (uint16_t) val;
+}
/*****************************************************************************
* External bakery lock interface.
@@ -83,4 +101,4 @@
#endif /* __ASSEMBLY__ */
-#endif /* __BAKERY_LOCK_H__ */
+#endif /* BAKERY_LOCK_H */
diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h
index 6447360..1ea19ca 100644
--- a/include/lib/el3_runtime/aarch32/context.h
+++ b/include/lib/el3_runtime/aarch32/context.h
@@ -1,26 +1,28 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __CONTEXT_H__
-#define __CONTEXT_H__
+#ifndef CONTEXT_H
+#define CONTEXT_H
+
+#include <utils_def.h>
/*******************************************************************************
* Constants that allow assembler code to access members of and the 'regs'
* structure at their correct offsets.
******************************************************************************/
-#define CTX_REGS_OFFSET 0x0
-#define CTX_GPREG_R0 0x0
-#define CTX_GPREG_R1 0x4
-#define CTX_GPREG_R2 0x8
-#define CTX_GPREG_R3 0xC
-#define CTX_LR 0x10
-#define CTX_SCR 0x14
-#define CTX_SPSR 0x18
-#define CTX_NS_SCTLR 0x1C
-#define CTX_REGS_END 0x20
+#define CTX_REGS_OFFSET U(0x0)
+#define CTX_GPREG_R0 U(0x0)
+#define CTX_GPREG_R1 U(0x4)
+#define CTX_GPREG_R2 U(0x8)
+#define CTX_GPREG_R3 U(0xC)
+#define CTX_LR U(0x10)
+#define CTX_SCR U(0x14)
+#define CTX_SPSR U(0x18)
+#define CTX_NS_SCTLR U(0x1C)
+#define CTX_REGS_END U(0x20)
#ifndef __ASSEMBLY__
@@ -31,7 +33,7 @@
* Common constants to help define the 'cpu_context' structure and its
* members below.
*/
-#define WORD_SHIFT 2
+#define WORD_SHIFT U(2)
#define DEFINE_REG_STRUCT(name, num_regs) \
typedef struct name { \
uint32_t _regs[num_regs]; \
@@ -64,4 +66,4 @@
#endif /* __ASSEMBLY__ */
-#endif /* __CONTEXT_H__ */
+#endif /* CONTEXT_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index b990674..8c5f4c6 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __CONTEXT_H__
-#define __CONTEXT_H__
+#ifndef CONTEXT_H
+#define CONTEXT_H
#include <utils_def.h>
@@ -347,4 +347,4 @@
#endif /* __ASSEMBLY__ */
-#endif /* __CONTEXT_H__ */
+#endif /* CONTEXT_H */
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index c5bbb2b..149ac3f 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -1,16 +1,15 @@
/*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __CM_H__
-#define __CM_H__
+#ifndef CONTEXT_MGMT_H
+#define CONTEXT_MGMT_H
#include <arch.h>
#include <assert.h>
#include <context.h>
-#include <context_mgmt.h>
#include <stdint.h>
/*******************************************************************************
@@ -80,4 +79,4 @@
void cm_set_next_context(void *context);
#endif /* AARCH32 */
-#endif /* __CM_H__ */
+#endif /* CONTEXT_MGMT_H */
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index b695950..561f8be 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -144,9 +144,9 @@
void init_cpu_ops(void);
#define get_cpu_data(_m) _cpu_data()->_m
-#define set_cpu_data(_m, _v) _cpu_data()->_m = _v
+#define set_cpu_data(_m, _v) _cpu_data()->_m = (_v)
#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
-#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v
+#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = (_v)
/* ((cpu_data_t *)0)->_m is a dummy to get the sizeof the struct member _m */
#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
&(_cpu_data()->_m), \
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
index 8aec707..fcd36e8 100644
--- a/include/lib/spinlock.h
+++ b/include/lib/spinlock.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __SPINLOCK_H__
-#define __SPINLOCK_H__
+#ifndef SPINLOCK_H
+#define SPINLOCK_H
#ifndef __ASSEMBLY__
@@ -26,4 +26,4 @@
#endif
-#endif /* __SPINLOCK_H__ */
+#endif /* SPINLOCK_H */
diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h
index 4a1d43c..ed57fc9 100644
--- a/include/plat/arm/board/common/v2m_def.h
+++ b/include/plat/arm/board/common/v2m_def.h
@@ -48,9 +48,9 @@
#define V2M_SYS_LED_EL_SHIFT 0x1
#define V2M_SYS_LED_EC_SHIFT 0x3
-#define V2M_SYS_LED_SS_MASK 0x1
-#define V2M_SYS_LED_EL_MASK 0x3
-#define V2M_SYS_LED_EC_MASK 0x1f
+#define V2M_SYS_LED_SS_MASK U(0x1)
+#define V2M_SYS_LED_EL_MASK U(0x3)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
/* V2M sysid register bits */
#define V2M_SYS_ID_REV_SHIFT 28
@@ -59,28 +59,28 @@
#define V2M_SYS_ID_ARCH_SHIFT 8
#define V2M_SYS_ID_FPGA_SHIFT 0
-#define V2M_SYS_ID_REV_MASK 0xf
-#define V2M_SYS_ID_HBI_MASK 0xfff
-#define V2M_SYS_ID_BLD_MASK 0xf
-#define V2M_SYS_ID_ARCH_MASK 0xf
-#define V2M_SYS_ID_FPGA_MASK 0xff
+#define V2M_SYS_ID_REV_MASK U(0xf)
+#define V2M_SYS_ID_HBI_MASK U(0xfff)
+#define V2M_SYS_ID_BLD_MASK U(0xf)
+#define V2M_SYS_ID_ARCH_MASK U(0xf)
+#define V2M_SYS_ID_FPGA_MASK U(0xff)
#define V2M_SYS_ID_BLD_LENGTH 4
/* NOR Flash */
-#define V2M_FLASH0_BASE 0x08000000
-#define V2M_FLASH0_SIZE 0x04000000
-#define V2M_FLASH_BLOCK_SIZE 0x00040000 /* 256 KB */
+#define V2M_FLASH0_BASE UL(0x08000000)
+#define V2M_FLASH0_SIZE UL(0x04000000)
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
-#define V2M_IOFPGA_BASE 0x1c000000
-#define V2M_IOFPGA_SIZE 0x03000000
+#define V2M_IOFPGA_BASE UL(0x1c000000)
+#define V2M_IOFPGA_SIZE UL(0x03000000)
/* PL011 UART related constants */
-#define V2M_IOFPGA_UART0_BASE 0x1c090000
-#define V2M_IOFPGA_UART1_BASE 0x1c0a0000
-#define V2M_IOFPGA_UART2_BASE 0x1c0b0000
-#define V2M_IOFPGA_UART3_BASE 0x1c0c0000
+#define V2M_IOFPGA_UART0_BASE UL(0x1c090000)
+#define V2M_IOFPGA_UART1_BASE UL(0x1c0a0000)
+#define V2M_IOFPGA_UART2_BASE UL(0x1c0b0000)
+#define V2M_IOFPGA_UART3_BASE UL(0x1c0c0000)
#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000
#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000
@@ -88,15 +88,15 @@
#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000
/* SP804 timer related constants */
-#define V2M_SP804_TIMER0_BASE 0x1C110000
-#define V2M_SP804_TIMER1_BASE 0x1C120000
+#define V2M_SP804_TIMER0_BASE UL(0x1C110000)
+#define V2M_SP804_TIMER1_BASE UL(0x1C120000)
/* SP810 controller */
-#define V2M_SP810_BASE 0x1c020000
-#define V2M_SP810_CTRL_TIM0_SEL (1 << 15)
-#define V2M_SP810_CTRL_TIM1_SEL (1 << 17)
-#define V2M_SP810_CTRL_TIM2_SEL (1 << 19)
-#define V2M_SP810_CTRL_TIM3_SEL (1 << 21)
+#define V2M_SP810_BASE UL(0x1c020000)
+#define V2M_SP810_CTRL_TIM0_SEL BIT_32(15)
+#define V2M_SP810_CTRL_TIM1_SEL BIT_32(17)
+#define V2M_SP810_CTRL_TIM2_SEL BIT_32(19)
+#define V2M_SP810_CTRL_TIM3_SEL BIT_32(21)
/*
* The flash can be mapped either as read-only or read-write.
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 0f5b57f..088d59d 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -21,7 +21,7 @@
*****************************************************************************/
/* Special value used to verify platform parameters from BL2 to BL31 */
-#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
+#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
#define ARM_SYSTEM_COUNT 1
@@ -350,8 +350,8 @@
* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space of BL2 meminfo.
*/
-#define ARM_TB_FW_CONFIG_BASE ARM_BL_RAM_BASE + sizeof(meminfo_t)
-#define ARM_TB_FW_CONFIG_LIMIT ARM_BL_RAM_BASE + PAGE_SIZE
+#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
/*******************************************************************************
* BL1 specific defines.
@@ -482,7 +482,7 @@
# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
- + (1 << 21))
+ + (UL(1) << 21))
# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
@@ -511,7 +511,7 @@
#define BL2U_LIMIT BL2_LIMIT
#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
-#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
+#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
/*
* ID of the secure physical generic timer interrupt used by the TSP.
diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h
index cb17c95..3ad6d54 100644
--- a/include/plat/arm/common/arm_dyn_cfg_helpers.h
+++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h
@@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __ARM_DYN_CFG_HELPERS_H__
-#define __ARM_DYN_CFG_HELPERS_H__
+#ifndef ARM_DYN_CFG_HELPERS_H
+#define ARM_DYN_CFG_HELPERS_H
#include <stddef.h>
#include <stdint.h>
@@ -19,4 +19,4 @@
int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr,
size_t heap_size);
-#endif /* __ARM_DYN_CFG_HELPERS_H__ */
+#endif /* ARM_DYN_CFG_HELPERS_H */
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 80cea28..ad0a120 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -57,7 +57,7 @@
uint32_t scr, sctlr;
regs_t *reg_ctx;
- assert(ctx);
+ assert(ctx != NULL);
security_state = GET_SECURITY_STATE(ep->h.attr);
@@ -97,7 +97,7 @@
assert(((ep->spsr >> SPSR_E_SHIFT) & SPSR_E_MASK) ==
(EP_GET_EE(ep->h.attr) >> EP_EE_SHIFT));
- sctlr = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0;
+ sctlr = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
sctlr |= (SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_V_BIT));
write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr);
}
@@ -178,11 +178,11 @@
cpu_context_t *ctx = cm_get_context(security_state);
bool el2_unused = false;
- assert(ctx);
+ assert(ctx != NULL);
if (security_state == NON_SECURE) {
scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR);
- if (scr & SCR_HCE_BIT) {
+ if ((scr & SCR_HCE_BIT) != 0U) {
/* Use SCTLR value to initialize HSCTLR */
hsctlr = read_ctx_reg(get_regs_ctx(ctx),
CTX_NS_SCTLR);
@@ -199,8 +199,8 @@
write_scr(read_scr() & ~SCR_NS_BIT);
isb();
- } else if (read_id_pfr1() &
- (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) {
+ } else if ((read_id_pfr1() &
+ (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) != 0U) {
el2_unused = true;
/*
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index f037e18..39c27d0 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -68,7 +68,7 @@
gp_regs_t *gp_regs;
unsigned long sctlr_elx, actlr_elx;
- assert(ctx);
+ assert(ctx != NULL);
security_state = GET_SECURITY_STATE(ep->h.attr);
@@ -84,7 +84,7 @@
* the required value depending on the state of the SPSR_EL3 and the
* Security state and entrypoint attributes of the next EL.
*/
- scr_el3 = read_scr();
+ scr_el3 = (uint32_t)read_scr();
scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
SCR_ST_BIT | SCR_HCE_BIT);
/*
@@ -103,7 +103,7 @@
* Secure timer registers to EL3, from AArch64 state only, if specified
* by the entrypoint attributes.
*/
- if (EP_GET_ST(ep->h.attr))
+ if (EP_GET_ST(ep->h.attr) != 0U)
scr_el3 |= SCR_ST_BIT;
#if !HANDLE_EA_EL3_FIRST
@@ -133,10 +133,9 @@
* AArch64 and next EL is EL2, or if next execution state is AArch32 and
* next mode is Hyp.
*/
- if ((GET_RW(ep->spsr) == MODE_RW_64
- && GET_EL(ep->spsr) == MODE_EL2)
- || (GET_RW(ep->spsr) != MODE_RW_64
- && GET_M32(ep->spsr) == MODE32_hyp)) {
+ if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
+ || ((GET_RW(ep->spsr) != MODE_RW_64)
+ && (GET_M32(ep->spsr) == MODE32_hyp))) {
scr_el3 |= SCR_HCE_BIT;
}
@@ -151,7 +150,7 @@
* SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
* required by PSCI specification)
*/
- sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0;
+ sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
if (GET_RW(ep->spsr) == MODE_RW_64)
sctlr_elx |= SCTLR_EL1_RES1;
else {
@@ -291,20 +290,21 @@
uint32_t sctlr_elx, scr_el3, mdcr_el2;
cpu_context_t *ctx = cm_get_context(security_state);
bool el2_unused = false;
- uint64_t hcr_el2 = 0;
+ uint64_t hcr_el2 = 0U;
- assert(ctx);
+ assert(ctx != NULL);
if (security_state == NON_SECURE) {
- scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
- if (scr_el3 & SCR_HCE_BIT) {
+ scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx),
+ CTX_SCR_EL3);
+ if ((scr_el3 & SCR_HCE_BIT) != 0U) {
/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
- sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx),
- CTX_SCTLR_EL1);
+ sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx),
+ CTX_SCTLR_EL1);
sctlr_elx &= SCTLR_EE_BIT;
sctlr_elx |= SCTLR_EL2_RES1;
write_sctlr_el2(sctlr_elx);
- } else if (EL_IMPLEMENTED(2)) {
+ } else if (el_implemented(2) != EL_IMPL_NONE) {
el2_unused = true;
/*
@@ -314,7 +314,7 @@
* Set EL2 register width appropriately: Set HCR_EL2
* field to match SCR_EL3.RW.
*/
- if (scr_el3 & SCR_RW_BIT)
+ if ((scr_el3 & SCR_RW_BIT) != 0U)
hcr_el2 |= HCR_RW_BIT;
/*
@@ -470,7 +470,7 @@
cpu_context_t *ctx;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
el1_sysregs_context_save(get_sysregs_ctx(ctx));
@@ -487,7 +487,7 @@
cpu_context_t *ctx;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
el1_sysregs_context_restore(get_sysregs_ctx(ctx));
@@ -509,7 +509,7 @@
el3_state_t *state;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
/* Populate EL3 state so that ERET jumps to the correct entry */
state = get_el3state_ctx(ctx);
@@ -527,7 +527,7 @@
el3_state_t *state;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
/* Populate EL3 state so that ERET jumps to the correct entry */
state = get_el3state_ctx(ctx);
@@ -549,21 +549,21 @@
uint32_t scr_el3;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
/* Ensure that the bit position is a valid one */
- assert((1 << bit_pos) & SCR_VALID_BIT_MASK);
+ assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
/* Ensure that the 'value' is only a bit wide */
- assert(value <= 1);
+ assert(value <= 1U);
/*
* Get the SCR_EL3 value from the cpu context, clear the desired bit
* and set it to its new value.
*/
state = get_el3state_ctx(ctx);
- scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
- scr_el3 &= ~(1 << bit_pos);
+ scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
+ scr_el3 &= ~(1U << bit_pos);
scr_el3 |= value << bit_pos;
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
}
@@ -578,11 +578,11 @@
el3_state_t *state;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
/* Populate EL3 state so that ERET jumps to the correct entry */
state = get_el3state_ctx(ctx);
- return read_ctx_reg(state, CTX_SCR_EL3);
+ return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
}
/*******************************************************************************
@@ -595,7 +595,7 @@
cpu_context_t *ctx;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
cm_set_next_context(ctx);
}
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c
index 03277c3..8e86790 100644
--- a/lib/locks/bakery/bakery_lock_coherent.c
+++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -35,9 +35,9 @@
*/
#define assert_bakery_entry_valid(_entry, _bakery) do { \
- assert(_bakery); \
- assert(_entry < BAKERY_LOCK_MAX_CPUS); \
-} while (0)
+ assert((_bakery) != NULL); \
+ assert((_entry) < BAKERY_LOCK_MAX_CPUS); \
+} while (false)
/* Obtain a ticket for a given CPU */
static unsigned int bakery_get_ticket(bakery_lock_t *bakery, unsigned int me)
@@ -46,7 +46,7 @@
unsigned int they;
/* Prevent recursive acquisition */
- assert(!bakery_ticket_number(bakery->lock_data[me]));
+ assert(bakery_ticket_number(bakery->lock_data[me]) == 0U);
/*
* Flag that we're busy getting our ticket. All CPUs are iterated in the
@@ -58,9 +58,9 @@
* ticket value. That's OK as the lock is acquired based on the priority
* value, not the ticket value alone.
*/
- my_ticket = 0;
+ my_ticket = 0U;
bakery->lock_data[me] = make_bakery_data(CHOOSING_TICKET, my_ticket);
- for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) {
+ for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) {
their_ticket = bakery_ticket_number(bakery->lock_data[they]);
if (their_ticket > my_ticket)
my_ticket = their_ticket;
@@ -105,8 +105,8 @@
* Now that we got our ticket, compute our priority value, then compare
* with that of others, and proceed to acquire the lock
*/
- my_prio = PRIORITY(my_ticket, me);
- for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) {
+ my_prio = bakery_get_priority(my_ticket, me);
+ for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) {
if (me == they)
continue;
@@ -120,7 +120,8 @@
* (valid) ticket value. If they do, compare priorities
*/
their_ticket = bakery_ticket_number(their_bakery_data);
- if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) {
+ if ((their_ticket != 0U) &&
+ (bakery_get_priority(their_ticket, they) < my_prio)) {
/*
* They have higher priority (lower value). Wait for
* their ticket value to change (either release the lock
@@ -148,7 +149,7 @@
unsigned int me = plat_my_core_pos();
assert_bakery_entry_valid(me, bakery);
- assert(bakery_ticket_number(bakery->lock_data[me]));
+ assert(bakery_ticket_number(bakery->lock_data[me]) != 0U);
/*
* Ensure that other observers see any stores in the critical section
@@ -156,7 +157,7 @@
* Then signal other waiting contenders.
*/
dmbst();
- bakery->lock_data[me] = 0;
+ bakery->lock_data[me] = 0U;
dsb();
sev();
}
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index b947da9..beae63c 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -53,21 +53,31 @@
IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE);
#endif
-#define get_bakery_info(_cpu_ix, _lock) \
- (bakery_info_t *)((uintptr_t)_lock + _cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
+static inline bakery_lock_t *get_bakery_info(unsigned int cpu_ix,
+ bakery_lock_t *lock)
+{
+ return (bakery_info_t *)((uintptr_t)lock +
+ cpu_ix * PERCPU_BAKERY_LOCK_SIZE);
+}
-#define write_cache_op(_addr, _cached) \
- do { \
- (_cached ? dccvac((uintptr_t)_addr) :\
- dcivac((uintptr_t)_addr));\
- dsbish();\
- } while (0)
+static inline void write_cache_op(uintptr_t addr, bool cached)
+{
+ if (cached)
+ dccvac(addr);
+ else
+ dcivac(addr);
-#define read_cache_op(_addr, _cached) if (_cached) \
- dccivac((uintptr_t)_addr)
+ dsbish();
+}
+
+static inline void read_cache_op(uintptr_t addr, bool cached)
+{
+ if (cached)
+ dccivac(addr);
+}
/* Helper function to check if the lock is acquired */
-static inline int is_lock_acquired(const bakery_info_t *my_bakery_info,
+static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info,
int is_cached)
{
/*
@@ -78,8 +88,8 @@
* operations were not propagated to all the caches in the system.
* Hence do a `read_cache_op()` prior to read.
*/
- read_cache_op(my_bakery_info, is_cached);
- return !!(bakery_ticket_number(my_bakery_info->lock_data));
+ read_cache_op((uintptr_t)my_bakery_info, is_cached);
+ return bakery_ticket_number(my_bakery_info->lock_data) != 0U;
}
static unsigned int bakery_get_ticket(bakery_lock_t *lock,
@@ -94,7 +104,7 @@
* it is not NULL.
*/
my_bakery_info = get_bakery_info(me, lock);
- assert(my_bakery_info);
+ assert(my_bakery_info != NULL);
/* Prevent recursive acquisition.*/
assert(!is_lock_acquired(my_bakery_info, is_cached));
@@ -103,16 +113,16 @@
* Tell other contenders that we are through the bakery doorway i.e.
* going to allocate a ticket for this cpu.
*/
- my_ticket = 0;
+ my_ticket = 0U;
my_bakery_info->lock_data = make_bakery_data(CHOOSING_TICKET, my_ticket);
- write_cache_op(my_bakery_info, is_cached);
+ write_cache_op((uintptr_t)my_bakery_info, is_cached);
/*
* Iterate through the bakery information of each contender to allocate
* the highest ticket number for this cpu.
*/
- for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) {
+ for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) {
if (me == they)
continue;
@@ -121,9 +131,9 @@
* ensure that a stale copy is not read.
*/
their_bakery_info = get_bakery_info(they, lock);
- assert(their_bakery_info);
+ assert(their_bakery_info != NULL);
- read_cache_op(their_bakery_info, is_cached);
+ read_cache_op((uintptr_t)their_bakery_info, is_cached);
/*
* Update this cpu's ticket number if a higher ticket number is
@@ -141,7 +151,7 @@
++my_ticket;
my_bakery_info->lock_data = make_bakery_data(CHOSEN_TICKET, my_ticket);
- write_cache_op(my_bakery_info, is_cached);
+ write_cache_op((uintptr_t)my_bakery_info, is_cached);
return my_ticket;
}
@@ -167,8 +177,8 @@
* Now that we got our ticket, compute our priority value, then compare
* with that of others, and proceed to acquire the lock
*/
- my_prio = PRIORITY(my_ticket, me);
- for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) {
+ my_prio = bakery_get_priority(my_ticket, me);
+ for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) {
if (me == they)
continue;
@@ -177,11 +187,11 @@
* ensure that a stale copy is not read.
*/
their_bakery_info = get_bakery_info(they, lock);
- assert(their_bakery_info);
+ assert(their_bakery_info != NULL);
/* Wait for the contender to get their ticket */
do {
- read_cache_op(their_bakery_info, is_cached);
+ read_cache_op((uintptr_t)their_bakery_info, is_cached);
their_bakery_data = their_bakery_info->lock_data;
} while (bakery_is_choosing(their_bakery_data));
@@ -190,7 +200,7 @@
* (valid) ticket value. If they do, compare priorities
*/
their_ticket = bakery_ticket_number(their_bakery_data);
- if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) {
+ if (their_ticket && (bakery_get_priority(their_ticket, they) < my_prio)) {
/*
* They have higher priority (lower value). Wait for
* their ticket value to change (either release the lock
@@ -199,7 +209,7 @@
*/
do {
wfe();
- read_cache_op(their_bakery_info, is_cached);
+ read_cache_op((uintptr_t)their_bakery_info, is_cached);
} while (their_ticket
== bakery_ticket_number(their_bakery_info->lock_data));
}
@@ -231,7 +241,7 @@
* Then signal other waiting contenders.
*/
dmbst();
- my_bakery_info->lock_data = 0;
- write_cache_op(my_bakery_info, is_cached);
+ my_bakery_info->lock_data = 0U;
+ write_cache_op((uintptr_t)my_bakery_info, is_cached);
sev();
}
diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
index eb6f77f..a8ed9d3 100644
--- a/plat/arm/board/fvp/fvp_def.h
+++ b/plat/arm/board/fvp/fvp_def.h
@@ -31,70 +31,70 @@
* FVP memory map related constants
******************************************************************************/
-#define FLASH1_BASE 0x0c000000
-#define FLASH1_SIZE 0x04000000
+#define FLASH1_BASE UL(0x0c000000)
+#define FLASH1_SIZE UL(0x04000000)
-#define PSRAM_BASE 0x14000000
-#define PSRAM_SIZE 0x04000000
+#define PSRAM_BASE UL(0x14000000)
+#define PSRAM_SIZE UL(0x04000000)
-#define VRAM_BASE 0x18000000
-#define VRAM_SIZE 0x02000000
+#define VRAM_BASE UL(0x18000000)
+#define VRAM_SIZE UL(0x02000000)
/* Aggregate of all devices in the first GB */
-#define DEVICE0_BASE 0x20000000
-#define DEVICE0_SIZE 0x0c200000
+#define DEVICE0_BASE UL(0x20000000)
+#define DEVICE0_SIZE UL(0x0c200000)
/*
* In case of FVP models with CCN, the CCN register space overlaps into
* the NSRAM area.
*/
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
-#define DEVICE1_BASE 0x2e000000
-#define DEVICE1_SIZE 0x1A00000
+#define DEVICE1_BASE UL(0x2e000000)
+#define DEVICE1_SIZE UL(0x1A00000)
#else
-#define DEVICE1_BASE 0x2f000000
-#define DEVICE1_SIZE 0x200000
-#define NSRAM_BASE 0x2e000000
-#define NSRAM_SIZE 0x10000
+#define DEVICE1_BASE UL(0x2f000000)
+#define DEVICE1_SIZE UL(0x200000)
+#define NSRAM_BASE UL(0x2e000000)
+#define NSRAM_SIZE UL(0x10000)
#endif
/* Devices in the second GB */
-#define DEVICE2_BASE 0x7fe00000
-#define DEVICE2_SIZE 0x00200000
+#define DEVICE2_BASE UL(0x7fe00000)
+#define DEVICE2_SIZE UL(0x00200000)
-#define PCIE_EXP_BASE 0x40000000
-#define TZRNG_BASE 0x7fe60000
+#define PCIE_EXP_BASE UL(0x40000000)
+#define TZRNG_BASE UL(0x7fe60000)
/* Non-volatile counters */
-#define TRUSTED_NVCTR_BASE 0x7fe70000
-#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000)
-#define TFW_NVCTR_SIZE 4
-#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004)
-#define NTFW_CTR_SIZE 4
+#define TRUSTED_NVCTR_BASE UL(0x7fe70000)
+#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000))
+#define TFW_NVCTR_SIZE UL(4)
+#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004))
+#define NTFW_CTR_SIZE UL(4)
/* Keys */
-#define SOC_KEYS_BASE 0x7fe80000
-#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
-#define TZ_PUB_KEY_HASH_SIZE 32
-#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
-#define HU_KEY_SIZE 16
-#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
-#define END_KEY_SIZE 32
+#define SOC_KEYS_BASE UL(0x7fe80000)
+#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000))
+#define TZ_PUB_KEY_HASH_SIZE UL(32)
+#define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020))
+#define HU_KEY_SIZE UL(16)
+#define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044))
+#define END_KEY_SIZE UL(32)
/* Constants to distinguish FVP type */
-#define HBI_BASE_FVP 0x020
-#define REV_BASE_FVP_V0 0x0
-#define REV_BASE_FVP_REVC 0x2
+#define HBI_BASE_FVP U(0x020)
+#define REV_BASE_FVP_V0 U(0x0)
+#define REV_BASE_FVP_REVC U(0x2)
-#define HBI_FOUNDATION_FVP 0x010
-#define REV_FOUNDATION_FVP_V2_0 0x0
-#define REV_FOUNDATION_FVP_V2_1 0x1
-#define REV_FOUNDATION_FVP_v9_1 0x2
-#define REV_FOUNDATION_FVP_v9_6 0x3
+#define HBI_FOUNDATION_FVP U(0x010)
+#define REV_FOUNDATION_FVP_V2_0 U(0x0)
+#define REV_FOUNDATION_FVP_V2_1 U(0x1)
+#define REV_FOUNDATION_FVP_v9_1 U(0x2)
+#define REV_FOUNDATION_FVP_v9_6 U(0x3)
-#define BLD_GIC_VE_MMAP 0x0
-#define BLD_GIC_A53A57_MMAP 0x1
+#define BLD_GIC_VE_MMAP U(0x0)
+#define BLD_GIC_A53A57_MMAP U(0x1)
-#define ARCH_MODEL 0x1
+#define ARCH_MODEL U(0x1)
/* FVP Power controller base address*/
#define PWRC_BASE UL(0x1c100000)
@@ -104,26 +104,26 @@
#define SP804_TIMER_CLKDIV 35
/* SP810 controller. FVP specific flags */
-#define FVP_SP810_CTRL_TIM0_OV (1 << 16)
-#define FVP_SP810_CTRL_TIM1_OV (1 << 18)
-#define FVP_SP810_CTRL_TIM2_OV (1 << 20)
-#define FVP_SP810_CTRL_TIM3_OV (1 << 22)
+#define FVP_SP810_CTRL_TIM0_OV BIT_32(16)
+#define FVP_SP810_CTRL_TIM1_OV BIT_32(18)
+#define FVP_SP810_CTRL_TIM2_OV BIT_32(20)
+#define FVP_SP810_CTRL_TIM3_OV BIT_32(22)
/*******************************************************************************
* GIC-400 & interrupt handling related constants
******************************************************************************/
/* VE compatible GIC memory map */
-#define VE_GICD_BASE 0x2c001000
-#define VE_GICC_BASE 0x2c002000
-#define VE_GICH_BASE 0x2c004000
-#define VE_GICV_BASE 0x2c006000
+#define VE_GICD_BASE UL(0x2c001000)
+#define VE_GICC_BASE UL(0x2c002000)
+#define VE_GICH_BASE UL(0x2c004000)
+#define VE_GICV_BASE UL(0x2c006000)
/* Base FVP compatible GIC memory map */
-#define BASE_GICD_BASE 0x2f000000
-#define BASE_GICR_BASE 0x2f100000
-#define BASE_GICC_BASE 0x2c000000
-#define BASE_GICH_BASE 0x2c010000
-#define BASE_GICV_BASE 0x2c02f000
+#define BASE_GICD_BASE UL(0x2f000000)
+#define BASE_GICR_BASE UL(0x2f100000)
+#define BASE_GICC_BASE UL(0x2c000000)
+#define BASE_GICH_BASE UL(0x2c010000)
+#define BASE_GICV_BASE UL(0x2c02f000)
#define FVP_IRQ_TZ_WDOG 56
#define FVP_IRQ_SEC_SYS_TIMER 57
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index ed1a302..44ab1b3 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
/* Enable the dynamic translation tables library. */
#ifdef AARCH32
@@ -44,26 +44,26 @@
*/
#define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT
-#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
-#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
-#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
+#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000)
+#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */
-#define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000
-#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
+#define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000)
+#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* No SCP in FVP */
-#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0)
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
-#define PLAT_ARM_DRAM2_SIZE ULL(0x80000000)
+#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
/*
* Load address of BL33 for this platform port
*/
-#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + U(0x8000000))
+#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000))
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
@@ -94,18 +94,18 @@
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
* plus a little space for growth.
*/
-#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
+#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
/*
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
*/
#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
#endif
/*
@@ -113,9 +113,9 @@
* little space for growth.
*/
#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
+# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000)
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x11000
+# define PLAT_ARM_MAX_BL2_SIZE UL(0x11000)
#endif
/*
@@ -123,7 +123,7 @@
* calculated using the current BL31 PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
-#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
+#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
#ifdef AARCH32
/*
@@ -131,7 +131,7 @@
* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
-# define PLAT_ARM_MAX_BL32_SIZE 0x3B000
+# define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000)
#endif
/*
@@ -139,28 +139,28 @@
*/
#if defined(IMAGE_BL1)
# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
+# define PLATFORM_STACK_SIZE UL(0x1000)
# else
-# define PLATFORM_STACK_SIZE 0x440
+# define PLATFORM_STACK_SIZE UL(0x440)
# endif
#elif defined(IMAGE_BL2)
# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
+# define PLATFORM_STACK_SIZE UL(0x1000)
# else
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE UL(0x400)
# endif
#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE UL(0x400)
#elif defined(IMAGE_BL31)
# if ENABLE_SPM
-# define PLATFORM_STACK_SIZE 0x500
+# define PLATFORM_STACK_SIZE UL(0x500)
# elif PLAT_XLAT_TABLES_DYNAMIC
-# define PLATFORM_STACK_SIZE 0x800
+# define PLATFORM_STACK_SIZE UL(0x800)
# else
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE UL(0x400)
# endif
#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
+# define PLATFORM_STACK_SIZE UL(0x440)
#endif
#define MAX_IO_DEVICES 3
@@ -191,20 +191,20 @@
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
-#define PLAT_FVP_SMMUV3_BASE 0x2b400000
+#define PLAT_FVP_SMMUV3_BASE UL(0x2b400000)
/* CCI related constants */
-#define PLAT_FVP_CCI400_BASE 0x2c090000
+#define PLAT_FVP_CCI400_BASE UL(0x2c090000)
#define PLAT_FVP_CCI400_CLUS0_SL_PORT 3
#define PLAT_FVP_CCI400_CLUS1_SL_PORT 4
/* CCI-500/CCI-550 on Base platform */
-#define PLAT_FVP_CCI5XX_BASE 0x2a000000
+#define PLAT_FVP_CCI5XX_BASE UL(0x2a000000)
#define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5
#define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6
/* CCN related constants. Only CCN 502 is currently supported */
-#define PLAT_ARM_CCN_BASE 0x2e000000
+#define PLAT_ARM_CCN_BASE UL(0x2e000000)
#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
/* System timer related constants */
@@ -229,7 +229,7 @@
* Give access to the CPUs and Virtio. Some devices
* would normally use the default ID so allow that too.
*/
-#define PLAT_ARM_TZC_BASE 0x2a4a0000
+#define PLAT_ARM_TZC_BASE UL(0x2a4a0000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
@@ -268,4 +268,4 @@
#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
ARM_SP_IMAGE_NS_BUF_SIZE)
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index d4a77f0..89e28ef 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
/* Enable the dynamic translation tables library. */
#ifdef AARCH32
@@ -41,7 +41,7 @@
JUNO_CLUSTER1_CORE_COUNT)
/* Cryptocell HW Base address */
-#define PLAT_CRYPTOCELL_BASE 0x60050000
+#define PLAT_CRYPTOCELL_BASE UL(0x60050000)
/*
* Other platform porting definitions are provided by included headers
@@ -52,13 +52,13 @@
*/
#define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT
-#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
/* Use the bypass address */
#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
-#define NSRAM_BASE 0x2e000000
-#define NSRAM_SIZE 0x00008000 /* 32KB */
+#define NSRAM_BASE UL(0x2e000000)
+#define NSRAM_SIZE UL(0x00008000) /* 32KB */
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
@@ -71,9 +71,9 @@
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
#if TRUSTED_BOARD_BOOT
-#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000
+#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000)
#else
-#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000
+#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000)
#endif /* TRUSTED_BOARD_BOOT */
/*
@@ -115,18 +115,18 @@
* plus a little space for growth.
*/
#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
+# define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
#else
-# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000
+# define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000)
#endif
/*
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
*/
#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
#endif
/*
@@ -135,14 +135,14 @@
*/
#if TRUSTED_BOARD_BOOT
#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
-# define PLAT_ARM_MAX_BL2_SIZE 0x1F000
+# define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000)
#elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA
-# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
+# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000)
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x1C000
+# define PLAT_ARM_MAX_BL2_SIZE UL(0x1C000)
#endif
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0xF000
+# define PLAT_ARM_MAX_BL2_SIZE UL(0xF000)
#endif
/*
@@ -151,7 +151,7 @@
* BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE.
* Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE.
*/
-#define PLAT_ARM_MAX_BL31_SIZE 0x3E000
+#define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000)
#if JUNO_AARCH32_EL3_RUNTIME
/*
@@ -160,7 +160,7 @@
* BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE.
* Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE.
*/
-#define PLAT_ARM_MAX_BL32_SIZE 0x3E000
+#define PLAT_ARM_MAX_BL32_SIZE UL(0x3E000)
#endif
/*
@@ -168,26 +168,26 @@
*/
#if defined(IMAGE_BL1)
# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
+# define PLATFORM_STACK_SIZE UL(0x1000)
# else
-# define PLATFORM_STACK_SIZE 0x440
+# define PLATFORM_STACK_SIZE UL(0x440)
# endif
#elif defined(IMAGE_BL2)
# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
+# define PLATFORM_STACK_SIZE UL(0x1000)
# else
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE UL(0x400)
# endif
#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE UL(0x400)
#elif defined(IMAGE_BL31)
# if PLAT_XLAT_TABLES_DYNAMIC
-# define PLATFORM_STACK_SIZE 0x800
+# define PLATFORM_STACK_SIZE UL(0x800)
# else
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE UL(0x400)
# endif
#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
+# define PLATFORM_STACK_SIZE UL(0x440)
#endif
/*
@@ -197,7 +197,7 @@
#define PLAT_LOG_LEVEL_ASSERT 40
/* CCI related constants */
-#define PLAT_ARM_CCI_BASE 0x2c090000
+#define PLAT_ARM_CCI_BASE UL(0x2c090000)
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3
@@ -205,7 +205,7 @@
#define PLAT_ARM_NSTIMER_FRAME_ID 1
/* TZC related constants */
-#define PLAT_ARM_TZC_BASE 0x2a4a0000
+#define PLAT_ARM_TZC_BASE UL(0x2a4a0000)
#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \
TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \
@@ -223,13 +223,13 @@
*/
/* GIC related constants (no GICR in GIC-400) */
-#define PLAT_ARM_GICD_BASE 0x2c010000
-#define PLAT_ARM_GICC_BASE 0x2c02f000
-#define PLAT_ARM_GICH_BASE 0x2c04f000
-#define PLAT_ARM_GICV_BASE 0x2c06f000
+#define PLAT_ARM_GICD_BASE UL(0x2c010000)
+#define PLAT_ARM_GICC_BASE UL(0x2c02f000)
+#define PLAT_ARM_GICH_BASE UL(0x2c04f000)
+#define PLAT_ARM_GICV_BASE UL(0x2c06f000)
/* MHU related constants */
-#define PLAT_CSS_MHU_BASE 0x2b1f0000
+#define PLAT_CSS_MHU_BASE UL(0x2b1f0000)
/*
* Base address of the first memory region used for communication between AP
@@ -243,7 +243,7 @@
* 32-bit word on all CSS platforms. On Juno, part of this configuration is
* which CPU is the primary, according to the shift and mask definitions below.
*/
-#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80)
+#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80))
#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4
#endif
@@ -252,13 +252,13 @@
* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
* SCP_BL2 size plus a little space for growth.
*/
-#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000
+#define PLAT_CSS_MAX_SCP_BL2_SIZE UL(0x14000)
/*
* PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
* SCP_BL2U size plus a little space for growth.
*/
-#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000
+#define PLAT_CSS_MAX_SCP_BL2U_SIZE UL(0x14000)
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
CSS_G1S_IRQ_PROPS(grp), \
@@ -287,9 +287,9 @@
*/
/* CSS SoC NIC-400 Global Programmers View (GPV) */
-#define PLAT_SOC_CSS_NIC400_BASE 0x2a000000
+#define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000)
#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h
index 95f2b39..5301886 100644
--- a/plat/arm/board/juno/juno_def.h
+++ b/plat/arm/board/juno/juno_def.h
@@ -14,20 +14,20 @@
******************************************************************************/
/* Board revisions */
-#define REV_JUNO_R0 0x1 /* Rev B */
-#define REV_JUNO_R1 0x2 /* Rev C */
-#define REV_JUNO_R2 0x3 /* Rev D */
+#define REV_JUNO_R0 U(0x1) /* Rev B */
+#define REV_JUNO_R1 U(0x2) /* Rev C */
+#define REV_JUNO_R2 U(0x3) /* Rev D */
/* Bypass offset from start of NOR flash */
-#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
+#define BL1_ROM_BYPASS_OFFSET UL(0x03EC0000)
-#define EMMC_BASE 0x0c000000
-#define EMMC_SIZE 0x04000000
+#define EMMC_BASE UL(0x0c000000)
+#define EMMC_SIZE UL(0x04000000)
-#define PSRAM_BASE 0x14000000
-#define PSRAM_SIZE 0x02000000
+#define PSRAM_BASE UL(0x14000000)
+#define PSRAM_SIZE UL(0x02000000)
-#define JUNO_SSC_VER_PART_NUM 0x030
+#define JUNO_SSC_VER_PART_NUM U(0x030)
/*******************************************************************************
* Juno topology related constants
@@ -54,19 +54,19 @@
/*******************************************************************************
* TRNG related constants
******************************************************************************/
-#define TRNG_BASE 0x7FE60000ULL
+#define TRNG_BASE UL(0x7FE60000)
#define TRNG_NOUTPUTS 4
-#define TRNG_STATUS 0x10
-#define TRNG_INTMASK 0x14
-#define TRNG_CONFIG 0x18
-#define TRNG_CONTROL 0x1C
+#define TRNG_STATUS UL(0x10)
+#define TRNG_INTMASK UL(0x14)
+#define TRNG_CONFIG UL(0x18)
+#define TRNG_CONTROL UL(0x1C)
#define TRNG_NBYTES 16 /* Number of bytes generated per round. */
/*******************************************************************************
* MMU-401 related constants
******************************************************************************/
-#define MMU401_SSD_OFFSET 0x4000
-#define MMU401_DMA330_BASE 0x7fb00000
+#define MMU401_SSD_OFFSET UL(0x4000)
+#define MMU401_DMA330_BASE UL(0x7fb00000)
/*******************************************************************************
* Interrupt handling constants
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 6b14785..49f0074 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -63,7 +63,7 @@
uint32_t spsr;
/* Figure out what mode we enter the non-secure world in */
- mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+ mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index 057d772..c2a4bb1 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -122,8 +122,8 @@
void arm_load_tb_fw_config(void)
{
int err;
- uintptr_t config_base = 0;
- image_desc_t *image_desc;
+ uintptr_t config_base = 0UL;
+ image_desc_t *desc;
image_desc_t arm_tb_fw_info = {
.image_id = TB_FW_CONFIG_ID,
@@ -148,12 +148,11 @@
tb_fw_cfg_dtb_size = (size_t)arm_tb_fw_info.image_info.image_max_size;
/* The BL2 ep_info arg0 is modified to point to TB_FW_CONFIG */
- image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
- assert(image_desc != NULL);
- image_desc->ep_info.args.arg0 = config_base;
+ desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
+ assert(desc != NULL);
+ desc->ep_info.args.arg0 = config_base;
- INFO("BL1: TB_FW_CONFIG loaded at address = %p\n",
- (void *) config_base);
+ INFO("BL1: TB_FW_CONFIG loaded at address = 0x%lx\n", config_base);
#if TRUSTED_BOARD_BOOT && defined(DYN_DISABLE_AUTH)
int tb_fw_node;
@@ -240,7 +239,7 @@
*/
if (config_ids[i] != HW_CONFIG_ID) {
- if (check_uptr_overflow(image_base, image_size) != 0)
+ if (check_uptr_overflow(image_base, image_size))
continue;
/* Ensure the configs don't overlap with BL31 */
diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c
index b12d82c..8fa864d 100644
--- a/plat/arm/common/execution_state_switch.c
+++ b/plat/arm/common/execution_state_switch.c
@@ -117,7 +117,7 @@
* Switching from AArch64 to AArch32. Ensure this CPU implements
* the target EL in AArch32.
*/
- impl = from_el2 ? EL_IMPLEMENTED(2) : EL_IMPLEMENTED(1);
+ impl = from_el2 ? el_implemented(2) : el_implemented(1);
if (impl != EL_IMPL_A64_A32)
goto exec_denied;
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index aad350b..1d7da00 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -99,7 +99,7 @@
uint32_t spsr;
/* Figure out what mode we enter the non-secure world in */
- mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+ mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
index f57dd63..0e79e0a 100644
--- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
@@ -191,7 +191,7 @@
uint32_t spsr;
/* Figure out what mode we enter the non-secure world in */
- mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+ mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
diff --git a/plat/layerscape/common/ls_common.c b/plat/layerscape/common/ls_common.c
index abf6525..afd5927 100644
--- a/plat/layerscape/common/ls_common.c
+++ b/plat/layerscape/common/ls_common.c
@@ -147,7 +147,7 @@
uint32_t spsr;
/* Figure out what mode we enter the non-secure world in */
- mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+ mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c
index 96a0bd8..8df7dad 100644
--- a/plat/mediatek/mt6795/bl31_plat_setup.c
+++ b/plat/mediatek/mt6795/bl31_plat_setup.c
@@ -339,7 +339,7 @@
next_image_info = &bl33_image_ep_info;
/* Figure out what mode we enter the non-secure world in */
- if (EL_IMPLEMENTED(2)) {
+ if (el_implemented(2) != EL_IMPL_NONE) {
INFO("Kernel_EL2\n");
mode = MODE_EL2;
} else{
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index d76621d..b3c3960 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -118,7 +118,7 @@
unsigned int mode;
/* Figure out what mode we enter the non-secure world in */
- mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
+ mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in