diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 6fce24e..a59b92c 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -57,6 +57,30 @@
 
 check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
 
+workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326
+	/* Apply workaround */
+	mov x0, #1
+	msr S3_6_C15_C4_0, x0
+	isb
+
+	mov x0, #0x0100
+	movk x0, #0x0E08, lsl #16
+	msr S3_6_C15_C4_2, x0
+
+	mov x0, #0x0300
+	movk x0, #0x0F1F, lsl #16
+	movk x0, #0x0008, lsl #32
+	msr S3_6_C15_C4_3, x0
+
+	mov x0, #0x03F1
+	movk x0, #0x00C0, lsl #16
+	msr S3_6_C15_C4_1, x0
+
+	isb
+workaround_reset_end cortex_a510, ERRATUM(2080326)
+
+check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2)
+
 workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
 	/*
 	 * Force L2 allocation of transient lines by setting
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index e12795f..e7b0e54 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -769,6 +769,11 @@
 # present in r0p0 and r0p1 but there is no workaround for those revisions.
 CPU_FLAG_LIST += ERRATA_A510_2041909
 
+# Flag to aply erratum 2080326 workaround during reset. This erratum applies
+# to revision r0p2 of the Cortex-A510 cpu and is fixed in r0p3. The issue is
+# also present in r0p0 and r0p1 but there is no workaround for those revisions.
+CPU_FLAG_LIST += ERRATA_A510_2080326
+
 # Flag to apply erratum 2250311 workaround during reset. This erratum applies
 # to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
 CPU_FLAG_LIST += ERRATA_A510_2250311