tree 64a6e0de66ab7c1ba538dd25fbdbbc1ae5a17983
parent 9d8bbcd76ffd31a1c3d581f88c653bbf3be13010
author Yann Gautier <yann.gautier@st.com> 1559656537 +0200
committer Yann Gautier <yann.gautier@st.com> 1560773031 +0200

clk: stm32mp1: correctly handle Clock Spreading Generator

To activate the CSG option, the driver needs to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator.
This bit should not be cleared when starting the PLL.

Change-Id: Ie5c720ff03655f27a7e7e9e7ccf8295dd046112f
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>