refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants
Rename the Miscellaneous Control register constants from MISC_REGx to
MISC_CTRLx.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4d43bbda44b090de4ecf2d52cfc468f9683cc3b5
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index 5fd5f83..db235c2 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -450,7 +450,7 @@
*/
data = 0;
mask = PHY_REF_CLK_SEL;
- reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0, sd_ip_addr), data, mask);
+ reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_CTRL0, sd_ip_addr), data, mask);
/*
* 9. Set correct reference clock frequency in COMPHY register
@@ -731,8 +731,8 @@
/*
* 10. Enable the output of 500M clock
*/
- data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
- usb3_reg_set(reg_base, COMPHY_MISC_REG0, data, REG_16_BIT_MASK);
+ data = MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN;
+ usb3_reg_set(reg_base, COMPHY_MISC_CTRL0, data, REG_16_BIT_MASK);
/*
* 11. Set 20-bit data width
@@ -829,7 +829,7 @@
CFG_SEL_20B, CFG_SEL_20B);
/* 3. Force to use reg setting for PCIe mode */
- reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR,
+ reg_set16(MISC_CTRL1_ADDR(PCIE) + COMPHY_SD_ADDR,
SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
/* 4. Change RX wait */
@@ -843,8 +843,8 @@
IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK);
/* 6. Enable the output of 100M/125M/500M clock */
- reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR,
- MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
+ reg_set16(MISC_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
+ MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
REG_16_BIT_MASK);
/*
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 214c6f0..63ee959 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -122,16 +122,16 @@
#define IDLE_SYNC_EN BIT(12)
#define IDLE_SYNC_EN_DEFAULT_VALUE 0x60
-#define COMPHY_MISC_REG0 0x4F
-#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0 * PHY_SHFT(unit))
+#define COMPHY_MISC_CTRL0 0x4F
+#define MISC_CTRL0_ADDR(unit) (COMPHY_MISC_CTRL0 * PHY_SHFT(unit))
#define CLK100M_125M_EN BIT(4)
#define TXDCLK_2X_SEL BIT(6)
#define CLK500M_EN BIT(7)
#define PHY_REF_CLK_SEL BIT(10)
-#define MISC_REG0_DEFAULT_VALUE 0xA00D
+#define MISC_CTRL0_DEFAULT_VALUE 0xA00D
-#define COMPHY_MISC_REG1 0x73
-#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1 * PHY_SHFT(unit))
+#define COMPHY_MISC_CTRL1 0x73
+#define MISC_CTRL1_ADDR(unit) (COMPHY_MISC_CTRL1 * PHY_SHFT(unit))
#define SEL_BITS_PCIE_FORCE BIT(15)
#define COMPHY_GEN2_SET3 0x112