Merge changes from topics "hm/errata-refactor", "jc/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-x2 to use cpu helpers
refactor(cpus): convert the Cortex-x2 to use the errata framework
refactor(cpus): reorder Cortex-x2 errata by ascending order
refactor(cpus): convert the Cortex-A65AE to use the errata framework
refactor(cpus): convert the Cortex-A510 to use cpu helpers
refactor(cpus): convert the Cortex-A510 to use the errata framework
refactor(cpus): reorder Cortex-A510 errata by ascending order
chore(fvp): add Aarch32 Cortex-A53 to the build
refactor(cpus): add Cortex-A53 errata framework information
feat(cpus): add errata framework helpers
chore(brcm): include cpu_helpers.S for bl2 build
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index 6207066..e3a7ebf 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -24,3 +24,8 @@
sphinx:
configuration: docs/conf.py
+
+# Auxiliary formats to export to (in addition to the default HTML output).
+formats:
+ - pdf
+
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index 61b5763..9f996bd 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -194,10 +194,12 @@
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dpu_aclk>;
- hdmi-transmitter@70 {
+ hdmi_tx: hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
video-ports = <0x234501>;
+ #sound-dai-cells = <0>;
+ audio-ports = <2 0x03>;
port {
tda998x_0_input: endpoint {
remote-endpoint = <&dp_pl0_out0>;
@@ -255,6 +257,52 @@
};
};
};
+
+ iofpga_i2s: xlnx-i2s@1c150000 {
+ #sound-dai-cells = <0>;
+ compatible = "xlnx,i2s-transmitter-1.0";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1c150000 0x0 0x10000>;
+ xlnx,dwidth = <0x18>;
+ xlnx,num-channels = <1>;
+ };
+
+ audio_formatter: audio-formatter@1c100000 {
+ compatible = "xlnx,audio-formatter-1.0";
+ reg = <0x0 0x1c000000 0x0 0x10000>;
+ #sound-dai-cells = <0>;
+ interrupt-names = "irq_mm2s";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "s_axi_lite_aclk", "aud_mclk", "m_axis_mm2s_aclk";
+ clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&audio_master>;
+ simple-audio-card,frame-master = <&audio_master>;
+ audio_master: simple-audio-card,cpu {
+ sound-dai = <&iofpga_i2s>;
+ clocks = <&i2s_audclk>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi_tx>;
+ };
+
+ simple-audio-card,plat {
+ sound-dai = <&audio_formatter>;
+ };
+ };
+
+ i2s_audclk: i2s_audclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ clock-output-names = "iofpga:i2s_audclk";
+ };
};
&gic {
diff --git a/fdts/morello.dtsi b/fdts/morello.dtsi
index 20640c5..7f39d75 100644
--- a/fdts/morello.dtsi
+++ b/fdts/morello.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,6 +88,13 @@
clock-output-names = "apb_pclk";
};
+ soc_refclk85mhz: refclk85mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <85000000>;
+ clock-output-names = "iofpga:aclk";
+ };
+
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S
index 96b63cf..45bd8d3 100644
--- a/lib/cpus/aarch64/neoverse_e1.S
+++ b/lib/cpus/aarch64/neoverse_e1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,20 +21,18 @@
#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* -------------------------------------------------
- * The CPU Ops reset function for Neoverse-E1.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func neoverse_e1_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
+/*
+ * ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S and applies to neoverse_e1.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184
+.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa
+add_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
- ret x19
-endfunc neoverse_e1_reset_func
+cpu_reset_func_start neoverse_e1
+cpu_reset_func_end neoverse_e1
func neoverse_e1_cpu_pwr_dwn
mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
@@ -44,27 +42,7 @@
ret
endfunc neoverse_e1_cpu_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N1. Must follow AAPCS.
- */
-func neoverse_e1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_e1_errata_report
-#endif
-
+errata_report_shim neoverse_e1
.section .rodata.neoverse_e1_regs, "aS"
neoverse_e1_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 2cf94c7..36a7ee7 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,20 +27,17 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1043202.
- * This applies to revision r0p0 and r1p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
+/*
+ * ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S and applies to Neoverse N1.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func errata_n1_1043202_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1043202
- cbz x0, 1f
+.equ check_erratum_neoverse_n1_936184, check_errata_dsu_936184
+.equ erratum_neoverse_n1_936184_wa, errata_dsu_936184_wa
+add_erratum_entry neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
+workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
@@ -50,314 +47,72 @@
msr CPUPMR_EL3, x0
ldr x0, =0x800200071
msr CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_n1_1043202_wa
+workaround_reset_end neoverse_n1, ERRATUM(1043202)
-func check_errata_1043202
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1043202
+check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0)
-/* --------------------------------------------------
- * Disable speculative loads if Neoverse N1 supports
- * SSBS.
- *
- * Shall clobber: x0.
- * --------------------------------------------------
- */
-func neoverse_n1_disable_speculative_loads
- /* Check if the PE implements SSBS */
- mrs x0, id_aa64pfr1_el1
- tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
- b.eq 1f
+workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
+workaround_reset_end neoverse_n1, ERRATUM(1073348)
- /* Disable speculative loads */
- msr SSBS, xzr
+check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0)
-1:
- ret
-endfunc neoverse_n1_disable_speculative_loads
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1073348
- * This applies to revision r0p0 and r1p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1073348_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1073348
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1073348_wa
-
-func check_errata_1073348
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1073348
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1130799
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1130799_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1130799
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1130799_wa
-
-func check_errata_1130799
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1130799
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1165347
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1165347_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1165347
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1165347_wa
+workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
+workaround_reset_end neoverse_n1, ERRATUM(1130799)
-func check_errata_1165347
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1165347
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1207823
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1207823_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1207823
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1207823_wa
+check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0)
-func check_errata_1207823
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1207823
+workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
+workaround_reset_end neoverse_n1, ERRATUM(1165347)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1220197
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1220197_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1220197
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
- msr NEOVERSE_N1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1220197_wa
+check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0)
-func check_errata_1220197
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1220197
+workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
+workaround_reset_end neoverse_n1, ERRATUM(1207823)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1257314
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1257314_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1257314
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR3_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
- msr NEOVERSE_N1_CPUACTLR3_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1257314_wa
+check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0)
-func check_errata_1257314
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1257314
+workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK
+workaround_reset_end neoverse_n1, ERRATUM(1220197)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1262606
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1262606_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1262606
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1262606_wa
+check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0)
-func check_errata_1262606
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262606
+workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
+workaround_reset_end neoverse_n1, ERRATUM(1257314)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1262888
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1262888_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1262888
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
- msr NEOVERSE_N1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1262888_wa
+check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0)
-func check_errata_1262888
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262888
+workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1262606)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1275112
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1275112_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1275112
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1275112_wa
+check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0)
-func check_errata_1275112
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1275112
+workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
+workaround_reset_end neoverse_n1, ERRATUM(1262888)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1315703.
- * This applies to revision <= r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1315703_wa
- /* Compare x0 against revision r3p1 */
- mov x17, x30
- bl check_errata_1315703
- cbz x0, 1f
+check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0)
- mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
- msr NEOVERSE_N1_CPUACTLR2_EL1, x0
+workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1275112)
-1:
- ret x17
-endfunc errata_n1_1315703_wa
+check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0)
-func check_errata_1315703
- /* Applies to everything <= r3p0. */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1315703
+workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
+workaround_reset_end neoverse_n1, ERRATUM(1315703)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1542419.
- * This applies to revisions r3p0 - r4p0 of Neoverse N1
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1542419_wa
- /* Compare x0 against revision r3p0 and r4p0 */
- mov x17, x30
- bl check_errata_1542419
- cbz x0, 1f
+check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0)
+workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
@@ -368,67 +123,17 @@
ldr x0, =0x08000020007D
msr CPUPCR_EL3, x0
isb
-1:
- ret x17
-endfunc errata_n1_1542419_wa
+workaround_reset_end neoverse_n1, ERRATUM(1542419)
-func check_errata_1542419
- /* Applies to everything r3p0 - r4p0. */
- mov x1, #0x30
- mov x2, #0x40
- b cpu_rev_var_range
-endfunc check_errata_1542419
+check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1868343.
- * This applies to revision <= r4p0 of Neoverse N1.
- * This workaround is the same as the workaround for
- * errata 1262606 and 1275112 but applies to a wider
- * revision range.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1868343_wa
- /*
- * Compare x0 against revision r4p0
- */
- mov x17, x30
- bl check_errata_1868343
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_n1_1868343_wa
+workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1868343)
-func check_errata_1868343
- /* Applies to everything <= r4p0 */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1868343
+check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1946160.
- * This applies to revisions r3p0, r3p1, r4p0, and
- * r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
- * and r2p0 but there is no fix in these revisions.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1946160_wa
- /*
- * Compare x0 against r3p0 - r4p1
- */
- mov x17, x30
- bl check_errata_1946160
- cbz x0, 1f
-
+workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -437,7 +142,6 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
mov x0, #4
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800082
@@ -446,7 +150,6 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
mov x0, #5
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800200
@@ -455,147 +158,62 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
isb
-1:
- ret x17
-endfunc errata_n1_1946160_wa
+workaround_reset_end neoverse_n1, ERRATUM(1946160)
-func check_errata_1946160
- /* Applies to r3p0 - r4p1. */
- mov x1, #0x30
- mov x2, #0x41
- b cpu_rev_var_range
-endfunc check_errata_1946160
+check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #2743102
- * This applies to revisions <= r4p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_n1_2743102_wa
- mov x17, x30
- bl check_errata_2743102
- cbz x0, 1f
-
+workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_n1_2743102_wa
+workaround_runtime_end neoverse_n1, ERRATUM(2743102)
-func check_errata_2743102
- /* Applies to all revisions <= r4p1 */
- mov x1, #0x41
- b cpu_rev_var_ls
-endfunc check_errata_2743102
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func neoverse_n1_reset_func
- mov x19, x30
+check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1)
- bl neoverse_n1_disable_speculative_loads
-
- /* Forces all cacheable atomic instructions to be near */
- mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
- msr NEOVERSE_N1_CPUACTLR2_EL1, x0
- isb
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_N1_1043202
- mov x0, x18
- bl errata_n1_1043202_wa
-#endif
-
-#if ERRATA_N1_1073348
- mov x0, x18
- bl errata_n1_1073348_wa
-#endif
-
-#if ERRATA_N1_1130799
- mov x0, x18
- bl errata_n1_1130799_wa
-#endif
-
-#if ERRATA_N1_1165347
- mov x0, x18
- bl errata_n1_1165347_wa
-#endif
-
-#if ERRATA_N1_1207823
- mov x0, x18
- bl errata_n1_1207823_wa
-#endif
-
-#if ERRATA_N1_1220197
- mov x0, x18
- bl errata_n1_1220197_wa
-#endif
-
-#if ERRATA_N1_1257314
- mov x0, x18
- bl errata_n1_1257314_wa
-#endif
-
-#if ERRATA_N1_1262606
- mov x0, x18
- bl errata_n1_1262606_wa
-#endif
+workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-N1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_n1
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_n1, CVE(2022, 23960)
-#if ERRATA_N1_1262888
- mov x0, x18
- bl errata_n1_1262888_wa
-#endif
+check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_N1_1275112
- mov x0, x18
- bl errata_n1_1275112_wa
-#endif
+/* --------------------------------------------------
+ * Disable speculative loads if Neoverse N1 supports
+ * SSBS.
+ *
+ * Shall clobber: x0.
+ * --------------------------------------------------
+ */
+func neoverse_n1_disable_speculative_loads
+ /* Check if the PE implements SSBS */
+ mrs x0, id_aa64pfr1_el1
+ tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
+ b.eq 1f
-#if ERRATA_N1_1315703
- mov x0, x18
- bl errata_n1_1315703_wa
-#endif
+ /* Disable speculative loads */
+ msr SSBS, xzr
-#if ERRATA_N1_1542419
- mov x0, x18
- bl errata_n1_1542419_wa
-#endif
+1:
+ ret
+endfunc neoverse_n1_disable_speculative_loads
-#if ERRATA_N1_1868343
- mov x0, x18
- bl errata_n1_1868343_wa
-#endif
+cpu_reset_func_start neoverse_n1
+ bl neoverse_n1_disable_speculative_loads
-#if ERRATA_N1_1946160
- mov x0, x18
- bl errata_n1_1946160_wa
-#endif
+ /* Forces all cacheable atomic instructions to be near */
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
+ isb
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
- msr actlr_el3, x0
-
+ sysreg_bit_set actlr_el3, NEOVERSE_N1_ACTLR_AMEN_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
- msr actlr_el2, x0
-
+ sysreg_bit_set actlr_el2, NEOVERSE_N1_ACTLR_AMEN_BIT
/* Enable group0 counters */
mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
msr CPUAMCNTENSET_EL0, x0
@@ -603,27 +221,9 @@
#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some system may have External LLC, core needs to be made aware */
- mrs x0, NEOVERSE_N1_CPUECTLR_EL1
- orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
- msr NEOVERSE_N1_CPUECTLR_EL1, x0
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-N1 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_n1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_n1_reset_func
+cpu_reset_func_end neoverse_n1
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -634,55 +234,15 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
- msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
-#if ERRATA_N1_2743102
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n1_2743102_wa
- mov x30, x15
-#endif /* ERRATA_N1_2743102 */
+ sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
+
+ apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
+
isb
ret
endfunc neoverse_n1_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N1. Must follow AAPCS.
- */
-func neoverse_n1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
- report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
- report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
- report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
- report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
- report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
- report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
- report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
- report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
- report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
- report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
- report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
- report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
- report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
- report_errata ERRATA_N1_2743102, neoverse_n1, 2743102
- report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
- report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_n1_errata_report
-#endif
+errata_report_shim neoverse_n1
/*
* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB