Merge changes from topics "hm/errata-refactor", "jc/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-x2 to use cpu helpers
refactor(cpus): convert the Cortex-x2 to use the errata framework
refactor(cpus): reorder Cortex-x2 errata by ascending order
refactor(cpus): convert the Cortex-A65AE to use the errata framework
refactor(cpus): convert the Cortex-A510 to use cpu helpers
refactor(cpus): convert the Cortex-A510 to use the errata framework
refactor(cpus): reorder Cortex-A510 errata by ascending order
chore(fvp): add Aarch32 Cortex-A53 to the build
refactor(cpus): add Cortex-A53 errata framework information
feat(cpus): add errata framework helpers
chore(brcm): include cpu_helpers.S for bl2 build
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h
index 6af85a8..337aac3 100644
--- a/include/lib/cpus/aarch64/cortex_a510.h
+++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,11 +14,13 @@
******************************************************************************/
#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
+#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1)
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2)
-#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38)
+#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38)
+#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3)
/*******************************************************************************
* CPU Power Control register specific definitions
@@ -30,6 +32,12 @@
* Complex auxiliary control register specific definitions
******************************************************************************/
#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25)
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2)
/*******************************************************************************
* Auxiliary control register specific definitions
@@ -37,5 +45,11 @@
#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17)
#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1)
-#endif /* CORTEX_A510_H */
\ No newline at end of file
+#endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 404b7f9..d945d7c 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -444,6 +444,19 @@
.endm
/*
+ * BFI : Inserts bitfield into a system register.
+ *
+ * BFI{cond} Rd, Rn, #lsb, #width
+ */
+.macro sysreg_bitfield_insert _reg:req, _src:req, _lsb:req, _width:req
+ /* Source value for BFI */
+ mov x1, #\_src
+ mrs x0, \_reg
+ bfi x0, x1, #\_lsb, #\_width
+ msr \_reg, x0
+.endm
+
+/*
* Apply erratum
*
* _cpu:
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S
index 6e3ff81..89b238a 100644
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,6 +44,8 @@
bx lr
endfunc check_errata_819472
+add_erratum_entry cortex_a53, ERRATUM(819472), ERRATA_A53_819472
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A53 Errata #824069.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -59,6 +61,8 @@
bx lr
endfunc check_errata_824069
+add_erratum_entry cortex_a53, ERRATUM(824069), ERRATA_A53_824069
+
/* --------------------------------------------------
* Errata Workaround for Cortex A53 Errata #826319.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -89,6 +93,8 @@
b cpu_rev_var_ls
endfunc check_errata_826319
+add_erratum_entry cortex_a53, ERRATUM(826319), ERRATA_A53_826319
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A53 Errata #827319.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -104,6 +110,8 @@
bx lr
endfunc check_errata_827319
+add_erratum_entry cortex_a53, ERRATUM(827319), ERRATA_A53_827319
+
/* ---------------------------------------------------------------------
* Disable the cache non-temporal hint.
*
@@ -142,6 +150,9 @@
b cpu_rev_var_ls
endfunc check_errata_disable_non_temporal_hint
+add_erratum_entry cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT, \
+ disable_non_temporal_hint
+
/* --------------------------------------------------
* Errata Workaround for Cortex A53 Errata #855873.
*
@@ -176,6 +187,8 @@
b cpu_rev_var_hs
endfunc check_errata_855873
+add_erratum_entry cortex_a53, ERRATUM(855873), ERRATA_A53_855873
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A53.
* Shall clobber: r0-r6
@@ -284,31 +297,7 @@
b cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A53. Must follow AAPCS.
- */
-func cortex_a53_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A53_819472, cortex_a53, 819472
- report_errata ERRATA_A53_824069, cortex_a53, 824069
- report_errata ERRATA_A53_826319, cortex_a53, 826319
- report_errata ERRATA_A53_827319, cortex_a53, 827319
- report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
- report_errata ERRATA_A53_855873, cortex_a53, 855873
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a53_errata_report
-#endif
+errata_report_shim cortex_a53
declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
cortex_a53_reset_func, \
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index e10ebb0..6fce24e 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -21,110 +21,15 @@
#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #1922240.
- * This applies only to revision r0p0 (fixed in r0p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_1922240_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1922240
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240
/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- mov x1, #3
- bfi x0, x1, #10, #2
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_1922240_wa
-
-func check_errata_1922240
- /* Applies to r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1922240
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2288014.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0. (fixed in r1p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2288014_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2288014
- cbz x0, 1f
-
- /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- mov x1, #1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2288014_wa
-
-func check_errata_2288014
- /* Applies to r1p0 and below */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2288014
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2042739.
- * This applies only to revisions r0p0, r0p1 and r0p2.
- * (fixed in r0p3)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2042739_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2042739
- cbz x0, 1f
-
- /* Apply the workaround by disabling ReadPreferUnique. */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2042739_wa
+ sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \
+ CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(1922240)
-func check_errata_2042739
- /* Applies to revisions r0p0 - r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2042739
+check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2041909.
- * This applies only to revision r0p2 and it is fixed in
- * r0p3. The issue is also present in r0p0 and r0p1 but
- * there is no workaround in those revisions.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x2, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2041909_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2041909
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909
/* Apply workaround */
mov x0, xzr
msr S3_6_C15_C4_0, x0
@@ -140,39 +45,55 @@
mov x0, #0x3F1
movk x0, #0x110, lsl #16
msr S3_6_C15_C4_1, x0
- isb
+workaround_reset_end cortex_a510, ERRATUM(2041909)
+
+check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2)
+
+workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739
+ /* Apply the workaround by disabling ReadPreferUnique. */
+ sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \
+ CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2042739)
-1:
- ret x17
-endfunc errata_cortex_a510_2041909_wa
+check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
-func check_errata_2041909
- /* Applies only to revision r0p2 */
- mov x1, #0x02
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2041909
+workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
+ /*
+ * Force L2 allocation of transient lines by setting
+ * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
+ */
+ mrs x0, CORTEX_A510_CPUECTLR_EL1
+ mov x1, #1
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
+ msr CORTEX_A510_CPUECTLR_EL1, x0
+workaround_reset_end cortex_a510, ERRATUM(2172148)
+
+check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950
+ /* Set bit 18 in CPUACTLR_EL1 */
+ sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
+ CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH
+
+ /* Set bit 25 in CMPXACTLR_EL1 */
+ sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
+ CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH
+
+workaround_reset_end cortex_a510, ERRATUM(2218950)
+
+check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0)
/* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2250311.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
* This workaround is not a typical errata fix. MPMM
* is disabled here, but this conflicts with the BL31
* MPMM support. So in addition to simply disabling
* the feature, a flag is set in the MPMM library
* indicating that it should not be enabled even if
* ENABLE_MPMM=1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
-func errata_cortex_a510_2250311_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2250311
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311
/* Disable MPMM */
mrs x0, CPUMPMMCR_EL3
bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
@@ -182,227 +103,68 @@
/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
bl mpmm_errata_disable
#endif
-
-1:
- ret x17
-endfunc errata_cortex_a510_2250311_wa
-
-func check_errata_2250311
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2250311
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2218950.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2218950_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2218950
- cbz x0, 1f
-
- /* Source register for BFI */
- mov x1, #1
-
- /* Set bit 18 in CPUACTLR_EL1 */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
- /* Set bit 25 in CMPXACTLR_EL1 */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- bfi x0, x1, #25, #1
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2218950_wa
+workaround_reset_end cortex_a510, ERRATUM(2250311)
-func check_errata_2218950
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2218950
+check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2172148.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2172148_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2172148
- cbz x0, 1f
-
- /*
- * Force L2 allocation of transient lines by setting
- * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
- */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #1
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2172148_wa
-
-func check_errata_2172148
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2172148
+workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014
+ /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
+ sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \
+ CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2288014)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2347730.
- * This applies to revisions r0p0 - r0p3, r1p0, r1p1.
- * It is fixed in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_cortex_a510_2347730_wa
- mov x17, x30
- bl check_errata_2347730
- cbz x0, 1f
+check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
+workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
/*
* Set CPUACTLR_EL1[17] to 1'b1, which disables
* specific microarchitectural clock gating
* behaviour.
*/
- mrs x1, CORTEX_A510_CPUACTLR_EL1
- orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17
- msr CORTEX_A510_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_a510_2347730_wa
-
-func check_errata_2347730
- /* Applies to revisions r1p1 and lower. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2347730
+ sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17
+workaround_reset_end cortex_a510, ERRATUM(2347730)
- /*---------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2371937.
- * This applies to revisions r1p1 and lower, and is
- * fixed in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- *---------------------------------------------------
- */
-func errata_cortex_a510_2371937_wa
- mov x17, x30
- bl check_errata_2371937
- cbz x0, 1f
+check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1)
+workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937
/*
* Cacheable atomic operations can be forced
* to be executed near by setting
* IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found
* in [40:38] of CPUECTLR_EL1.
*/
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR
- bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3
- msr CORTEX_A510_CPUECTLR_EL1, x0
-1:
- ret x17
-endfunc errata_cortex_a510_2371937_wa
-
-func check_errata_2371937
- /* Applies to r1p1 and lower */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2371937
-
- /* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2666669
- * This applies to revisions r1p1 and lower, and is fixed
- * in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ------------------------------------------------------
- */
-func errata_cortex_a510_2666669_wa
- mov x17, x30
- bl check_errata_2666669
- cbz x0, 1f
-
- /*
- * Workaround will set IMP_CPUACTLR_EL1[38]
- * to 0b1.
- */
- mrs x1, CORTEX_A510_CPUACTLR_EL1
- orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38
- msr CORTEX_A510_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_a510_2666669_wa
+ sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \
+ CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2371937)
-func check_errata_2666669
- /* Applies to r1p1 and lower */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2666669
+check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1)
-/* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Erratum 2684597.
- * This erratum applies to revision r0p0, r0p1, r0p2,
- * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
- * is fixed in r1p3.
- * Shall clobber: x0-x17
- * ------------------------------------------------------
- */
- .globl errata_cortex_a510_2684597_wa
-func errata_cortex_a510_2684597_wa
- mov x17, x30
- /* Ensure this errata is only applied to Cortex-A510 cores */
- jump_if_cpu_midr CORTEX_A510_MIDR, 1f
- b 2f
+workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669
+ sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38
+workaround_reset_end cortex_a510, ERRATUM(2666669)
-1:
- /* Check workaround compatibility. */
- mov x0, x18
- bl check_errata_2684597
- cbz x0, 2f
+check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1)
+.global erratum_cortex_a510_2684597_wa
+workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR
/*
* Many assemblers do not yet understand the "tsb csync" mnemonic,
* so use the equivalent hint instruction.
*/
hint #18 /* tsb csync */
-2:
- ret x17
-endfunc errata_cortex_a510_2684597_wa
-/* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Erratum 2684597.
- * This erratum applies to revision r0p0, r0p1, r0p2,
- * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
- * is fixed in r1p3.
- * Shall clobber: x0-x17
- * ------------------------------------------------------
+workaround_runtime_end cortex_a510, ERRATUM(2684597)
+
+check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
+
+/*
+ * ERRATA_DSU_2313941 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a510
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func check_errata_2684597
- /* Applies to revision < r1p3 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2684597
+.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -413,112 +175,17 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A510_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A510_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a510_core_pwr_dwn
- /*
- * Errata printing function for Cortex-A510. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a510_errata_report
- stp x8, x30, [sp, #-16]!
+errata_report_shim cortex_a510
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A510_1922240, cortex_a510, 1922240
- report_errata ERRATA_A510_2041909, cortex_a510, 2041909
- report_errata ERRATA_A510_2042739, cortex_a510, 2042739
- report_errata ERRATA_A510_2172148, cortex_a510, 2172148
- report_errata ERRATA_A510_2218950, cortex_a510, 2218950
- report_errata ERRATA_A510_2250311, cortex_a510, 2250311
- report_errata ERRATA_A510_2288014, cortex_a510, 2288014
- report_errata ERRATA_A510_2347730, cortex_a510, 2347730
- report_errata ERRATA_A510_2371937, cortex_a510, 2371937
- report_errata ERRATA_A510_2666669, cortex_a510, 2666669
- report_errata ERRATA_A510_2684597, cortex_a510, 2684597
- report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a510_errata_report
-#endif
-
-func cortex_a510_reset_func
- mov x19, x30
-
+cpu_reset_func_start cortex_a510
/* Disable speculative loads */
msr SSBS, xzr
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_A510_1922240
- mov x0, x18
- bl errata_cortex_a510_1922240_wa
-#endif
-
-#if ERRATA_A510_2288014
- mov x0, x18
- bl errata_cortex_a510_2288014_wa
-#endif
-
-#if ERRATA_A510_2042739
- mov x0, x18
- bl errata_cortex_a510_2042739_wa
-#endif
-
-#if ERRATA_A510_2041909
- mov x0, x18
- bl errata_cortex_a510_2041909_wa
-#endif
-
-#if ERRATA_A510_2250311
- mov x0, x18
- bl errata_cortex_a510_2250311_wa
-#endif
-
-#if ERRATA_A510_2218950
- mov x0, x18
- bl errata_cortex_a510_2218950_wa
-#endif
-
-#if ERRATA_A510_2371937
- mov x0, x18
- bl errata_cortex_a510_2371937_wa
-#endif
-
-#if ERRATA_A510_2172148
- mov x0, x18
- bl errata_cortex_a510_2172148_wa
-#endif
-
-#if ERRATA_A510_2347730
- mov x0, x18
- bl errata_cortex_a510_2347730_wa
-#endif
-
-#if ERRATA_A510_2666669
- mov x0, x18
- bl errata_cortex_a510_2666669_wa
-#endif
-
- isb
- ret x19
-endfunc cortex_a510_reset_func
+cpu_reset_func_end cortex_a510
/* ---------------------------------------------
* This function provides Cortex-A510 specific
diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S
index ac6583e..85d1894 100644
--- a/lib/cpus/aarch64/cortex_a65ae.S
+++ b/lib/cpus/aarch64/cortex_a65ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,49 +22,26 @@
#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-/* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A65.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a65ae_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
+ /*
+ * ERRATA_DSU_936184 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a65ae
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184
+.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
- ret x19
-endfunc cortex_a65ae_reset_func
+cpu_reset_func_start cortex_a65ae
+cpu_reset_func_end cortex_a65ae
func cortex_a65ae_cpu_pwr_dwn
- mrs x0, CORTEX_A65AE_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A65AE_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a65ae_cpu_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A65AE. Must follow AAPCS.
- */
-func cortex_a65ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a65ae_errata_report
-#endif
+errata_report_shim cortex_a65ae
.section .rodata.cortex_a65ae_regs, "aS"
cortex_a65ae_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index 497bd52..816a58f 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -26,20 +26,7 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2002765.
- * This applies to revisions r0p0, r1p0, and r2p0 and
- * is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2002765_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2002765
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
ldr x0, =0x6
msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0xF3A08002
@@ -48,119 +35,24 @@
msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x40000001003ff
msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
- isb
-
-1:
- ret x17
-endfunc errata_cortex_x2_2002765_wa
-
-func check_errata_2002765
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2002765
+workaround_reset_end cortex_x2, ERRATUM(2002765)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2058056.
- * This applies to revisions r0p0, r1p0, and r2p0 and
- * is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2058056_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2058056
- cbz x0, 1f
-
- mrs x1, CORTEX_X2_CPUECTLR2_EL1
- mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
- msr CORTEX_X2_CPUECTLR2_EL1, x1
+check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0)
-1:
- ret x17
-endfunc errata_cortex_x2_2058056_wa
+workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096
+ sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end cortex_x2, ERRATUM(2017096)
-func check_errata_2058056
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2058056
+check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2083908.
- * This applies to revision r2p0 and is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x2, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2083908_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2083908
- cbz x0, 1f
+workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056
+ sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
+ CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
+workaround_reset_end cortex_x2, ERRATUM(2058056)
- /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
- mrs x1, CORTEX_X2_CPUACTLR5_EL1
- orr x1, x1, #BIT(13)
- msr CORTEX_X2_CPUACTLR5_EL1, x1
-
-1:
- ret x17
-endfunc errata_cortex_x2_2083908_wa
+check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 0)
-func check_errata_2083908
- /* Applies to r2p0 */
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2083908
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2017096.
- * This applies only to revisions r0p0, r1p0 and r2p0
- * and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2017096_wa
- /* Compare x0 against revision r0p0 to r2p0 */
- mov x17, x30
- bl check_errata_2017096
- cbz x0, 1f
- mrs x1, CORTEX_X2_CPUECTLR_EL1
- orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
- msr CORTEX_X2_CPUECTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_x2_2017096_wa
-
-func check_errata_2017096
- /* Applies to r0p0, r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2017096
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2081180.
- * This applies to revision r0p0, r1p0 and r2p0
- * and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2081180_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2081180
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
/* Apply instruction patching sequence */
ldr x0, =0x3
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
@@ -178,34 +70,26 @@
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x10002001003F3
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_x2_2081180_wa
+workaround_reset_end cortex_x2, ERRATUM(2081180)
-func check_errata_2081180
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2081180
+check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata 2216384.
- * This applies to revisions r0p0, r1p0, and r2p0
- * and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2216384_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2216384
- cbz x0, 1f
+workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908
+ /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
+ sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13)
+workaround_reset_end cortex_x2, ERRATUM(2083908)
+
+check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
+
+workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715
+ /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
+ sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_x2, ERRATUM(2147715)
+
+check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
- mrs x1, CORTEX_X2_CPUACTLR5_EL1
- orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
- msr CORTEX_X2_CPUACTLR5_EL1, x1
+workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384
+ sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
/* Apply instruction patching sequence */
ldr x0, =0x5
@@ -216,138 +100,52 @@
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
- isb
-
-1:
- ret x17
-endfunc errata_x2_2216384_wa
+workaround_reset_end cortex_x2, ERRATUM(2216384)
-func check_errata_2216384
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2216384
+check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* ---------------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2147715.
- * This applies only to revisions r2p0 and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------
- */
-func errata_x2_2147715_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2147715
- cbz x0, 1f
-
- /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
- mrs x1, CORTEX_X2_CPUACTLR_EL1
- orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22
- msr CORTEX_X2_CPUACTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_x2_2147715_wa
-
-func check_errata_2147715
- /* Applies to r2p0 */
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2147715
-
- /* ---------------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2282622.
- * This applies to revision r0p0, r1p0, r2p0 and r2p1.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------------
- */
-func errata_x2_2282622_wa
- /* Compare x0 against revision r2p1 */
- mov x17, x30
- bl check_errata_2282622
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622
/* Apply the workaround */
- mrs x1, CORTEX_X2_CPUACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_X2_CPUACTLR2_EL1, x1
+ sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_x2, ERRATUM(2282622)
-1:
- ret x17
-endfunc errata_x2_2282622_wa
+check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
-func check_errata_2282622
- /* Applies to r0p0, r1p0, r2p0 and r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2282622
+workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
+ /* Set bit 40 in CPUACTLR2_EL1 */
+ sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_x2, ERRATUM(2371105)
- /* -------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2371105.
- * This applies to revisions <= r2p0 and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_x2_2371105_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2371105
- cbz x0, 1f
+check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0)
- /* Set bit 40 in CPUACTLR2_EL1 */
- mrs x1, CORTEX_X2_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40
- msr CORTEX_X2_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_x2_2371105_wa
+workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_reset_end cortex_x2, ERRATUM(2768515)
-func check_errata_2371105
- /* Applies to <= r2p0. */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2371105
+check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata #2768515
- * This applies to revisions <= r2p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
+workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-X2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func errata_x2_2768515_wa
- mov x17, x30
- bl check_errata_2768515
- cbz x0, 1f
+ override_vector_table wa_cve_vbar_cortex_x2
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x2, CVE(2022, 23960)
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_x2_2768515_wa
+check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-func check_errata_2768515
- /* Applies to all revisions <= r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2768515
+/*
+ * ERRATA_DSU_2313941 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_x2
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -358,122 +156,24 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_X2_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X2_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
#if ERRATA_X2_2768515
mov x15, x30
bl cpu_get_rev_var
- bl errata_x2_2768515_wa
+ bl erratum_cortex_x2_2768515_wa
mov x30, x15
#endif /* ERRATA_X2_2768515 */
isb
ret
endfunc cortex_x2_core_pwr_dwn
- /*
- * Errata printing function for Cortex X2. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_x2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X2_2002765, cortex_x2, 2002765
- report_errata ERRATA_X2_2017096, cortex_x2, 2017096
- report_errata ERRATA_X2_2058056, cortex_x2, 2058056
- report_errata ERRATA_X2_2081180, cortex_x2, 2081180
- report_errata ERRATA_X2_2083908, cortex_x2, 2083908
- report_errata ERRATA_X2_2147715, cortex_x2, 2147715
- report_errata ERRATA_X2_2216384, cortex_x2, 2216384
- report_errata ERRATA_X2_2282622, cortex_x2, 2282622
- report_errata ERRATA_X2_2371105, cortex_x2, 2371105
- report_errata ERRATA_X2_2768515, cortex_x2, 2768515
- report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960
- report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x2_errata_report
-#endif
-
-func cortex_x2_reset_func
- mov x19, x30
+errata_report_shim cortex_x2
+cpu_reset_func_start cortex_x2
/* Disable speculative loads */
msr SSBS, xzr
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_X2_2002765
- mov x0, x18
- bl errata_cortex_x2_2002765_wa
-#endif
-
-#if ERRATA_X2_2058056
- mov x0, x18
- bl errata_cortex_x2_2058056_wa
-#endif
-
-#if ERRATA_X2_2083908
- mov x0, x18
- bl errata_cortex_x2_2083908_wa
-#endif
-
-#if ERRATA_X2_2017096
- mov x0, x18
- bl errata_x2_2017096_wa
-#endif
-
-#if ERRATA_X2_2081180
- mov x0, x18
- bl errata_x2_2081180_wa
-#endif
-
-#if ERRATA_X2_2216384
- mov x0, x18
- bl errata_x2_2216384_wa
-#endif
-
-#if ERRATA_X2_2147715
- mov x0, x18
- bl errata_x2_2147715_wa
-#endif
-
-#if ERRATA_X2_2282622
- mov x0, x18
- bl errata_x2_2282622_wa
-#endif
-
-#if ERRATA_X2_2371105
- mov x0, x18
- bl errata_x2_2371105_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-X2 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_x2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_x2_reset_func
+cpu_reset_func_end cortex_x2
/* ---------------------------------------------
* This function provides Cortex X2 specific
diff --git a/lib/psci/aarch64/runtime_errata.S b/lib/psci/aarch64/runtime_errata.S
index 8d46691..89e3e12 100644
--- a/lib/psci/aarch64/runtime_errata.S
+++ b/lib/psci/aarch64/runtime_errata.S
@@ -20,7 +20,7 @@
mov x18, x0
#if ERRATA_A510_2684597
- bl errata_cortex_a510_2684597_wa
+ bl erratum_cortex_a510_2684597_wa
#endif
ret x19
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 7df150e..e790f92 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -222,7 +222,8 @@
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
- lib/cpus/aarch32/cortex_a57.S
+ lib/cpus/aarch32/cortex_a57.S \
+ lib/cpus/aarch32/cortex_a53.S
endif
BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk
index aa2fe86..67413c6 100644
--- a/plat/brcm/board/stingray/platform.mk
+++ b/plat/brcm/board/stingray/platform.mk
@@ -210,7 +210,8 @@
BL2_SOURCES += plat/${SOC_DIR}/driver/ihost_pll_config.c \
plat/${SOC_DIR}/src/bl2_setup.c \
- plat/${SOC_DIR}/driver/swreg.c
+ plat/${SOC_DIR}/driver/swreg.c \
+ lib/cpus/aarch64/cpu_helpers.S
ifeq (${USE_DDR},yes)
PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ddr/soc/include