diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index bffca72..9b934c9 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -477,8 +477,8 @@
 
 Arm Morello and N1SDP Platform ports
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Manoj Kumar <manoj.kumar3@arm.com>
-:|G|: `manojkumar-arm`_
+:|M|: Anurag Koul <anurag.koul@arm.com>
+:|G|: `anukou`_
 :|M|: Chandni Cherukuri <chandni.cherukuri@arm.com>
 :|G|: `chandnich`_
 :|F|: plat/arm/board/morello
@@ -954,7 +954,7 @@
 .. _raghuncstate: https://github.com/raghuncstate
 .. _CJKay: https://github.com/cjkay
 .. _nmenon: https://github.com/nmenon
-.. _manojkumar-arm: https://github.com/manojkumar-arm
+.. _anukou: https://github.com/anukou
 .. _chandnich: https://github.com/chandnich
 .. _abdellatif-elkhlifi: https://github.com/abdellatif-elkhlifi
 .. _vishnu-banavath: https://github.com/vishnu-banavath
diff --git a/drivers/rpi3/sdhost/rpi3_sdhost.c b/drivers/rpi3/sdhost/rpi3_sdhost.c
index c4b6fca..90c8509 100644
--- a/drivers/rpi3/sdhost/rpi3_sdhost.c
+++ b/drivers/rpi3/sdhost/rpi3_sdhost.c
@@ -245,13 +245,12 @@
 
 static void rpi3_sdhost_initialize(void)
 {
-	uintptr_t reg_base = rpi3_sdhost_params.reg_base;
-
 	assert((rpi3_sdhost_params.reg_base & MMC_BLOCK_MASK) == 0);
 
 	rpi3_sdhost_reset();
 
-	mmio_write_32(reg_base + HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_PREFERVAL);
+	rpi3_sdhost_set_ios(rpi3_sdhost_params.clk_rate_initial,
+		rpi3_sdhost_params.bus_width);
 	udelay(300);
 }
 
diff --git a/fdts/stm32mp15-bl2.dtsi b/fdts/stm32mp15-bl2.dtsi
index f956b05..18a4ba9 100644
--- a/fdts/stm32mp15-bl2.dtsi
+++ b/fdts/stm32mp15-bl2.dtsi
@@ -3,6 +3,9 @@
  * Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
  */
 
+/omit-if-no-ref/ &i2c6;
+/omit-if-no-ref/ &spi6;
+
 / {
 #if !STM32MP_EMMC && !STM32MP_SDMMC
 	aliases {
@@ -39,11 +42,9 @@
 #if !STM32MP_USB_PROGRAMMER
 		/delete-node/ usbphyc@5a006000;
 #endif
-		/delete-node/ spi@5c001000;
 		/delete-node/ rtc@5c004000;
 		/delete-node/ etzpc@5c007000;
 		/delete-node/ stgen@5c008000;
-		/delete-node/ i2c@5c009000;
 		/delete-node/ tamp@5c00a000;
 	};
 
diff --git a/fdts/stm32mp15-bl32.dtsi b/fdts/stm32mp15-bl32.dtsi
index c5a815e..6882224 100644
--- a/fdts/stm32mp15-bl32.dtsi
+++ b/fdts/stm32mp15-bl32.dtsi
@@ -3,6 +3,9 @@
  * Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
  */
 
+/omit-if-no-ref/ &i2c6;
+/omit-if-no-ref/ &spi6;
+
 / {
 	aliases {
 		/delete-property/ mmc0;
@@ -23,8 +26,6 @@
 		/delete-node/ mmc@58005000;
 		/delete-node/ mmc@58007000;
 		/delete-node/ usbphyc@5a006000;
-		/delete-node/ spi@5c001000;
 		/delete-node/ stgen@5c008000;
-		/delete-node/ i2c@5c009000;
 	};
 };
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 9b55658..89f4b40 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1322,11 +1322,19 @@
  * FEAT_HCX - Extended Hypervisor Configuration Register
  ******************************************************************************/
 #define HCRX_EL2		S3_4_C1_C2_2
+#define HCRX_EL2_MSCEn_BIT	(UL(1) << 11)
+#define HCRX_EL2_MCE2_BIT	(UL(1) << 10)
+#define HCRX_EL2_CMOW_BIT	(UL(1) << 9)
+#define HCRX_EL2_VFNMI_BIT	(UL(1) << 8)
+#define HCRX_EL2_VINMI_BIT	(UL(1) << 7)
+#define HCRX_EL2_TALLINT_BIT	(UL(1) << 6)
+#define HCRX_EL2_SMPME_BIT	(UL(1) << 5)
 #define HCRX_EL2_FGTnXS_BIT	(UL(1) << 4)
 #define HCRX_EL2_FnXS_BIT	(UL(1) << 3)
 #define HCRX_EL2_EnASR_BIT	(UL(1) << 2)
 #define HCRX_EL2_EnALS_BIT	(UL(1) << 1)
 #define HCRX_EL2_EnAS0_BIT	(UL(1) << 0)
+#define HCRX_EL2_INIT_VAL	ULL(0x0)
 
 /*******************************************************************************
  * FEAT_TCR2 - Extended Translation Control Register
diff --git a/include/drivers/rpi3/sdhost/rpi3_sdhost.h b/include/drivers/rpi3/sdhost/rpi3_sdhost.h
index 1653240..f4f6ec8 100644
--- a/include/drivers/rpi3/sdhost/rpi3_sdhost.h
+++ b/include/drivers/rpi3/sdhost/rpi3_sdhost.h
@@ -15,6 +15,7 @@
 struct rpi3_sdhost_params {
 	uintptr_t	reg_base;
 	uint32_t	clk_rate;
+	uint32_t	clk_rate_initial;
 	uint32_t	bus_width;
 	uint32_t        flags;
 	uint32_t	current_cmd;
@@ -57,6 +58,8 @@
 #define HC_CMD_READ			0x0040
 #define HC_CMD_COMMAND_MASK		0x003f
 
+#define RPI3_SDHOST_MAX_CLOCK		250000000	// technically, we should obtain this number from the mailbox
+
 #define HC_CLOCKDIVISOR_MAXVAL		0x07ff
 #define HC_CLOCKDIVISOR_PREFERVAL	0x027b
 #define HC_CLOCKDIVISOR_SLOWVAL		0x0148
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 886e1f3..e10ebb0 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -382,7 +382,11 @@
 	bl	check_errata_2684597
 	cbz	x0, 2f
 
-	tsb	csync
+	/*
+	 * Many assemblers do not yet understand the "tsb csync" mnemonic,
+	 * so use the equivalent hint instruction.
+	 */
+	hint	#18			/* tsb csync */
 2:
 	ret	x17
 endfunc errata_cortex_a510_2684597_wa
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 94d5ee1..c411b73 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -274,6 +274,19 @@
 	u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) &
 			PMCR_EL0_N_MASK);
 	write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2);
+
+	if (is_feat_hcx_supported()) {
+		/*
+		 * Initialize register HCRX_EL2 with its init value.
+		 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a
+		 * chance that this can lead to unexpected behavior in lower
+		 * ELs that have not been updated since the introduction of
+		 * this feature if not properly initialized, especially when
+		 * it comes to those bits that enable/disable traps.
+		 */
+		write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2,
+			HCRX_EL2_INIT_VAL);
+	}
 #endif /* CTX_INCLUDE_EL2_REGS */
 }
 
@@ -612,8 +625,22 @@
 	assert(ctx != NULL);
 
 	if (security_state == NON_SECURE) {
+		uint64_t el2_implemented = el_implemented(2);
+
 		scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
 						 CTX_SCR_EL3);
+
+		if (((scr_el3 & SCR_HCE_BIT) != 0U)
+			|| (el2_implemented != EL_IMPL_NONE)) {
+			/*
+			 * If context is not being used for EL2, initialize
+			 * HCRX_EL2 with its init value here.
+			 */
+			if (is_feat_hcx_supported()) {
+				write_hcrx_el2(HCRX_EL2_INIT_VAL);
+			}
+		}
+
 		if ((scr_el3 & SCR_HCE_BIT) != 0U) {
 			/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
 			sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
@@ -629,7 +656,7 @@
 			sctlr_elx |= SCTLR_IESB_BIT;
 #endif
 			write_sctlr_el2(sctlr_elx);
-		} else if (el_implemented(2) != EL_IMPL_NONE) {
+		} else if (el2_implemented != EL_IMPL_NONE) {
 			el2_unused = true;
 
 			/*
diff --git a/plat/mediatek/drivers/apusys/apusys.c b/plat/mediatek/drivers/apusys/apusys.c
index 1d34627..c82b3a7 100644
--- a/plat/mediatek/drivers/apusys/apusys.c
+++ b/plat/mediatek/drivers/apusys/apusys.c
@@ -11,6 +11,35 @@
 #include "apusys.h"
 #include "apusys_power.h"
 #include <lib/mtk_init/mtk_init.h>
+#include <mtk_sip_svc.h>
+
+static u_register_t apusys_kernel_handler(u_register_t x1,
+					  u_register_t x2,
+					  u_register_t x3,
+					  u_register_t x4,
+					  void *handle,
+					  struct smccc_res *smccc_ret)
+{
+	uint32_t request_ops;
+	int32_t ret = -1;
+
+	request_ops = (uint32_t)x1;
+
+	switch (request_ops) {
+	case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON:
+		ret = apusys_kernel_apusys_pwr_top_on();
+		break;
+	case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF:
+		ret = apusys_kernel_apusys_pwr_top_off();
+		break;
+	default:
+		ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
+		break;
+	}
+
+	return ret;
+}
+DECLARE_SMC_HANDLER(MTK_SIP_APUSYS_CONTROL, apusys_kernel_handler);
 
 int apusys_init(void)
 {
diff --git a/plat/mediatek/drivers/apusys/apusys.h b/plat/mediatek/drivers/apusys/apusys.h
index 5fdd2ec..1592cff 100644
--- a/plat/mediatek/drivers/apusys/apusys.h
+++ b/plat/mediatek/drivers/apusys/apusys.h
@@ -9,4 +9,10 @@
 
 #define MODULE_TAG "[APUSYS]"
 
+enum MTK_APUSYS_KERNEL_OP {
+	MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON,	/*  0 */
+	MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF,/*  1 */
+	MTK_APUSYS_KERNEL_OP_NUM,
+};
+
 #endif
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
index d7b0d24..ac62f2f 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
@@ -10,6 +10,7 @@
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <lib/mmio.h>
+#include <lib/spinlock.h>
 #include <lib/utils_def.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 
@@ -18,6 +19,9 @@
 #include "apusys_power.h"
 #include <mtk_mmap_pool.h>
 
+static spinlock_t apu_lock;
+static bool apusys_top_on;
+
 static int apu_poll(uintptr_t reg, uint32_t mask, uint32_t value, uint32_t timeout_us)
 {
 	uint32_t reg_val, count;
@@ -43,6 +47,135 @@
 	return -1;
 }
 
+static void apu_xpu2apusys_d4_slv_en(enum APU_D4_SLV_CTRL en)
+{
+	switch (en) {
+	case D4_SLV_OFF:
+		mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0,
+				INFRA_FMEM_BUS_u_SI21_CTRL_EN);
+		mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0,
+				INFRA_FMEM_BUS_u_SI22_CTRL_EN);
+		mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0,
+				INFRA_FMEM_BUS_u_SI11_CTRL_EN);
+		mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0,
+				INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN);
+		break;
+	case D4_SLV_ON:
+		mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0,
+				INFRA_FMEM_BUS_u_SI21_CTRL_EN);
+		mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0,
+				INFRA_FMEM_BUS_u_SI22_CTRL_EN);
+		mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0,
+				INFRA_FMEM_BUS_u_SI11_CTRL_EN);
+		mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0,
+				INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN);
+		break;
+	default:
+		ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, en);
+		break;
+	}
+}
+
+static void apu_pwr_flow_remote_sync(uint32_t cfg)
+{
+	mmio_write_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG, (cfg & 0x1));
+}
+
+int apusys_kernel_apusys_pwr_top_on(void)
+{
+	int ret;
+
+	spin_lock(&apu_lock);
+
+	if (apusys_top_on == true) {
+		INFO(MODULE_TAG "%s: APUSYS already powered on!\n", __func__);
+		spin_unlock(&apu_lock);
+		return 0;
+	}
+
+	apu_pwr_flow_remote_sync(1);
+
+	mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, AFC_ENA);
+
+	mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_SET);
+
+	ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY,
+		       PWR_RDY, PWR_RDY, APU_TOP_ON_POLLING_TIMEOUT_US);
+	if (ret != 0) {
+		ERROR(MODULE_TAG "%s polling RPC RDY timeout, ret %d\n", __func__, ret);
+		spin_unlock(&apu_lock);
+		return ret;
+	}
+
+	ret = apu_poll(APU_RPC_BASE + APU_RPC_STATUS,
+		       RPC_STATUS_RDY, RPC_STATUS_RDY, APU_TOP_ON_POLLING_TIMEOUT_US);
+	if (ret != 0) {
+		ERROR(MODULE_TAG "%s polling ARE FSM timeout, ret %d\n", __func__, ret);
+		spin_unlock(&apu_lock);
+		return ret;
+	}
+
+	mmio_write_32(APU_VCORE_BASE + APUSYS_VCORE_CG_CLR, CG_CLR);
+	mmio_write_32(APU_RCX_BASE + APU_RCX_CG_CLR, CG_CLR);
+
+	apu_xpu2apusys_d4_slv_en(D4_SLV_OFF);
+
+	apusys_top_on = true;
+
+	spin_unlock(&apu_lock);
+	return ret;
+}
+
+static void apu_sleep_rpc_rcx(void)
+{
+	mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_CLR);
+	udelay(10);
+
+	mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, (RPC_CTRL | RSV10));
+	udelay(10);
+
+	mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, CLR_IRQ);
+	udelay(10);
+
+	mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, SLEEP_REQ);
+	udelay(100);
+}
+
+int apusys_kernel_apusys_pwr_top_off(void)
+{
+	int ret;
+
+	spin_lock(&apu_lock);
+
+	if (apusys_top_on == false) {
+		INFO(MODULE_TAG "%s: APUSYS already powered off!\n", __func__);
+		spin_unlock(&apu_lock);
+		return 0;
+	}
+
+	apu_xpu2apusys_d4_slv_en(D4_SLV_ON);
+
+	if (mmio_read_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG) == 0) {
+		apu_pwr_flow_remote_sync(1);
+	} else {
+		apu_sleep_rpc_rcx();
+	}
+
+	ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY,
+		       PWR_RDY, PWR_OFF, APU_TOP_OFF_POLLING_TIMEOUT_US);
+	if (ret != 0) {
+		ERROR(MODULE_TAG "%s timeout to wait RPC sleep (val:%d), ret %d\n",
+		      __func__, APU_TOP_OFF_POLLING_TIMEOUT_US, ret);
+		spin_unlock(&apu_lock);
+		return ret;
+	}
+
+	apusys_top_on = false;
+
+	spin_unlock(&apu_lock);
+	return ret;
+}
+
 static void get_pll_pcw(const uint32_t clk_rate, uint32_t *r1, uint32_t *r2)
 {
 	unsigned int fvco = clk_rate;
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.h b/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
index 1f68bd2..b4968d6 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
@@ -24,6 +24,11 @@
 	APU_ARE_NUM,
 };
 
+enum APU_D4_SLV_CTRL {
+	D4_SLV_OFF = 0,
+	D4_SLV_ON,
+};
+
 #define APU_POLL_STEP_US			(5)
 
 #define OUT_CLK_FREQ_MIN			(1500)
@@ -40,20 +45,26 @@
 #define APU_ARE_POLLING_TIMEOUT_US		(10000)
 
 /* APU related reg */
+#define APU_VCORE_BASE				(APU_RCX_VCORE_CONFIG)
+#define APU_RCX_BASE				(APU_RCX_CONFIG)
 #define APU_RPC_BASE				(APU_RPCTOP)
 #define APU_PCU_BASE				(APU_PCUTOP)
 #define APU_ARE0_BASE				(APU_ARETOP_ARE0)
 #define APU_ARE1_BASE				(APU_ARETOP_ARE1)
 #define APU_ARE2_BASE				(APU_ARETOP_ARE2)
+#define APU_MBOX0_BASE				(APU_MBOX0)
 #define APU_AO_CTL_BASE				(APU_AO_CTRL)
 #define APU_PLL_BASE				(APU_PLL)
 #define APU_ACC_BASE				(APU_ACC)
 #define APU_ACX0_RPC_LITE_BASE			(APU_ACX0_RPC_LITE)
 
 /* RPC offset define */
+#define APU_RPC_TOP_CON				(0x0000)
 #define APU_RPC_TOP_SEL				(0x0004)
+#define APU_RPC_STATUS				(0x0014)
 #define APU_RPC_TOP_SEL_1			(0x0018)
 #define APU_RPC_HW_CON				(0x001c)
+#define APU_RPC_INTF_PWR_RDY			(0x0044)
 #define APU_RPC_SW_TYPE0			(0x0200)
 
 /* RPC control */
@@ -68,6 +79,15 @@
 #define RPC_CTRL				(0x0000009e)
 #define RPC_TOP_CTRL				(0x0800501e)
 #define RPC_TOP_CTRL1				BIT(20)
+#define AFC_ENA					BIT(16)
+#define REG_WAKEUP_SET				BIT(8)
+#define REG_WAKEUP_CLR				BIT(12)
+#define PWR_RDY					BIT(0)
+#define PWR_OFF					(0)
+#define RPC_STATUS_RDY				BIT(29)
+#define RSV10					BIT(10)
+#define CLR_IRQ					(0x6)
+#define SLEEP_REQ				BIT(0)
 
 /* PLL offset define */
 #define PLL4H_PLL1_CON1				(0x000c)
@@ -137,6 +157,12 @@
 #define ARE_ENTRY1_SRAM_L_INIT			(0x76543210)
 #define ARE_CONFG_INI				BIT(2)
 
+/* VCORE offset define */
+#define APUSYS_VCORE_CG_CLR			(0x0008)
+
+/* RCX offset define */
+#define APU_RCX_CG_CLR				(0x0008)
+
 /* SPM offset define */
 #define APUSYS_BUCK_ISOLATION			(0x03ec)
 
@@ -149,6 +175,18 @@
 /* apu_rcx_ao_ctrl control */
 #define VCORE_ARE_REQ				BIT(2)
 
+/* xpu2apusys */
+#define INFRA_FMEM_BUS_u_SI21_CTRL_0		(0x002c)
+#define INFRA_FMEM_BUS_u_SI22_CTRL_0		(0x0044)
+#define INFRA_FMEM_BUS_u_SI11_CTRL_0		(0x0048)
+#define INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0	(0x01d0)
+
+/* xpu2apusys */
+#define INFRA_FMEM_BUS_u_SI21_CTRL_EN		BIT(12)
+#define INFRA_FMEM_BUS_u_SI22_CTRL_EN		BIT(13)
+#define INFRA_FMEM_BUS_u_SI11_CTRL_EN		BIT(11)
+#define INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN	BIT(15)
+
 /* PCU offset define */
 #define APU_PCU_CTRL_SET			(0x0000)
 #define APU_PCU_BUCK_STEP_SEL			(0x0030)
@@ -188,6 +226,13 @@
 #define APU_RPC_SW_TYPE8			(0x0220)
 #define APU_RPC_SW_TYPE9			(0x0224)
 
+/* power flow sync */
+#define PWR_FLOW_SYNC_REG			(0x0440)
+
+#define CG_CLR					(0xffffffff)
+
 int apusys_power_init(void);
+int apusys_kernel_apusys_pwr_top_on(void);
+int apusys_kernel_apusys_pwr_top_off(void);
 
 #endif /* APUSYS_POWER_H */
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 576dc3d..fc9725e 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -28,6 +28,9 @@
  * APUSYS related constants
  ******************************************************************************/
 #define BCRM_FMEM_PDN_BASE	(IO_PHYS + 0x00276000)
+#define APU_RCX_CONFIG		(IO_PHYS + 0x09020000)
+#define APU_RCX_VCORE_CONFIG	(IO_PHYS + 0x090e0000)
+#define APU_MBOX0		(IO_PHYS + 0x090e1000)
 #define APU_RPCTOP		(IO_PHYS + 0x090f0000)
 #define APU_PCUTOP		(IO_PHYS + 0x090f1000)
 #define APU_AO_CTRL		(IO_PHYS + 0x090f2000)
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index 803f8e2..98b8254 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -23,15 +23,14 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CLUSTER1_CORE_COUNT	U(0)
 #else
-#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
 /*
  * Define the number of cores per cluster used in calculating core position.
  * The cluster number is shifted by this value and added to the core ID,
  * so its value represents log2(cores/cluster).
- * Default is 2**(2) = 4 cores per cluster.
+ * Default is 2**(4) = 16 cores per cluster.
  */
-#define PLATFORM_CPU_PER_CLUSTER_SHIFT	U(2)
-
+#define PLATFORM_CPU_PER_CLUSTER_SHIFT	U(4)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	(U(1) << PLATFORM_CPU_PER_CLUSTER_SHIFT)
 #define PLATFORM_CLUSTER_COUNT		U(2)
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CLUSTER1_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c
index db71817..80e4d8d 100644
--- a/plat/rpi/rpi3/rpi3_bl2_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl2_setup.c
@@ -35,7 +35,9 @@
 	params.reg_base = RPI3_SDHOST_BASE;
 	params.bus_width = MMC_BUS_WIDTH_1;
 	params.clk_rate = 50000000;
+	params.clk_rate_initial = (RPI3_SDHOST_MAX_CLOCK / HC_CLOCKDIVISOR_MAXVAL);
 	mmc_info.mmc_dev_type = MMC_IS_SD_HC;
+	mmc_info.ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4;
 	rpi3_sdhost_init(&params, &mmc_info);
 }
 
diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c
index ed7f270..1167d34 100644
--- a/plat/xilinx/versal/aarch64/versal_common.c
+++ b/plat/xilinx/versal/aarch64/versal_common.c
@@ -23,7 +23,7 @@
 	MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(FPD_MAINCCI_BASE, FPD_MAINCCI_SIZE, MT_DEVICE | MT_RW |
+	MAP_REGION_FLAT(PLAT_ARM_CCI_BASE, PLAT_ARM_CCI_SIZE, MT_DEVICE | MT_RW |
 			MT_SECURE),
 	{ 0 }
 };
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index ce4d98c..2ba0422 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -50,6 +50,7 @@
  * CCI-400 related constants
  ******************************************************************************/
 #define PLAT_ARM_CCI_BASE		0xFD000000
+#define PLAT_ARM_CCI_SIZE		0x00100000
 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX	4
 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX	5
 
@@ -110,9 +111,6 @@
 #define CRF_RST_APU_ACPU_RESET		(1 << 0)
 #define CRF_RST_APU_ACPU_PWRON_RESET	(1 << 10)
 
-#define FPD_MAINCCI_BASE	0xFD000000
-#define FPD_MAINCCI_SIZE	0x00100000
-
 /* APU registers and bitfields */
 #define FPD_APU_BASE		0xFD5C0000U
 #define FPD_APU_CONFIG_0	(FPD_APU_BASE + 0x20U)