commit cf7cf5449297cf0e86e9b1f7150174e2aab89528
author Govindraj Raja <govindraj.raja@arm.com> Tue Jan 21 12:32:14 2025 -0600
committer Govindraj Raja <govindraj.raja@arm.com> Mon Feb 03 10:14:33 2025 -0600
tree c368dfe2264e1f0fcd8c0058a8092285afa02013
parent 4c3a46171cef846478f7c81b384414f2091b3c0e

fix(cpus): workaround for Cortex-A710 erratum 3701772

Cortex-A710 erratum 3701772 that applies to all revisions <= r2p1
and is still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest/

Change-Id: I997c9cfaa75321f22b4f690c4d3f234c0b51c670
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

lib/cpus/cpu-ops.mk

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 1984689..81ce131 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -642,6 +642,11 @@
 # open.
 CPU_FLAG_LIST += ERRATA_A710_2778471
 
+# Flag to apply erratum  3701772 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r2p0, r2p1
+# of the Cortex-A710 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A710_3701772
+
 # Flag to apply erratum 2002655 workaround during reset. This erratum applies
 # to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_N2_2002655