Merge pull request #1276 from swarren/issue-551
Make all build results depend on all makefiles
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 8cf15b8..c9e8748 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -1582,6 +1582,7 @@
<path-to>/Foundation_Platform \
--cores=4 \
+ --arm-v8.0 \
--secure-memory \
--visualization \
--gicv3 \
@@ -1600,6 +1601,12 @@
and enable the GICv3 device in the model. Note that without this option,
the Foundation FVP defaults to legacy (Versatile Express) memory map which
is not supported by ARM Trusted Firmware.
+- In order for the Arm Trusted Firmware to run correctly on the Foundation
+ Model the architecture versions must match. The Foundation FVP defaults to
+ the highest v8.x version it supports but the default build for Arm Trusted
+ Firmware is for v8.0. To avoid issues either start the Foundation Model to
+ use v8.0 architecture using the ``--arm-v8.0`` option or build Arm Trusted
+ Firmware with an appropriate value for ``ARM_ARCH_MINOR``.
Running on the AEMv8 Base FVP with reset to BL1 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h
index f092cf1..89156ed 100644
--- a/drivers/arm/tzc/tzc_common_private.h
+++ b/drivers/arm/tzc/tzc_common_private.h
@@ -169,8 +169,6 @@
nsaid_permissions); \
}
-#if ENABLE_ASSERTIONS
-
static inline unsigned int _tzc_read_peripheral_id(uintptr_t base)
{
unsigned int id;
@@ -182,6 +180,7 @@
return id;
}
+#if ENABLE_ASSERTIONS
#ifdef AARCH32
static inline unsigned long long _tzc_get_max_top_addr(int addr_width)
{
diff --git a/drivers/synopsys/ufs/dw_ufs.c b/drivers/synopsys/ufs/dw_ufs.c
index d8ed5b6..b0ea3e7 100644
--- a/drivers/synopsys/ufs/dw_ufs.c
+++ b/drivers/synopsys/ufs/dw_ufs.c
@@ -97,10 +97,21 @@
int result;
unsigned int data, tx_lanes, rx_lanes;
uintptr_t base;
+ unsigned int flags;
assert((params != NULL) && (params->reg_base != 0));
base = params->reg_base;
+ flags = params->flags;
+ if ((flags & UFS_FLAGS_VENDOR_SKHYNIX) != 0U) {
+ NOTICE("ufs: H**** device must set VS_DebugSaveConfigTime 0x10\n");
+ /* VS_DebugSaveConfigTime */
+ result = ufshc_dme_set(0xd0a0, 0x0, 0x10);
+ assert(result == 0);
+ /* sync length */
+ result = ufshc_dme_set(0x1556, 0x0, 0x48);
+ assert(result == 0);
+ }
result = ufshc_dme_get(PA_TACTIVATE_OFFSET, 0, &data);
assert(result == 0);
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index d513d0a..254866f 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -705,11 +705,27 @@
}
}
+static void ufs_get_device_info(struct ufs_dev_desc *card_data)
+{
+ uint8_t desc_buf[DESC_DEVICE_MAX_SIZE];
+
+ ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0,
+ (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE);
+
+ /*
+ * getting vendor (manufacturerID) and Bank Index in big endian
+ * format
+ */
+ card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) |
+ (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]));
+}
+
int ufs_init(const ufs_ops_t *ops, ufs_params_t *params)
{
int result;
unsigned int data;
uic_cmd_t cmd;
+ struct ufs_dev_desc card = {0};
assert((params != NULL) &&
(params->reg_base != 0) &&
@@ -750,10 +766,17 @@
ops->phy_init(&ufs_params);
result = ufshc_link_startup(ufs_params.reg_base);
assert(result == 0);
+
+ ufs_enum();
+
+ ufs_get_device_info(&card);
+ if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) {
+ ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX;
+ }
+
ops->phy_set_pwr_mode(&ufs_params);
}
- ufs_enum();
(void)result;
return 0;
}
diff --git a/include/drivers/ufs.h b/include/drivers/ufs.h
index 3a4f1c7..88dedc5 100644
--- a/include/drivers/ufs.h
+++ b/include/drivers/ufs.h
@@ -7,6 +7,8 @@
#ifndef __UFS_H__
#define __UFS_H__
+#include <utils_def.h>
+
/* register map of UFSHCI */
/* Controller Capabilities */
#define CAP 0x00
@@ -214,6 +216,9 @@
#define DESC_TYPE_INTERCONNECT 0x04
#define DESC_TYPE_STRING 0x05
+#define DESC_DEVICE_MAX_SIZE 0x1F
+#define DEVICE_DESC_PARAM_MANF_ID 0x18
+
#define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */
#define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */
@@ -246,8 +251,22 @@
#define FLAG_DEVICE_INIT 0x01
+#define UFS_VENDOR_SKHYNIX U(0x1AD)
+
+#define MAX_MODEL_LEN 16
+/**
+ * ufs_dev_desc - ufs device details from the device descriptor
+ * @wmanufacturerid: card details
+ * @model: card model
+ */
+struct ufs_dev_desc {
+ uint16_t wmanufacturerid;
+ int8_t model[MAX_MODEL_LEN + 1];
+};
+
/* UFS Driver Flags */
#define UFS_FLAGS_SKIPINIT (1 << 0)
+#define UFS_FLAGS_VENDOR_SKHYNIX (U(1) << 2)
typedef struct sense_data {
uint8_t resp_code : 7;
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 72e42c6..ddc0808 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -206,7 +206,8 @@
*/
.globl print_errata_status
func print_errata_status
- push {r4, lr}
+ /* r12 is pushed only for the sake of 8-byte stack alignment */
+ push {r4, r5, r12, lr}
#ifdef IMAGE_BL1
/*
* BL1 doesn't have per-CPU data. So retrieve the CPU operations
@@ -241,6 +242,6 @@
blxne r4
1:
#endif
- pop {r4, pc}
+ pop {r4, r5, r12, pc}
endfunc print_errata_status
#endif
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 5d83118..906ed19 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -24,6 +24,20 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
+/*
+ * Check that BL2_BASE is atleast a page over ARM_BL_RAM_BASE. The page is for
+ * `meminfo_t` data structure and TB_FW_CONFIG passed from BL1. Not needed
+ * when BL2 is compiled for BL_AT_EL3 as BL2 doesn't need any info from BL1 and
+ * BL2 is loaded at base of usable SRAM.
+ */
+#if BL2_AT_EL3
+#define BL1_MEMINFO_OFFSET 0x0
+#else
+#define BL1_MEMINFO_OFFSET PAGE_SIZE
+#endif
+
+CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows);
+
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl2_early_platform_setup
#pragma weak bl2_platform_setup
diff --git a/plat/arm/common/sp_min/arm_sp_min.mk b/plat/arm/common/sp_min/arm_sp_min.mk
index e6792ca..edab884 100644
--- a/plat/arm/common/sp_min/arm_sp_min.mk
+++ b/plat/arm/common/sp_min/arm_sp_min.mk
@@ -5,6 +5,13 @@
#
# SP MIN source files common to ARM standard platforms
+
+# Skip building BL1 and BL2 if RESET_TO_SP_MIN flag is set.
+ifeq (${RESET_TO_SP_MIN},1)
+ BL1_SOURCES =
+ BL2_SOURCES =
+endif
+
BL32_SOURCES += plat/arm/common/arm_pm.c \
plat/arm/common/arm_topology.c \
plat/arm/common/sp_min/arm_sp_min_setup.c \
diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c
index 38e1a61..ca6c03b 100644
--- a/plat/common/plat_gicv2.c
+++ b/plat/common/plat_gicv2.c
@@ -134,6 +134,8 @@
type == INTR_TYPE_EL3 ||
type == INTR_TYPE_NS);
+ assert(sec_state_is_valid(security_state));
+
/* Non-secure interrupts are signaled on the IRQ line always */
if (type == INTR_TYPE_NS)
return __builtin_ctz(SCR_IRQ_BIT);
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 334fbe4..26633c2 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -150,12 +150,12 @@
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/common/gic_common.c \
+ plat/common/plat_gicv2.c \
plat/common/plat_psci_common.c \
plat/qemu/qemu_pm.c \
plat/qemu/topology.c \
plat/qemu/aarch64/plat_helpers.S \
- plat/qemu/qemu_bl31_setup.c \
- plat/qemu/qemu_gic.c
+ plat/qemu/qemu_bl31_setup.c
endif
# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
diff --git a/plat/qemu/qemu_gic.c b/plat/qemu/qemu_gic.c
deleted file mode 100644
index 41b5eb4..0000000
--- a/plat/qemu/qemu_gic.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <bl_common.h>
-#include <gicv2.h>
-#include <interrupt_mgmt.h>
-
-uint32_t plat_ic_get_pending_interrupt_id(void)
-{
- return gicv2_get_pending_interrupt_id();
-}
-
-uint32_t plat_ic_get_pending_interrupt_type(void)
-{
- return gicv2_get_pending_interrupt_type();
-}
-
-uint32_t plat_ic_acknowledge_interrupt(void)
-{
- return gicv2_acknowledge_interrupt();
-}
-
-uint32_t plat_ic_get_interrupt_type(uint32_t id)
-{
- uint32_t group;
-
- group = gicv2_get_interrupt_group(id);
-
- /* Assume that all secure interrupts are S-EL1 interrupts */
- if (!group)
- return INTR_TYPE_S_EL1;
- else
- return INTR_TYPE_NS;
-
-}
-
-void plat_ic_end_of_interrupt(uint32_t id)
-{
- gicv2_end_of_interrupt(id);
-}
-
-uint32_t plat_interrupt_type_to_line(uint32_t type,
- uint32_t security_state)
-{
- assert(type == INTR_TYPE_S_EL1 ||
- type == INTR_TYPE_EL3 ||
- type == INTR_TYPE_NS);
-
- assert(sec_state_is_valid(security_state));
-
- /* Non-secure interrupts are signalled on the IRQ line always */
- if (type == INTR_TYPE_NS)
- return __builtin_ctz(SCR_IRQ_BIT);
-
- /*
- * Secure interrupts are signalled using the IRQ line if the FIQ_EN
- * bit is not set else they are signalled using the FIQ line.
- */
- if (gicv2_is_fiq_enabled())
- return __builtin_ctz(SCR_FIQ_BIT);
- else
- return __builtin_ctz(SCR_IRQ_BIT);
-}
-
diff --git a/plat/qemu/sp_min/sp_min-qemu.mk b/plat/qemu/sp_min/sp_min-qemu.mk
index 5e8875b..e93a0c2 100644
--- a/plat/qemu/sp_min/sp_min-qemu.mk
+++ b/plat/qemu/sp_min/sp_min-qemu.mk
@@ -6,7 +6,6 @@
BL32_SOURCES += plat/qemu/sp_min/sp_min_setup.c \
plat/qemu/aarch32/plat_helpers.S \
- plat/qemu/qemu_gic.c \
plat/qemu/qemu_pm.c \
plat/qemu/topology.c
@@ -14,7 +13,8 @@
lib/cpus/aarch32/cortex_a15.S
BL32_SOURCES += plat/common/aarch32/platform_mp_stack.S \
- plat/common/plat_psci_common.c
+ plat/common/plat_psci_common.c \
+ plat/common/plat_gicv2.c
BL32_SOURCES += drivers/arm/gic/v2/gicv2_helpers.c \