Merge changes from topic "bridge-en" into integration
* changes:
intel: Add function to check fpga readiness
intel: Add bridge control for FPGA reconfig
intel: FPGA config_isdone() status query
intel: System Manager refactoring
intel: Refactor reset manager driver
intel: Enable bridge access in Intel platform
intel: Modify non secure access function
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 86b7ab8..9587d48 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -18,13 +18,13 @@
#include "agilex_clock_manager.h"
#include "agilex_memory_controller.h"
#include "agilex_pinmux.h"
-#include "agilex_reset_manager.h"
-#include "agilex_system_manager.h"
#include "ccu/ncore_ccu.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
+#include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
#include "wdt/watchdog.h"
@@ -74,7 +74,10 @@
socfpga_delay_timer_init();
init_ncore_ccu();
init_hard_memory_controller();
- enable_ns_bridge_access();
+ mailbox_init();
+
+ if (!intel_mailbox_is_fpga_not_ready())
+ socfpga_bridges_enable();
}
@@ -107,8 +110,6 @@
info.mmc_dev_type = MMC_IS_SD;
info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
- mailbox_init();
-
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
dw_mmc_init(¶ms, &info);
diff --git a/plat/intel/soc/agilex/include/agilex_memory_controller.h b/plat/intel/soc/agilex/include/agilex_memory_controller.h
index 419bd2e..3746d92 100644
--- a/plat/intel/soc/agilex/include/agilex_memory_controller.h
+++ b/plat/intel/soc/agilex/include/agilex_memory_controller.h
@@ -24,9 +24,6 @@
#define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \
(((value) & 0x00000060) >> 5)
-#define AGX_RSTMGR_BRGMODRST 0xffd1102c
-#define AGX_RSTMGR_BRGMODRST_DDRSCH 0x00000040
-
#define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
#define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
diff --git a/plat/intel/soc/agilex/include/agilex_reset_manager.h b/plat/intel/soc/agilex/include/agilex_reset_manager.h
deleted file mode 100644
index a1b6297..0000000
--- a/plat/intel/soc/agilex/include/agilex_reset_manager.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef AGX_RESETMANAGER_H
-#define AGX_RESETMANAGER_H
-
-#define AGX_RSTMGR_HDSKEN 0xffd11010
-#define AGX_RSTMGR_PER0MODRST 0xffd11024
-#define AGX_RSTMGR_PER1MODRST 0xffd11028
-#define AGX_RSTMGR_BRGMODRST 0xffd1102c
-
-#define AGX_RSTMGR_PER0MODRST_EMAC0 0x00000001
-#define AGX_RSTMGR_PER0MODRST_EMAC1 0x00000002
-#define AGX_RSTMGR_PER0MODRST_EMAC2 0x00000004
-#define AGX_RSTMGR_PER0MODRST_USB0 0x00000008
-#define AGX_RSTMGR_PER0MODRST_USB1 0x00000010
-#define AGX_RSTMGR_PER0MODRST_NAND 0x00000020
-#define AGX_RSTMGR_PER0MODRST_SDMMC 0x00000080
-#define AGX_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
-#define AGX_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
-#define AGX_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
-#define AGX_RSTMGR_PER0MODRST_USB0OCP 0x00000800
-#define AGX_RSTMGR_PER0MODRST_USB1OCP 0x00001000
-#define AGX_RSTMGR_PER0MODRST_NANDOCP 0x00002000
-#define AGX_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
-#define AGX_RSTMGR_PER0MODRST_DMA 0x00010000
-#define AGX_RSTMGR_PER0MODRST_SPIM0 0x00020000
-#define AGX_RSTMGR_PER0MODRST_SPIM1 0x00040000
-#define AGX_RSTMGR_PER0MODRST_SPIS0 0x00080000
-#define AGX_RSTMGR_PER0MODRST_SPIS1 0x00100000
-#define AGX_RSTMGR_PER0MODRST_DMAOCP 0x00200000
-#define AGX_RSTMGR_PER0MODRST_EMACPTP 0x00400000
-#define AGX_RSTMGR_PER0MODRST_DMAIF0 0x01000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF1 0x02000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF2 0x04000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF3 0x08000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF4 0x10000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF5 0x20000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF6 0x40000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF7 0x80000000
-
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG0 0x1
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG1 0x2
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG2 0x4
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG3 0x8
-#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
-#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
-#define AGX_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
-#define AGX_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
-#define AGX_RSTMGR_PER1MODRST_I2C0 0x00000100
-#define AGX_RSTMGR_PER1MODRST_I2C1 0x00000200
-#define AGX_RSTMGR_PER1MODRST_I2C2 0x00000400
-#define AGX_RSTMGR_PER1MODRST_I2C3 0x00000800
-#define AGX_RSTMGR_PER1MODRST_I2C4 0x00001000
-#define AGX_RSTMGR_PER1MODRST_UART0 0x00010000
-#define AGX_RSTMGR_PER1MODRST_UART1 0x00020000
-#define AGX_RSTMGR_PER1MODRST_GPIO0 0x01000000
-#define AGX_RSTMGR_PER1MODRST_GPIO1 0x02000000
-
-#define AGX_RSTMGR_HDSKEN_FPGAHSEN 0x00000004
-#define AGX_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
-#define AGX_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
-#define AGX_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
-#define AGX_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
-#define AGX_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
-
-#define AGX_RSTMGR_BRGMODRST_SOC2FPGA 0x1
-#define AGX_RSTMGR_BRGMODRST_LWHPS2FPGA 0x2
-#define AGX_RSTMGR_BRGMODRST_FPGA2SOC 0x4
-#define AGX_RSTMGR_BRGMODRST_MPFE 0x40
-
-void deassert_peripheral_reset(void);
-void config_hps_hs_before_warm_reset(void);
-
-#endif
-
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
deleted file mode 100644
index be29536..0000000
--- a/plat/intel/soc/agilex/include/agilex_system_manager.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef AGX_SYSTEMMANAGER_H
-#define AGX_SYSTEMMANAGER_H
-
-#define AGX_FIREWALL_SOC2FPGA 0xffd21200
-#define AGX_FIREWALL_LWSOC2FPGA 0xffd21300
-
-#define AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
-#define AGX_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
-#define AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
-#define AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010
-#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c
-#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020
-#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024
-#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028
-#define AGX_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c
-#define AGX_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030
-#define AGX_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034
-#define AGX_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040
-#define AGX_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044
-#define AGX_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048
-#define AGX_NOC_FW_L4_PER_SCR_I2C0 0xffd21050
-#define AGX_NOC_FW_L4_PER_SCR_I2C1 0xffd21054
-#define AGX_NOC_FW_L4_PER_SCR_I2C2 0xffd21058
-#define AGX_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c
-#define AGX_NOC_FW_L4_PER_SCR_I2C4 0xffd21060
-#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064
-#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068
-#define AGX_NOC_FW_L4_PER_SCR_UART0 0xffd2106c
-#define AGX_NOC_FW_L4_PER_SCR_UART1 0xffd21070
-
-#define AGX_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120
-#define AGX_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c
-#define AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130
-#define AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134
-#define AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138
-#define AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140
-#define AGX_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144
-#define AGX_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148
-#define AGX_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c
-#define AGX_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154
-#define AGX_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158
-#define AGX_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c
-#define AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160
-#define AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164
-#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168
-#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c
-#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170
-#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174
-#define AGX_NOC_FW_L4_SYS_SCR_DAP 0xffd21178
-#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190
-#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194
-
-#define AGX_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
-#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
-
-#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x))
-#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
-#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
-#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
-
-#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
-#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
-
-void enable_ns_bridge_access(void);
-
-#endif
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index a346cb5..b4e0921 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -16,8 +16,13 @@
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE 0xff808000
-#define SOCFPGA_RSTMGR_OFST 0xffd11000
-#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020
+#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300
#endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index ef02a8d..f47c3f1 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -38,14 +38,14 @@
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
plat/intel/soc/agilex/soc/agilex_memory_controller.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
- plat/intel/soc/agilex/soc/agilex_reset_manager.c \
- plat/intel/soc/agilex/soc/agilex_system_manager.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
+ plat/intel/soc/common/soc/socfpga_reset_manager.c \
+ plat/intel/soc/common/soc/socfpga_system_manager.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c \
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -60,6 +60,7 @@
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
+ plat/intel/soc/common/soc/socfpga_reset_manager.c
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index 96b669c..c6c48ba 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -11,8 +11,8 @@
#include <lib/mmio.h>
#include "agilex_clock_manager.h"
-#include "agilex_system_manager.h"
#include "socfpga_handoff.h"
+#include "socfpga_system_manager.h"
uint32_t wait_pll_lock(void)
@@ -261,9 +261,9 @@
CLKMGR_PERPLL_EN_RESET);
/* Pass clock source frequency into scratch register */
- mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
+ mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1),
hoff_ptr->hps_osc_clk_h);
- mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
+ mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2),
hoff_ptr->fpga_clk_hz);
}
@@ -275,14 +275,14 @@
switch (CLKMGR_PSRC(pllglob)) {
case CLKMGR_PLLGLOB_PSRC_EOSC1:
- scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
+ scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
ref_clk = mmio_read_32(scr_reg);
break;
case CLKMGR_PLLGLOB_PSRC_INTOSC:
ref_clk = CLKMGR_INTOSC_HZ;
break;
case CLKMGR_PLLGLOB_PSRC_F2S:
- scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
+ scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
ref_clk = mmio_read_32(scr_reg);
break;
default:
diff --git a/plat/intel/soc/agilex/soc/agilex_reset_manager.c b/plat/intel/soc/agilex/soc/agilex_reset_manager.c
deleted file mode 100644
index 65d2029..0000000
--- a/plat/intel/soc/agilex/soc/agilex_reset_manager.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-
-#include "agilex_reset_manager.h"
-
-void deassert_peripheral_reset(void)
-{
- mmio_clrbits_32(AGX_RSTMGR_PER1MODRST,
- AGX_RSTMGR_PER1MODRST_WATCHDOG0 |
- AGX_RSTMGR_PER1MODRST_WATCHDOG1 |
- AGX_RSTMGR_PER1MODRST_WATCHDOG2 |
- AGX_RSTMGR_PER1MODRST_WATCHDOG3 |
- AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 |
- AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 |
- AGX_RSTMGR_PER1MODRST_SPTIMER0 |
- AGX_RSTMGR_PER1MODRST_SPTIMER1 |
- AGX_RSTMGR_PER1MODRST_I2C0 |
- AGX_RSTMGR_PER1MODRST_I2C1 |
- AGX_RSTMGR_PER1MODRST_I2C2 |
- AGX_RSTMGR_PER1MODRST_I2C3 |
- AGX_RSTMGR_PER1MODRST_I2C4 |
- AGX_RSTMGR_PER1MODRST_UART0 |
- AGX_RSTMGR_PER1MODRST_UART1 |
- AGX_RSTMGR_PER1MODRST_GPIO0 |
- AGX_RSTMGR_PER1MODRST_GPIO1);
-
- mmio_clrbits_32(AGX_RSTMGR_PER0MODRST,
- AGX_RSTMGR_PER0MODRST_EMAC0OCP |
- AGX_RSTMGR_PER0MODRST_EMAC1OCP |
- AGX_RSTMGR_PER0MODRST_EMAC2OCP |
- AGX_RSTMGR_PER0MODRST_USB0OCP |
- AGX_RSTMGR_PER0MODRST_USB1OCP |
- AGX_RSTMGR_PER0MODRST_NANDOCP |
- AGX_RSTMGR_PER0MODRST_SDMMCOCP |
- AGX_RSTMGR_PER0MODRST_DMAOCP);
-
- mmio_clrbits_32(AGX_RSTMGR_PER0MODRST,
- AGX_RSTMGR_PER0MODRST_EMAC0 |
- AGX_RSTMGR_PER0MODRST_EMAC1 |
- AGX_RSTMGR_PER0MODRST_EMAC2 |
- AGX_RSTMGR_PER0MODRST_USB0 |
- AGX_RSTMGR_PER0MODRST_USB1 |
- AGX_RSTMGR_PER0MODRST_NAND |
- AGX_RSTMGR_PER0MODRST_SDMMC |
- AGX_RSTMGR_PER0MODRST_DMA |
- AGX_RSTMGR_PER0MODRST_SPIM0 |
- AGX_RSTMGR_PER0MODRST_SPIM1 |
- AGX_RSTMGR_PER0MODRST_SPIS0 |
- AGX_RSTMGR_PER0MODRST_SPIS1 |
- AGX_RSTMGR_PER0MODRST_EMACPTP |
- AGX_RSTMGR_PER0MODRST_DMAIF0 |
- AGX_RSTMGR_PER0MODRST_DMAIF1 |
- AGX_RSTMGR_PER0MODRST_DMAIF2 |
- AGX_RSTMGR_PER0MODRST_DMAIF3 |
- AGX_RSTMGR_PER0MODRST_DMAIF4 |
- AGX_RSTMGR_PER0MODRST_DMAIF5 |
- AGX_RSTMGR_PER0MODRST_DMAIF6 |
- AGX_RSTMGR_PER0MODRST_DMAIF7);
-
- mmio_clrbits_32(AGX_RSTMGR_BRGMODRST,
- AGX_RSTMGR_BRGMODRST_MPFE);
-}
-
-void config_hps_hs_before_warm_reset(void)
-{
- uint32_t or_mask = 0;
-
- or_mask |= AGX_RSTMGR_HDSKEN_SDRSELFREFEN;
- or_mask |= AGX_RSTMGR_HDSKEN_FPGAHSEN;
- or_mask |= AGX_RSTMGR_HDSKEN_ETRSTALLEN;
- or_mask |= AGX_RSTMGR_HDSKEN_L2FLUSHEN;
- or_mask |= AGX_RSTMGR_HDSKEN_L3NOC_DBG;
- or_mask |= AGX_RSTMGR_HDSKEN_DEBUG_L3NOC;
-
- mmio_setbits_32(AGX_RSTMGR_HDSKEN, or_mask);
-}
-
diff --git a/plat/intel/soc/agilex/soc/agilex_system_manager.c b/plat/intel/soc/agilex/soc/agilex_system_manager.c
deleted file mode 100644
index 88e895d..0000000
--- a/plat/intel/soc/agilex/soc/agilex_system_manager.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-
-#include "agilex_system_manager.h"
-
-void enable_nonsecure_access(void)
-{
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
- DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
-
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
-
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
-
- mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
-}
-
-void enable_ns_bridge_access(void)
-{
- mmio_write_32(AGX_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL);
- mmio_write_32(AGX_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL);
-}
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index c5f2fbe..c4b9e59 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -120,5 +120,6 @@
void mailbox_clear_response(void);
uint32_t intel_mailbox_get_config_status(uint32_t cmd);
+int intel_mailbox_is_fpga_not_ready(void);
#endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/include/socfpga_reset_manager.h b/plat/intel/soc/common/include/socfpga_reset_manager.h
index 3fbf242..637f8df 100644
--- a/plat/intel/soc/common/include/socfpga_reset_manager.h
+++ b/plat/intel/soc/common/include/socfpga_reset_manager.h
@@ -7,12 +7,102 @@
#ifndef SOCFPGA_RESETMANAGER_H
#define SOCFPGA_RESETMANAGER_H
-#define SOCFPGA_RSTMGR_STAT 0xffd11000
-#define SOCFPGA_RSTMGR_HDSKEN 0xffd11010
-#define SOCFPGA_RSTMGR_COLDMODRST 0xffd11034
-#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0xffd11064
+#include "socfpga_plat_def.h"
+
+
+/* Register Mapping */
+
+#define SOCFPGA_RSTMGR_STAT 0x000
+#define SOCFPGA_RSTMGR_HDSKEN 0x010
+#define SOCFPGA_RSTMGR_MPUMODRST 0x020
+#define SOCFPGA_RSTMGR_PER0MODRST 0x024
+#define SOCFPGA_RSTMGR_PER1MODRST 0x028
+#define SOCFPGA_RSTMGR_BRGMODRST 0x02c
+#define SOCFPGA_RSTMGR_COLDMODRST 0x034
+#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064
+
+/* Field Mapping */
+
+#define RSTMGR_PER0MODRST_EMAC0 0x00000001
+#define RSTMGR_PER0MODRST_EMAC1 0x00000002
+#define RSTMGR_PER0MODRST_EMAC2 0x00000004
+#define RSTMGR_PER0MODRST_USB0 0x00000008
+#define RSTMGR_PER0MODRST_USB1 0x00000010
+#define RSTMGR_PER0MODRST_NAND 0x00000020
+#define RSTMGR_PER0MODRST_SDMMC 0x00000080
+#define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
+#define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
+#define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
+#define RSTMGR_PER0MODRST_USB0OCP 0x00000800
+#define RSTMGR_PER0MODRST_USB1OCP 0x00001000
+#define RSTMGR_PER0MODRST_NANDOCP 0x00002000
+#define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
+#define RSTMGR_PER0MODRST_DMA 0x00010000
+#define RSTMGR_PER0MODRST_SPIM0 0x00020000
+#define RSTMGR_PER0MODRST_SPIM1 0x00040000
+#define RSTMGR_PER0MODRST_SPIS0 0x00080000
+#define RSTMGR_PER0MODRST_SPIS1 0x00100000
+#define RSTMGR_PER0MODRST_DMAOCP 0x00200000
+#define RSTMGR_PER0MODRST_EMACPTP 0x00400000
+#define RSTMGR_PER0MODRST_DMAIF0 0x01000000
+#define RSTMGR_PER0MODRST_DMAIF1 0x02000000
+#define RSTMGR_PER0MODRST_DMAIF2 0x04000000
+#define RSTMGR_PER0MODRST_DMAIF3 0x08000000
+#define RSTMGR_PER0MODRST_DMAIF4 0x10000000
+#define RSTMGR_PER0MODRST_DMAIF5 0x20000000
+#define RSTMGR_PER0MODRST_DMAIF6 0x40000000
+#define RSTMGR_PER0MODRST_DMAIF7 0x80000000
+
+#define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001
+#define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002
+#define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004
+#define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008
+#define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
+#define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
+#define RSTMGR_PER1MODRST_SPTIMER0 0x00000040
+#define RSTMGR_PER1MODRST_SPTIMER1 0x00000080
+#define RSTMGR_PER1MODRST_I2C0 0x00000100
+#define RSTMGR_PER1MODRST_I2C1 0x00000200
+#define RSTMGR_PER1MODRST_I2C2 0x00000400
+#define RSTMGR_PER1MODRST_I2C3 0x00000800
+#define RSTMGR_PER1MODRST_I2C4 0x00001000
+#define RSTMGR_PER1MODRST_UART0 0x00010000
+#define RSTMGR_PER1MODRST_UART1 0x00020000
+#define RSTMGR_PER1MODRST_GPIO0 0x01000000
+#define RSTMGR_PER1MODRST_GPIO1 0x02000000
+
+#define RSTMGR_HDSKEN_FPGAHSEN 0x00000004
+#define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
+#define RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
+#define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
+#define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
+#define RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
+
+#define RSTMGR_BRGMODRST_SOC2FPGA 0x1
+#define RSTMGR_BRGMODRST_LWHPS2FPGA 0x2
+#define RSTMGR_BRGMODRST_FPGA2SOC 0x4
+#define RSTMGR_BRGMODRST_F2SSDRAM1 0x10
+#define RSTMGR_BRGMODRST_F2SSDRAM2 0x20
+#define RSTMGR_BRGMODRST_MPFE 0x40
+#define RSTMGR_BRGMODRST_DDRSCH 0x40
+
+/* Definitions */
+
+#define RSTMGR_L2_MODRST 0x0100
+#define RSTMGR_HDSKEN_SET 0x010D
+
+/* Macros */
+
+#define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE \
+ + (SOCFPGA_RSTMGR_##_reg))
+#define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field)
+
+/* Function Declarations */
+
+void deassert_peripheral_reset(void);
+void config_hps_hs_before_warm_reset(void);
-#define SOCFPGA_RSTMGR_HDSKEN_SET 0x0000010D
-#define SOCFPGA_RSTMGR_SDMWARMRST 0x00000002
+int socfpga_bridges_enable(void);
+int socfpga_bridges_disable(void);
#endif /* SOCFPGA_RESETMANAGER_H */
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
new file mode 100644
index 0000000..f1637ae
--- /dev/null
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SOCFPGA_SYSTEMMANAGER_H
+#define SOCFPGA_SYSTEMMANAGER_H
+
+#include "socfpga_plat_def.h"
+
+/* System Manager Register Map */
+
+#define SOCFPGA_SYSMGR_SDMMC 0x28
+
+#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc
+#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0
+#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4
+
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
+
+/* Field Masking */
+
+#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
+
+#define IDLE_DATA_LWSOC2FPGA BIT(0)
+#define IDLE_DATA_SOC2FPGA BIT(4)
+#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
+
+#define SCR_AXI_AP_MASK BIT(24)
+#define SCR_FPGA2SOC_MASK BIT(16)
+#define SCR_MPU_MASK BIT(0)
+#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \
+ | SCR_MPU_MASK)
+#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
+
+/* Macros */
+
+#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ + (SOCFPGA_SYSMGR_##_reg))
+
+#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \
+ + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
+
+#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
+ + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
+
+/* L3 Interconnect Register Map */
+#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000
+#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004
+#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028
+#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030
+#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040
+#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044
+#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068
+#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070
+
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
+
+#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
+#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
+
+void enable_nonsecure_access(void);
+void enable_ns_peripheral_access(void);
+void enable_ns_bridge_access(void);
+
+#endif /* SOCFPGA_SYSTEMMANAGER_H */
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index eb35c4a..8d7c1d6 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -316,3 +316,13 @@
return MBOX_CFGSTAT_STATE_CONFIG;
}
+
+int intel_mailbox_is_fpga_not_ready(void)
+{
+ int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
+
+ if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
+ ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
+
+ return ret;
+}
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
new file mode 100644
index 0000000..32604c9
--- /dev/null
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <errno.h>
+#include <lib/mmio.h>
+
+#include "socfpga_mailbox.h"
+#include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
+
+
+void deassert_peripheral_reset(void)
+{
+ mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST),
+ RSTMGR_FIELD(PER1, WATCHDOG0) |
+ RSTMGR_FIELD(PER1, WATCHDOG1) |
+ RSTMGR_FIELD(PER1, WATCHDOG2) |
+ RSTMGR_FIELD(PER1, WATCHDOG3) |
+ RSTMGR_FIELD(PER1, L4SYSTIMER0) |
+ RSTMGR_FIELD(PER1, L4SYSTIMER1) |
+ RSTMGR_FIELD(PER1, SPTIMER0) |
+ RSTMGR_FIELD(PER1, SPTIMER1) |
+ RSTMGR_FIELD(PER1, I2C0) |
+ RSTMGR_FIELD(PER1, I2C1) |
+ RSTMGR_FIELD(PER1, I2C2) |
+ RSTMGR_FIELD(PER1, I2C3) |
+ RSTMGR_FIELD(PER1, I2C4) |
+ RSTMGR_FIELD(PER1, UART0) |
+ RSTMGR_FIELD(PER1, UART1) |
+ RSTMGR_FIELD(PER1, GPIO0) |
+ RSTMGR_FIELD(PER1, GPIO1));
+
+ mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
+ RSTMGR_FIELD(PER0, EMAC0OCP) |
+ RSTMGR_FIELD(PER0, EMAC1OCP) |
+ RSTMGR_FIELD(PER0, EMAC2OCP) |
+ RSTMGR_FIELD(PER0, USB0OCP) |
+ RSTMGR_FIELD(PER0, USB1OCP) |
+ RSTMGR_FIELD(PER0, NANDOCP) |
+ RSTMGR_FIELD(PER0, SDMMCOCP) |
+ RSTMGR_FIELD(PER0, DMAOCP));
+
+ mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
+ RSTMGR_FIELD(PER0, EMAC0) |
+ RSTMGR_FIELD(PER0, EMAC1) |
+ RSTMGR_FIELD(PER0, EMAC2) |
+ RSTMGR_FIELD(PER0, USB0) |
+ RSTMGR_FIELD(PER0, USB1) |
+ RSTMGR_FIELD(PER0, NAND) |
+ RSTMGR_FIELD(PER0, SDMMC) |
+ RSTMGR_FIELD(PER0, DMA) |
+ RSTMGR_FIELD(PER0, SPIM0) |
+ RSTMGR_FIELD(PER0, SPIM1) |
+ RSTMGR_FIELD(PER0, SPIS0) |
+ RSTMGR_FIELD(PER0, SPIS1) |
+ RSTMGR_FIELD(PER0, EMACPTP) |
+ RSTMGR_FIELD(PER0, DMAIF0) |
+ RSTMGR_FIELD(PER0, DMAIF1) |
+ RSTMGR_FIELD(PER0, DMAIF2) |
+ RSTMGR_FIELD(PER0, DMAIF3) |
+ RSTMGR_FIELD(PER0, DMAIF4) |
+ RSTMGR_FIELD(PER0, DMAIF5) |
+ RSTMGR_FIELD(PER0, DMAIF6) |
+ RSTMGR_FIELD(PER0, DMAIF7));
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
+ mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+ RSTMGR_FIELD(BRG, MPFE));
+#endif
+}
+
+void config_hps_hs_before_warm_reset(void)
+{
+ uint32_t or_mask = 0;
+
+ or_mask |= RSTMGR_HDSKEN_SDRSELFREFEN;
+ or_mask |= RSTMGR_HDSKEN_FPGAHSEN;
+ or_mask |= RSTMGR_HDSKEN_ETRSTALLEN;
+ or_mask |= RSTMGR_HDSKEN_L2FLUSHEN;
+ or_mask |= RSTMGR_HDSKEN_L3NOC_DBG;
+ or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC;
+
+ mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask);
+}
+
+static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match)
+{
+ int time_out = 1000;
+
+ while (time_out--) {
+ if ((mmio_read_32(addr) & mask) == match) {
+ return 0;
+ }
+ }
+ return -ETIMEDOUT;
+}
+
+int socfpga_bridges_enable(void)
+{
+ /* Clear idle request */
+ mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0);
+
+ /* De-assert all bridges */
+ mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0);
+
+ /* Wait until idle ack becomes 0 */
+ return poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
+ IDLE_DATA_MASK, 0);
+}
+
+int socfpga_bridges_disable(void)
+{
+ /* Set idle request */
+ mmio_write_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), ~0);
+
+ /* Enable NOC timeout */
+ mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
+
+ /* Wait until each idle ack bit toggle to 1 */
+ if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
+ IDLE_DATA_MASK, IDLE_DATA_MASK))
+ return -ETIMEDOUT;
+
+ /* Wait until each idle status bit toggle to 1 */
+ if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS),
+ IDLE_DATA_MASK, IDLE_DATA_MASK))
+ return -ETIMEDOUT;
+
+ /* Assert all bridges */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
+ mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+ ~(RSTMGR_FIELD(BRG, DDRSCH) | RSTMGR_FIELD(BRG, FPGA2SOC)));
+#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
+ mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+ ~(RSTMGR_FIELD(BRG, MPFE) | RSTMGR_FIELD(BRG, FPGA2SOC)));
+#endif
+
+ /* Disable NOC timeout */
+ mmio_clrbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
+
+ return 0;
+}
diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_system_manager.c
new file mode 100644
index 0000000..a64053c
--- /dev/null
+++ b/plat/intel/soc/common/soc/socfpga_system_manager.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include "socfpga_system_manager.h"
+
+void enable_nonsecure_access(void)
+{
+ enable_ns_peripheral_access();
+ enable_ns_bridge_access();
+}
+
+void enable_ns_peripheral_access(void)
+{
+ mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_REGISTER), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_DATA), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_ECC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_READ_ECC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_WRITE_ECC),
+ DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_PER_SCR(USB0_REGISTER), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(USB1_REGISTER), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(USB0_ECC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(USB1_ECC), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER0), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER1), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_SLAVE0), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_SLAVE1), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC0), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC1), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC2), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC0RX_ECC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC0TX_ECC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC1RX_ECC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC1TX_ECC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC2RX_ECC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC2TX_ECC), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_PER_SCR(SDMMC), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(SDMMC_ECC), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO0), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO1), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_PER_SCR(I2C0), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(I2C1), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(I2C2), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(I2C3), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(I2C4), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_PER_SCR(SP_TIMER1), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_PER_SCR(UART0), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_PER_SCR(UART1), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(DMA_ECC), DISABLE_L4_FIREWALL);
+
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(OCRAM_ECC), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(CLK_MGR), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(IO_MGR), DISABLE_L4_FIREWALL);
+
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(RST_MGR), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(SYS_MGR), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(OSC0_TIMER), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(OSC1_TIMER), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG0), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG1), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG2), DISABLE_L4_FIREWALL);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG3), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(DAP), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_PROBES), DISABLE_L4_FIREWALL);
+
+ mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL);
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
+ mmio_clrbits_32(SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
+ mmio_clrbits_32(SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
+
+ mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3));
+#endif
+
+}
+
+void enable_ns_bridge_access(void)
+{
+ mmio_write_32(SOCFPGA_SOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL);
+ mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL);
+}
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index 1ba48ea..d8a6c19 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -47,7 +47,7 @@
mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
/* release core reset */
- mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+ mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
return PSCI_E_SUCCESS;
}
@@ -78,7 +78,7 @@
__func__, i, target_state->pwr_domain_state[i]);
/* assert core reset */
- mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+ mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
}
@@ -117,7 +117,7 @@
__func__, i, target_state->pwr_domain_state[i]);
/* release core reset */
- mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+ mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
}
/*******************************************************************************
@@ -148,13 +148,13 @@
mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS);
/* Increase timeout */
- mmio_write_32(SOCFPGA_RSTMGR_HDSKTIMEOUT, 0xffffff);
+ mmio_write_32(SOCFPGA_RSTMGR(HDSKTIMEOUT), 0xffffff);
/* Enable handshakes */
- mmio_setbits_32(SOCFPGA_RSTMGR_HDSKEN, SOCFPGA_RSTMGR_HDSKEN_SET);
+ mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET);
/* Reset L2 module */
- mmio_setbits_32(SOCFPGA_RSTMGR_COLDMODRST, 0x100);
+ mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100);
while (1)
wfi();
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index ce88fb4..41dae9e 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -11,6 +11,7 @@
#include <tools_share/uuid.h>
#include "socfpga_mailbox.h"
+#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
/* Number of SiP Calls implemented */
@@ -27,6 +28,7 @@
static int max_blocks;
static uint32_t bytes_per_block;
static uint32_t blocks_submitted;
+static int is_partial_reconfig;
struct fpga_config_info {
uint32_t addr;
@@ -93,9 +95,14 @@
return 0;
}
-static uint32_t intel_mailbox_fpga_config_isdone(void)
+static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type)
{
- uint32_t ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
+ uint32_t ret;
+
+ if (query_type == 1)
+ ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
+ else
+ ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
if (ret) {
if (ret == MBOX_CFGSTAT_STATE_CONFIG)
@@ -104,6 +111,12 @@
return INTEL_SIP_SMC_STATUS_ERROR;
}
+ if (query_type != 1) {
+ /* full reconfiguration */
+ if (!is_partial_reconfig)
+ socfpga_bridges_enable(); /* Enable bridge */
+ }
+
return INTEL_SIP_SMC_STATUS_OK;
}
@@ -191,6 +204,8 @@
uint32_t response[3];
int status = 0;
+ is_partial_reconfig = config_type;
+
mailbox_clear_response();
mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0);
@@ -220,6 +235,12 @@
send_id = 0;
rcv_id = 0;
+ /* full reconfiguration */
+ if (!is_partial_reconfig) {
+ /* Disable bridge */
+ socfpga_bridges_disable();
+ }
+
return 0;
}
@@ -368,7 +389,7 @@
SMC_UUID_RET(handle, intl_svc_uid);
case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
- status = intel_mailbox_fpga_config_isdone();
+ status = intel_mailbox_fpga_config_isdone(x1);
SMC_RET4(handle, status, 0, 0, 0);
case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 85a60d6..7d183db 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -19,11 +19,11 @@
#include "socfpga_handoff.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
+#include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
#include "s10_clock_manager.h"
#include "s10_memory_controller.h"
#include "s10_pinmux.h"
-#include "s10_reset_manager.h"
-#include "s10_system_manager.h"
#include "wdt/watchdog.h"
@@ -72,6 +72,10 @@
socfpga_delay_timer_init();
init_hard_memory_controller();
+ mailbox_init();
+
+ if (!intel_mailbox_is_fpga_not_ready())
+ socfpga_bridges_enable();
}
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index 29bd176..29f57c4 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -17,11 +17,12 @@
#include <platform_def.h>
#include "socfpga_private.h"
-#include "s10_reset_manager.h"
+#include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
#include "s10_memory_controller.h"
#include "s10_pinmux.h"
#include "s10_clock_manager.h"
-#include "s10_system_manager.h"
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
diff --git a/plat/intel/soc/stratix10/include/s10_memory_controller.h b/plat/intel/soc/stratix10/include/s10_memory_controller.h
index ad7cb9d..155b279 100644
--- a/plat/intel/soc/stratix10/include/s10_memory_controller.h
+++ b/plat/intel/soc/stratix10/include/s10_memory_controller.h
@@ -22,8 +22,6 @@
#define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \
(((value) & 0x00000060) >> 5)
-#define S10_RSTMGR_BRGMODRST 0xffd1102c
-#define S10_RSTMGR_BRGMODRST_DDRSCH 0x00000040
#define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
#define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
diff --git a/plat/intel/soc/stratix10/include/s10_reset_manager.h b/plat/intel/soc/stratix10/include/s10_reset_manager.h
deleted file mode 100644
index 731a8dd..0000000
--- a/plat/intel/soc/stratix10/include/s10_reset_manager.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __S10_RESETMANAGER_H__
-#define __S10_RESETMANAGER_H__
-
-#define S10_RSTMGR_PER0MODRST 0xffd11024
-#define S10_RSTMGR_PER1MODRST 0xffd11028
-#define S10_RSTMGR_HDSKEN 0xffd11010
-
-#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
-#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
-#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
-#define S10_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
-#define S10_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
-#define S10_RSTMGR_PER0MODRST_DMAOCP 0x00200000
-#define S10_RSTMGR_PER0MODRST_DMA 0x00010000
-#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
-#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
-#define S10_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
-#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
-#define S10_RSTMGR_PER0MODRST_EMACPTP 0x00400000
-#define S10_RSTMGR_PER0MODRST_NANDOCP 0x00002000
-#define S10_RSTMGR_PER0MODRST_NAND 0x00000020
-#define S10_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
-#define S10_RSTMGR_PER0MODRST_SDMMC 0x00000080
-#define S10_RSTMGR_PER0MODRST_SPIM0 0x00020000
-#define S10_RSTMGR_PER0MODRST_SPIM1 0x00040000
-#define S10_RSTMGR_PER0MODRST_SPIS0 0x00080000
-#define S10_RSTMGR_PER0MODRST_SPIS1 0x00100000
-#define S10_RSTMGR_PER0MODRST_USB0OCP 0x00000800
-#define S10_RSTMGR_PER0MODRST_USB0 0x00000008
-#define S10_RSTMGR_PER0MODRST_USB1OCP 0x00001000
-#define S10_RSTMGR_PER0MODRST_USB1 0x00000010
-
-#define S10_RSTMGR_PER1MODRST_WATCHDOG0 0x1
-#define S10_RSTMGR_PER1MODRST_WATCHDOG1 0x2
-#define S10_RSTMGR_PER1MODRST_WATCHDOG2 0x4
-#define S10_RSTMGR_PER1MODRST_WATCHDOG3 0x8
-#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
-#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
-#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
-#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
-#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
-#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
-#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
-#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
-#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
-#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
-#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
-#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
-#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
-#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
-#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
-#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
-#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
-#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
-#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
-#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
-#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
-#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
-#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
-#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
-#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
-#define S10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
-#define S10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004
-#define S10_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
-#define S10_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
-
-#define S10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
-#define S10_RSTMGR_PER0MODRST_DMAIF0 0x01000000
-#define S10_RSTMGR_PER0MODRST_DMAIF1 0x02000000
-#define S10_RSTMGR_PER0MODRST_DMAIF2 0x04000000
-#define S10_RSTMGR_PER0MODRST_DMAIF3 0x08000000
-#define S10_RSTMGR_PER0MODRST_DMAIF4 0x10000000
-#define S10_RSTMGR_PER0MODRST_DMAIF5 0x20000000
-#define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000
-#define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000
-
-void deassert_peripheral_reset(void);
-void config_hps_hs_before_warm_reset(void);
-
-#endif
-
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
deleted file mode 100644
index 4abfedb..0000000
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
-#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
-#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
-#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028
-#define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c
-#define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030
-#define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034
-#define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040
-#define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044
-#define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048
-#define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050
-#define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054
-#define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058
-#define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c
-#define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068
-#define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c
-#define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070
-
-#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120
-#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c
-#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130
-#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134
-#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138
-#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140
-#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144
-#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148
-#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c
-#define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154
-#define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158
-#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c
-#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160
-#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174
-#define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194
-
-#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
-#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
-
-#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
-#define SYSMGR_MMC 0x28
-#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
-#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
-#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
-#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
-
-
-#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
-
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index ab723f7..9dc5151 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -15,8 +15,14 @@
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE 0xff808000
-#define SOCFPGA_RSTMGR_OFST 0xffd11000
-#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020
+#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300
+
#endif /* PLATSOCFPGA_DEF_H */
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index e7251c4..efbab24 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -38,14 +38,14 @@
plat/intel/soc/stratix10/soc/s10_clock_manager.c \
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
- plat/intel/soc/stratix10/soc/s10_reset_manager.c \
- plat/intel/soc/stratix10/soc/s10_system_manager.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
+ plat/intel/soc/common/soc/socfpga_reset_manager.c \
+ plat/intel/soc/common/soc/socfpga_system_manager.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c
@@ -59,6 +59,7 @@
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
+ plat/intel/soc/common/soc/socfpga_reset_manager.c
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
index e4ff7ac..1e092de 100644
--- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
@@ -12,8 +12,8 @@
#include <platform_def.h>
#include "s10_clock_manager.h"
-#include "s10_system_manager.h"
#include "socfpga_handoff.h"
+#include "socfpga_system_manager.h"
void wait_pll_lock(void)
@@ -190,9 +190,9 @@
ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);
/* Pass clock source frequency into scratch register */
- mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
+ mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1),
hoff_ptr->hps_osc_clk_h);
- mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
+ mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2),
hoff_ptr->fpga_clk_hz);
}
@@ -205,14 +205,14 @@
switch (ALT_CLKMGR_PSRC(pllglob)) {
case ALT_CLKMGR_PLLGLOB_PSRC_EOSC1:
- scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
+ scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
ref_clk = mmio_read_32(scr_reg);
break;
case ALT_CLKMGR_PLLGLOB_PSRC_INTOSC:
ref_clk = ALT_CLKMGR_INTOSC_HZ;
break;
case ALT_CLKMGR_PLLGLOB_PSRC_F2S:
- scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
+ scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
ref_clk = mmio_read_32(scr_reg);
break;
default:
diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c
index cb45251..ac756ab 100644
--- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c
+++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c
@@ -15,6 +15,7 @@
#include <string.h>
#include "s10_memory_controller.h"
+#include "socfpga_reset_manager.h"
#define ALT_CCU_NOC_DI_SET_MSK 0x10
@@ -184,7 +185,7 @@
return status;
}
- mmio_clrbits_32(S10_RSTMGR_BRGMODRST, S10_RSTMGR_BRGMODRST_DDRSCH);
+ mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_FIELD(BRG, DDRSCH));
status = mem_calibration();
if (status) {
diff --git a/plat/intel/soc/stratix10/soc/s10_reset_manager.c b/plat/intel/soc/stratix10/soc/s10_reset_manager.c
deleted file mode 100644
index 8b7420b..0000000
--- a/plat/intel/soc/stratix10/soc/s10_reset_manager.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <assert.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/console.h>
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-#include "s10_reset_manager.h"
-
-void deassert_peripheral_reset(void)
-{
- mmio_clrbits_32(S10_RSTMGR_PER1MODRST,
- S10_RSTMGR_PER1MODRST_WATCHDOG0 |
- S10_RSTMGR_PER1MODRST_WATCHDOG1 |
- S10_RSTMGR_PER1MODRST_WATCHDOG2 |
- S10_RSTMGR_PER1MODRST_WATCHDOG3 |
- S10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
- S10_RSTMGR_PER1MODRST_L4SYSTIMER1 |
- S10_RSTMGR_PER1MODRST_SPTIMER0 |
- S10_RSTMGR_PER1MODRST_SPTIMER1 |
- S10_RSTMGR_PER1MODRST_I2C0 |
- S10_RSTMGR_PER1MODRST_I2C1 |
- S10_RSTMGR_PER1MODRST_I2C2 |
- S10_RSTMGR_PER1MODRST_I2C3 |
- S10_RSTMGR_PER1MODRST_I2C4 |
- S10_RSTMGR_PER1MODRST_UART0 |
- S10_RSTMGR_PER1MODRST_UART1 |
- S10_RSTMGR_PER1MODRST_GPIO0 |
- S10_RSTMGR_PER1MODRST_GPIO1);
-
- mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
- S10_RSTMGR_PER0MODRST_EMAC0OCP |
- S10_RSTMGR_PER0MODRST_EMAC1OCP |
- S10_RSTMGR_PER0MODRST_EMAC2OCP |
- S10_RSTMGR_PER0MODRST_USB0OCP |
- S10_RSTMGR_PER0MODRST_USB1OCP |
- S10_RSTMGR_PER0MODRST_NANDOCP |
- S10_RSTMGR_PER0MODRST_SDMMCOCP |
- S10_RSTMGR_PER0MODRST_DMAOCP);
-
- mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
- S10_RSTMGR_PER0MODRST_EMAC0 |
- S10_RSTMGR_PER0MODRST_EMAC1 |
- S10_RSTMGR_PER0MODRST_EMAC2 |
- S10_RSTMGR_PER0MODRST_USB0 |
- S10_RSTMGR_PER0MODRST_USB1 |
- S10_RSTMGR_PER0MODRST_NAND |
- S10_RSTMGR_PER0MODRST_SDMMC |
- S10_RSTMGR_PER0MODRST_DMA |
- S10_RSTMGR_PER0MODRST_SPIM0 |
- S10_RSTMGR_PER0MODRST_SPIM1 |
- S10_RSTMGR_PER0MODRST_SPIS0 |
- S10_RSTMGR_PER0MODRST_SPIS1 |
- S10_RSTMGR_PER0MODRST_EMACPTP |
- S10_RSTMGR_PER0MODRST_DMAIF0 |
- S10_RSTMGR_PER0MODRST_DMAIF1 |
- S10_RSTMGR_PER0MODRST_DMAIF2 |
- S10_RSTMGR_PER0MODRST_DMAIF3 |
- S10_RSTMGR_PER0MODRST_DMAIF4 |
- S10_RSTMGR_PER0MODRST_DMAIF5 |
- S10_RSTMGR_PER0MODRST_DMAIF6 |
- S10_RSTMGR_PER0MODRST_DMAIF7);
-
-}
-
-void config_hps_hs_before_warm_reset(void)
-{
- uint32_t or_mask = 0;
-
- or_mask |= S10_RSTMGR_HDSKEN_SDRSELFREFEN;
- or_mask |= S10_RSTMGR_HDSKEN_FPGAHSEN;
- or_mask |= S10_RSTMGR_HDSKEN_ETRSTALLEN;
- or_mask |= S10_RSTMGR_HDSKEN_L2FLUSHEN;
- or_mask |= S10_RSTMGR_HDSKEN_L3NOC_DBG;
- or_mask |= S10_RSTMGR_HDSKEN_DEBUG_L3NOC;
-
- mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask);
-}
-
diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c
deleted file mode 100644
index a2ed5a3..0000000
--- a/plat/intel/soc/stratix10/soc/s10_system_manager.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-#include "s10_system_manager.h"
-
-void enable_nonsecure_access(void)
-{
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
- DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
-
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
-
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
-
- mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
- mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
-
- mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3));
-
-}
-